9444 lines
593 KiB
Plaintext
9444 lines
593 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC3220/30/40/50 On-Chip Peripherals
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; @Props: Released
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; @Author: BOB
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; @Changelog: 2009-02-23 BOB
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: user.manual.lpc3220.lpc3230.lpc3240.lpc3250.pdf Rev. 00.27 (2008-11-20)
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; @Core: ARM926EJ-S
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perlpc3xxx.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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width 0xb
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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AUTOINDENT.POP
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tree.end
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tree "System Control"
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base ad:0x40004014
|
|
width 10.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "BOOT_MAP,Boot Map Control Register"
|
|
bitfld.long 0x0 0. " ARM_Res_Vec ,Internal ROM/RAM located in the ARM reset vector" "IROM,IRAM"
|
|
width 0xB
|
|
tree.end
|
|
tree "Clocking And Power Control"
|
|
base ad:0x40004000
|
|
width 14.
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "PWR_CTRL,Power Control Register"
|
|
bitfld.long 0x0 10. " HCLK/ARMCLK ,Force HCLK and ARMCLK to run with PERIPH_CLK frequency" "Normal mode,PERIPH_CLK"
|
|
bitfld.long 0x0 9. " EMCSREFREQ ,SDRAM self refresh request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 8. " EMCSREFREQUPD ,MPMCSREFREQ update" "No action,Update"
|
|
bitfld.long 0x0 7. " SDRAMAESREFEN ,SDRAM auto exit self refresh enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HIGHCOREPIN ,HIGHCORE pin level" "Low,High"
|
|
bitfld.long 0x0 4. " SYSCLKENPIN ,SYSCLKEN pin level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SYSCLKEN ,SYSCLKEN mode (Not STOP/STOP)" "High/Tri-state,SYSCLKENPLvl"
|
|
bitfld.long 0x0 2. " RUNMODCTRL ,RUN mode control" "Direct,Normal"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HIGHCORE ,Core voltage supply level signalling control (STOP/Not STOP)" "High/Low,HIGHCOREPIN"
|
|
bitfld.long 0x0 0. " STOPMODCTRL ,Device STOP mode control" "Not in STOP,In STOP"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "OSC_CTRL,Main Oscillator Control Register"
|
|
hexmask.long.byte 0x0 2.--8. 1. " CAPLOAD ,SYSX_IN and SYSX_OUT capatitance load (X 0.1 pF)"
|
|
bitfld.long 0x0 1. " MAINOSCTEST ,Main oscillator test mode" "Normal,Test"
|
|
textline " "
|
|
bitfld.long 0x0 0. " MAINOSCEN ,Main oscillator enable" "Enabled,Disabled"
|
|
line.long 0x4 "SYSCLK_CTRL,SYSCLK Control Register"
|
|
hexmask.long.word 0x4 2.--11. 1. " TRIGGWAIT ,How long a bad phase must be present before the clock switching is triggered"
|
|
bitfld.long 0x4 1. " CLKSOURC ,13 MHz clock source/Main oscillator" "Main oscillator,13 MHz clock source"
|
|
textline " "
|
|
bitfld.long 0x4 0. " SYSCLKMUX ,SYSCLK MUX status (clock source)" "Main oscillator,13 MHz PLL397 output"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PLL397_CTRL,PLL397 Control Register"
|
|
bitfld.long 0x0 10. " PLLMSLOCK ,PLL main lock" "Not locked,Locked"
|
|
bitfld.long 0x0 9. " PLL397BYP ,PLL397 bypass control" "No bypass,Bypass"
|
|
textline " "
|
|
bitfld.long 0x0 6.--8. " PLL397BIAS ,PLL397 charge pump bias control" "Normal setting,-12.5% of resistance,-25% of resistance,-37.5% of resistance,+12.5% of resistance,+25% of resistance,+37.5% of resistance,+50% of resistance"
|
|
bitfld.long 0x0 1. " PLL397OPER ,PLL397 operational control" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PLLLOCKSTAT ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "HCLKPLL_CTRL,HCLK PLL Control Register"
|
|
bitfld.long 0x0 16. " PLLPWDN ,PLL Power down mode" "Power down,Operating"
|
|
bitfld.long 0x0 15. " BYPASSCTRL ,Bypass control" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0 14. " DIROUTPCTRL ,PLL direct output control" "Post driver,CCO clock"
|
|
bitfld.long 0x0 13. " FBACKDIV ,Feedback divider path control" "CCO clock,FCLKOUT"
|
|
textline " "
|
|
bitfld.long 0x0 11.--12. " PLLPDIVIDE ,PLL post-divider (P) setting" "P=1,P=2,P=4,P=8"
|
|
bitfld.long 0x0 9.--10. " PLLNDIVIDER ,PLL pre-divider (N) setting" "N=1,N=2,N=3,N=4"
|
|
textline " "
|
|
hexmask.long.byte 0x0 1.--8. 1. " PLLMDIVIDER ,PLL feedback divider (M) setting"
|
|
bitfld.long 0x0 0. " PLLLOCKSTAT ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HCLKDIV_CTRL,HCLK Divider Control Register"
|
|
bitfld.long 0x0 7.--8. " DDRAM_CLK ,DDRAM_CLK control" "Stopped,Nominal speed,Half speed,?..."
|
|
bitfld.long 0x0 2.--6. " PERIPHCLKDIV ,PERIPH_CLK divider control" "Not divided,Divided by 2,Divided by 3,Divided by 4,Divided by 5,Divided by 6,Divided by 7,Divided by 8,Divided by 9,Divided by 10,Divided by 11,Divided by 12,Divided by 13,Divided by 14,Divided by 15,Divided by 16,Divided by 17,Divided by 18,Divided by 19,Divided by 20,Divided by 21,Divided by 22,Divided by 23,Divided by 24,Divided by 25,Divided by 26,Divided by 27,Divided by 28,Divided by 29,Divided by 30,Divided by 31,Divided by 32"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " HCLKDIV ,HCLK divider control" "Not divided,Divided by 2,Divided by 4,?..."
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "TEST_CLK,Test Clock Selection Register"
|
|
bitfld.long 0x0 5.--6. " GPOTESTCLKOUT ,Output on GPO_00/TEST_CLK1 pin" "PERIPH_CLK,RTC clock,Main oscillator,?..."
|
|
bitfld.long 0x0 4. " GPOTEST1MODE ,GPO_00 / TST_CLK1 output mode" "Connected to GPIO,GPOTESTCLKOUT"
|
|
textline " "
|
|
bitfld.long 0x0 1.--3. " TST_CLK2OUT ,Output on TST_CLK2 pin" "HCLK,PERIPH_CLK,USB clock,Reserved,Reserved,Main oscillator,Reserved,PLL397 output"
|
|
bitfld.long 0x0 0. " TST_CLK2MOD ,TST_CLK2O mode" "Turned off,TST_CLK2OUT"
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "AUTOCLK_CTRL,Autoclock Control Register"
|
|
bitfld.long 0x0 6. " ACLKUSB ,Autoclock enable on USB Slave HCLK" "Stop after 128 HCLK,Always clocked"
|
|
bitfld.long 0x0 1. " ACLKIRAM ,Autoclock enable on IRAM" "Stop after 16 HCLK,Always clocked"
|
|
textline " "
|
|
bitfld.long 0x0 0. " ACLKIROM ,Autoclock enable on IROM" "Stop after 8 HCLK,Always clocked"
|
|
tree "Start Enable Registers"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "START_ER_PIN,Start Enable register for Pin Sources"
|
|
bitfld.long 0x0 31. " U7_RX ,U7_RX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " U5_RX/USB_DAT_VP ,U5_RX/USB_DAT_VP pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_28 ,GPI_28 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " U3_RX ,U3_RX pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " U2_RX ,U2_RX pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " U1_RX ,U1_RX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " GPI_06/HSTIM_CAP ,GPI_06/HSTIM_CAP pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_05 ,GPI_05 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " GPI_04 ,GPI_04 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPI_03 ,GPI_03 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " GPI_02 ,GPI_02 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_01/SERVICE_N ,GPI_01/SERVICE_N pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " GPI_00/I2S1RX_SDA ,GPI_00 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,GPI_07 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPI_19/U4_RX ,GPI_19/U4_RX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " GPI_09 ,GPI_09 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPI_08 ,GPI_08 pin enable" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "START_ER_INT,Start Enable Register for Internal Sources"
|
|
bitfld.long 0x0 31. " TS_INT/AD_IRQ , Touchscreen/ADC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " TS_P , TS_P, Touch screen interface press detect" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " TS_AUX ,TS_AUX Touch screen interface auxiliary interrupt detect" "Enabled,Disabled"
|
|
bitfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " RTC_INT ,RTC interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " USB_INT ,USB interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x0 7. " ETHMAC , Ethernet MAC Start request" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " P[07]/P1[23] ,Enable Port 0 and Port 1 start request" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x0 6. " P[07]/P1[23] ,Enable Port 0 and Port 1 start request" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,GPIO_05 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " GPIO_04 ,GPIO_04 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,GPIO_03 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " GPIO_02 ,GPIO_02 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,GPIO_01 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " GPIO_00 ,GPIO_00 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "P0_INTR_ER,Port 0 and 1 interrupt and start register control"
|
|
bitfld.long 0x00 31. " P1.23 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " P1.22 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " P1.21 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P1.20 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " P1.19 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P1.18 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P1.17 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P1.16 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P0.15 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P1.14 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P1.13 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P1.12 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P1.11 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P1.10 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P1.9 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P1.8 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " P1.7 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P1.6 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P1.5 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P1.4 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " P1.3 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P1.2 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P1.1 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P1.0 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P0.7 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P0.6 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P0.5 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P0.4 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P0.3 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P0.2 ,Interrupt and start enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P0.1 ,Interrupt and start enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0.0 ,Interrupt and start enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Start Status Registers"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "START_SR_PIN,Start Status Register for Pin Sources"
|
|
bitfld.long 0x0 31. " U7_RX ,U7_RX pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 26. " U5_RX/USB_DAT_VP ,U5_RX/USB_DAT_VP pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_28 ,GPI_28 pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 24. " U3_RX ,U3_RX pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 22. " U2_RX ,U2_RX pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 21. " U1_RX ,U1_RX pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 16. " GPI_06/HSTIM_CAP ,GPI_06/HSTIM_CAP pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_05 ,GPI_05 pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 14. " GPI_04 ,GPI_04 pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPI_03 ,GPI_03 pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 12. " GPI_02 ,GPI_02 pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_01/SERVICE_N ,GPI_01/SERVICE_N pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 10. " GPI_00/I2S1RX_SDA ,GPI_00/I2S1RX_SDA pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,GPI_07 pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPI_19/U4_RX ,GPI_19/U4_RX pin state after masking" "Inactice,Active"
|
|
bitfld.long 0x0 4. " GPI_09 ,GPI_09 pin state after masking" "Inactice,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPI_08 ,GPI_08 pin state after masking" "Inactice,Active"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "START_SR_INT,Start Status Register for Internal Sources"
|
|
bitfld.long 0x0 31. " TS_INT/AD_IRQ , Touchscreen/ADC state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 30. " TS_P , TS_P , Touch screen interface press detect state after masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 29. " TS_AUX ,TS_AUX Touch screen interface auxiliary interrupt detect" "Inactive,Active"
|
|
bitfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK state after masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MSTIMER_INT ,MSTIMER state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 24. " RTC_INT ,RTC state after masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 22. " USB_INT ,USB_INT state after masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USB_I2C_INT ,USB_I2C state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER state after masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner state after masking" "Inactive,Active"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x0 7. " ETHMAC , Ethernet MAC Start request state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 6. " P[07]/P1[23] , Port 0 and Port 1 start request state after masking" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x0 6. " P[07]/P1[23] , Port 0 and Port 1 start request state after masking" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,GPIO_05 state after masking" "Inactive,Active"
|
|
bitfld.long 0x0 4. " GPIO_04 ,GPIO_04 state after masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,GPIO_03 state after masking" "Inactive,Active"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "START_RSR_PIN,Start Raw Status Register for Pin Sources"
|
|
eventfld.long 0x0 31. " U7_RX ,U7_RX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 26. " U5_RX/USB_DAT_VP ,U5_RX/USB_DAT_VP pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 25. " GPI_28 ,GPI_28 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 24. " U3_RX ,U3_RX pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 22. " U2_RX ,U2_RX pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 21. " U1_RX ,U1_RX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 16. " GPI_06/HSTIM_CAP ,GPI_06/HSTIM_CAP pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 15. " GPI_05 ,GPI_05 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 14. " GPI_04 ,GPI_04 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 13. " GPI_03 ,GPI_03 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 12. " GPI_02 ,GPI_02 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 11. " GPI_01/SERVICE_N ,GPI_01/SERVICE_N pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 10. " GPI_00/I2S1RX_SDA ,GPI_00/I2S1RX_SDA pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 7. " GPI_07 ,GPI_07 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 5. " GPI_19/U4_RX ,GPI_19/U4_RX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 4. " GPI_09 ,GPI_09 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 3. " GPI_08 ,GPI_08 pin state before masking" "Inactive,Active"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "START_RSR_INT,Start Raw Status Register for Internal Sources"
|
|
eventfld.long 0x0 31. " TS_INT/AD_IRQ , Touchscreen/ADC before masking" "Inactive,Active"
|
|
eventfld.long 0x0 30. " TS_P , TS_P , Touch screen interface press detect state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 29. " TS_AUX ,TS_AUX Touch screen interface auxiliary interrupt detect state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt before masking" "Inactive,Active"
|
|
eventfld.long 0x0 24. " RTC_INT ,RTC interrupt before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK before masking" "Inactive,Active"
|
|
eventfld.long 0x0 22. " USB_INT ,USB interrupt before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt before masking" "Inactive,Active"
|
|
eventfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt before masking" "Inactive,Active"
|
|
eventfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt before masking" "Inactive,Active"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x0 7. " ETHMAC , Ethernet MAC Start request state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 6. " P[07]/P1[23] , Port 0 and Port 1 start request state before masking" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x0 6. " P[07]/P1[23] , Port 0 and Port 1 start request state before masking" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x0 5. " GPIO_05 ,GPIO_05 before masking" "Inactive,Active"
|
|
eventfld.long 0x0 4. " GPIO_04 ,GPIO_04 before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 3. " GPIO_03 ,GPIO_03 before masking" "Inactive,Active"
|
|
tree.end
|
|
tree "Start Activation Polarity Registers"
|
|
textline " "
|
|
group.long 0x3C++0x03
|
|
line.long 0x0 "START_APR_PIN,Start Activation Polarity Register for Pin Sources"
|
|
bitfld.long 0x0 31. " U7_RX ,U7_RX pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 26. " U5_RX/USB_DAT_VP ,U5_RX/USB_DAT_VP pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_28 ,GPI_28 pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 24. " U3_RX ,U3_RX pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 22. " U2_RX ,U2_RX pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 21. " U1_RX ,U1_RX pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 16. " GPI_06/HSTIM_CAP ,GPI_06/HSTIM_CAP pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_05 ,GPI_05 pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 14. " GPI_04 ,GPI_04 pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPI_03 ,GPI_03 pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 12. " GPI_02 ,GPI_02 pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_01/SERVICE_N ,GPI_01/SERVICE_N pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 10. " GPI_00/I2S1RX_SDA ,GPI_00/I2S1RX_SDA pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,GPI_07 pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPI_19/U4_RX ,GPI_19/U4_RX pin active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 4. " GPI_09 ,GPI_09 pin active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPI_08 ,GPI_08 pin active state capture" "Falling,Rising"
|
|
group.long 0x2C++0x03
|
|
line.long 0x0 "START_APR_INT,Start Activation Polarity Register for Internal Sources"
|
|
bitfld.long 0x0 31. " TS_INT/AD_IRQ , Touchscreen/ADC interrupt active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 30. " TS_P , TS_P Touch screen interface press detect active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 29. " TS_AUX ,TS_AUX Touch screen interface auxiliary active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 24. " RTC_INT ,RTC interrupt active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 22. " USB_INT ,USB interrupt active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt active state capture" "Falling,Rising"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x0 7. " ETHMAC , Ethernet MAC Start request active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 6. " P[07]/P1[23] , Port 0 and Port 1 start request active state capture" "Falling,Rising"
|
|
else
|
|
bitfld.long 0x0 6. " P[07]/P1[23] , Port 0 and Port 1 start request active state capture" "Falling,Rising"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,GPIO_05 active state capture" "Falling,Rising"
|
|
bitfld.long 0x0 4. " GPIO_04 ,GPIO_04 active state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,GPIO_03 active state capture" "Falling,Rising"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x0 24. " USBSLAVEHCLK ,USB Slave HCLK control" "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " USB_I2CEN ,Control signal for mux" "ip_3506_otg_tx_en_n,'0'"
|
|
textline " "
|
|
bitfld.long 0x0 22. " USBDEVNEEDCLK ,Usb_dev_need_clk enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " USBHOSTNEEDCLK ,Usb_host_need_clk enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " USB_CLKEN2 ,USB_Clken2 clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 19.--20. " PADSCTRL ,Pad control for USB_DAT_VP and USB_SE0_VM pads" "Pull-up added to pad,Bus keeper,No added function,Pull-down added to pad"
|
|
textline " "
|
|
bitfld.long 0x0 17. " USB_CLKEN1 ,USB_Clken1 clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " PLLPWRDOWN ,PLL Power down mode" "Power down,Operating"
|
|
textline " "
|
|
bitfld.long 0x0 15. " BYPASSCTRL ,Bypass control" "Not bypassed,Bypassed"
|
|
bitfld.long 0x0 14. " DIROUTCTRL ,Direct output control" "Post driver,CCO clock"
|
|
textline " "
|
|
bitfld.long 0x0 13. " FBACKDRIVPATH ,Feedback divider path control" "CCO clock,post PLL_CLKOUT"
|
|
bitfld.long 0x0 11.--12. " PLLPOSTDIV ,PLL post-divider (P) setting" "Divide by 2 (P=1),Divide by 4 (P=2),Divide by 8 (P=4),Divide by 16 (P=8)"
|
|
textline " "
|
|
bitfld.long 0x0 9.--10. " PLLPREDIV ,PLL pre-divider (N) setting" "1,2,3,4"
|
|
hexmask.long.byte 0x0 1.--8. 1. " PLLFBACKDIV ,PLL feedback divider (M) setting"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PLLLOCK ,PLL LOCK status" "Not locked,Locked"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "USB_DIV,USB clock pre-divide register"
|
|
bitfld.long 0x00 0.--3. " USB_RATE ,Controls the USB pre-clock divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "MS_CTRL,Memory Card Control Register"
|
|
bitfld.long 0x0 10. " SDPINSDIS ,Disable SD_card pins" "No,Yes"
|
|
bitfld.long 0x0 9. " PULLUPEN ,Pull-ups to MSSDIO pins enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " MSSDIO2/3 ,MSSDIO2 and MSSDIO3 pad control" "Pull-up,No pull-up"
|
|
bitfld.long 0x0 7. " MSSDIO1 ,MSSDIO1 pad control" "Pull-up,No pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 6. " MSSDIO0/MSBS ,MSSDIO1/MSBS pad control" "Pull-up,No pull-up"
|
|
bitfld.long 0x0 5. " SDCLKCTRL ,SD Card clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " DIVRATIO ,MSSDCLK equal ARM PLL output clock" "Stopped,Divided by 1,Divided by 2,Divided by 3,Divided by 4,Divided by 5,Divided by 6,Divided by 7,Divided by 8,Divided by 9,Divided by 10,Divided by 11,Divided by 12,Divided by 13,Divided by 14,Divided by 15"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "DMACLK_CTRL,DMA Clock Control Register"
|
|
bitfld.long 0x0 0. " DMACLKEN ,All clocks to DMA enable" "Stopped,Enabled"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "FLASHCLK_CTRL,NAND Flash Clock Control Register"
|
|
bitfld.long 0x0 5. " NANDFLSHCI ,NAND Flash controller interrupt connected to the interrupt controller" "SLC,MLC"
|
|
bitfld.long 0x0 4. " DMA_REQ_RNB ,NAND_DMA_REQ on NAND_RnB enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DMA_REQ_INT ,NAND_DMA_REQ on NAND_INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SLC/MLCSEL ,SLC/MLC NAND Flash controller select" "MLC,SLC"
|
|
textline " "
|
|
bitfld.long 0x0 1. " MLC_NANDCLKEN ,MLC NAND Flash clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " SLC_NANDCLKEN ,SLC NAND Flash clock enable control" "Disabled,Enabled"
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "MACCLK_CTRL,Ethernet MAC Clock Control register"
|
|
bitfld.long 0x00 3.--4. " HDW_INF_CTRL ,Ethernet MAC Hardware interface control" "Not connected,MII Mode,Not connected,RMII Mode"
|
|
bitfld.long 0x00 2. " MASTER_CLK ,Master Interface Clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLAVE_CLK ,Slave Interface Clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " REG_CLK ,Control Registers Clock" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
if ((d.l(ad:0x40004000+0x54)&0x100)==0x0)
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "LCDCLK_CTRL,LCD Clock Control register"
|
|
bitfld.long 0x00 8. " DISPLAY_TYPE ,Sets the Display type" "TFT,STN"
|
|
bitfld.long 0x00 6.--7. " MODE_SELECT ,Selects output pin group" "12-bit/18 pins,16-bit/22 pins,16-bit/24 pins,24-bit/30 pins"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCLK_ENABLE ,HCLK signal to LCD controller enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLKDIV ,LCD panel clock prescaler selection" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31."
|
|
else
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "LCDCLK_CTRL,LCD Clock Control register"
|
|
bitfld.long 0x00 8. " DISPLAY_TYPE ,Sets the Display type" "TFT,STN"
|
|
bitfld.long 0x00 6.--7. " MODE_SELECT ,Selects output pin group" "Single Panel/10 pins,Single Panel/14 pins,Dual Panel/14 pins,Dual Panel/22 pins"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCLK_ENABLE ,HCLK signal to LCD controller enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " CLKDIV ,LCD panel clock prescaler selection" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31."
|
|
endif
|
|
endif
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "I2S_CTRL,I2S Clock Control register"
|
|
bitfld.long 0x00 6. " I2S1_CLK_TX_MODE ,I2S1 CLK TX MODE Select" "TX_CLK,RX_CLK"
|
|
bitfld.long 0x00 5. " I2S1_CLK_RX_MODE ,I2S1 CLK RX MODE Select" "RX_CLK,TX_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 4. " I2S1 DMA1 ,I2S1 DMA1 Connection Control" "UART7 RX,I2S1 DMA"
|
|
bitfld.long 0x00 3. " I2S0_CLK_TX_MODE ,I2S0 CLK TX MODE Select" "TX_CLK,RX_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2S0_CLK_RX_MODE ,I2S0 CLK RX MODE Select" "RX_CLK,TX_CLK"
|
|
bitfld.long 0x00 1. " I2S1_CLK ,I2S1_CLK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " I2S0_CLK ,I2S0_CLK Enable" "Disabled,Enabled"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "SSP_CTRL,SSP Control register"
|
|
bitfld.long 0x00 5. " SSP1_RX_DMA ,SSP1 RX DMA connection control" "SPI2 Connected to DMA,SSP1 RX Connected to DMA"
|
|
bitfld.long 0x00 4. " SSP1_TX_DMA ,SSP1 TX DMA connection control" "SPI1 Connected to DMA,SSP1 TX Connected to DMA"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SSP0_RX_DMA ,SSP0 RX DMA connection control" "SPI3 Connected to DMA,SSP0 RX Connected to DMA"
|
|
bitfld.long 0x00 2. " SSP0_TX_DMA ,SSP0 TX DMA connection control" "SPI4 Connected to DMA,SSP0 TX Connected to DMA"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SSP1 ,SSP1 clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SSP0 ,SSP0 clock enable control" "Disabled,Enabled"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI Block Control Register"
|
|
bitfld.long 0x0 7. " SPI2_DATIO ,SPI2_DATIO output level" "Low,High"
|
|
bitfld.long 0x0 6. " SPI2_CLK ,SPI2_CLK output level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " OUTPIN2CTRL ,SPI2_DATIO and SPI2_CLK outputs control" "By bits [7:6],By SPI2"
|
|
bitfld.long 0x0 4. " SPI2CLKEN ,SPI2 clock enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SPI1_DATIO ,SPI1_DATIO output level" "Low,High"
|
|
bitfld.long 0x0 2. " SPI1_CLK ,SPI1_CLK output level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " OUTPIN1CTRL ,SPI1_DATIO and SPI1_CLK outputs control" "By bits [3:2],By SPI1"
|
|
bitfld.long 0x0 0. " SPI1CLKEN ,SPI1 clock enable control" "Disabled,Enabled"
|
|
group.long 0xAC++0x13
|
|
line.long 0x0 "I2CCLK_CTRL,I2C Clock Control Register"
|
|
bitfld.long 0x0 4. " USB_I2CDRVRSTR ,Driver strength control for USB_I2C_SCL and USB_I2C_SDA" "Low drive,High drive"
|
|
bitfld.long 0x0 3. " I2C2DRVRSTR ,I2C2_SCL and I2C2_SDA driver strength control" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x0 2. " I2C1DRVRSTR ,I2C1_SCL and I2C1_SDA driver strength control" "Low drive,High drive"
|
|
bitfld.long 0x0 1. " I2C2_HCLKEN ,I2C2 block enable" "Stopped,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " I2C1_HCLKEN ,I2C1 block enable" "Stopped,Enabled"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "TIMCLK_CTRL1,Timer Clock Control1 and MCPWM register"
|
|
bitfld.long 0x00 6. " MOTOR ,Motor Control clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TIMER3 ,Timer 3 clock enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMER2 ,Timer 2 clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMER1 ,Timer 1 clock enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIMER0 ,Timer 0 clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMER5 ,Timer 5 clock enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIMER4 ,Timer 4 clock enable control" "Disabled,Enabled"
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "TIMCLK_CTRL,Timer Clock Control Register"
|
|
bitfld.long 0x00 1. " HSTIMER ,HSTimer clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDGCLK ,Watchdog clock enable control" "Disabled,Enabled"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADCLK_CTRL,ADC Clock Control Register"
|
|
bitfld.long 0x0 0. " ADCCLKCTRL ,32 kHz clock to ADC block control" "Disabled,Enabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "ADCLK_CTRL1,ADC Clock Control1 register"
|
|
bitfld.long 0x00 8. " ADCCLK_SEL ,ADC clock select" "RTC clock,PERIPH_CLK"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADC_FREQ ,Controls the clock divider for ADC when Peripheral clock (bit 8) is enabled"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "KEYCLK_CTRL,Keyboard Scan Clock Control Register"
|
|
bitfld.long 0x00 0. " KEYCLKCTRL ,Clock to keyboard block control" "Disabled,Enabled"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PWMCLK_CTRL,PWM Clock Control Register"
|
|
bitfld.long 0x00 8.--11. " PWM2_FREQ ,Controls the clock divider for PWM2" "Off,CLKin,CLKin/2,CLKin/3,CLKin/4,CLKin/5,CLKin/6,CLKin/7,CLKin/8,CLKin/9,CLKin/10,CLKin/11,CLKin/12,CLKin/13,CLKin/14,CLKin/15"
|
|
bitfld.long 0x00 4.--7. " PWM1_FREQ ,Controls the clock divider for PWM1" "Off,CLKin,CLKin/2,CLKin/3,CLKin/4,CLKin/5,CLKin/6,CLKin/7,CLKin/8,CLKin/9,CLKin/10,CLKin/11,CLKin/12,CLKin/13,CLKin/14,CLKin/15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWM2SRC ,PWM2 clock source selection" "32 kHz RTC_CLK,PERIPH_CLK"
|
|
bitfld.long 0x00 2. " PWM2CLKEN ,Clock to PWM2 block enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWM1SRC ,PWM1 clock source selection" "32 kHz RTC_CLK,PERIPH_CLK"
|
|
bitfld.long 0x00 0. " PWM1CLKEN ,Clock to PWM1 block enable" "Disabled,Enabled"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "UARTCLK_CTRL,UART Clock Control Register"
|
|
bitfld.long 0x0 3. " UART6 ,Uart6 HCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " UART5 ,Uart5 HCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UART4 ,Uart4 HCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " UART3 ,Uart3 HCLK enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Interrupt Controller"
|
|
base ad:0x40008000
|
|
width 10.
|
|
tree "Main Interrupt Controller"
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "MIC_ER,Interrupt Enable Register for the Main Interrupt Controller"
|
|
bitfld.long 0x00 31. " SUB2FIQN ,High priority (IRQ) interrupts from SIC2" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SUB1FIQN ,High priority (IRQ) interrupts from SIC1" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x00 29. " ETHERNET ,Ethernet interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " IIR1 ,UART1 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIR2 ,UART2 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IIR7 ,UART7 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I2S1 ,I2S1 Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " I2S0 ,I2S0 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SSP1 ,SSP1 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SSP0 ,SSP0 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TIMER3 ,Timer3 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TIMER2 ,Timer2 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMER1 ,Timer1 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TIMER0 ,Timer0 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Disabled,Enabled"
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
bitfld.long 0x00 14. " LCD_INT ,Interrupt from the LCD controller" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IIR6 ,UART6 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IIR5 ,UART5 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IIR4 ,UART4 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IIR3 ,UART3 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WATCH_INT ,Watchdog Timer interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMER5 ,Timer5 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMER4/MCPWM ,Timer4 or Motor Contoller PWM interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUB2IRQN ,Low priority (IRQ) interrupts from SIC2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SUB1IRQN ,Low priority (IRQ) interrupts from SIC1" "Disabled,Enabled"
|
|
line.long 0x04 "MIC_RSR,Main Interrupt Controller Raw Status Register"
|
|
eventfld.long 0x04 31. " SUB2FIQN ,High priority (IRQ) interrupts from SIC2" "Inactive,Active"
|
|
eventfld.long 0x04 30. " SUB1FIQN ,High priority (IRQ) interrupts from SIC1" "Inactive,Active"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
eventfld.long 0x04 29. " ETHERNET ,Ethernet interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Inactive,Active"
|
|
else
|
|
eventfld.long 0x04 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x04 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Inactive,Active"
|
|
eventfld.long 0x04 26. " IIR1 ,UART1 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 25. " IIR2 ,UART2 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 24. " IIR7 ,UART7 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 23. " I2S1 ,I2S1 Interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 22. " I2S0 ,I2S0 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 21. " SSP1 ,SSP1 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 20. " SSP0 ,SSP0 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 19. " TIMER3 ,Timer3 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 18. " TIMER2 ,Timer2 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 17. " TIMER1 ,Timer1 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 16. " TIMER0 ,Timer0 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Inactive,Active"
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
eventfld.long 0x04 14. " LCD_INT ,Interrupt from the LCD controller" "Inactive,Active"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x04 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Inactive,Active"
|
|
eventfld.long 0x04 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 10. " IIR6 ,UART6 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 9. " IIR5 ,UART5 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 8. " IIR4 ,UART4 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 7. " IIR3 ,UART3 interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 6. " WATCH_INT ,Watchdog Timer interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 4. " TIMER5 ,Timer5 interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 3. " TIMER4/MCPWM ,Timer4 or Motor Contoller PWM interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 1. " SUB2IRQN ,Low priority (IRQ) interrupts from SIC2" "Inactive,Active"
|
|
eventfld.long 0x04 0. " SUB1IRQN ,Low priority (IRQ) interrupts from SIC1" "Inactive,Active"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "MIC_SR,Main Interrupt Controller Status Register"
|
|
bitfld.long 0x00 31. " SUB2FIQN ,High priority (IRQ) interrupts from SIC2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " SUB1FIQN ,High priority (IRQ) interrupts from SIC1" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x00 29. " ETHERNET ,Ethernet interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " DMA_INT ,General Purpose DMA Controller interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 28. " DMA_INT ,General Purpose DMA Controller interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IIR1 ,UART1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIR2 ,UART2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IIR7 ,UART7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I2S1 ,I2S1 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I2S0 ,I2S0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SSP1 ,SSP1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " SSP0 ,SSP0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TIMER3 ,Timer3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " TIMER2 ,Timer2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMER1 ,Timer1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " TIMER0 ,Timer0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "No interrupt,Interrupt"
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
bitfld.long 0x00 14. " LCD_INT ,Interrupt from the LCD controller" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IIR6 ,UART6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IIR5 ,UART5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IIR4 ,UART4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " IIR3 ,UART3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WATCH_INT ,Watchdog Timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMER5 ,Timer5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " TIMER4/MCPWM ,Timer4 or Motor Contoller PWM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUB2IRQN ,Low priority (IRQ) interrupts from SIC2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " SUB1IRQN ,Low priority (IRQ) interrupts from SIC1" "No interrupt,Interrupt"
|
|
group.long 0x0C++0xB
|
|
line.long 0x00 "MIC_APR,Main Interrupt Controller Activation Polarity Register"
|
|
bitfld.long 0x00 31. " SUB2FIQN ,High priority (IRQ) interrupts from SIC2" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 30. " SUB1FIQN ,High priority (IRQ) interrupts from SIC1" "Low/Falling,High/Rising"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x00 29. " ETHERNET ,Ethernet interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Low/Falling,High/Rising"
|
|
else
|
|
bitfld.long 0x00 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Low/Falling,High/Rising"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 26. " IIR1 ,UART1 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIR2 ,UART2 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 24. " IIR7 ,UART7 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I2S1 ,I2S1 Interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 22. " I2S0 ,I2S0 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SSP1 ,SSP1 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 20. " SSP0 ,SSP0 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TIMER3 ,Timer3 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 18. " TIMER2 ,Timer2 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMER1 ,Timer1 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 16. " TIMER0 ,Timer0 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Low/Falling,High/Rising"
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
bitfld.long 0x00 14. " LCD_INT ,Interrupt from the LCD controller" "Low/Falling,High/Rising"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IIR6 ,UART6 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 9. " IIR5 ,UART5 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IIR4 ,UART4 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 7. " IIR3 ,UART3 interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WATCH_INT ,Watchdog Timer interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMER5 ,Timer5 interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 3. " TIMER4/MCPWM ,Timer4 or Motor Contoller PWM interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SUB2IRQN ,Low priority (IRQ) interrupts from SIC2" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 0. " SUB1IRQN ,Low priority (IRQ) interrupts from SIC1" "Low/Falling,High/Rising"
|
|
line.long 0x04 "MIC_ATR,Main Interrupt Controller Activation Type Register"
|
|
bitfld.long 0x04 31. " SUB2FIQN ,High priority (IRQ) interrupts from SIC2" "Level,Edge"
|
|
bitfld.long 0x04 30. " SUB1FIQN ,High priority (IRQ) interrupts from SIC1" "Level,Edge"
|
|
textline " "
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x04 29. " ETHERNET ,Ethernet interrupt" "Level,Edge"
|
|
bitfld.long 0x04 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Level,Edge"
|
|
else
|
|
bitfld.long 0x04 28. " DMA_INT ,General Purpose DMA Controller interrupt" "Level,Edge"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Level,Edge"
|
|
bitfld.long 0x04 26. " IIR1 ,UART1 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 25. " IIR2 ,UART2 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 24. " IIR7 ,UART7 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I2S1 ,I2S1 Interrupt" "Level,Edge"
|
|
bitfld.long 0x04 22. " I2S0 ,I2S0 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SSP1 ,SSP1 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 20. " SSP0 ,SSP0 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 19. " Timer3 ,Timer3 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 18. " Timer2 ,Timer2 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 17. " Timer1 ,Timer1 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 16. " Timer0 ,Timer0 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Level,Edge"
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
bitfld.long 0x04 14. " LCD_INT ,Interrupt from the LCD controller" "Level,Edge"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Level,Edge"
|
|
bitfld.long 0x04 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IIR6 ,UART6 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 9. " IIR5 ,UART5 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 8. " IIR4 ,UART4 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 7. " IIR3 ,UART3 interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WATCH_INT ,Watchdog Timer interrupt" "Level,Edge"
|
|
bitfld.long 0x04 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TIMER5 ,Timer5 interrupt" "Level,Edge"
|
|
bitfld.long 0x04 3. " TIMER4/MCPWM ,Timer4 or Motor Contoller PWM interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SUB2IRQN ,Low priority (IRQ) interrupts from SIC2" "Level,Edge"
|
|
bitfld.long 0x04 0. " SUB1IRQN ,Low priority (IRQ) interrupts from SIC1" "Level,Edge"
|
|
line.long 0x08 "MIC_ITR,Main Interrupt Controller Interrupt Type Register"
|
|
bitfld.long 0x08 31. " SUB2FIQN ,High priority (IRQ) interrupts from SIC2" "IRQ,FIQ"
|
|
bitfld.long 0x08 30. " SUB1FIQN ,High priority (IRQ) interrupts from SIC1" "IRQ,FIQ"
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
bitfld.long 0x08 29. " ETHERNET ,Ethernet interrupt" "IRQ,FIQ"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 28. " DMA_INT ,General Purpose DMA Controller interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "IRQ,FIQ"
|
|
bitfld.long 0x08 26. " IIR1 ,UART1 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IIR2 ,UART2 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " IIR7 ,UART7 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 23. " I2S1 ,I2S1 Interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 22. " I2S0 ,I2S0 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 21. " SSP1 ,SSP1 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " SSP0 ,SSP0 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TIMER3 ,Timer3 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 18. " TIMER2 ,Timer2 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 17. " TIMER1 ,Timer1 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TIMER0 ,Timer0 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "IRQ,FIQ"
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
bitfld.long 0x08 14. " LCD_INT ,Interrupt from the LCD controller" "IRQ,FIQ"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "IRQ,FIQ"
|
|
bitfld.long 0x08 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " IIR6 ,UART6 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 9. " IIR5 ,UART5 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 8. " IIR4 ,UART4 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " IIR3 ,UART3 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 6. " WATCH_INT ,Watchdog Timer interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " TIMER5 ,Timer5 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TIMER4/MCPWM ,Timer4 or Motor Contoller PWM interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 1. " SUB2IRQN ,Low priority (IRQ) interrupts from SIC2" "IRQ,FIQ"
|
|
bitfld.long 0x08 0. " SUB1IRQN ,Low priority (IRQ) interrupts from SIC1" "IRQ,FIQ"
|
|
tree.end
|
|
tree "Sub Interrupt Controller 1"
|
|
group.long 0x04000++0x7
|
|
line.long 0x00 "SIC1_ER,Interrupt Enable Register for Sub Interrupt Controller 1"
|
|
bitfld.long 0x00 31. " USB_I2C_INT ,Interrupt from the USB I2C interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USB_DEV_HP_INT ,USB high priority interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USB_DEV_LP_INT ,USB low priority interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USB_DEV_DMA_INT ,USB DMA interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " USB_HOST_INT ,USB host interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " USB_OTG_ATX_INT_N ,External USB transceiver interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " USB_OTG_TIMER_INT ,USB timer interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SW_INT ,Software interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " KEY_IRQ ,Keyboard scanner interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TS_AUX ,Touch screen aux interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TS_IRQ(ADC_INT) ,Touch screen irq interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TS_P ,Touch screen pen down interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPI_28 ,Interrupt from the GPI_28 pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " JTAG_COMM_RX ,RX full interrupt from the JTAG Communication Channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JTAG_COMM_TX ,TX empty interrupt from the JTAG Communication Channel" "Disabled,Enabled"
|
|
line.long 0x04 "SIC1_RSR,Sub1 Raw Status Register"
|
|
eventfld.long 0x04 31. " USB_I2C_INT ,Interrupt from the USB I2C interface" "Inactive,Active"
|
|
eventfld.long 0x04 30. " USB_DEV_HP_INT ,USB high priority interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 29. " USB_DEV_LP_INT ,USB low priority interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 28. " USB_DEV_DMA_INT ,USB DMA interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 27. " USB_HOST_INT ,USB host interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 26. " USB_OTG_ATX_INT_N ,External USB transceiver interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 25. " USB_OTG_TIMER_INT ,USB timer interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 24. " SW_INT ,Software interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Inactive,Active"
|
|
eventfld.long 0x04 22. " KEY_IRQ ,Keyboard scanner interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Inactive,Active"
|
|
eventfld.long 0x04 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Inactive,Active"
|
|
eventfld.long 0x04 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Inactive,Active"
|
|
eventfld.long 0x04 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Inactive,Active"
|
|
eventfld.long 0x04 8. " TS_AUX ,Touch screen aux interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 7. " TS_IRQ(ADC_INT) ,Touch screen irq interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 6. " TS_P ,Touch screen pen down interrupt" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 4. " GPI_28 ,Interrupt from the GPI_28 pin" "Inactive,Active"
|
|
eventfld.long 0x04 2. " JTAG_COMM_RX ,RX full interrupt from the JTAG Communication Channel" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 1. " JTAG_COMM_TX ,TX empty interrupt from the JTAG Communication Channel" "Inactive,Active"
|
|
rgroup.long 0x04008++0xB
|
|
line.long 0x00 "SIC1_SR,Sub1 Status Register"
|
|
bitfld.long 0x00 31. " USB_I2C_INT ,Interrupt from the USB I2C interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " USB_DEV_HP_INT ,USB high priority interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USB_DEV_LP_INT ,USB low priority interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " USB_DEV_DMA_INT ,USB DMA interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " USB_HOST_INT ,USB host interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " USB_OTG_ATX_INT_N ,External USB transceiver interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " USB_OTG_TIMER_INT ,USB timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " SW_INT ,Software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SPI1_INT ,Interrupt from the SPI1 interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " KEY_IRQ ,Keyboard scanner interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI2_INT ,Interrupt from the SPI2 interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " TS_AUX ,Touch screen aux interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TS_IRQ(ADC_INT) ,Touch screen irq interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " TS_P ,Touch screen pen down interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPI_28 ,Interrupt from the GPI_28 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " JTAG_COMM_RX ,RX full interrupt from the JTAG Communication Channel" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JTAG_COMM_TX ,TX empty interrupt from the JTAG Communication Channel" "No interrupt,Interrupt"
|
|
group.long 0x0400C++0xB
|
|
line.long 0x00 "SIC1_APR,Sub1 Activation Polarity Register"
|
|
bitfld.long 0x00 31. " USB_I2C_INT ,Interrupt from the USB I2C interface" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 30. " USB_DEV_HP_INT ,USB high priority interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USB_DEV_LP_INT ,USB low priority interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 28. " USB_DEV_DMA_INT ,USB DMA interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 27. " USB_HOST_INT ,USB host interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 26. " USB_OTG_ATX_INT_N ,External USB transceiver interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 25. " USB_OTG_TIMER_INT ,USB timer interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 24. " SW_INT ,Software interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 22. " KEY_IRQ ,Keyboard scanner interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 8. " TS_AUX ,Touch screen aux interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TS_IRQ(ADC_INT) ,Touch screen irq interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 6. " TS_P ,Touch screen pen down interrupt" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPI_28 ,Interrupt from the GPI_28 pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 2. " JTAG_COMM_RX ,RX full interrupt from the JTAG Communication Channel" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JTAG_COMM_TX ,TX empty interrupt from the JTAG Communication Channel" "Low/Falling,High/Rising"
|
|
line.long 0x04 "SIC1_ATR,Sub1 Activation Type Register"
|
|
bitfld.long 0x04 31. " USB_I2C_INT ,Interrupt from the USB I2C interface" "Level,Edge"
|
|
bitfld.long 0x04 30. " USB_DEV_HP_INT ,USB high priority interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 29. " USB_DEV_LP_INT ,USB low priority interrupt" "Level,Edge"
|
|
bitfld.long 0x04 28. " USB_DEV_DMA_INT ,USB DMA interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 27. " USB_HOST_INT ,USB host interrupt" "Level,Edge"
|
|
bitfld.long 0x04 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 25. " USB_OTG_TIMER_INT ,USB timer interrupt" "Level,Edge"
|
|
bitfld.long 0x04 24. " SW_INT ,Software interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Level,Edge"
|
|
bitfld.long 0x04 22. " KEY_IRQ ,Keyboard scanner interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Level,Edge"
|
|
bitfld.long 0x04 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Level,Edge"
|
|
bitfld.long 0x04 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Level,Edge"
|
|
bitfld.long 0x04 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Level,Edge"
|
|
bitfld.long 0x04 8. " TS_AUX ,Touch screen aux interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TS_IRQ(ADC_INT) ,Touch screen irq interrupt" "Level,Edge"
|
|
bitfld.long 0x04 6. " TS_P ,Touch screen pen down interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GPI_28 ,Interrupt from the GPI_28 pin" "Level,Edge"
|
|
bitfld.long 0x04 2. " JTAG_COMM_RX ,RX full interrupt from the JTAG Communication Channel" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 1. " JTAG_COMM_TX ,TX empty interrupt from the JTAG Communication Channel" "Level,Edge"
|
|
line.long 0x08 "SIC1_ITR,Sub1 Interrupt Type Register"
|
|
bitfld.long 0x08 31. " USB_I2C_INT ,Interrupt from the USB I2C interface" "IRQ,FIQ"
|
|
bitfld.long 0x08 30. " USB_DEV_HP_INT ,USB high priority interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 29. " USB_DEV_LP_INT ,USB low priority interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 28. " USB_DEV_DMA_INT ,USB DMA interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 27. " USB_host_int ,USB host interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 25. " USB_OTG_TIMER_INT ,USB timer interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " SW_INT ,Software interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SPI1_INT ,Interrupt from the SPI1 interface" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " KEY_IRQ ,Keyboard scanner interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "IRQ,FIQ"
|
|
bitfld.long 0x08 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "IRQ,FIQ"
|
|
bitfld.long 0x08 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "IRQ,FIQ"
|
|
bitfld.long 0x08 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 12. " SPI2_INT ,Interrupt from the SPI2 interface" "IRQ,FIQ"
|
|
bitfld.long 0x08 8. " TS_AUX ,Touch screen aux interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 7. " TS_IRQ(ADC_INT) ,Touch screen irq interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 6. " TS_P ,Touch screen pen down interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 4. " GPI_28 ,Interrupt from the GPI_28 pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " JTAG_COMM_RX ,RX full interrupt from the JTAG Communication Channel" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 1. " JTAG_COMM_TX ,TX empty interrupt from the JTAG Communication Channel" "IRQ,FIQ"
|
|
tree.end
|
|
tree "Sub Interrupt Controller 2"
|
|
group.long 0x8000++0x7
|
|
line.long 0x00 "SIC2_ER,Interrupt Enable Register for Sub Interrupt Controller 2"
|
|
bitfld.long 0x00 31. " SYSCLKmux ,SYSCLK Mux interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " U5_RX ,Interrupt from the UART5 RX pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " GPI_19 ,Interrupt from the GPI_19 (U4_RX) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PN_GPIO ,ALL Port 0 and Port 1 GPIO pins OR'ed" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Disabled,Enabled"
|
|
line.long 0x04 "SIC2_RSR,Sub2 Raw Status Register"
|
|
eventfld.long 0x04 31. " SYSCLKMUX ,SYSCLK Mux interrupt" "Inactive,Active"
|
|
eventfld.long 0x04 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Inactive,Active"
|
|
eventfld.long 0x04 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Inactive,Active"
|
|
eventfld.long 0x04 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Inactive,Active"
|
|
eventfld.long 0x04 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Inactive,Active"
|
|
eventfld.long 0x04 19. " U5_RX ,Interrupt from the UART5 RX pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Inactive,Active"
|
|
eventfld.long 0x04 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Inactive,Active"
|
|
eventfld.long 0x04 11. " GPI_19 ,Interrupt from the GPI_19 (U4_RX) pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Inactive,Active"
|
|
eventfld.long 0x04 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 8. " PN_GPIO ,ALL Port 0 and Port 1 GPIO pins OR'ed" "Inactive,Active"
|
|
eventfld.long 0x04 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Inactive,Active"
|
|
eventfld.long 0x04 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Inactive,Active"
|
|
eventfld.long 0x04 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Inactive,Active"
|
|
eventfld.long 0x04 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Inactive,Active"
|
|
rgroup.long 0x8008++0x3
|
|
line.long 0x00 "SIC2_SR,Sub2 Status Register"
|
|
bitfld.long 0x00 31. " SYSCLKMUX ,SYSCLK Mux interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " GPI_05 ,Interrupt from the GPI_05 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPI_03 ,Interrupt from the GPI_03 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " GPI_02 ,Interrupt from the GPI_02 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " GPI_00 ,Interrupt from the GPI_00 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " U5_RX ,Interrupt from the UART5 RX pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " GPI_07 ,Interrupt from the GPI_07 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " GPI_19 ,Interrupt from the GPI_19 (U4_RX) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PN_GPIO ,ALL Port 0 and Port 1 GPIO pins OR'ed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "No interrupt,Interrupt"
|
|
group.long 0x800C++0xB
|
|
line.long 0x00 "SIC2_APR,Sub2 Activation Polarity Register"
|
|
bitfld.long 0x00 31. " SYSCLKMUX ,SYSCLK Mux interrupt" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 19. " U5_RX ,Interrupt from the UART5 RX pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 11. " GPI_19 ,Interrupt from the GPI_19 (U4_RX) pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PN_GPIO ,ALL Port 0 and Port 1 GPIO pins OR'ed" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Low/Falling,High/Rising"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Low/Falling,High/Rising"
|
|
line.long 0x04 "SIC2_ATR,Sub2 Activation Type Register"
|
|
bitfld.long 0x04 31. " SYSCLKMUX ,SYSCLK Mux interrupt" "Level,Edge"
|
|
bitfld.long 0x04 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Level,Edge"
|
|
bitfld.long 0x04 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Level,Edge"
|
|
bitfld.long 0x04 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Level,Edge"
|
|
bitfld.long 0x04 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Level,Edge"
|
|
bitfld.long 0x04 19. " U5_RX ,Interrupt from the UART5 RX pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Level,Edge"
|
|
bitfld.long 0x04 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Level,Edge"
|
|
bitfld.long 0x04 11. " GPI_19 ,Interrupt from the GPI_19 (U4_RX) pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Level,Edge"
|
|
bitfld.long 0x04 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PN_GPIO ,ALL Port 0 and Port 1 GPIO pins OR'ed" "Level,Edge"
|
|
bitfld.long 0x04 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Level,Edge"
|
|
bitfld.long 0x04 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Level,Edge"
|
|
bitfld.long 0x04 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Level,Edge"
|
|
bitfld.long 0x04 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x04 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Level,Edge"
|
|
line.long 0x08 "SIC2_ITR,Sub2 Interrupt Type Register"
|
|
bitfld.long 0x08 31. " SYSCLKMUX ,SYSCLK Mux interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 27. " GPI_05 ,Interrupt from the GPI_05 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 25. " GPI_03 ,Interrupt from the GPI_03 pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " GPI_02 ,Interrupt from the GPI_02 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " GPI_00 ,Interrupt from the GPI_00 pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 19. " U5_RX ,Interrupt from the UART5 RX pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "FIQ,IRQ"
|
|
bitfld.long 0x08 15. " GPI_07 ,Interrupt from the GPI_07 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 11. " GPI_19 ,Interrupt from the GPI_19 (U4_RX) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 8. " PN_GPIO ,ALL Port 0 and Port 1 GPIO pins OR'ed" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "IRQ,FIQ"
|
|
bitfld.long 0x08 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "IRQ,FIQ"
|
|
tree.end
|
|
base ad:0x400040A8
|
|
textline " "
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "SW_INT,Software Interrupt Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. " PASSPARAM ,Parameter to the interrupt service routine"
|
|
bitfld.long 0x00 0. " SW_INT ,Software interrupt source" "Inactive,Active"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "GPDMA (General Purpose DMA)"
|
|
tree "General DMA Registers"
|
|
base ad:0x31000000
|
|
width 19.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x0 "DMACIntStat,DMA Interrupt Status Register"
|
|
bitfld.long 0x0 7. " IntStat7 ,DMA channel 7 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 6. " IntStat6 ,DMA channel 6 interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntStat5 ,DMA channel 5 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 4. " IntStat4 ,DMA channel 4 interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntStat3 ,DMA channel 3 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 2. " IntStat2 ,DMA channel 2 interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntStat1 ,DMA channel 1 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 0. " IntStat0 ,DMA channel 0 interrupt" "Inactive,Active"
|
|
line.long 0x4 "DMACIntTCStat,DMA Interrupt Terminal Count Request Status Register"
|
|
bitfld.long 0x4 7. " IntTCStat7 ,DMA channel 7 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 6. " IntTCStat6 ,DMA channel 6 terminal count interrupt request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x4 5. " IntTCStat5 ,DMA channel 5 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 4. " IntTCStat4 ,DMA channel 4 terminal count interrupt request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x4 3. " IntTCStat3 ,DMA channel 3 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 2. " IntTCStat2 ,DMA channel 2 terminal count interrupt request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x4 1. " IntTCStat1 ,DMA channel 1 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 0. " IntTCStat0 ,DMA channel 0 terminal count interrupt request" "Inactive,Active"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x0 "DMACIntTCClear,DMA Interrupt Terminal Count Request Clear Register"
|
|
bitfld.long 0x0 7. " IntTCClear7 ,DMA channel 7 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 6. " IntTCClear6 ,DMA channel 6 terminal count interrupt request clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntTCClear5 ,DMA channel 5 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 4. " IntTCClear4 ,DMA channel 4 terminal count interrupt request clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntTCClear3 ,DMA channel 3 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 2. " IntTCClear2 ,DMA channel 2 terminal count interrupt request clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntTCClear1 ,DMA channel 1 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " IntTCClear0 ,DMA channel 0 terminal count interrupt request clear" "No effect,Clear"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "DMACIntErrStat,DMA Interrupt Error Status Register"
|
|
bitfld.long 0x0 7. " IntErrStat7 ,DMA channel 7 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 6. " IntErrStat6 ,DMA channel 6 interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntErrStat5 ,DMA channel 5 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 4. " IntErrStat4 ,DMA channel 4 interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntErrStat3 ,DMA channel 3 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 2. " IntErrStat2 ,DMA channel 2 interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntErrStat1 ,DMA channel 1 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 0. " IntErrStat0 ,DMA channel 0 interrupt error status" "No error,Error"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "DMACIntErrClr,DMA Interrupt Error Clear Register"
|
|
bitfld.long 0x0 7. " IntErrClr7 ,DMA channel 7 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 6. " IntErrClr6 ,DMA channel 6 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntErrClr5 ,DMA channel 5 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 4. " IntErrClr4 ,DMA channel 4 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntErrClr3 ,DMA channel 3 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 2. " IntErrClr2 ,DMA channel 2 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntErrClr1 ,DMA channel 1 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " IntErrClr0 ,DMA channel 0 interrupt error clear" "No effect,Clear"
|
|
rgroup.long 0x14++0xB
|
|
line.long 0x0 "DMACRawIntTCStat,DMA Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x0 7. " RawIntTCStat7 ,DMA channel 7 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " RawIntTCStat6 ,DMA channel 6 terminal count interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RawIntTCStat5 ,DMA channel 5 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " RawIntTCStat4 ,DMA channel 4 terminal count interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RawIntTCStat3 ,DMA channel 3 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " RawIntTCStat2 ,DMA channel 2 terminal count interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RawIntTCStat1 ,DMA channel 1 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " RawIntTCStat0 ,DMA channel 0 terminal count interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x4 "DMACRawIntErrStat,DMA Raw Error Interrupt Status Register"
|
|
bitfld.long 0x4 7. " RawIntErrStat7 ,DMA channel 7 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 6. " RawIntErrStat6 ,DMA channel 6 raw interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RawIntErrStat5 ,DMA channel 5 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 4. " RawIntErrStat4 ,DMA channel 4 raw interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 3. " RawIntErrStat3 ,DMA channel 3 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 2. " RawIntErrStat2 ,DMA channel 2 raw interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 1. " RawIntErrStat1 ,DMA channel 1 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 0. " RawIntErrStat0 ,DMA channel 0 raw interrupt error status" "No error,Error"
|
|
line.long 0x8 "DMACEnbldChns,DMA Enabled Channel Register"
|
|
bitfld.long 0x8 7. " Channel7En ,DMA channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " Channel6En ,DMA channel 6 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 5. " Channel5En ,DMA channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 4. " Channel4En ,DMA channel 4 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 3. " Channel3En ,DMA channel 3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " Channel2En ,DMA channel 2 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " Channel1En ,DMA channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " Channel0En ,DMA channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "DMACSoftBReq,DMA Software Burst Request Register"
|
|
bitfld.long 0x0 15. " SoftBReq15 ,DMA burst request for line 15" "No effect,Requested"
|
|
bitfld.long 0x0 14. " SoftBReq14 ,DMA burst request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SoftBReq13 ,DMA burst request for line 13" "No effect,Requested"
|
|
bitfld.long 0x0 12. " SoftBReq12 ,DMA burst request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SoftBReq11 ,DMA burst request for line 11" "No effect,Requested"
|
|
bitfld.long 0x0 10. " SoftBReq10 ,DMA burst request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SoftBReq9 ,DMA burst request for line 9" "No effect,Requested"
|
|
bitfld.long 0x0 8. " SoftBReq8 ,DMA burst request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 7. " SoftBReq7 ,DMA burst request for line 7" "No effect,Requested"
|
|
bitfld.long 0x0 6. " SoftBReq6 ,DMA burst request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SoftBReq5 ,DMA burst request for line 5" "No effect,Requested"
|
|
bitfld.long 0x0 4. " SoftBReq4 ,DMA burst request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SoftBReq3 ,DMA burst request for line 3" "No effect,Requested"
|
|
bitfld.long 0x0 2. " SoftBReq2 ,DMA burst request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SoftBReq1 ,DMA burst request for line 1" "No effect,Requested"
|
|
bitfld.long 0x0 0. " SoftBReq0 ,DMA burst request for line 0" "No effect,Requested"
|
|
line.long 0x4 "DMACSoftSReq,DMA Software Single Request Register"
|
|
bitfld.long 0x4 15. " SoftSReq15 ,DMA single transfer request for line 15" "No effect,Requested"
|
|
bitfld.long 0x4 14. " SoftSReq14 ,DMA single transfer request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 13. " SoftSReq13 ,DMA single transfer request for line 13" "No effect,Requested"
|
|
bitfld.long 0x4 12. " SoftSReq12 ,DMA single transfer request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 11. " SoftSReq11 ,DMA single transfer request for line 11" "No effect,Requested"
|
|
bitfld.long 0x4 10. " SoftSReq10 ,DMA single transfer request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 9. " SoftSReq9 ,DMA single transfer request for line 9" "No effect,Requested"
|
|
bitfld.long 0x4 8. " SoftSReq8 ,DMA single transfer request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 7. " SoftSReq7 ,DMA single transfer request for line 7" "No effect,Requested"
|
|
bitfld.long 0x4 6. " SoftSReq6 ,DMA single transfer request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SoftSReq5 ,DMA single transfer request for line 5" "No effect,Requested"
|
|
bitfld.long 0x4 4. " SoftSReq4 ,DMA single transfer request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 3. " SoftSReq3 ,DMA single transfer request for line 3" "No effect,Requested"
|
|
bitfld.long 0x4 2. " SoftSReq2 ,DMA single transfer request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 1. " SoftSReq1 ,DMA single transfer request for line 1" "No effect,Requested"
|
|
bitfld.long 0x4 0. " SoftSReq0 ,DMA single transfer request for line 0" "No effect,Requested"
|
|
line.long 0x8 "DMACSoftLBReq,DMA Software Last Burst Requested Register"
|
|
bitfld.long 0x8 15. " SoftLBReq15 ,DMA last burst request for line 15" "No effect,Requested"
|
|
bitfld.long 0x8 14. " SoftLBReq14 ,DMA last burst request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 13. " SoftLBReq13 ,DMA last burst request for line 13" "No effect,Requested"
|
|
bitfld.long 0x8 12. " SoftLBReq12 ,DMA last burst request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 11. " SoftLBReq11 ,DMA last burst request for line 11" "No effect,Requested"
|
|
bitfld.long 0x8 10. " SoftLBReq10 ,DMA last burst request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 9. " SoftLBReq9 ,DMA last burst request for line 9" "No effect,Requested"
|
|
bitfld.long 0x8 8. " SoftLBReq8 ,DMA last burst request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 7. " SoftLBReq7 ,DMA last burst request for line 7" "No effect,Requested"
|
|
bitfld.long 0x8 6. " SoftLBReq6 ,DMA last burst request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 5. " SoftLBReq5 ,DMA last burst request for line 5" "No effect,Requested"
|
|
bitfld.long 0x8 4. " SoftLBReq4 ,DMA last burst request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 3. " SoftLBReq3 ,DMA last burst request for line 3" "No effect,Requested"
|
|
bitfld.long 0x8 2. " SoftLBReq2 ,DMA last burst request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 1. " SoftLBReq1 ,DMA last burst request for line 1" "No effect,Requested"
|
|
bitfld.long 0x8 0. " SoftLBReq0 ,DMA last burst request for line 0" "No effect,Requested"
|
|
line.long 0xC "DMACSoftLSReq,DMA Software Last Single Requested Register"
|
|
bitfld.long 0xC 15. " SoftLSReq15 ,DMA last single transfer request for line 15" "No effect,Requested"
|
|
bitfld.long 0xC 14. " SoftLSReq14 ,DMA last single transfer request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 13. " SoftLSReq13 ,DMA last single transfer request for line 13" "No effect,Requested"
|
|
bitfld.long 0xC 12. " SoftLSReq12 ,DMA last single transfer request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 11. " SoftLSReq11 ,DMA last single transfer request for line 11" "No effect,Requested"
|
|
bitfld.long 0xC 10. " SoftLSReq10 ,DMA last single transfer request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 9. " SoftLSReq9 ,DMA last single transfer request for line 9" "No effect,Requested"
|
|
bitfld.long 0xC 8. " SoftLSReq8 ,DMA last single transfer request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 7. " SoftLSReq7 ,DMA last single transfer request for line 7" "No effect,Requested"
|
|
bitfld.long 0xC 6. " SoftLSReq6 ,DMA last single transfer request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 5. " SoftLSReq5 ,DMA last single transfer request for line 5" "No effect,Requested"
|
|
bitfld.long 0xC 4. " SoftLSReq4 ,DMA last single transfer request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 3. " SoftLSReq3 ,DMA last single transfer request for line 3" "No effect,Requested"
|
|
bitfld.long 0xC 2. " SoftLSReq2 ,DMA last single transfer request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 1. " SoftLSReq1 ,DMA last single transfer request for line 1" "No effect,Requested"
|
|
bitfld.long 0xC 0. " SoftLSReq0 ,DMA last single transfer request for line 0" "No effect,Requested"
|
|
line.long 0x10 "DMACConfig,DMA Configuration Register"
|
|
bitfld.long 0x10 2. " M1 ,AHB Master 1 endianness configuration" "Little-endian,Big-endian"
|
|
bitfld.long 0x10 1. " M0 ,AHB Master 0 endianness configuration" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,DMA controller enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 0"
|
|
base ad:0x31000100
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC0SrcAddr,DMA Channel 0 Source Address Register"
|
|
line.long 0x4 "DMACC0DestAddr,DMA Channel 0 Destination Address Register"
|
|
line.long 0x8 "DMACC0LLI,DMA Channel 0 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC0Control,DMA channel 0 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC0Config,Channel 0 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x31000120
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC1SrcAddr,DMA Channel 1 Source Address Register"
|
|
line.long 0x4 "DMACC1DestAddr,DMA Channel 1 Destination Address Register"
|
|
line.long 0x8 "DMACC1LLI,DMA Channel 1 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC1Control,DMA channel 1 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC1Config,Channel 1 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x31000140
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC2SrcAddr,DMA Channel 2 Source Address Register"
|
|
line.long 0x4 "DMACC2DestAddr,DMA Channel 2 Destination Address Register"
|
|
line.long 0x8 "DMACC2LLI,DMA Channel 2 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC2Control,DMA channel 2 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC2Config,Channel 2 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0x31000160
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC3SrcAddr,DMA Channel 3 Source Address Register"
|
|
line.long 0x4 "DMACC3DestAddr,DMA Channel 3 Destination Address Register"
|
|
line.long 0x8 "DMACC3LLI,DMA Channel 3 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC3Control,DMA channel 3 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC3Config,Channel 3 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0x31000180
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC4SrcAddr,DMA Channel 4 Source Address Register"
|
|
line.long 0x4 "DMACC4DestAddr,DMA Channel 4 Destination Address Register"
|
|
line.long 0x8 "DMACC4LLI,DMA Channel 4 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC4Control,DMA channel 4 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC4Config,Channel 4 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0x310001A0
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC5SrcAddr,DMA Channel 5 Source Address Register"
|
|
line.long 0x4 "DMACC5DestAddr,DMA Channel 5 Destination Address Register"
|
|
line.long 0x8 "DMACC5LLI,DMA Channel 5 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC5Control,DMA channel 5 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC5Config,Channel 5 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0x310001C0
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC6SrcAddr,DMA Channel 6 Source Address Register"
|
|
line.long 0x4 "DMACC6DestAddr,DMA Channel 6 Destination Address Register"
|
|
line.long 0x8 "DMACC6LLI,DMA Channel 6 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC6Control,DMA channel 6 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC6Config,Channel 6 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0x310001E0
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC7SrcAddr,DMA Channel 7 Source Address Register"
|
|
line.long 0x4 "DMACC7DestAddr,DMA Channel 7 Destination Address Register"
|
|
line.long 0x8 "DMACC7LLI,DMA Channel 7 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC7Control,DMA channel 7 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC7Config,Channel 7 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripheral/Memory to peripheral,Peripheral/Peripheral to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripheral ,Destination peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripheral ,Source peripheral" "I2S0 DMA0,NAND Flash,I2S1 DMA0,SPI2 Rx/SSP1 Rx,SD Card Rx Tx,Uart1 Tx,Uart1 Rx,Uart2 Tx,Uart2 Rx,Uart7 Tx,Uart7 Rx/I2S1 DMA1,SPI1 Rx Tx/SSP1 Tx,NAND Flash,I2S0 DMA1,Reserved/SSP0 Rx,Reserved/SSP0 Tx,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "EMC (External Memory Controller)"
|
|
base ad:0x40004000
|
|
width 23.
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SDRAMCLK_CTRL,SDRAM Clock Control Register"
|
|
bitfld.long 0x0 22. " SDRAM_PIN_SPEED3 ,Slew rate of the pin SDRAM pin RAM_CLK" "Fast,Slower"
|
|
textline " "
|
|
bitfld.long 0x0 21. " SDRAM_PIN_SPEED2 ,Slew rate of the pin SDRAM pads EMC_A[14:0].RAM_CKE.RAM_CS_N.RAM_RAS_N.RAM_CAS_N.RAM_WR_N." "Fast,Slower"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SDRAM_PIN_SPEED1 ,Slew rate of the pin SDRAM pads RAM_D[31:0] and RAM_DQM[3:0]" "Fast,Slower"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SW_DDR_RESET ,SDRAM controller reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 14.--18. " COMMAND_DELAY ,Delay command, data and address signals to SDRAM relative to EMC_CLK" "0 ns,0.25 ns,0.5 ns,0.75 ns,1 ns,1.25 ns,1.5 ns,1.75 ns,2 ns,2.25 ns,2.5 ns,2.75 ns,3 ns,3.25 ns,3.5 ns,3.75 ns,4 ns,4.25 ns,4.5 ns,4.75 ns,5 ns,5.25 ns,5.5 ns,5.75 ns,6 ns,6.25 ns,6.5 ns,6.75 ns,7 ns,7.25 ns,7.5 ns,7.75 ns"
|
|
textline " "
|
|
bitfld.long 0x0 13. " DCIRCSTAT ,Delay circuitry Adder status" "No under/overflow,Under/overflow"
|
|
textline " "
|
|
bitfld.long 0x0 10.--12. " SENSFACTOR ,Sensitivity Factor for DDR SDRAM calibration" "No shift right,Shift right with 1,Shift right with 2,Shift right with 3,Shift right with 4,Shift right with 5,Shift right with 6,Shift right with 7"
|
|
textline " "
|
|
bitfld.long 0x0 9. " CAL_DELAY , Delay settings for DDR SDRAM" "Un-calibrated,Calibrated"
|
|
textline " "
|
|
bitfld.long 0x0 8. " SW_DDR_CAL ,Manual DDR delay calibration" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x0 7. " RTC_TICK_EN ,Automatic DDR delay calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2.--6. " DDR_DQSIN_DELAY ,Delay of the DQS input from the DDR SDRAM device" "No delay,0.25 ns,0.50 ns,0.75 ns,1 ns,1.25 ns,1.5 ns,1.75 ns,2 ns,2.25 ns,2.5 ns,2.75 ns,3 ns,3.25 ns,3.5 ns,3.75 ns,4 ns,4.25 ns,4.5 ns,4.75 ns,5 ns,5.25 ns,5.5 ns,5.75 ns,6 ns,6.25 ns,6.5 ns,6.75 ns,7 ns,7.25 ns,7.5 ns,7.75 ns"
|
|
textline " "
|
|
bitfld.long 0x0 1. " DDR_SEL ,SRD or DDR selection" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x0 0. " SDRAMCLK ,SDRAM HCLK and Inverted HCLK Control" "Enabled,Disabled"
|
|
base ad:0x31080000
|
|
group.long 0x000++0x03
|
|
line.long 0x00 "EMCCONTROL,EMC Control Register"
|
|
bitfld.long 0x00 2. " L ,Low Power Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E ,EMC enable" "Disabled,Enabled"
|
|
rgroup.long 0x004++0x03
|
|
line.long 0x00 "EMCSTATUS,EMC Status Register"
|
|
bitfld.long 0x00 2. " SA ,Self-Refresh mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " B ,EMC busy" "Idle,Busy"
|
|
group.long 0x008++0x03
|
|
line.long 0x00 "EMCCONFIG,EMC Configuration Register"
|
|
bitfld.long 0x00 0. " N ,Endian mode" "Little-endian,Big-endian"
|
|
group.long 0x020++0x0B
|
|
line.long 0x00 "EMCDYNAMICCONTROL,Dynamic Control Register"
|
|
bitfld.long 0x00 13. " DP ,SDRAM deep power down mode" "Normal,Power Down"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " SDRAMIn ,SDRAM initialization code command" "NORMAL,MODE,PALL,NOP"
|
|
bitfld.long 0x00 5. " MMC ,Memory clock EMC_CLK control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IMCC ,Inverted Memory Clock Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " SRMCC ,Self-Refresh Clock Control" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SR ,Self-refresh Request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " CS ,Dynamic memory clock control" "Stop when Idle,Always running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CE ,Dynamic memory clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "EMCDYNAMICREFRESH,Dynamic Memory Refresh Timer Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " REFRESH ,Refresh timer"
|
|
line.long 0x08 "EMCDYNAMICREADCONFIG,Dynamic Memory Read Configuration Register"
|
|
bitfld.long 0x08 12. " DDR_DRP ,DDR SDRAM read data capture polarity" "Negative edge,Positive edge"
|
|
bitfld.long 0x08 8.--9. " DDR_DRD ,DDR SDRAM read data strategy" "Reserved,COMMAND_DELAY,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4. " SDR_SRP ,SDR SDRAM read data capture polarity" "Negative edge,Positive edge"
|
|
bitfld.long 0x08 0.--1. " SDR_SRD ,SDR SDRAM read data strategy" "Reserved,COMMAND_DELAY,?..."
|
|
group.long 0x030++0x2B
|
|
line.long 0x00 "EMCDYNAMICTRP,Dynamic Memory Percentage Command Period Register"
|
|
bitfld.long 0x00 0.--3. " TRP ,Precharge Command Period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x04 "EMCDYNAMICTRAS,Dynamic Memory Active to Precharge Command Period Register"
|
|
bitfld.long 0x04 0.--3. " TRAS ,Active-to-Precharge Command Period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x08 "EMCDYNAMICTSREX,Dynamic Memory Self-refresh Exit Time Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " TSREX ,Self-refresh exit time"
|
|
group.long 0x44++0x1B
|
|
line.long 0x00 "EMCDYNAMICTWR,Dynamic Memory Write Recovery Time Register"
|
|
bitfld.long 0x00 0.--3. " TWR ,Write recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x04 "EMCDYNAMICTRC,Dynamic Memory Active to Active Command Period Register"
|
|
bitfld.long 0x04 0.--4. " TRC ,Active to active command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
line.long 0x08 "EMCDYNAMICTRFC,Dynamic Memory Auto-refresh Period Register"
|
|
bitfld.long 0x08 0.--4. " TRFC ,Auto-refresh period and auto-refresh to active command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
line.long 0x0C "EMCDYNAMICTXSR,Dynamic Memory Exit Self-refresh Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TXSR ,Exit self-refresh to active command time"
|
|
line.long 0x10 "EMCDYNAMICTRRD,Dynamic Memory Active Bank A to Active Bank B Time Register"
|
|
bitfld.long 0x10 0.--3. " TRRD ,Active bank A to active bank B latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x14 "EMCDYNAMICTMRD,Dynamic Memory Load Mode Register to Active Command Time"
|
|
bitfld.long 0x14 0.--3. " TMRD ,Load mode register to active command time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x18 "EMCDYNAMICCDLR,Dynamic Memory Last Data In to Read Command Time"
|
|
bitfld.long 0x18 0.--3. " tCDLR , Last data in to read command time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x080++0x03
|
|
line.long 0x00 "EMCSTATICEXTENDEDWAIT,Static Memory Extended Wait Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " EXTENDEDWAIT ,Extended wait time out"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "EMCDYNAMICCONFIG0,Dynamic Memory Configuration Register"
|
|
bitfld.long 0x00 20. " P ,Memory write protect" "Not protected,Protected"
|
|
hexmask.long.byte 0x00 7.--14. 1. " AM ,Address mapping"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MD ,Memory device" "SDR SDRAM,Reserved,Low power SDR,Reserved,DDR SDRAM,Reserved,Low power DDR,?..."
|
|
line.long 0x04 "EMCDYNAMICRASCAS0,Dynamic Memory RAS/CAS Delay Register"
|
|
bitfld.long 0x04 7.--10. " CAS ,CAS latency" "Reserved,0.5 cycle,1 cycle,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles"
|
|
bitfld.long 0x04 0.--3. " RAS ,RAS latency (active to read/write delay)" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x120++0x7
|
|
line.long 0x00 "EMCDYNAMICCONFIG1,Dynamic Memory Configuration Register"
|
|
bitfld.long 0x00 20. " P ,Memory write protect" "Not protected,Protected"
|
|
hexmask.long.byte 0x00 7.--14. 1. " AM ,Address mapping"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MD ,Memory device" "SDR SDRAM,Reserved,Low power SDR,Reserved,DDR SDRAM,Reserved,Low power DDR,?..."
|
|
line.long 0x04 "EMCDYNAMICRASCAS1,Dynamic Memory RAS/CAS Delay Register"
|
|
bitfld.long 0x04 7.--10. " CAS ,CAS latency" "Reserved,0.5 cycle,1 cycle,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles"
|
|
bitfld.long 0x04 0.--3. " RAS ,RAS latency (active to read/write delay)" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "EMCSTATICCONFIG0,Static Memory Configuration Register 0"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " EW ,Static Extended Wait" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "Read-High/Write-Low,Read-Low/Write-Low"
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory Width" "8 bits,16 bits,32bit,?..."
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "EMCSTATICCONFIG1,Static Memory Configuration Register 1"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " EW ,Static Extended Wait" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "Read-High/Write-Low,Read-Low/Write-Low"
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory Width" "8 bits,16 bits,32bit,?..."
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "EMCSTATICCONFIG2,Static Memory Configuration Register 2"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " EW ,Static Extended Wait" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "Read-High/Write-Low,Read-Low/Write-Low"
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory Width" "8 bits,16 bits,32bit,?..."
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "EMCSTATICCONFIG3,Static Memory Configuration Register 3"
|
|
bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " EW ,Static Extended Wait" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PB ,Byte lane state" "Read-High/Write-Low,Read-Low/Write-Low"
|
|
bitfld.long 0x00 6. " PC ,Chip select polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " MW ,Memory Width" "8 bits,16 bits,32bit,?..."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "EMCSTATICWAITWEN0,Static Memory Write Enable Delay Register 0"
|
|
bitfld.long 0x00 0.--3. " WAITWEN ,Delay from chip select assertion to write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "EMCSTATICWAITWEN1,Static Memory Write Enable Delay Register 1"
|
|
bitfld.long 0x00 0.--3. " WAITWEN ,Delay from chip select assertion to write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "EMCSTATICWAITWEN2,Static Memory Write Enable Delay Register 2"
|
|
bitfld.long 0x00 0.--3. " WAITWEN ,Delay from chip select assertion to write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "EMCSTATICWAITWEN3,Static Memory Write Enable Delay Register 3"
|
|
bitfld.long 0x00 0.--3. " WAITWEN ,Delay from chip select assertion to write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "EMCSTATICWAITOEN0,Static Memory Output Enable Delay Registers"
|
|
bitfld.long 0x00 0.--3. " WAITOEN ,Delay from chip select assertion to output enable" "No dealay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "EMCSTATICWAITOEN1,Static Memory Output Enable Delay Registers"
|
|
bitfld.long 0x00 0.--3. " WAITOEN ,Delay from chip select assertion to output enable" "No dealay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "EMCSTATICWAITOEN2,Static Memory Output Enable Delay Registers"
|
|
bitfld.long 0x00 0.--3. " WAITOEN ,Delay from chip select assertion to output enable" "No dealay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "EMCSTATICWAITOEN3,Static Memory Output Enable Delay Registers"
|
|
bitfld.long 0x00 0.--3. " WAITOEN ,Delay from chip select assertion to output enable" "No dealay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "EMCSTATICWAITRD0,Static Memory Read Delay Registers 0"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "EMCSTATICWAITRD1,Static Memory Read Delay Registers 1"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "EMCSTATICWAITRD2,Static Memory Read Delay Registers 2"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "EMCSTATICWAITRD3,Static Memory Read Delay Registers 3"
|
|
bitfld.long 0x00 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "EMCSTATICWAITPAGE0,Static Memory Page Mode Read Delay Registers 0"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "EMCSTATICWAITPAGE1,Static Memory Page Mode Read Delay Registers 1"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "EMCSTATICWAITPAGE2,Static Memory Page Mode Read Delay Registers 2"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "EMCSTATICWAITPAGE3,Static Memory Page Mode Read Delay Registers 3"
|
|
bitfld.long 0x00 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "EMCSTATICWAITWR0,Static Memory Write Delay Registers 0"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "EMCSTATICWAITWR1,Static Memory Write Delay Registers 1"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "EMCSTATICWAITWR2,Static Memory Write Delay Registers 2"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "EMCSTATICWAITWR3,Static Memory Write Delay Registers 3"
|
|
bitfld.long 0x00 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "EMCSTATICWAITTURN0,Static Memory Turnaound Delay Registers 0"
|
|
bitfld.long 0x00 0.--3. " WAITTURN ,Bus turnaround cycles in AHB HCLK cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "EMCSTATICWAITTURN1,Static Memory Turnaound Delay Registers 1"
|
|
bitfld.long 0x00 0.--3. " WAITTURN ,Bus turnaround cycles in AHB HCLK cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "EMCSTATICWAITTURN2,Static Memory Turnaound Delay Registers 2"
|
|
bitfld.long 0x00 0.--3. " WAITTURN ,Bus turnaround cycles in AHB HCLK cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "EMCSTATICWAITTURN3,Static Memory Turnaound Delay Registers 3"
|
|
bitfld.long 0x00 0.--3. " WAITTURN ,Bus turnaround cycles in AHB HCLK cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "EMCAHBCONTROL0,EMC AHB Control Register"
|
|
bitfld.long 0x00 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
group.long 0x460++0x3
|
|
line.long 0x00 "EMCAHBCONTROL3,EMC AHB Control Register"
|
|
bitfld.long 0x00 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
group.long 0x480++0x3
|
|
line.long 0x00 "EMCAHBCONTROL4,EMC AHB Control Register"
|
|
bitfld.long 0x00 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x00 "EMCAHBSTATUS0,EMC AHB Status Register"
|
|
bitfld.long 0x00 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
rgroup.long 0x464++0x3
|
|
line.long 0x00 "EMCAHBSTATUS3,EMC AHB Status Register"
|
|
bitfld.long 0x00 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
rgroup.long 0x484++0x3
|
|
line.long 0x00 "EMCAHBSTATUS4,EMC AHB Status Register"
|
|
bitfld.long 0x00 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
group.long 0x408++0x3
|
|
line.long 0x00 "EMCAHBSTATUS0,EMC AHB Status Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
group.long 0x468++0x3
|
|
line.long 0x00 "EMCAHBSTATUS3,EMC AHB Status Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
group.long 0x488++0x3
|
|
line.long 0x00 "EMCAHBSTATUS4,EMC AHB Status Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
base ad:0x40004000
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DDR_LAP_NOM,DDR Calibration Nominal Value"
|
|
rgroup.long 0x70++0x7
|
|
line.long 0x0 "DDR_LAP_COUNT,DDR Calibration Measured Value"
|
|
line.long 0x4 "DDR_CAL_DELAY,DDR Calibration Delay Value"
|
|
hexmask.long.byte 0x4 0.--4. 1. " CurrentCalDel ,Current calibrated delay setting"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ML FLASH (Multi-Level NAND Flash Controller)"
|
|
base ad:0x200B8000
|
|
width 22.
|
|
wgroup.long 0x00++0x2F
|
|
line.long 0x0 "MLC_CMD,MLC NAND flash Command register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CmdCode ,Command Code"
|
|
line.long 0x4 "MLC_ADDR,MLC NAND flash Address register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " Address ,Flash address"
|
|
line.long 0x8 "MLC_ECC_ENC_REG,MLC NAND ECC Encode Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " Start ,Write to start data encode cycle"
|
|
line.long 0xC "MLC_ECC_DEC_REG,MLC NAND ECC Decode Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. " Start ,Write to start data encode cycle"
|
|
line.long 0x10 "MLC_ECC_AUTO_ENC_REG,MLC NAND ECC Auto Encode Register"
|
|
bitfld.long 0x10 8. " APrCmdEn ,Auto-program command enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 0.--7. 1. " AProgCmd ,Auto-program command"
|
|
line.long 0x14 "MLC_ECC_AUTO_DEC_REG,MLC NAND ECC Auto Decode Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " Start ,Write to start automatic decode cycle"
|
|
line.long 0x18 "MLC_RPR,MLC NAND Read Parity Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " Force ,Write to force the controller to read 10 byte parity data"
|
|
line.long 0x1C "MLC_WPR,MLC NAND Write Parity Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " Force ,Write to force the controller to write 10 byte parity data"
|
|
line.long 0x20 "MLC_RUBP,MLC NAND Reset User Buffer Pointer Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " Force ,Write to force the serial Data Buffer pointer to the start of the user data region"
|
|
line.long 0x24 "MLC_ROBP,MLC NAND Reset Overhead Buffer Pointer Register"
|
|
bitfld.long 0x24 0. " Force ,Force the serial Data Buffer pointer to start of the overhead data region" "Forced,Forced"
|
|
line.long 0x28 "MLC_SW_WP_ADD_LOW,MLC NAND Software Write Protection Address Low Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " LoBound ,The lower bound for the write protected area"
|
|
line.long 0x2C "MLC_SW_WP_ADD_HIG,MLC NAND Software Write Protection Address High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " HiBound ,The upper bound for the write protected area"
|
|
if ((d.l(ad:0x200B8000+0x30)&0x4)==0x4)
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x00 "MLC_ICR,MLC NAND Controller Configuration Register"
|
|
bitfld.long 0x00 3. " SWWrProt ,Software Write protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BlockSiz ,Size of block flash device" "Small,Large"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AddrCnt ,NAND flash address word count" "4,5"
|
|
bitfld.long 0x00 0. " BusWidth ,NAND flash I/O bus with" "8-bit,16-bit"
|
|
else
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x00 "MLC_ICR,MLC NAND Controller Configuration Register"
|
|
bitfld.long 0x00 3. " SWWrProt ,Software Write protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BlockSiz ,Size of block flash device" "Small,Large"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AddrCnt ,NAND flash address word count" "3,4"
|
|
bitfld.long 0x00 0. " BusWidth ,NAND flash I/O bus with" "8-bit,16-bit"
|
|
endif
|
|
wgroup.long 0x34++0x7
|
|
line.long 0x00 "MLC_TIME_REG,MLC NAND Timing Register"
|
|
bitfld.long 0x00 24.--25. " TCEA_DELAY ,nCE low to dout valid (tCEA)" "0,1,2,3"
|
|
bitfld.long 0x00 19.--23. " BUSY_DELAY ,Read/Write high to busy (tWB/tRB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " NAND_TA ,Read high to high impedance (tRHZ)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " RD_HIGH ,Read high hold time (tREH)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RD_LOW ,Read pulse width (tRP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WR_HIGH ,Write high hold time (tWH)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " WR_LOW ,Write pulse width (tWP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "MLC_IRQ_MR,MLC NAND Interrupt Mask Register"
|
|
bitfld.long 0x04 5. " NANDRdy ,NAND Ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ContRdy ,Controller Ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DecFail ,Decode failure interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DecErDet ,Decode error detected interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ECCRdy ,ECC Encode/Decode ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WProtFau ,Software write protection fault interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "MLC_IRQ_SR,MLC NAND Interrupt Status Register"
|
|
bitfld.long 0x0 5. " NANDRdy ,NAND Ready interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 4. " ContRdy ,Controller Ready interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DecFail ,Decode failureinterrupt" "Inactive,Active"
|
|
bitfld.long 0x0 2. " DecErDet ,Decode error detected interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ECCRdy ,ECC Encode/Decode ready interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 0. " WProtFau ,Software write protection fault interrupt" "Inactive,Active"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "MLC_LOCK_PR,MLC NAND Lock Protection Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " Unlock ,Write a value of 0xA25E to this register unlock the access"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "MLC_ISR,MLC NAND Status Register"
|
|
bitfld.long 0x0 6. " DecFail ,Decoder Failure" "Not failed,Failed"
|
|
bitfld.long 0x0 4.--5. " R/SSymEr ,Number of R/S symbols errors" "One symbol,Two symbol,Three symbol,Four symbol"
|
|
textline " "
|
|
bitfld.long 0x0 3. " ErDetect ,Errors detected" "Not detected,Detected"
|
|
bitfld.long 0x0 2. " ECCRdy ,ECC ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ContrRdy ,Controller ready" "Not ready,Ready"
|
|
bitfld.long 0x0 0. " NANDRdy ,NAND ready" "Not ready,Ready"
|
|
wgroup.long 0x4C++0x3
|
|
line.long 0x0 "MLC_CEH,MLC NAND Chip-Enable Host Control Register"
|
|
bitfld.long 0x0 0. " nCEassert ,Force nCE assert" "Forced,Normal"
|
|
base ad:0x200B0000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MLC_DATA,MLC NAND Data register"
|
|
base ad:0x200A8000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MLC_BUFF,MLC NAND Buffer register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SL FLASH (Single-Level NAND Flash Controller)"
|
|
base ad:0x20020000
|
|
width 14.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "SLC_DATA,SLC NAND flash Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Data ,NAND flash read or write data"
|
|
wgroup.long 0x04++0xB
|
|
line.long 0x0 "SLC_ADDR,SLC NAND flash Address Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Address ,NAND flash read or write address"
|
|
line.long 0x4 "SLC_CMD,SLC NAND flash Command Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " Command ,NAND flash command"
|
|
line.long 0x8 "SLC_STOP,SLC NAND flash STOP Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " Stop ,Write to stop all command/address sequences"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SLC_CTRL,SLC NAND flash Control Register"
|
|
bitfld.long 0x0 2. " SW_RESET ,Reset of the SLC NAND flash controller" "No reset,Reset"
|
|
bitfld.long 0x0 1. " ECC_CLEAR ,Clear of ECC parity bits and counter reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 0. " DMA_START ,DMA data channel start" "Not started,Started"
|
|
line.long 0x4 "SLC_CFG,SLC NAND flash Configuration Register"
|
|
bitfld.long 0x4 5. " CE_LOW ,CEn always low" "Not always,Always"
|
|
bitfld.long 0x4 4. " DMA_ECC ,DMA ECC channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " ECC_EN ,ECC enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " DMA_BURST ,Burst enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " DMA_DIR ,DMA read from or write to SLC" "Write,Read"
|
|
bitfld.long 0x4 0. " WIDTH ,External device width select" "8-bit,Not used"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SLC_STAT,SLC NAND flash Status Register"
|
|
bitfld.long 0x0 2. " DMA_ACTIVE ,DMA_FIFO status" "No data,Contain data"
|
|
bitfld.long 0x0 1. " SLC_ACTIVE ,SLC_FIFO status" "No data,Contain data"
|
|
bitfld.long 0x0 0. " READY ,NAND flash device ready signal" "Busy,Ready"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SLC_INT_STAT,SLC NAND flash Interrupt Status Register"
|
|
setclrfld.long 0x0 1. 0x8 1. 0xC 1. " INT_TC_set/clr ,Terminal Count interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x8 0. 0xC 0. " INT_RDY_set/clr ,Device ready interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SLC_IEN,SLC NAND flash Interrupt Enable Register"
|
|
bitfld.long 0x0 1. " INT_TC_EN ,Enable interrupt when TC has reached 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " INT_RDY_EN ,enable interrupt when RDY asserted" "Disabled,Enabled"
|
|
group.long 0x2C++0x7
|
|
line.long 0x0 "SLC_TAC,SLC NAND flash Timing Arcs configuration Register"
|
|
bitfld.long 0x0 28.--31. " W_RDY ,The time before the signal RDY is tested in clock cycles" "0 clock,2 clocks,4 clocks,6 clocks,8 clocks,10 clocks,12 clocks,14 clocks,16 clocks,18 clocks,20 clocks,22 clocks,24 clocks,26 clocks,28 clocks,30 clocks"
|
|
bitfld.long 0x0 24.--27. " W_WIDTH ,Write pulse width in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x0 20.--23. " W_HOLD ,Write hold time of ALE, CLE, CEn, and Data in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " W_SETUP ,Write setup time of ALE, CLE, CEn, and Data in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x0 12.--15. " R_RDY ,Time before the signal RDY is tested in clock cycles" "0 clock,2 clocks,4 clocks,6 clocks,8 clocks,10 clocks,12 clocks,14 clocks,?..."
|
|
bitfld.long 0x0 8.--11. " R_WIDTH ,Read pulse in clock cycles" "0 clock,2 clocks,4 clocks,6 clocks,8 clocks,10 clocks,12 clocks,14 clocks,16 clocks,18 clocks,20 clocks,22 clocks,24 clocks,26 clocks,28 clocks,30 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " R_HOLD ,Read hold time of ALE, CLE, and CEn in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x0 0.--3. " R_SETUP ,Read setup time of ALE, CLE, and CEn in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
line.long 0x4 "SLC_TC,SLC NAND flash Transfer Count Register"
|
|
hexmask.long 0x4 0.--15. 1. " T_C ,Number of remaining bytes to be transferred to or from NAND flash memory"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "SLC_ECC,SLC NAND flash Error Correction Code Register"
|
|
hexmask.long.word 0x0 6.--21. 1. " LP[15:0] ,Line parity"
|
|
hexmask.long.byte 0x0 0.--5. 1. " CP[5:0] ,Column parity"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SLC_DMA_DATA,SLC NAND flash DMA Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " 1DBT ,First data byte transferred"
|
|
hexmask.long.byte 0x0 16.--23. 1. " 2DBT ,Second data byte transferred"
|
|
hexmask.long.byte 0x0 8.--15. 1. " 3DBT ,Third data byte transferred"
|
|
hexmask.long.byte 0x0 0.--7. 1. " 4DBT ,Fourth data byte transferred"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
tree "LCD (Liquid Crystal Display)"
|
|
base ad:0x31040000
|
|
width 14.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "LCD_TIMH,Horizontal Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " HBP ,Horizontal back porch"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HFP ,Horizontal front porch"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSW ,Horizontal synchronization pulse width"
|
|
hexmask.long.byte 0x00 2.--7. 1. " PPL ,Pixels-per-line"
|
|
line.long 0x04 "LCD_TIMV,Vertical Timing Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VBP ,Vertical back porch"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VFP ,Vertical front porch"
|
|
hexmask.long.byte 0x04 10.--15. 1. " VSW ,Vertical synchronization pulse width"
|
|
hexmask.long.word 0x04 0.--9. 1. " LPP ,Lines per panel"
|
|
line.long 0x08 "LCD_POL,Clock and Signal Polarity Register"
|
|
bitfld.long 0x08 27.--31. " PCD_HI ,Upper five bits of panel clock divisor" "Reserved,Single/color,Single/monochrome 4-bit,Reserved,Dual/color,Reserved,Dual/monochrome 4-bit and Single/monochrome 8-bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Dual/monochrome 8-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x08 26. " BCD ,Bypass pixel clock divider" "Not bypassed,Bypassed"
|
|
hexmask.long.word 0x08 16.--25. 1. " CPL ,Clocks per line"
|
|
textline " "
|
|
bitfld.long 0x08 14. " IOE ,Invert output enable" "Active High,Active Low"
|
|
bitfld.long 0x08 13. " IPC ,Invert panel clock" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x08 12. " IHS ,Invert horizontal synchronization" "Active High/Inactive Low,Active Low/Inactive High"
|
|
bitfld.long 0x08 11. " IVS ,Invert vertical synchronization" "Active High/Inactive Low,Active Low/Inactive High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " ACB ,AC bias pin frequency" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31."
|
|
bitfld.long 0x08 5. " CLKSEL ,Clock Select" "HCLK,LCDCLKIN"
|
|
textline " "
|
|
bitfld.long 0x08 0.--4. " PCD_LO ,Lower five bits of panel clock divisor (panel/mode)" "Reserved,Single/color,Single/monochrome 4-bit,Reserved,Dual/color,Reserved,Dual/monochrome 4-bit and Single/monochrome 8-bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Dual/monochrome 8-bit,?..."
|
|
line.long 0x0c "LCD_LE,Line End Control Register"
|
|
bitfld.long 0x0C 16. " LEE ,LCD Line end enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " LED ,Line-end delay"
|
|
line.long 0x10 "LCD_UPBASE,Upper Panel Frame Base Address Register"
|
|
hexmask.long 0x10 3.--31. 0x8 " LCDUPBASE ,LCD upper panel base address"
|
|
line.long 0x14 "LCD_LPBASE,Lower Panel Frame Base Address Register"
|
|
hexmask.long 0x14 3.--31. 0x8 " LCDLPBASE ,LCD lower panel base address"
|
|
if (((data.long(ad:(0x31040000+0x18)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LCD_CTRL,LCD Control Register"
|
|
bitfld.long 0x00 16. " WATERMARK ,LCD DMA FIFO watermark level" "4,8"
|
|
bitfld.long 0x00 12.--13. " LcdVComp ,LCD Vertical Compare Interrupt" "Vertical synchronization,Back porch,Active video,Front porch"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LcdPwr ,LCD power enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BEPO ,Big-Endian Pixel Ordering" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BEBO ,Big-endian Byte Order" "Little endian,Big endian"
|
|
bitfld.long 0x00 8. " BGR ,Color format selection" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LcdDual ,Single or Dual LCD panel selection" "Single,Dual"
|
|
bitfld.long 0x00 6. " LcdMono8 ,Monochrome LCD interface width" "4-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LcdTFT ,LCD panel TFT type selection" "STN,TFT"
|
|
bitfld.long 0x00 1.--3. " LcdBpp ,LCD bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,24 bpp,16 bpp (5:6:5),12 bpp (4:4:4)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LcdEn ,LCD enable control bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LCD_CTRL,LCD Control Register"
|
|
bitfld.long 0x00 16. " WATERMARK ,LCD DMA FIFO watermark level" "4,8"
|
|
bitfld.long 0x00 12.--13. " LcdVComp ,LCD Vertical Compare Interrupt" "Vertical synchronization,Back porch,Active video,Front porch"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LcdPwr ,LCD power enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BEPO ,Big-Endian Pixel Ordering" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BEBO ,Big-endian Byte Order" "Little endian,Big endian"
|
|
bitfld.long 0x00 8. " BGR ,Color format selection" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LcdDual ,Single or Dual LCD panel selection" "Single,Dual"
|
|
bitfld.long 0x00 6. " LcdMono8 ,Monochrome LCD interface width" "4-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LcdTFT ,LCD panel TFT type selection" "STN,TFT"
|
|
bitfld.long 0x00 4. " LcdBW ,STN LCD monochrome/color selection" "Color,Monochrome"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " LcdBpp ,LCD bits per pixel" "1 bpp,2 bpp,4 bpp,8 bpp,16 bpp,Reserved,16 bpp (5:6:5),12 bpp (4:4:4)"
|
|
bitfld.long 0x00 0. " LcdEn ,LCD enable control bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "LCD_INTMSK,Interrupt Mask Register"
|
|
bitfld.long 0x00 4. " BERIM ,AHB master error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VCompIM ,Vertical compare interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LNBUIM ,LCD next base address update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FUFIM ,FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "LCD_INTRAW,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 4. " BERRAW ,AHB master bus error raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VCompRIS ,Vertical compare raw interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LNBURIS ,LCD next address base update raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " FUFRIS ,FIFO underflow raw interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "LCD_INTSTAT,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 4. " BERMIS ,AHB master bus error masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " VCompMIS ,Vertical compare masked interrupt status" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LNBUMIS ,LCD next address base update masked interrupt status" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " FUFMIS ,FIFO underflow masked interrupt status" "Not masked,Masked"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "LCD_INTCLR,Interrupt Clear Register"
|
|
bitfld.long 0x00 4. " BERIC ,AHB master error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " VCompIC ,Vertical compare interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LNBUIC ,LCD next address base update interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FUFIC ,FIFO underflow interrupt clear" "No effect,Clear"
|
|
rgroup.long 0x2c++0x7
|
|
line.long 0x00 "LCD_UPCURR,Upper Panel Current Address Register"
|
|
line.long 0x04 "LCD_LPCURR,Lower Panel Current Address Register"
|
|
width 11.
|
|
tree "Color Palette Registers"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "LCD_PAL0,Color Palette Register 0"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "LCD_PAL1,Color Palette Register 1"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "LCD_PAL2,Color Palette Register 2"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x20C++0x3
|
|
line.long 0x00 "LCD_PAL3,Color Palette Register 3"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "LCD_PAL4,Color Palette Register 4"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x214++0x3
|
|
line.long 0x00 "LCD_PAL5,Color Palette Register 5"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "LCD_PAL6,Color Palette Register 6"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x21C++0x3
|
|
line.long 0x00 "LCD_PAL7,Color Palette Register 7"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "LCD_PAL8,Color Palette Register 8"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x224++0x3
|
|
line.long 0x00 "LCD_PAL9,Color Palette Register 9"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x228++0x3
|
|
line.long 0x00 "LCD_PAL10,Color Palette Register 10"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x22C++0x3
|
|
line.long 0x00 "LCD_PAL11,Color Palette Register 11"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x230++0x3
|
|
line.long 0x00 "LCD_PAL12,Color Palette Register 12"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x234++0x3
|
|
line.long 0x00 "LCD_PAL13,Color Palette Register 13"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x238++0x3
|
|
line.long 0x00 "LCD_PAL14,Color Palette Register 14"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x23C++0x3
|
|
line.long 0x00 "LCD_PAL15,Color Palette Register 15"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x240++0x3
|
|
line.long 0x00 "LCD_PAL16,Color Palette Register 16"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x244++0x3
|
|
line.long 0x00 "LCD_PAL17,Color Palette Register 17"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x248++0x3
|
|
line.long 0x00 "LCD_PAL18,Color Palette Register 18"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x24C++0x3
|
|
line.long 0x00 "LCD_PAL19,Color Palette Register 19"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x250++0x3
|
|
line.long 0x00 "LCD_PAL20,Color Palette Register 20"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x254++0x3
|
|
line.long 0x00 "LCD_PAL21,Color Palette Register 21"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x258++0x3
|
|
line.long 0x00 "LCD_PAL22,Color Palette Register 22"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x25C++0x3
|
|
line.long 0x00 "LCD_PAL23,Color Palette Register 23"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "LCD_PAL24,Color Palette Register 24"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x264++0x3
|
|
line.long 0x00 "LCD_PAL25,Color Palette Register 25"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x268++0x3
|
|
line.long 0x00 "LCD_PAL26,Color Palette Register 26"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x26C++0x3
|
|
line.long 0x00 "LCD_PAL27,Color Palette Register 27"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x270++0x3
|
|
line.long 0x00 "LCD_PAL28,Color Palette Register 28"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x274++0x3
|
|
line.long 0x00 "LCD_PAL29,Color Palette Register 29"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x278++0x3
|
|
line.long 0x00 "LCD_PAL30,Color Palette Register 30"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x27C++0x3
|
|
line.long 0x00 "LCD_PAL31,Color Palette Register 31"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x280++0x3
|
|
line.long 0x00 "LCD_PAL32,Color Palette Register 32"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x284++0x3
|
|
line.long 0x00 "LCD_PAL33,Color Palette Register 33"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x288++0x3
|
|
line.long 0x00 "LCD_PAL34,Color Palette Register 34"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x28C++0x3
|
|
line.long 0x00 "LCD_PAL35,Color Palette Register 35"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x290++0x3
|
|
line.long 0x00 "LCD_PAL36,Color Palette Register 36"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x294++0x3
|
|
line.long 0x00 "LCD_PAL37,Color Palette Register 37"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x298++0x3
|
|
line.long 0x00 "LCD_PAL38,Color Palette Register 38"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x29C++0x3
|
|
line.long 0x00 "LCD_PAL39,Color Palette Register 39"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x00 "LCD_PAL40,Color Palette Register 40"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x00 "LCD_PAL41,Color Palette Register 41"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2A8++0x3
|
|
line.long 0x00 "LCD_PAL42,Color Palette Register 42"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2AC++0x3
|
|
line.long 0x00 "LCD_PAL43,Color Palette Register 43"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2B0++0x3
|
|
line.long 0x00 "LCD_PAL44,Color Palette Register 44"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2B4++0x3
|
|
line.long 0x00 "LCD_PAL45,Color Palette Register 45"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2B8++0x3
|
|
line.long 0x00 "LCD_PAL46,Color Palette Register 46"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2BC++0x3
|
|
line.long 0x00 "LCD_PAL47,Color Palette Register 47"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x00 "LCD_PAL48,Color Palette Register 48"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2C4++0x3
|
|
line.long 0x00 "LCD_PAL49,Color Palette Register 49"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x00 "LCD_PAL50,Color Palette Register 50"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2CC++0x3
|
|
line.long 0x00 "LCD_PAL51,Color Palette Register 51"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x00 "LCD_PAL52,Color Palette Register 52"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2D4++0x3
|
|
line.long 0x00 "LCD_PAL53,Color Palette Register 53"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2D8++0x3
|
|
line.long 0x00 "LCD_PAL54,Color Palette Register 54"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2DC++0x3
|
|
line.long 0x00 "LCD_PAL55,Color Palette Register 55"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x00 "LCD_PAL56,Color Palette Register 56"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x00 "LCD_PAL57,Color Palette Register 57"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2E8++0x3
|
|
line.long 0x00 "LCD_PAL58,Color Palette Register 58"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2EC++0x3
|
|
line.long 0x00 "LCD_PAL59,Color Palette Register 59"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x00 "LCD_PAL60,Color Palette Register 60"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x00 "LCD_PAL61,Color Palette Register 61"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2F8++0x3
|
|
line.long 0x00 "LCD_PAL62,Color Palette Register 62"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x2FC++0x3
|
|
line.long 0x00 "LCD_PAL63,Color Palette Register 63"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "LCD_PAL64,Color Palette Register 64"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x304++0x3
|
|
line.long 0x00 "LCD_PAL65,Color Palette Register 65"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x308++0x3
|
|
line.long 0x00 "LCD_PAL66,Color Palette Register 66"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x30C++0x3
|
|
line.long 0x00 "LCD_PAL67,Color Palette Register 67"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x310++0x3
|
|
line.long 0x00 "LCD_PAL68,Color Palette Register 68"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x314++0x3
|
|
line.long 0x00 "LCD_PAL69,Color Palette Register 69"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x318++0x3
|
|
line.long 0x00 "LCD_PAL70,Color Palette Register 70"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x31C++0x3
|
|
line.long 0x00 "LCD_PAL71,Color Palette Register 71"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x320++0x3
|
|
line.long 0x00 "LCD_PAL72,Color Palette Register 72"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x324++0x3
|
|
line.long 0x00 "LCD_PAL73,Color Palette Register 73"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x328++0x3
|
|
line.long 0x00 "LCD_PAL74,Color Palette Register 74"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x32C++0x3
|
|
line.long 0x00 "LCD_PAL75,Color Palette Register 75"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x330++0x3
|
|
line.long 0x00 "LCD_PAL76,Color Palette Register 76"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x334++0x3
|
|
line.long 0x00 "LCD_PAL77,Color Palette Register 77"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x338++0x3
|
|
line.long 0x00 "LCD_PAL78,Color Palette Register 78"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x33C++0x3
|
|
line.long 0x00 "LCD_PAL79,Color Palette Register 79"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x340++0x3
|
|
line.long 0x00 "LCD_PAL80,Color Palette Register 80"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x344++0x3
|
|
line.long 0x00 "LCD_PAL81,Color Palette Register 81"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x348++0x3
|
|
line.long 0x00 "LCD_PAL82,Color Palette Register 82"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x34C++0x3
|
|
line.long 0x00 "LCD_PAL83,Color Palette Register 83"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x350++0x3
|
|
line.long 0x00 "LCD_PAL84,Color Palette Register 84"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x354++0x3
|
|
line.long 0x00 "LCD_PAL85,Color Palette Register 85"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x358++0x3
|
|
line.long 0x00 "LCD_PAL86,Color Palette Register 86"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x35C++0x3
|
|
line.long 0x00 "LCD_PAL87,Color Palette Register 87"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x360++0x3
|
|
line.long 0x00 "LCD_PAL88,Color Palette Register 88"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x364++0x3
|
|
line.long 0x00 "LCD_PAL89,Color Palette Register 89"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x368++0x3
|
|
line.long 0x00 "LCD_PAL90,Color Palette Register 90"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x36C++0x3
|
|
line.long 0x00 "LCD_PAL91,Color Palette Register 91"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x370++0x3
|
|
line.long 0x00 "LCD_PAL92,Color Palette Register 92"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x374++0x3
|
|
line.long 0x00 "LCD_PAL93,Color Palette Register 93"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x378++0x3
|
|
line.long 0x00 "LCD_PAL94,Color Palette Register 94"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x37C++0x3
|
|
line.long 0x00 "LCD_PAL95,Color Palette Register 95"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "LCD_PAL96,Color Palette Register 96"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x384++0x3
|
|
line.long 0x00 "LCD_PAL97,Color Palette Register 97"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x388++0x3
|
|
line.long 0x00 "LCD_PAL98,Color Palette Register 98"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x38C++0x3
|
|
line.long 0x00 "LCD_PAL99,Color Palette Register 99"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x390++0x3
|
|
line.long 0x00 "LCD_PAL100,Color Palette Register 100"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x394++0x3
|
|
line.long 0x00 "LCD_PAL101,Color Palette Register 101"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x398++0x3
|
|
line.long 0x00 "LCD_PAL102,Color Palette Register 102"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x39C++0x3
|
|
line.long 0x00 "LCD_PAL103,Color Palette Register 103"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3A0++0x3
|
|
line.long 0x00 "LCD_PAL104,Color Palette Register 104"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3A4++0x3
|
|
line.long 0x00 "LCD_PAL105,Color Palette Register 105"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3A8++0x3
|
|
line.long 0x00 "LCD_PAL106,Color Palette Register 106"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3AC++0x3
|
|
line.long 0x00 "LCD_PAL107,Color Palette Register 107"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3B0++0x3
|
|
line.long 0x00 "LCD_PAL108,Color Palette Register 108"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3B4++0x3
|
|
line.long 0x00 "LCD_PAL109,Color Palette Register 109"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3B8++0x3
|
|
line.long 0x00 "LCD_PAL110,Color Palette Register 110"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3BC++0x3
|
|
line.long 0x00 "LCD_PAL111,Color Palette Register 111"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x00 "LCD_PAL112,Color Palette Register 112"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3C4++0x3
|
|
line.long 0x00 "LCD_PAL113,Color Palette Register 113"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3C8++0x3
|
|
line.long 0x00 "LCD_PAL114,Color Palette Register 114"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3CC++0x3
|
|
line.long 0x00 "LCD_PAL115,Color Palette Register 115"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3D0++0x3
|
|
line.long 0x00 "LCD_PAL116,Color Palette Register 116"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x00 "LCD_PAL117,Color Palette Register 117"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3D8++0x3
|
|
line.long 0x00 "LCD_PAL118,Color Palette Register 118"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3DC++0x3
|
|
line.long 0x00 "LCD_PAL119,Color Palette Register 119"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x00 "LCD_PAL120,Color Palette Register 120"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3E4++0x3
|
|
line.long 0x00 "LCD_PAL121,Color Palette Register 121"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3E8++0x3
|
|
line.long 0x00 "LCD_PAL122,Color Palette Register 122"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3EC++0x3
|
|
line.long 0x00 "LCD_PAL123,Color Palette Register 123"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x00 "LCD_PAL124,Color Palette Register 124"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3F4++0x3
|
|
line.long 0x00 "LCD_PAL125,Color Palette Register 125"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3F8++0x3
|
|
line.long 0x00 "LCD_PAL126,Color Palette Register 126"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
group.long 0x3FC++0x3
|
|
line.long 0x00 "LCD_PAL127,Color Palette Register 127"
|
|
bitfld.long 0x00 31. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 26.--30. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 21.--25. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 16.--20. 1. " R[4:0] ,Red palette data"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I ,Intensity (RGB 6:6:6 TFT only)" "Low,High"
|
|
hexmask.long.byte 0x00 10.--14. 1. " B[4:0] ,Blue palette data"
|
|
hexmask.long.byte 0x00 5.--9. 1. " G[4:0] ,Green palette data"
|
|
hexmask.long.byte 0x00 0.--4. 1. " R[4:0] ,Red palette data"
|
|
tree.end
|
|
width 14.
|
|
tree "Cursor Image Registers"
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "CRSR_IMG0,Cursor Image Register 0"
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "CRSR_IMG1,Cursor Image Register 1"
|
|
group.long 0x808++0x3
|
|
line.long 0x00 "CRSR_IMG2,Cursor Image Register 2"
|
|
group.long 0x80C++0x3
|
|
line.long 0x00 "CRSR_IMG3,Cursor Image Register 3"
|
|
group.long 0x810++0x3
|
|
line.long 0x00 "CRSR_IMG4,Cursor Image Register 4"
|
|
group.long 0x814++0x3
|
|
line.long 0x00 "CRSR_IMG5,Cursor Image Register 5"
|
|
group.long 0x818++0x3
|
|
line.long 0x00 "CRSR_IMG6,Cursor Image Register 6"
|
|
group.long 0x81C++0x3
|
|
line.long 0x00 "CRSR_IMG7,Cursor Image Register 7"
|
|
group.long 0x820++0x3
|
|
line.long 0x00 "CRSR_IMG8,Cursor Image Register 8"
|
|
group.long 0x824++0x3
|
|
line.long 0x00 "CRSR_IMG9,Cursor Image Register 9"
|
|
group.long 0x828++0x3
|
|
line.long 0x00 "CRSR_IMG10,Cursor Image Register 10"
|
|
group.long 0x82C++0x3
|
|
line.long 0x00 "CRSR_IMG11,Cursor Image Register 11"
|
|
group.long 0x830++0x3
|
|
line.long 0x00 "CRSR_IMG12,Cursor Image Register 12"
|
|
group.long 0x834++0x3
|
|
line.long 0x00 "CRSR_IMG13,Cursor Image Register 13"
|
|
group.long 0x838++0x3
|
|
line.long 0x00 "CRSR_IMG14,Cursor Image Register 14"
|
|
group.long 0x83C++0x3
|
|
line.long 0x00 "CRSR_IMG15,Cursor Image Register 15"
|
|
group.long 0x840++0x3
|
|
line.long 0x00 "CRSR_IMG16,Cursor Image Register 16"
|
|
group.long 0x844++0x3
|
|
line.long 0x00 "CRSR_IMG17,Cursor Image Register 17"
|
|
group.long 0x848++0x3
|
|
line.long 0x00 "CRSR_IMG18,Cursor Image Register 18"
|
|
group.long 0x84C++0x3
|
|
line.long 0x00 "CRSR_IMG19,Cursor Image Register 19"
|
|
group.long 0x850++0x3
|
|
line.long 0x00 "CRSR_IMG20,Cursor Image Register 20"
|
|
group.long 0x854++0x3
|
|
line.long 0x00 "CRSR_IMG21,Cursor Image Register 21"
|
|
group.long 0x858++0x3
|
|
line.long 0x00 "CRSR_IMG22,Cursor Image Register 22"
|
|
group.long 0x85C++0x3
|
|
line.long 0x00 "CRSR_IMG23,Cursor Image Register 23"
|
|
group.long 0x860++0x3
|
|
line.long 0x00 "CRSR_IMG24,Cursor Image Register 24"
|
|
group.long 0x864++0x3
|
|
line.long 0x00 "CRSR_IMG25,Cursor Image Register 25"
|
|
group.long 0x868++0x3
|
|
line.long 0x00 "CRSR_IMG26,Cursor Image Register 26"
|
|
group.long 0x86C++0x3
|
|
line.long 0x00 "CRSR_IMG27,Cursor Image Register 27"
|
|
group.long 0x870++0x3
|
|
line.long 0x00 "CRSR_IMG28,Cursor Image Register 28"
|
|
group.long 0x874++0x3
|
|
line.long 0x00 "CRSR_IMG29,Cursor Image Register 29"
|
|
group.long 0x878++0x3
|
|
line.long 0x00 "CRSR_IMG30,Cursor Image Register 30"
|
|
group.long 0x87C++0x3
|
|
line.long 0x00 "CRSR_IMG31,Cursor Image Register 31"
|
|
group.long 0x880++0x3
|
|
line.long 0x00 "CRSR_IMG32,Cursor Image Register 32"
|
|
group.long 0x884++0x3
|
|
line.long 0x00 "CRSR_IMG33,Cursor Image Register 33"
|
|
group.long 0x888++0x3
|
|
line.long 0x00 "CRSR_IMG34,Cursor Image Register 34"
|
|
group.long 0x88C++0x3
|
|
line.long 0x00 "CRSR_IMG35,Cursor Image Register 35"
|
|
group.long 0x890++0x3
|
|
line.long 0x00 "CRSR_IMG36,Cursor Image Register 36"
|
|
group.long 0x894++0x3
|
|
line.long 0x00 "CRSR_IMG37,Cursor Image Register 37"
|
|
group.long 0x898++0x3
|
|
line.long 0x00 "CRSR_IMG38,Cursor Image Register 38"
|
|
group.long 0x89C++0x3
|
|
line.long 0x00 "CRSR_IMG39,Cursor Image Register 39"
|
|
group.long 0x8A0++0x3
|
|
line.long 0x00 "CRSR_IMG40,Cursor Image Register 40"
|
|
group.long 0x8A4++0x3
|
|
line.long 0x00 "CRSR_IMG41,Cursor Image Register 41"
|
|
group.long 0x8A8++0x3
|
|
line.long 0x00 "CRSR_IMG42,Cursor Image Register 42"
|
|
group.long 0x8AC++0x3
|
|
line.long 0x00 "CRSR_IMG43,Cursor Image Register 43"
|
|
group.long 0x8B0++0x3
|
|
line.long 0x00 "CRSR_IMG44,Cursor Image Register 44"
|
|
group.long 0x8B4++0x3
|
|
line.long 0x00 "CRSR_IMG45,Cursor Image Register 45"
|
|
group.long 0x8B8++0x3
|
|
line.long 0x00 "CRSR_IMG46,Cursor Image Register 46"
|
|
group.long 0x8BC++0x3
|
|
line.long 0x00 "CRSR_IMG47,Cursor Image Register 47"
|
|
group.long 0x8C0++0x3
|
|
line.long 0x00 "CRSR_IMG48,Cursor Image Register 48"
|
|
group.long 0x8C4++0x3
|
|
line.long 0x00 "CRSR_IMG49,Cursor Image Register 49"
|
|
group.long 0x8C8++0x3
|
|
line.long 0x00 "CRSR_IMG50,Cursor Image Register 50"
|
|
group.long 0x8CC++0x3
|
|
line.long 0x00 "CRSR_IMG51,Cursor Image Register 51"
|
|
group.long 0x8D0++0x3
|
|
line.long 0x00 "CRSR_IMG52,Cursor Image Register 52"
|
|
group.long 0x8D4++0x3
|
|
line.long 0x00 "CRSR_IMG53,Cursor Image Register 53"
|
|
group.long 0x8D8++0x3
|
|
line.long 0x00 "CRSR_IMG54,Cursor Image Register 54"
|
|
group.long 0x8DC++0x3
|
|
line.long 0x00 "CRSR_IMG55,Cursor Image Register 55"
|
|
group.long 0x8E0++0x3
|
|
line.long 0x00 "CRSR_IMG56,Cursor Image Register 56"
|
|
group.long 0x8E4++0x3
|
|
line.long 0x00 "CRSR_IMG57,Cursor Image Register 57"
|
|
group.long 0x8E8++0x3
|
|
line.long 0x00 "CRSR_IMG58,Cursor Image Register 58"
|
|
group.long 0x8EC++0x3
|
|
line.long 0x00 "CRSR_IMG59,Cursor Image Register 59"
|
|
group.long 0x8F0++0x3
|
|
line.long 0x00 "CRSR_IMG60,Cursor Image Register 60"
|
|
group.long 0x8F4++0x3
|
|
line.long 0x00 "CRSR_IMG61,Cursor Image Register 61"
|
|
group.long 0x8F8++0x3
|
|
line.long 0x00 "CRSR_IMG62,Cursor Image Register 62"
|
|
group.long 0x8FC++0x3
|
|
line.long 0x00 "CRSR_IMG63,Cursor Image Register 63"
|
|
group.long 0x900++0x3
|
|
line.long 0x00 "CRSR_IMG64,Cursor Image Register 64"
|
|
group.long 0x904++0x3
|
|
line.long 0x00 "CRSR_IMG65,Cursor Image Register 65"
|
|
group.long 0x908++0x3
|
|
line.long 0x00 "CRSR_IMG66,Cursor Image Register 66"
|
|
group.long 0x90C++0x3
|
|
line.long 0x00 "CRSR_IMG67,Cursor Image Register 67"
|
|
group.long 0x910++0x3
|
|
line.long 0x00 "CRSR_IMG68,Cursor Image Register 68"
|
|
group.long 0x914++0x3
|
|
line.long 0x00 "CRSR_IMG69,Cursor Image Register 69"
|
|
group.long 0x918++0x3
|
|
line.long 0x00 "CRSR_IMG70,Cursor Image Register 70"
|
|
group.long 0x91C++0x3
|
|
line.long 0x00 "CRSR_IMG71,Cursor Image Register 71"
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "CRSR_IMG72,Cursor Image Register 72"
|
|
group.long 0x924++0x3
|
|
line.long 0x00 "CRSR_IMG73,Cursor Image Register 73"
|
|
group.long 0x928++0x3
|
|
line.long 0x00 "CRSR_IMG74,Cursor Image Register 74"
|
|
group.long 0x92C++0x3
|
|
line.long 0x00 "CRSR_IMG75,Cursor Image Register 75"
|
|
group.long 0x930++0x3
|
|
line.long 0x00 "CRSR_IMG76,Cursor Image Register 76"
|
|
group.long 0x934++0x3
|
|
line.long 0x00 "CRSR_IMG77,Cursor Image Register 77"
|
|
group.long 0x938++0x3
|
|
line.long 0x00 "CRSR_IMG78,Cursor Image Register 78"
|
|
group.long 0x93C++0x3
|
|
line.long 0x00 "CRSR_IMG79,Cursor Image Register 79"
|
|
group.long 0x940++0x3
|
|
line.long 0x00 "CRSR_IMG80,Cursor Image Register 80"
|
|
group.long 0x944++0x3
|
|
line.long 0x00 "CRSR_IMG81,Cursor Image Register 81"
|
|
group.long 0x948++0x3
|
|
line.long 0x00 "CRSR_IMG82,Cursor Image Register 82"
|
|
group.long 0x94C++0x3
|
|
line.long 0x00 "CRSR_IMG83,Cursor Image Register 83"
|
|
group.long 0x950++0x3
|
|
line.long 0x00 "CRSR_IMG84,Cursor Image Register 84"
|
|
group.long 0x954++0x3
|
|
line.long 0x00 "CRSR_IMG85,Cursor Image Register 85"
|
|
group.long 0x958++0x3
|
|
line.long 0x00 "CRSR_IMG86,Cursor Image Register 86"
|
|
group.long 0x95C++0x3
|
|
line.long 0x00 "CRSR_IMG87,Cursor Image Register 87"
|
|
group.long 0x960++0x3
|
|
line.long 0x00 "CRSR_IMG88,Cursor Image Register 88"
|
|
group.long 0x964++0x3
|
|
line.long 0x00 "CRSR_IMG89,Cursor Image Register 89"
|
|
group.long 0x968++0x3
|
|
line.long 0x00 "CRSR_IMG90,Cursor Image Register 90"
|
|
group.long 0x96C++0x3
|
|
line.long 0x00 "CRSR_IMG91,Cursor Image Register 91"
|
|
group.long 0x970++0x3
|
|
line.long 0x00 "CRSR_IMG92,Cursor Image Register 92"
|
|
group.long 0x974++0x3
|
|
line.long 0x00 "CRSR_IMG93,Cursor Image Register 93"
|
|
group.long 0x978++0x3
|
|
line.long 0x00 "CRSR_IMG94,Cursor Image Register 94"
|
|
group.long 0x97C++0x3
|
|
line.long 0x00 "CRSR_IMG95,Cursor Image Register 95"
|
|
group.long 0x980++0x3
|
|
line.long 0x00 "CRSR_IMG96,Cursor Image Register 96"
|
|
group.long 0x984++0x3
|
|
line.long 0x00 "CRSR_IMG97,Cursor Image Register 97"
|
|
group.long 0x988++0x3
|
|
line.long 0x00 "CRSR_IMG98,Cursor Image Register 98"
|
|
group.long 0x98C++0x3
|
|
line.long 0x00 "CRSR_IMG99,Cursor Image Register 99"
|
|
group.long 0x990++0x3
|
|
line.long 0x00 "CRSR_IMG100,Cursor Image Register 100"
|
|
group.long 0x994++0x3
|
|
line.long 0x00 "CRSR_IMG101,Cursor Image Register 101"
|
|
group.long 0x998++0x3
|
|
line.long 0x00 "CRSR_IMG102,Cursor Image Register 102"
|
|
group.long 0x99C++0x3
|
|
line.long 0x00 "CRSR_IMG103,Cursor Image Register 103"
|
|
group.long 0x9A0++0x3
|
|
line.long 0x00 "CRSR_IMG104,Cursor Image Register 104"
|
|
group.long 0x9A4++0x3
|
|
line.long 0x00 "CRSR_IMG105,Cursor Image Register 105"
|
|
group.long 0x9A8++0x3
|
|
line.long 0x00 "CRSR_IMG106,Cursor Image Register 106"
|
|
group.long 0x9AC++0x3
|
|
line.long 0x00 "CRSR_IMG107,Cursor Image Register 107"
|
|
group.long 0x9B0++0x3
|
|
line.long 0x00 "CRSR_IMG108,Cursor Image Register 108"
|
|
group.long 0x9B4++0x3
|
|
line.long 0x00 "CRSR_IMG109,Cursor Image Register 109"
|
|
group.long 0x9B8++0x3
|
|
line.long 0x00 "CRSR_IMG110,Cursor Image Register 110"
|
|
group.long 0x9BC++0x3
|
|
line.long 0x00 "CRSR_IMG111,Cursor Image Register 111"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x00 "CRSR_IMG112,Cursor Image Register 112"
|
|
group.long 0x9C4++0x3
|
|
line.long 0x00 "CRSR_IMG113,Cursor Image Register 113"
|
|
group.long 0x9C8++0x3
|
|
line.long 0x00 "CRSR_IMG114,Cursor Image Register 114"
|
|
group.long 0x9CC++0x3
|
|
line.long 0x00 "CRSR_IMG115,Cursor Image Register 115"
|
|
group.long 0x9D0++0x3
|
|
line.long 0x00 "CRSR_IMG116,Cursor Image Register 116"
|
|
group.long 0x9D4++0x3
|
|
line.long 0x00 "CRSR_IMG117,Cursor Image Register 117"
|
|
group.long 0x9D8++0x3
|
|
line.long 0x00 "CRSR_IMG118,Cursor Image Register 118"
|
|
group.long 0x9DC++0x3
|
|
line.long 0x00 "CRSR_IMG119,Cursor Image Register 119"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x00 "CRSR_IMG120,Cursor Image Register 120"
|
|
group.long 0x9E4++0x3
|
|
line.long 0x00 "CRSR_IMG121,Cursor Image Register 121"
|
|
group.long 0x9E8++0x3
|
|
line.long 0x00 "CRSR_IMG122,Cursor Image Register 122"
|
|
group.long 0x9EC++0x3
|
|
line.long 0x00 "CRSR_IMG123,Cursor Image Register 123"
|
|
group.long 0x9F0++0x3
|
|
line.long 0x00 "CRSR_IMG124,Cursor Image Register 124"
|
|
group.long 0x9F4++0x3
|
|
line.long 0x00 "CRSR_IMG125,Cursor Image Register 125"
|
|
group.long 0x9F8++0x3
|
|
line.long 0x00 "CRSR_IMG126,Cursor Image Register 126"
|
|
group.long 0x9FC++0x3
|
|
line.long 0x00 "CRSR_IMG127,Cursor Image Register 127"
|
|
group.long 0xA00++0x3
|
|
line.long 0x00 "CRSR_IMG128,Cursor Image Register 128"
|
|
group.long 0xA04++0x3
|
|
line.long 0x00 "CRSR_IMG129,Cursor Image Register 129"
|
|
group.long 0xA08++0x3
|
|
line.long 0x00 "CRSR_IMG130,Cursor Image Register 130"
|
|
group.long 0xA0C++0x3
|
|
line.long 0x00 "CRSR_IMG131,Cursor Image Register 131"
|
|
group.long 0xA10++0x3
|
|
line.long 0x00 "CRSR_IMG132,Cursor Image Register 132"
|
|
group.long 0xA14++0x3
|
|
line.long 0x00 "CRSR_IMG133,Cursor Image Register 133"
|
|
group.long 0xA18++0x3
|
|
line.long 0x00 "CRSR_IMG134,Cursor Image Register 134"
|
|
group.long 0xA1C++0x3
|
|
line.long 0x00 "CRSR_IMG135,Cursor Image Register 135"
|
|
group.long 0xA20++0x3
|
|
line.long 0x00 "CRSR_IMG136,Cursor Image Register 136"
|
|
group.long 0xA24++0x3
|
|
line.long 0x00 "CRSR_IMG137,Cursor Image Register 137"
|
|
group.long 0xA28++0x3
|
|
line.long 0x00 "CRSR_IMG138,Cursor Image Register 138"
|
|
group.long 0xA2C++0x3
|
|
line.long 0x00 "CRSR_IMG139,Cursor Image Register 139"
|
|
group.long 0xA30++0x3
|
|
line.long 0x00 "CRSR_IMG140,Cursor Image Register 140"
|
|
group.long 0xA34++0x3
|
|
line.long 0x00 "CRSR_IMG141,Cursor Image Register 141"
|
|
group.long 0xA38++0x3
|
|
line.long 0x00 "CRSR_IMG142,Cursor Image Register 142"
|
|
group.long 0xA3C++0x3
|
|
line.long 0x00 "CRSR_IMG143,Cursor Image Register 143"
|
|
group.long 0xA40++0x3
|
|
line.long 0x00 "CRSR_IMG144,Cursor Image Register 144"
|
|
group.long 0xA44++0x3
|
|
line.long 0x00 "CRSR_IMG145,Cursor Image Register 145"
|
|
group.long 0xA48++0x3
|
|
line.long 0x00 "CRSR_IMG146,Cursor Image Register 146"
|
|
group.long 0xA4C++0x3
|
|
line.long 0x00 "CRSR_IMG147,Cursor Image Register 147"
|
|
group.long 0xA50++0x3
|
|
line.long 0x00 "CRSR_IMG148,Cursor Image Register 148"
|
|
group.long 0xA54++0x3
|
|
line.long 0x00 "CRSR_IMG149,Cursor Image Register 149"
|
|
group.long 0xA58++0x3
|
|
line.long 0x00 "CRSR_IMG150,Cursor Image Register 150"
|
|
group.long 0xA5C++0x3
|
|
line.long 0x00 "CRSR_IMG151,Cursor Image Register 151"
|
|
group.long 0xA60++0x3
|
|
line.long 0x00 "CRSR_IMG152,Cursor Image Register 152"
|
|
group.long 0xA64++0x3
|
|
line.long 0x00 "CRSR_IMG153,Cursor Image Register 153"
|
|
group.long 0xA68++0x3
|
|
line.long 0x00 "CRSR_IMG154,Cursor Image Register 154"
|
|
group.long 0xA6C++0x3
|
|
line.long 0x00 "CRSR_IMG155,Cursor Image Register 155"
|
|
group.long 0xA70++0x3
|
|
line.long 0x00 "CRSR_IMG156,Cursor Image Register 156"
|
|
group.long 0xA74++0x3
|
|
line.long 0x00 "CRSR_IMG157,Cursor Image Register 157"
|
|
group.long 0xA78++0x3
|
|
line.long 0x00 "CRSR_IMG158,Cursor Image Register 158"
|
|
group.long 0xA7C++0x3
|
|
line.long 0x00 "CRSR_IMG159,Cursor Image Register 159"
|
|
group.long 0xA80++0x3
|
|
line.long 0x00 "CRSR_IMG160,Cursor Image Register 160"
|
|
group.long 0xA84++0x3
|
|
line.long 0x00 "CRSR_IMG161,Cursor Image Register 161"
|
|
group.long 0xA88++0x3
|
|
line.long 0x00 "CRSR_IMG162,Cursor Image Register 162"
|
|
group.long 0xA8C++0x3
|
|
line.long 0x00 "CRSR_IMG163,Cursor Image Register 163"
|
|
group.long 0xA90++0x3
|
|
line.long 0x00 "CRSR_IMG164,Cursor Image Register 164"
|
|
group.long 0xA94++0x3
|
|
line.long 0x00 "CRSR_IMG165,Cursor Image Register 165"
|
|
group.long 0xA98++0x3
|
|
line.long 0x00 "CRSR_IMG166,Cursor Image Register 166"
|
|
group.long 0xA9C++0x3
|
|
line.long 0x00 "CRSR_IMG167,Cursor Image Register 167"
|
|
group.long 0xAA0++0x3
|
|
line.long 0x00 "CRSR_IMG168,Cursor Image Register 168"
|
|
group.long 0xAA4++0x3
|
|
line.long 0x00 "CRSR_IMG169,Cursor Image Register 169"
|
|
group.long 0xAA8++0x3
|
|
line.long 0x00 "CRSR_IMG170,Cursor Image Register 170"
|
|
group.long 0xAAC++0x3
|
|
line.long 0x00 "CRSR_IMG171,Cursor Image Register 171"
|
|
group.long 0xAB0++0x3
|
|
line.long 0x00 "CRSR_IMG172,Cursor Image Register 172"
|
|
group.long 0xAB4++0x3
|
|
line.long 0x00 "CRSR_IMG173,Cursor Image Register 173"
|
|
group.long 0xAB8++0x3
|
|
line.long 0x00 "CRSR_IMG174,Cursor Image Register 174"
|
|
group.long 0xABC++0x3
|
|
line.long 0x00 "CRSR_IMG175,Cursor Image Register 175"
|
|
group.long 0xAC0++0x3
|
|
line.long 0x00 "CRSR_IMG176,Cursor Image Register 176"
|
|
group.long 0xAC4++0x3
|
|
line.long 0x00 "CRSR_IMG177,Cursor Image Register 177"
|
|
group.long 0xAC8++0x3
|
|
line.long 0x00 "CRSR_IMG178,Cursor Image Register 178"
|
|
group.long 0xACC++0x3
|
|
line.long 0x00 "CRSR_IMG179,Cursor Image Register 179"
|
|
group.long 0xAD0++0x3
|
|
line.long 0x00 "CRSR_IMG180,Cursor Image Register 180"
|
|
group.long 0xAD4++0x3
|
|
line.long 0x00 "CRSR_IMG181,Cursor Image Register 181"
|
|
group.long 0xAD8++0x3
|
|
line.long 0x00 "CRSR_IMG182,Cursor Image Register 182"
|
|
group.long 0xADC++0x3
|
|
line.long 0x00 "CRSR_IMG183,Cursor Image Register 183"
|
|
group.long 0xAE0++0x3
|
|
line.long 0x00 "CRSR_IMG184,Cursor Image Register 184"
|
|
group.long 0xAE4++0x3
|
|
line.long 0x00 "CRSR_IMG185,Cursor Image Register 185"
|
|
group.long 0xAE8++0x3
|
|
line.long 0x00 "CRSR_IMG186,Cursor Image Register 186"
|
|
group.long 0xAEC++0x3
|
|
line.long 0x00 "CRSR_IMG187,Cursor Image Register 187"
|
|
group.long 0xAF0++0x3
|
|
line.long 0x00 "CRSR_IMG188,Cursor Image Register 188"
|
|
group.long 0xAF4++0x3
|
|
line.long 0x00 "CRSR_IMG189,Cursor Image Register 189"
|
|
group.long 0xAF8++0x3
|
|
line.long 0x00 "CRSR_IMG190,Cursor Image Register 190"
|
|
group.long 0xAFC++0x3
|
|
line.long 0x00 "CRSR_IMG191,Cursor Image Register 191"
|
|
group.long 0xB00++0x3
|
|
line.long 0x00 "CRSR_IMG192,Cursor Image Register 192"
|
|
group.long 0xB04++0x3
|
|
line.long 0x00 "CRSR_IMG193,Cursor Image Register 193"
|
|
group.long 0xB08++0x3
|
|
line.long 0x00 "CRSR_IMG194,Cursor Image Register 194"
|
|
group.long 0xB0C++0x3
|
|
line.long 0x00 "CRSR_IMG195,Cursor Image Register 195"
|
|
group.long 0xB10++0x3
|
|
line.long 0x00 "CRSR_IMG196,Cursor Image Register 196"
|
|
group.long 0xB14++0x3
|
|
line.long 0x00 "CRSR_IMG197,Cursor Image Register 197"
|
|
group.long 0xB18++0x3
|
|
line.long 0x00 "CRSR_IMG198,Cursor Image Register 198"
|
|
group.long 0xB1C++0x3
|
|
line.long 0x00 "CRSR_IMG199,Cursor Image Register 199"
|
|
group.long 0xB20++0x3
|
|
line.long 0x00 "CRSR_IMG200,Cursor Image Register 200"
|
|
group.long 0xB24++0x3
|
|
line.long 0x00 "CRSR_IMG201,Cursor Image Register 201"
|
|
group.long 0xB28++0x3
|
|
line.long 0x00 "CRSR_IMG202,Cursor Image Register 202"
|
|
group.long 0xB2C++0x3
|
|
line.long 0x00 "CRSR_IMG203,Cursor Image Register 203"
|
|
group.long 0xB30++0x3
|
|
line.long 0x00 "CRSR_IMG204,Cursor Image Register 204"
|
|
group.long 0xB34++0x3
|
|
line.long 0x00 "CRSR_IMG205,Cursor Image Register 205"
|
|
group.long 0xB38++0x3
|
|
line.long 0x00 "CRSR_IMG206,Cursor Image Register 206"
|
|
group.long 0xB3C++0x3
|
|
line.long 0x00 "CRSR_IMG207,Cursor Image Register 207"
|
|
group.long 0xB40++0x3
|
|
line.long 0x00 "CRSR_IMG208,Cursor Image Register 208"
|
|
group.long 0xB44++0x3
|
|
line.long 0x00 "CRSR_IMG209,Cursor Image Register 209"
|
|
group.long 0xB48++0x3
|
|
line.long 0x00 "CRSR_IMG210,Cursor Image Register 210"
|
|
group.long 0xB4C++0x3
|
|
line.long 0x00 "CRSR_IMG211,Cursor Image Register 211"
|
|
group.long 0xB50++0x3
|
|
line.long 0x00 "CRSR_IMG212,Cursor Image Register 212"
|
|
group.long 0xB54++0x3
|
|
line.long 0x00 "CRSR_IMG213,Cursor Image Register 213"
|
|
group.long 0xB58++0x3
|
|
line.long 0x00 "CRSR_IMG214,Cursor Image Register 214"
|
|
group.long 0xB5C++0x3
|
|
line.long 0x00 "CRSR_IMG215,Cursor Image Register 215"
|
|
group.long 0xB60++0x3
|
|
line.long 0x00 "CRSR_IMG216,Cursor Image Register 216"
|
|
group.long 0xB64++0x3
|
|
line.long 0x00 "CRSR_IMG217,Cursor Image Register 217"
|
|
group.long 0xB68++0x3
|
|
line.long 0x00 "CRSR_IMG218,Cursor Image Register 218"
|
|
group.long 0xB6C++0x3
|
|
line.long 0x00 "CRSR_IMG219,Cursor Image Register 219"
|
|
group.long 0xB70++0x3
|
|
line.long 0x00 "CRSR_IMG220,Cursor Image Register 220"
|
|
group.long 0xB74++0x3
|
|
line.long 0x00 "CRSR_IMG221,Cursor Image Register 221"
|
|
group.long 0xB78++0x3
|
|
line.long 0x00 "CRSR_IMG222,Cursor Image Register 222"
|
|
group.long 0xB7C++0x3
|
|
line.long 0x00 "CRSR_IMG223,Cursor Image Register 223"
|
|
group.long 0xB80++0x3
|
|
line.long 0x00 "CRSR_IMG224,Cursor Image Register 224"
|
|
group.long 0xB84++0x3
|
|
line.long 0x00 "CRSR_IMG225,Cursor Image Register 225"
|
|
group.long 0xB88++0x3
|
|
line.long 0x00 "CRSR_IMG226,Cursor Image Register 226"
|
|
group.long 0xB8C++0x3
|
|
line.long 0x00 "CRSR_IMG227,Cursor Image Register 227"
|
|
group.long 0xB90++0x3
|
|
line.long 0x00 "CRSR_IMG228,Cursor Image Register 228"
|
|
group.long 0xB94++0x3
|
|
line.long 0x00 "CRSR_IMG229,Cursor Image Register 229"
|
|
group.long 0xB98++0x3
|
|
line.long 0x00 "CRSR_IMG230,Cursor Image Register 230"
|
|
group.long 0xB9C++0x3
|
|
line.long 0x00 "CRSR_IMG231,Cursor Image Register 231"
|
|
group.long 0xBA0++0x3
|
|
line.long 0x00 "CRSR_IMG232,Cursor Image Register 232"
|
|
group.long 0xBA4++0x3
|
|
line.long 0x00 "CRSR_IMG233,Cursor Image Register 233"
|
|
group.long 0xBA8++0x3
|
|
line.long 0x00 "CRSR_IMG234,Cursor Image Register 234"
|
|
group.long 0xBAC++0x3
|
|
line.long 0x00 "CRSR_IMG235,Cursor Image Register 235"
|
|
group.long 0xBB0++0x3
|
|
line.long 0x00 "CRSR_IMG236,Cursor Image Register 236"
|
|
group.long 0xBB4++0x3
|
|
line.long 0x00 "CRSR_IMG237,Cursor Image Register 237"
|
|
group.long 0xBB8++0x3
|
|
line.long 0x00 "CRSR_IMG238,Cursor Image Register 238"
|
|
group.long 0xBBC++0x3
|
|
line.long 0x00 "CRSR_IMG239,Cursor Image Register 239"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x00 "CRSR_IMG240,Cursor Image Register 240"
|
|
group.long 0xBC4++0x3
|
|
line.long 0x00 "CRSR_IMG241,Cursor Image Register 241"
|
|
group.long 0xBC8++0x3
|
|
line.long 0x00 "CRSR_IMG242,Cursor Image Register 242"
|
|
group.long 0xBCC++0x3
|
|
line.long 0x00 "CRSR_IMG243,Cursor Image Register 243"
|
|
group.long 0xBD0++0x3
|
|
line.long 0x00 "CRSR_IMG244,Cursor Image Register 244"
|
|
group.long 0xBD4++0x3
|
|
line.long 0x00 "CRSR_IMG245,Cursor Image Register 245"
|
|
group.long 0xBD8++0x3
|
|
line.long 0x00 "CRSR_IMG246,Cursor Image Register 246"
|
|
group.long 0xBDC++0x3
|
|
line.long 0x00 "CRSR_IMG247,Cursor Image Register 247"
|
|
group.long 0xBE0++0x3
|
|
line.long 0x00 "CRSR_IMG248,Cursor Image Register 248"
|
|
group.long 0xBE4++0x3
|
|
line.long 0x00 "CRSR_IMG249,Cursor Image Register 249"
|
|
group.long 0xBE8++0x3
|
|
line.long 0x00 "CRSR_IMG250,Cursor Image Register 250"
|
|
group.long 0xBEC++0x3
|
|
line.long 0x00 "CRSR_IMG251,Cursor Image Register 251"
|
|
group.long 0xBF0++0x3
|
|
line.long 0x00 "CRSR_IMG252,Cursor Image Register 252"
|
|
group.long 0xBF4++0x3
|
|
line.long 0x00 "CRSR_IMG253,Cursor Image Register 253"
|
|
group.long 0xBF8++0x3
|
|
line.long 0x00 "CRSR_IMG254,Cursor Image Register 254"
|
|
group.long 0xBFC++0x3
|
|
line.long 0x00 "CRSR_IMG255,Cursor Image Register 255"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xc00++0x17
|
|
line.long 0x00 "CRSR_CTRL,Cursor Control Register"
|
|
bitfld.long 0x00 4.--5. " CrsrNum[1:0] ,Cursor image number" "Cursor0,Cursor1,Cursor2,Cursor3"
|
|
bitfld.long 0x00 0. " CrsrOn ,Cursor enable" "Not displayed,Displayed"
|
|
line.long 0x04 "CRSR_CFG,Cursor Configuration Register"
|
|
bitfld.long 0x04 1. " FrameSync ,Cursor frame synchronization type" "Asynchronous,Synchronized"
|
|
bitfld.long 0x04 0. " CrsrSize ,Cursor size selection" "32x32,64x64"
|
|
line.long 0x08 "CRSR_PAL0,Cursor Palette Register 0"
|
|
hexmask.long.byte 0x08 16.--23. 1. " Blue ,Blue color component"
|
|
hexmask.long.byte 0x08 8.--15. 1. " Green ,Green color component"
|
|
hexmask.long.byte 0x08 0.--7. 1. " Red ,Red color component"
|
|
line.long 0x0c "CRSR_PAL1,Cursor Palette Register 1"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " Blue ,Blue color component"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " Green ,Green color component"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " Red ,Red color component"
|
|
line.long 0x10 "CRSR_XY,Cursor XY Position Register"
|
|
hexmask.long.word 0x10 16.--25. 1. " CrsrY ,Y ordinate of the cursor origin measured in pixels"
|
|
hexmask.long.word 0x10 0.--9. 1. " CrsrX ,X ordinate of the cursor origin measured in pixels"
|
|
line.long 0x14 "CRSR_CLIP,Cursor Clip Position Register"
|
|
hexmask.long.byte 0x14 8.--13. 1. " CrsrClipY ,Cursor clip position for Y direction"
|
|
hexmask.long.byte 0x14 0.--5. 1. " CrsrClipX ,Cursor clip position for X direction"
|
|
group.long 0xc20++0x3
|
|
line.long 0x00 "CRSR_INTMSK,Cursor Interrupt Mask Register"
|
|
bitfld.long 0x00 0. " CrsrIM ,Cursor interrupt mask" "Disabled,Enabled"
|
|
group.long 0xc28++0x7
|
|
line.long 0x00 "CRSR_INTRAW,Cursor Raw Interrupt Status Register"
|
|
setclrfld.long 0x00 0. 0x00 0. -0x4 0. " CrsrRIS_set/clr ,Cursor raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "CRSR_INTSTAT,Cursor Masked Interrupt Status Register"
|
|
setclrfld.long 0x04 0. 0x04 0. -0x8 0. " CrsrMIS_set/clr ,Cursor masked interrupt status" "Not masked,Masked"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "TSC (Touch Screen Controller)"
|
|
base ad:0x40048000
|
|
width 12.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "ADC_STAT,A/D Status Register"
|
|
bitfld.long 0x00 8. " TS_FIFO_OVERRUN ,Overrun status on TS FIFO" "No overrun,Overrun"
|
|
bitfld.long 0x00 7. " TS_FIFO_EMPTY ,Empty status on TS FIFO" "Not empty,Empty"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "ADC_SELECT,A/D Select State Register"
|
|
bitfld.long 0x00 8.--9. " TS_Ref- ," "TS_XM,TS_YM,Vss,?..."
|
|
bitfld.long 0x00 6.--7. " TS_Ref+ ," "TS_XP,TS_YP,VDDTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TS_IN ,Selects the input TS ADC" "TS_YM,TS_XM,TS_AUX,?..."
|
|
bitfld.long 0x00 3. " TS_YMC ,YM Control" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TS_YPC ,YP Control" "Disconnected,Connected"
|
|
bitfld.long 0x00 1. " TS_XMC ,XM Control" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TS_XPC ,XP Control" "Disconnected,Connected"
|
|
line.long 0x04 "ADC_CTRL,A/D Control Register"
|
|
bitfld.long 0x04 11.--12. " TS_FIFO_CTRL ,Set the level in the FIFO to trig the TSC_IRQ" "1,4,8,16"
|
|
bitfld.long 0x04 10. " TS_AUX_EN ,AUX ANALOG measure in auto mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7.--9. " TS_X_ACC ,Number of bits delivered by the ADC for all modes doing X direction measurement" "10 bits,9 bits,8 bits,7 bits,6 bits,5 bits,4 bits,3 bits"
|
|
bitfld.long 0x04 4.--6. " TS_Y_ACC ,Number of bits delivered by the ADC for all modes doing Y direction measurement." "10 bits,9 bits,8 bits,7 bits,6 bits,5 bits,4 bits,3 bits"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TS_POS_DET ,Auto mode" "Normal,Position detect"
|
|
bitfld.long 0x04 2. " TS_ADC_PDN_CTRL ,ADC power control" "Power down,Powered up"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TS_ADC_STROBE ,AD conversion" "No effect,Start"
|
|
bitfld.long 0x04 0. " TS_AUTO_EN ,Touch screen controller enable" "Disabled,Enabled"
|
|
width 17.
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "TSC_SAMPLE_FIFO,Touchscreen controller sample FIFO register"
|
|
bitfld.long 0x00 31. " TSC_P_LEVEL , Touch Screen press" "Pressed,Not pressed"
|
|
bitfld.long 0x00 30. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FIFO_OVERRUN ,FIFO Overrun" "No overrun,Overrun"
|
|
hexmask.long.word 0x00 16.--25. 1. " TS_X_VALUE ,The ADC value of the X co-ordinate"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " ADC_VALUE ,The ADC value of the Y co-ordinate"
|
|
group.long 0x10++0x2F
|
|
line.long 0x00 "TSC_DTR,Touchscreen controller Delay Time register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " TSC_DTR ,TS Controller Delay Time Register"
|
|
line.long 0x04 "TSC_RTR,Touchscreen controller Rise Time register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " TSC_RTR ,Touch Screen Controller rise time"
|
|
line.long 0x08 "TSC_UTR,Touchscreen controller Update Time register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " TSC_UTR ,Touch Screen Controller update time"
|
|
line.long 0x0C "TSC_TTR,Touchscreen controller Delay Time Register"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " TSC_TTR ,Controller touch time"
|
|
line.long 0x10 "TSC_DXP,Touchscreen controller Drain X Plate Time Register"
|
|
hexmask.long.tbyte 0x10 0.--19. 1. " TSC_DXP ,TS Controller Drain X Plate time"
|
|
line.long 0x14 "TSC_MIN_X,Touchscreen controller Minimum X value Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " TSC_MIN_X ,TS Controller Minimum X value"
|
|
line.long 0x18 "TSC_MAX_X,TS Controller Maximum X value"
|
|
hexmask.long.word 0x18 0.--9. 1. " TSC_MAX_X ,TS Controller Minimum X value"
|
|
line.long 0x1C "TSC_MIN_Y,Touchscreen controller Minimum Y value Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " TSC_MIN_Y ,TS Controller Minimum Y value"
|
|
line.long 0x20 "TSC_MAX_Y,Touchscreen controller Maximum Y value Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " TSC_MAX_Y ,TS Controller Maximum Y value"
|
|
line.long 0x24 "TSC_AUX_UTR,Touchscreen controller AUX Update Time Register"
|
|
line.long 0x28 "TSC_AUX_MIN,Touchscreen controller AUX Minimum value Register"
|
|
hexmask.long.word 0x28 0.--9. 1. " TSC_MAX_Y ,TS Controller Maximum Y value"
|
|
line.long 0x2C "TSC_AUX_MAX,Touchscreen controller AUX Maximum value Register"
|
|
hexmask.long.word 0x2C 0.--9. 1. " TSC_AUX_MAX ,TS Controller Maximum Auxiliary ADC value"
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "TSC_AUX_VALUE,Touchscreen controller AUX Value Register"
|
|
in
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "ADC_VALUE,Touchscreen controller ADC Value Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "ADC (Analog/Digital Converter)"
|
|
base ad:0x40048000
|
|
width 12.
|
|
group.long 0x04++0x7
|
|
line.long 0x0 "ADC_SELECT,A/D Select Register"
|
|
bitfld.long 0x0 8.--9. " AD_Ref- ,A/D negative reference voltage" "Reserved,Reserved,VSS_AD,?..."
|
|
bitfld.long 0x0 6.--7. " AD_Ref+ ,A/D positive reference voltage" "Reserved,Reserved,VDD_AD,?..."
|
|
bitfld.long 0x0 4.--5. " AD_IN ,A/D input select" "ADIN0,ADIN1,ADIN2,?..."
|
|
line.long 0x4 "ADCON,A/D Control Register"
|
|
bitfld.long 0x4 2. " AD_PDN_CTRL ,ADC power" "Powered down,Powered up"
|
|
bitfld.long 0x4 1. " AD_STROBE ,A/D conversion start" "No effect,Started"
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x0 "ADDAT,A/D Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "Keyboard Scan"
|
|
base ad:0x40050000
|
|
width 15.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "KS_DEB,Keypad De-bouncing Duration Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " DURATION ,Keypad de-bouncing duration"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "KS_STATE_COND,Keypad State Machine Current State Register"
|
|
bitfld.long 0x0 0.--1. " STATE ,State" "Idle,Scan Once,IRQ generation,Scan Matrix"
|
|
group.long 0x08++0xF
|
|
line.long 0x0 "KS_IRQ,Keypad Interrupt Register"
|
|
bitfld.long 0x0 0. " KIRQN ,Active interrupt" "Interrupt,No interrupt"
|
|
line.long 0x4 "KS_SCAN_CTL,Keypad Scan Delay Control Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " SCN_CTL ,Time between each keypad scan in STATE: Scan Matrix"
|
|
line.long 0x8 "KS_FAST_TST,Keypad Scan Clock Control Register"
|
|
bitfld.long 0x8 0. " JUMP ,Jump to" "No jump,STATE: Scan Once"
|
|
bitfld.long 0x8 1. " ClkSrc ,Clock Source" "Reserved,32 KHz RTC"
|
|
line.long 0xC "KS_MATRIX_DIM,Keypad Matrix Dimension Select Register"
|
|
bitfld.long 0xC 0.--3. " MX_DIM ,Matrix dimension" "Reserved,1 x 1,Reserved,Reserved,Reserved,Reserved,6 x 6,Reserved,8 x 8,?..."
|
|
rgroup.long 0x40++0x1F
|
|
line.long 0x0 "KS_DATA0,Keypad Data Register 0"
|
|
bitfld.long 0x0 7. " KEY_R0_C7 ,Key state of Column 7 on Row 0" "Low,High"
|
|
bitfld.long 0x0 6. " KEY_R0_C6 ,Key state of Column 6 on Row 0" "Low,High"
|
|
bitfld.long 0x0 5. " KEY_R0_C5 ,Key state of Column 5 on Row 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " KEY_R0_C4 ,Key state of Column 4 on Row 0" "Low,High"
|
|
bitfld.long 0x0 3. " KEY_R0_C3 ,Key state of Column 3 on Row 0" "Low,High"
|
|
bitfld.long 0x0 2. " KEY_R0_C2 ,Key state of Column 2 on Row 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " KEY_R0_C1 ,Key state of Column 1 on Row 0" "Low,High"
|
|
bitfld.long 0x0 0. " KEY_R0_C0 ,Key state of Column 0 on Row 0" "Low,High"
|
|
line.long 0x4 "KS_DATA1,Keypad Data Register 1"
|
|
bitfld.long 0x4 7. " KEY_R1_C7 ,Key state of Column 7 on Row 1" "Low,High"
|
|
bitfld.long 0x4 6. " KEY_R1_C6 ,Key state of Column 6 on Row 1" "Low,High"
|
|
bitfld.long 0x4 5. " KEY_R1_C5 ,Key state of Column 5 on Row 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 4. " KEY_R1_C4 ,Key state of Column 4 on Row 1" "Low,High"
|
|
bitfld.long 0x4 3. " KEY_R1_C3 ,Key state of Column 3 on Row 1" "Low,High"
|
|
bitfld.long 0x4 2. " KEY_R1_C2 ,Key state of Column 2 on Row 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 1. " KEY_R1_C1 ,Key state of Column 1 on Row 1" "Low,High"
|
|
bitfld.long 0x4 0. " KEY_R1_C0 ,Key state of Column 0 on Row 1" "Low,High"
|
|
line.long 0x8 "KS_DATA2,Keypad Data Register 2"
|
|
bitfld.long 0x8 7. " KEY_R2_C7 ,Key state of Column 7 on Row 2" "Low,High"
|
|
bitfld.long 0x8 6. " KEY_R2_C6 ,Key state of Column 6 on Row 2" "Low,High"
|
|
bitfld.long 0x8 5. " KEY_R2_C5 ,Key state of Column 5 on Row 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 4. " KEY_R2_C4 ,Key state of Column 4 on Row 2" "Low,High"
|
|
bitfld.long 0x8 3. " KEY_R2_C3 ,Key state of Column 3 on Row 2" "Low,High"
|
|
bitfld.long 0x8 2. " KEY_R2_C2 ,Key state of Column 2 on Row 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 1. " KEY_R2_C1 ,Key state of Column 1 on Row 2" "Low,High"
|
|
bitfld.long 0x8 0. " KEY_R2_C0 ,Key state of Column 0 on Row 2" "Low,High"
|
|
line.long 0xC "KS_DATA3,Keypad Data Register 3"
|
|
bitfld.long 0xC 7. " KEY_R3_C7 ,Key state of Column 7 on Row 3" "Low,High"
|
|
bitfld.long 0xC 6. " KEY_R3_C6 ,Key state of Column 6 on Row 3" "Low,High"
|
|
bitfld.long 0xC 5. " KEY_R3_C5 ,Key state of Column 5 on Row 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 4. " KEY_R3_C4 ,Key state of Column 4 on Row 3" "Low,High"
|
|
bitfld.long 0xC 3. " KEY_R3_C3 ,Key state of Column 3 on Row 3" "Low,High"
|
|
bitfld.long 0xC 2. " KEY_R3_C2 ,Key state of Column 2 on Row 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 1. " KEY_R3_C1 ,Key state of Column 1 on Row 3" "Low,High"
|
|
bitfld.long 0xC 0. " KEY_R3_C0 ,Key state of Column 0 on Row 3" "Low,High"
|
|
line.long 0x10 "KS_DATA4,Keypad Data Register 4"
|
|
bitfld.long 0x10 7. " KEY_R4_C7 ,Key state of Column 7 on Row 4" "Low,High"
|
|
bitfld.long 0x10 6. " KEY_R4_C6 ,Key state of Column 6 on Row 4" "Low,High"
|
|
bitfld.long 0x10 5. " KEY_R4_C5 ,Key state of Column 5 on Row 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 4. " KEY_R4_C4 ,Key state of Column 4 on Row 4" "Low,High"
|
|
bitfld.long 0x10 3. " KEY_R4_C3 ,Key state of Column 3 on Row 4" "Low,High"
|
|
bitfld.long 0x10 2. " KEY_R4_C2 ,Key state of Column 2 on Row 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 1. " KEY_R4_C1 ,Key state of Column 1 on Row 4" "Low,High"
|
|
bitfld.long 0x10 0. " KEY_R4_C0 ,Key state of Column 0 on Row 4" "Low,High"
|
|
line.long 0x14 "KS_DATA5,Keypad Data Register 5"
|
|
bitfld.long 0x14 7. " KEY_R5_C7 ,Key state of Column 7 on Row 5" "Low,High"
|
|
bitfld.long 0x14 6. " KEY_R5_C6 ,Key state of Column 6 on Row 5" "Low,High"
|
|
bitfld.long 0x14 5. " KEY_R5_C5 ,Key state of Column 5 on Row 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 4. " KEY_R5_C4 ,Key state of Column 4 on Row 5" "Low,High"
|
|
bitfld.long 0x14 3. " KEY_R5_C3 ,Key state of Column 3 on Row 5" "Low,High"
|
|
bitfld.long 0x14 2. " KEY_R5_C2 ,Key state of Column 2 on Row 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 1. " KEY_R5_C1 ,Key state of Column 1 on Row 5" "Low,High"
|
|
bitfld.long 0x14 0. " KEY_R5_C0 ,Key state of Column 0 on Row 5" "Low,High"
|
|
line.long 0x18 "KS_DATA6,Keypad Data Register 6"
|
|
bitfld.long 0x18 7. " KEY_R6_C7 ,Key state of Column 7 on Row 6" "Low,High"
|
|
bitfld.long 0x18 6. " KEY_R6_C6 ,Key state of Column 6 on Row 6" "Low,High"
|
|
bitfld.long 0x18 5. " KEY_R6_C5 ,Key state of Column 5 on Row 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 4. " KEY_R6_C4 ,Key state of Column 4 on Row 6" "Low,High"
|
|
bitfld.long 0x18 3. " KEY_R6_C3 ,Key state of Column 3 on Row 6" "Low,High"
|
|
bitfld.long 0x18 2. " KEY_R6_C2 ,Key state of Column 2 on Row 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 1. " KEY_R6_C1 ,Key state of Column 1 on Row 6" "Low,High"
|
|
bitfld.long 0x18 0. " KEY_R6_C0 ,Key state of Column 0 on Row 6" "Low,High"
|
|
line.long 0x1C "KS_DATA7,Keypad Data Register 7"
|
|
bitfld.long 0x1C 7. " KEY_R7_C7 ,Key state of Column 7 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 6. " KEY_R7_C6 ,Key state of Column 6 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 5. " KEY_R7_C5 ,Key state of Column 5 on Row 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " KEY_R7_C4 ,Key state of Column 4 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 3. " KEY_R7_C3 ,Key state of Column 3 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 2. " KEY_R7_C2 ,Key state of Column 2 on Row 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " KEY_R7_C1 ,Key state of Column 1 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 0. " KEY_R7_C0 ,Key state of Column 0 on Row 7" "Low,High"
|
|
width 0xB
|
|
tree.end
|
|
sif (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
tree "Ethernet Controller"
|
|
base sd:0x31060000
|
|
width 0x6
|
|
tree "MAC registers"
|
|
if (((data.long(ad:(0x31060000+0xFF4)))&0x80000000)==0x00000000)
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "MAC1,MAC configuration register 1"
|
|
bitfld.long 0x00 15. " SOFTRESET ,All modules within the MAC reset except the Host Interface" "No reset,Reset"
|
|
bitfld.long 0x00 14. " SIMULATIONRESET ,Reset random number generator within the Transmit Function" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RESETMCS/RX ,Reset the MAC Control Sublayer / Receive logic" "No reset,Reset"
|
|
bitfld.long 0x00 10. " RESETRX ,Ethernet receive logic reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RESETMCS/TX ,Reset the MAC Control Sublayer / Transmit logic" "No reset,Reset"
|
|
bitfld.long 0x00 8. " RESETTX ,Transmit Function logic reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPBACK ,MAC Transmit interface loop back to the MAC Receive interface" "Normal,Looped"
|
|
bitfld.long 0x00 3. " TXFLOWCONTROL ,PAUSE Flow Control frames transmission enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXFLOWCONTROL ,MAC received PAUSE Flow Control frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PASSALLRECEIVEFRAMES ,MAC pass all frames regardless of type" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RECEIVEENABLE ,Allow receive frames to be received" "Not allowed,Allowed"
|
|
line.long 0x4 "MAC2,MAC configuration register 2"
|
|
bitfld.long 0x04 14. " EXCESSDEFER ,MAC defer to carrier indefinitely as per the Standard" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " BACKPRESSURE/NOBACKOFF ,Immediately retransmit without backoff after the MAC incidentally causes a collision during back pressure" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " NOBACKOFF ,MAC immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LONGPREAMBLEENFORCEMENT ,MAC only allow receive packets which contain preamble fields less than 12 bytes in length" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PUREPREAMBLEENFORCEMENT ,MAC verify the content of the preamble to ensure it contains 0x55 and is error-free" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " AUTODETECTPADENABLE ,MAC automatically detect the type of frame by comparing the two octets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VLANPADENABLE ,MAC pad all short frames to 64 bytes and append a valid CRC" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PAD/CRCENABLE ,MAC pad all short frames" "Not padded,Padded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CRCENABLE ,Append a CRC to every frame whether padding was required or not" "Not appended,Appended"
|
|
bitfld.long 0x04 3. " DELAYEDCRC ,Number of bytes (if any) of proprietary header information that exist on the front of IEEE 802.3 frames" "No header,4 bytes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HUGEFRAMEENABLE ,Frames of any length transmit and receive" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " FRAMELENGTHCHECKING ,Both transmit and receive frame lengths compare to the Length/Type field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FULL-DUPLEX ,MAC Full-Duplex mode" "Disabled,Enabled"
|
|
line.long 0x8 "IPGT,Back-to-Back Inter-Packet-Gap register"
|
|
hexmask.long.byte 0x8 0.--6. 1. " BACK-TO-BACKINTER-PACKET-GAP ,Nibble time offset of the minimum possible period"
|
|
line.long 0xC "IPGR,Non Back-to-Back Inter-Packet-Gap register"
|
|
hexmask.long.byte 0xC 8.--14. 1. " NON-BACK-TO-BACK-INTER-PACKET-GAP_PART1 ,Optional carrierSense window"
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--6. 1. " NON-BACK-TO-BACK-INTER-PACKET-GAP_PART2 ,Non-Back-to-Back Inter-Packet-Gap"
|
|
line.long 0x10 "CLRT,Collision window / Retry register"
|
|
hexmask.long.byte 0x10 8.--13. 1. " COLLISIONWINDOW ,Slot time or collision window during which collisions occur in properly configured networks"
|
|
bitfld.long 0x10 0.--3. " RETRANSMISSIONMAXIMUM ,Number of retransmission attempts following a collision before aborting the packet due to excessive collisions" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15."
|
|
line.long 0x14 "MAXF,Maximum Frame register"
|
|
hexmask.long.word 0x14 0.--15. 1. " MAXIMUMFRAMELENGTH ,Maximum receive frame"
|
|
line.long 0x18 "SUPP,PHY Support register"
|
|
bitfld.long 0x18 8. " SPEED ,Configure the Reduced MII logic for the current operating speed" "10 Mbps,100 Mbps"
|
|
line.long 0x1C "TEST,Test register"
|
|
bitfld.long 0x1C 2. " TESTBACKPRESSURE ,MAC assert backpressure on the link" "Not asserted,Asserted"
|
|
bitfld.long 0x1C 1. " TESTPAUSE ,MAC Control sublayer inhibit transmissions" "Not inhibited,Inhibited"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " SHORTCUTPAUSEQUANTA ,Reduce the effective PAUSE quanta from 64 byte-times to 1 byte-time" "Not reduced,Reduced"
|
|
line.long 0x20 "MCFG,MII Mgmt Configuration register"
|
|
bitfld.long 0x20 15. " RESETMIIMGMT ,Reset the MII Management hardware" "No reset,Reset"
|
|
bitfld.long 0x20 2.--4. " CLOCKSELECT ,MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz" "Clock/4,Clock/4,Clock/6,Clock/8,Clock/10,Clock/14,Clock/20,Clock/28"
|
|
textline " "
|
|
bitfld.long 0x20 1. " SUPPRESSPREAMBLE ,MII Management hardware perform read/write cycles without the 32 bit preamble field" "Not performed,Performed"
|
|
bitfld.long 0x20 0. " SCANINCREMENT ,MII Management hardware perform read cycles across a range of PHYs" "Not performed,Performed"
|
|
line.long 0x24 "MCMD,MII Mgmt Command register"
|
|
bitfld.long 0x24 1. " SCAN ,MII Management hardware perform Read cycles continuously" "Not performed,Performed"
|
|
bitfld.long 0x24 0. " READ ,MII Management hardware perform a single Read cycle" "Not performed,Performed"
|
|
line.long 0x28 "MADR,MII Mgmt Address register"
|
|
bitfld.long 0x28 8.--12. " PHYADDRESS ,5 bit PHY Address field of Mgmt cycles" "Reserved,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
bitfld.long 0x28 0.--4. " REGISTERADDRESS ,5 bit Register Address field of Mgmt cycles" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "MWTD,MII Mgmt Write Data register"
|
|
hexmask.long.word 0x0 0.--15. 1. " WRITEDATA ,16 bit write data"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "MRDD,MII Mgmt Read Data register"
|
|
hexmask.long.word 0x0 0.--15. 1. " READDATA ,16 bit read data"
|
|
line.long 0x4 "MIND,MII Mgmt Indicators register"
|
|
bitfld.long 0x04 3. " MIILinkFail ,MII Link Fail" "Not failed,Failed"
|
|
bitfld.long 0x04 2. " NOTVALID ,Not valid" "Valid,Not valid"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SCANNING ,Scanning" "Not scanning,Scanning"
|
|
bitfld.long 0x04 0. " BUSY ,Busy" "Not busy,Busy"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "SA0,Station Address 0 register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " STATIONADDRESS1 ,First octet of the station address"
|
|
hexmask.long.byte 0x0 0.--7. 1. " STATIONADDRESS2 ,Second octet of the station address"
|
|
line.long 0x4 "SA1,Station Address 1 register"
|
|
hexmask.long.byte 0x4 8.--15. 1. " STATIONADDRESS3 ,Third octet of the station address"
|
|
hexmask.long.byte 0x4 0.--7. 1. " STATIONADDRESS4 ,Fourth octet of the station address"
|
|
line.long 0x8 "SA2,Station Address 2 register"
|
|
hexmask.long.byte 0x8 8.--15. 1. " STATIONADDRESS5 ,Fifth octet of the station address"
|
|
hexmask.long.byte 0x8 0.--7. 1. " STATIONADDRESS6 ,Sixth octet of the station address"
|
|
else
|
|
hgroup.long 0x0++0x37
|
|
hide.long 0x0 "MAC1,MAC configuration register 1"
|
|
hide.long 0x4 "MAC2,MAC configuration register 2"
|
|
hide.long 0x8 "IPGT,Back-to-Back Inter-Packet-Gap register"
|
|
hide.long 0xC "IPGR,Non Back-to-Back Inter-Packet-Gap register"
|
|
hide.long 0x10 "CLRT,Collision window / Retry register"
|
|
hide.long 0x14 "MAXF,Maximum Frame register"
|
|
hide.long 0x18 "SUPP,PHY Support register"
|
|
hide.long 0x1C "TEST,Test register"
|
|
hide.long 0x20 "MCFG,MII Mgmt Configuration register"
|
|
hide.long 0x24 "MCMD,MII Mgmt Command register"
|
|
hide.long 0x28 "MADR,MII Mgmt Address register"
|
|
hide.long 0x2C "MWTD,MII Mgmt Write Data register"
|
|
hide.long 0x30 "MRDD,MII Mgmt Read Data register"
|
|
hide.long 0x34 "MIND,MII Mgmt Indicators register"
|
|
hgroup.long 0x40++0xB
|
|
hide.long 0x0 "SA0,Station Address 0 register"
|
|
hide.long 0x4 "SA1,Station Address 1 register"
|
|
hide.long 0x8 "SA2,Station Address 2 register"
|
|
endif
|
|
tree.end
|
|
width 0x14
|
|
tree "Control registers"
|
|
if (((data.long(ad:(0x31060000+0xFF4)))&0x80000000)==0x00000000)
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "Command,Command register"
|
|
bitfld.long 0x00 10. " FullDuplex ,Full duplex operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMII ,Mode selection" "MII,RMII"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TxFlowControl ,Enable IEEE 802.3 / clause 31 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PassRxFilter ,Disable receive filtering" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PassRuntFrame ,Pass Runt Frame" "Filtered out,Passed"
|
|
bitfld.long 0x00 5. " RxReset ,Receive datapath reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TxReset ,Transmit datapath reset" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RegReset ,All datapaths and the host registers reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TxEnable ,Enable transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RxEnable ,Enable receive" "Disabled,Enabled"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x0 "Status,Status register"
|
|
bitfld.long 0x0 1. " TxStatus ,Transmit channel active" "Inactive,Active"
|
|
bitfld.long 0x0 0. " RxStatus ,Receive channel active" "Inactive,Active"
|
|
group.long 0x108++0xB
|
|
line.long 0x0 "RxDescriptor,Receive descriptor base address register"
|
|
hexmask.long 0x0 2.--31. 0x4 " RxDescriptor ,MSBs of receive descriptor base address"
|
|
line.long 0x4 "RxStatus,Receive status base address register"
|
|
hexmask.long 0x4 3.--31. 0x8 " RxStatus ,MSBs of receive status base address"
|
|
line.long 0x8 "RxDescriptorNumber,Receive number of descriptors register"
|
|
hexmask.long.word 0x8 0.--15. 1. " RxDescriptorNumber ,Number of descriptors in the descriptor array for which RxDescriptor is the base address"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x0 "RxProduceIndex,Receive produce index register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RxProduceIndex ,Index of the descriptor that is going to be filled next by the receive datapath"
|
|
group.long 0x118++0x13
|
|
line.long 0x0 "RxConsumeIndex,Receive consume index register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RxConsumeIndex ,Index of the descriptor that is going to be processed next by the receive"
|
|
line.long 0x4 "TxDescriptor,Transmit descriptor base address register"
|
|
hexmask.long 0x4 2.--31. 0x4 " TxDescriptor ,MSBs of transmit descriptor base address"
|
|
line.long 0x8 "TxStatus,Transmit status base address register"
|
|
hexmask.long 0x8 2.--31. 0x4 " TxStatus ,MSBs of transmit status base address"
|
|
line.long 0xC "TxDescriptorNumber,Transmit number of descriptors register"
|
|
hexmask.long.word 0xC 0.--15. 1. " TxDescriptorNumber ,Number of descriptors in the descriptor array for which TxDescriptor is the base address"
|
|
line.long 0x10 "TxProduceIndex,Transmit produce index register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TxProduceIndex ,Index of the descriptor that is going to be filled next by the transmit software driver"
|
|
rgroup.long 0x12C++0x3
|
|
line.long 0x0 "TxConsumeIndex,Transmit consume index register"
|
|
hexmask.long.word 0x0 0.--15. 1. " TxConsumeIndex ,Index of the descriptor that is going to be transmitted next by the transmit datapath"
|
|
rgroup.long 0x158++0xB
|
|
line.long 0x0 "TSV0,Transmit status vector 0 register"
|
|
bitfld.long 0x00 31. " VLAN ,Frame's length/type field contained 0x8100 which is the VLAN protocol identifier" "Not VLAN,VLAN"
|
|
bitfld.long 0x00 30. " Backpressure ,Carrier-sense method backpressure was previously applied" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 29. " Pause ,The frame was a control frame with a valid PAUSE opcode" "No PAUSE,PAUSE"
|
|
bitfld.long 0x00 28. " Controlframe ,The frame was a control frame" "Not control,Control"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--27. 1. " Totalbytes ,The total number of bytes transferred including collided attempts"
|
|
bitfld.long 0x00 11. " Underrun ,Host side caused buffer underrun" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x00 10. " Giant ,Byte count in frame greater than can be represented in the transmit byte count field in TSV1" "Not greater,Greater"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LateCollision ,Collision occur beyond collision window (512 bit times)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ExcessiveCollision ,Packet abort due to exceeding of maximum allowed number of collisions" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ExcessiveDefer ,Excessive Defer" "Not deferred,Deferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PacketDefer ,Packet Defer" "Not deferred,Deferred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " Broadcast ,Broadcast address" "Not broadcast,Broadcast"
|
|
textline " "
|
|
bitfld.long 0x00 4. " Multicast ,Multicast address" "Not multicast,Multicast"
|
|
textline " "
|
|
bitfld.long 0x00 3. " Done ,Transmission of packet complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOOR ,Length out of range" "In range,Out of range"
|
|
bitfld.long 0x00 1. " LCE ,Length check error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CRCerror ,CRC error" "No error,Error"
|
|
line.long 0x4 "TSV1,Transmit status vector 1 register"
|
|
bitfld.long 0x4 16.--19. " TCC ,Transmit collision count" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15."
|
|
hexmask.long.word 0x4 0.--15. 1. " TBC ,Transmit byte count"
|
|
line.long 0x8 "RSV,Receive status vector register"
|
|
bitfld.long 0x08 30. " VLAN ,Frame's length/type field contained 0x8100 which is the VLAN protocol identifier" "Not VLAN,VLAN"
|
|
textline " "
|
|
bitfld.long 0x08 29. " UnsupportedOpcode ,The current frame was recognized as a Control Frame but contains an unknown opcode" "Not unsupported,Unsupported"
|
|
textline " "
|
|
bitfld.long 0x08 28. " PAUSE ,The frame was a control frame with a valid PAUSE opcode" "No PAUSE,PAUSE"
|
|
textline " "
|
|
bitfld.long 0x08 27. " Controlframe ,The frame was a control frame" "Not control,Control"
|
|
textline " "
|
|
bitfld.long 0x08 26. " DribbleNibble ,After the end of packet another 1-7 bits were received" "No dribble nibble,Dribble nibble"
|
|
textline " "
|
|
bitfld.long 0x08 25. " Broadcast ,The packet destination was a broadcast address" "Not broadcast,Broadcast"
|
|
textline " "
|
|
bitfld.long 0x08 24. " Multicast ,The packet destination was a multicast address" "Not multicast,Multicast"
|
|
bitfld.long 0x08 23. " ReceiveOK ,The packet had valid CRC and no symbol errors" "Not OK,OK"
|
|
textline " "
|
|
bitfld.long 0x08 22. " LOOR ,Length out of range" "In range,Out of range"
|
|
bitfld.long 0x08 21. " LCE ,Length check error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CRCerror ,The attached CRC in the packet did not match the internally generated CRC" "No error,Error"
|
|
bitfld.long 0x08 19. " RCV ,Receive code violation" "Valid,Not valid"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEPS ,Carrier event previously seen" "Not seen,Seen"
|
|
bitfld.long 0x08 17. " RXDVEPS ,RXDV event previously seen" "Not seen,Seen"
|
|
textline " "
|
|
bitfld.long 0x08 16. " PPI ,Packet previously ignored" "Not dropped,Dropped"
|
|
hexmask.long.word 0x08 0.--15. 1. " RBC ,Received byte count"
|
|
group.long 0x170++0x3
|
|
line.long 0x0 "FlowControlCounter,Flow control counter register"
|
|
hexmask.long.word 0x0 16.--31. 1. " PauseTimer ,Pause Timer"
|
|
hexmask.long.word 0x0 0.--15. 1. " MirrorCounter ,Number of cycles before re-issuing the Pause control frame"
|
|
rgroup.long 0x174++0x3
|
|
line.long 0x0 "FlowControlStatus,Flow control status register"
|
|
hexmask.long.word 0x0 0.--15. 1. " MirrorCounterCurrent ,Mirror Counter Current"
|
|
else
|
|
hgroup.long 0x100++0x2F
|
|
hide.long 0x0 "Command,Command register"
|
|
hide.long 0x4 "Status,Status register"
|
|
hide.long 0x8 "RxDescriptor,Receive descriptor base address register"
|
|
hide.long 0xC "RxStatus,Receive status base address register"
|
|
hide.long 0x10 "RxDescriptorNumber,Receive number of descriptors register"
|
|
hide.long 0x14 "RxProduceIndex,Receive produce index register"
|
|
hide.long 0x18 "RxConsumeIndex,Receive consume index register"
|
|
hide.long 0x1C "TxDescriptor,Transmit descriptor base address register"
|
|
hide.long 0x20 "TxStatus,Transmit status base address register"
|
|
hide.long 0x24 "TxDescriptorNumber,Transmit number of descriptors register"
|
|
hide.long 0x28 "TxProduceIndex,Transmit produce index register"
|
|
hide.long 0x2C "TxConsumeIndex,Transmit consume index register"
|
|
hgroup.long 0x158++0xB
|
|
hide.long 0x0 "TSV0,Transmit status vector 0 register"
|
|
hide.long 0x4 "TSV1,Transmit status vector 1 register"
|
|
hide.long 0x8 "RSV,Receive status vector register"
|
|
hgroup.long 0x170++0x7
|
|
hide.long 0x0 "FlowControlCounter,Flow control counter register"
|
|
hide.long 0x4 "FlowControlStatus,Flow control status register"
|
|
endif
|
|
tree.end
|
|
width 0x13
|
|
tree "Receive filter registers"
|
|
if (((data.long(ad:(0x31060000+0xFF4)))&0x80000000)==0x00000000)
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "RxFilterCtrl,Receive filter control register"
|
|
bitfld.long 0x00 13. " RxFilterEnWoL ,Rx Filter Enable WoL" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MagicPacketEnWoL ,Magic Packet Enable WoL" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AcceptPerfectEn ,Accept Perfect Enable" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AcceptMulticastHashEn ,Accept Multicast Hash Enable" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AcceptUnicastHashEn ,Accept Unicast Hash Enable" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AcceptMulticastEn ,Accept Multicast Enable" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AcceptBroadcastEn ,Accept Broadcast Enable" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AcceptUnicastEn ,Accept Unicast Enable" "Not accepted,Accepted"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "RxFilterWoLStatus,Receive filter WoL status register"
|
|
bitfld.long 0x00 8. " MagicPacketWoL ,Magic Packet WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RxFilterWoL ,Rx Filter WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AcceptPerfectWoL ,Accept Perfect WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AcceptMulticastHashWoL ,Accept Multicast Hash WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AcceptUnicastHashWoL ,Accept Unicast Hash WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AcceptMulticastWoL ,Accept Multicast WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AcceptBroadcastWoL ,Accept Broadcast WoL" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AcceptUnicastWoL ,Accept Unicast WoL" "Not caused,Caused"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "RxFilterWoLClear,Receive filter WoL clear register"
|
|
bitfld.long 0x00 8. " MagicPacketWoLClr ,Magic Packet Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RxFilterWoLClr ,Receive Filter Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AcceptPerfectWoLClr ,Accept Perfect Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AcceptMulticastHashWoLClr ,Accept Multicast Hash Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AcceptUnicastHashWoLClr ,Accept Unicast Hash Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AcceptMulticastWoLClr ,Accept Multicast Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AcceptBroadcastWoLClr ,Accept Broadcast Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AcceptUnicastWoLClr ,Accept Unicast Wake-up on LAN Clear" "Not cleared,Cleared"
|
|
group.long 0x210++0x7
|
|
line.long 0x0 "HashFilterL,Hash filter table LSBs register"
|
|
line.long 0x4 "HashFilterH,Hash filter table MSBs register"
|
|
else
|
|
hgroup.long 0x200++0xB
|
|
hide.long 0x0 "RxFilterCtrl,Receive filter control register"
|
|
hide.long 0x4 "RxFilterWoLStatus,Receive filter WoL status register"
|
|
hide.long 0x8 "RxFilterWoLClear,Receive filter WoL clear register"
|
|
hgroup.long 0x210++0x7
|
|
hide.long 0x0 "HashFilterL,Hash filter table LSBs register"
|
|
hide.long 0x4 "HashFilterH,Hash filter table MSBs register"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree "Module control registers"
|
|
if (((data.long(ad:(0x31060000+0xFF4)))&0x80000000)==0x00000000)
|
|
group.long 0xFE0++0x3
|
|
line.long 0x0 "IntStatus,Interrupt status register"
|
|
setclrfld.long 0x00 13. 0xC 13. 0x8 13. " WakeupInt_Clear/Set ,Interrupt triggered by a Wakeup event detected by the receive filter" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0xC 12. 0x8 12. " SoftInt_Clear/Set ,Interrupt triggered by software writing a 1 to the SoftintSet bit in the IntSet register" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0xC 7. 0x8 7. " TxDoneInt_Clear/Set ,Interrupt triggered when a descriptor has been transmitted" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0xC 6. 0x8 6. " TxFinishedInt_Clear/Set ,Interrupt triggered when all transmit descriptors have been processed" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0xC 5. 0x8 5. " TxErrorInt_Clear/Set ,Interrupt trigger on transmit errors (LateCollision/ExcessiveCollision and ExcessiveDefer/NoDescriptor/Underrun)" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0xC 4. 0x8 4. " TxUnderrunInt_Clear/Set ,Interrupt set on a fatal underrun error in the transmit queue" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0xC 3. 0x8 3. " RxDoneInt_Clear/Set ,Interrupt triggered when a receive descriptor has been processed" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0xC 2. 0x8 2. " RxFinishedInt_Clear/Set ,Interrupt triggered when all receive descriptors have been processed" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0xC 1. 0x8 1. " RxErrorInt_Clear/Set ,Interrupt trigger on receive errors" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0xC 0. 0x8 0. " RxOverrunInt_Clear/Set ,Interrupt set on a fatal overrun error in the receive queue" "No interrupt,Interrupt"
|
|
group.long 0xFE4++0x3
|
|
line.long 0x0 "IntEnable,Interrupt enable register"
|
|
bitfld.long 0x00 13. " WakeupIntEn ,Enable for interrupt triggered by a Wakeup event detected by the receive filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SoftIntEn ,Enable for interrupt triggered by the SoftInt bit in the IntStatus register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TxDoneIntEn ,Enable for interrupt triggered when a descriptor has been transmitted" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TxFinishedIntEn ,Enable for interrupt triggered when all transmit descriptors have been processed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TxErrorIntEn ,Enable for interrupt trigger on transmit errors" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TxUnderrunIntEn ,Enable for interrupt trigger on transmit buffer or descriptor underrun situations" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RxDoneIntEn ,Enable for interrupt triggered when a receive descriptor has been processed" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RxFinishedIntEn ,Enable for interrupt triggered when all receive descriptors have been processed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RxErrorIntEn ,Enable for interrupt trigger on receive errors" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RxOverrunIntEn ,Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xFE0++0x7
|
|
hide.long 0x0 "IntStatus,Interrupt status register"
|
|
hide.long 0x4 "IntEnable,Interrupt enable register"
|
|
endif
|
|
group.long 0xFF4++0x3
|
|
line.long 0x0 "PowerDown,Power-down register"
|
|
bitfld.long 0x0 31. " PowerDownMACAHB ,Power Down Media Access Control AHB" "Access allowed,Access denied"
|
|
tree.end
|
|
wgroup vm:0x0++0x0
|
|
tree.end
|
|
endif
|
|
tree.open "USB Device Controller"
|
|
base ad:0x31020200
|
|
width 16.
|
|
tree "Interrupt Registers"
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "USBDevIntSt,USB Device Interrupt Status Register"
|
|
setclrfld.long 0x0 9. 0xC 9. 0x8 9. " ERR_INT_set/clr ,Error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0xC 8. 0x8 8. " EP_RLZED_set/clr ,Endpoints realized interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0xC 7. 0x8 7. " TxENDPKT_set/clr ,TxPacket length interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0xC 6. 0x8 6. " RxENDPKT_set/clr ,RxPacket length interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0xC 5. 0x8 5. " CDFULL_set/clr ,Command data register is full interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0xC 4. 0x8 4. " CCEMPTY_set/clr ,The command code register is empty interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0xC 3. 0x8 3. " DEV_STAT_set/clr ,Device state interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0xC 2. 0x8 2. " EP_SLOW_set/clr ,Slow interrupt transfer for the endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0xC 1. 0x8 1. " EP_FAST_set/clr ,Fast interrupt transfer for the endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0xC 0. 0x8 0. " FRAME_set/clr ,Frame interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "USBDevIntEn,USB Device Interrupt Enable Register"
|
|
bitfld.long 0x4 9. " ERR_INT ,Error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " EP_RLZED ,Endpoints realized interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 7. " TxENDPKT ,TxPacket length interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 6. " RxENDPKT ,RxPacket length interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " CDFULL ,Command data register is full interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " CCEMPTY ,The command code register is empty interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " DEV_STAT ,Device state interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " EP_SLOW ,Slow interrupt transfer for the endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " EP_FAST ,Fast interrupt transfer for the endpoint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0. " FRAME ,Frame interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "USBDevIntPri,USB Device Interrupt Priority Register"
|
|
bitfld.long 0x0 1. " EP_FAST ,Endpoint fast interrupt transfer priority" "Low,High"
|
|
bitfld.long 0x0 0. " FRAME ,Frame interruptpriority" "Low,High"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "USBEpIntSt,USB Endpoint Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0xC 31. 0x8 31. " EP15TX_set/clr ,Endpoint 15. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 30. 0xC 30. 0x8 30. " EP15RX_set/clr ,Endpoint 15. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0xC 29. 0x8 29. " EP14TX_set/clr ,Endpoint 14. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 28. 0xC 28. 0x8 28. " EP14RX_set/clr ,Endpoint 14. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0xC 27. 0x8 27. " EP13TX_set/clr ,Endpoint 13. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 26. 0xC 26. 0x8 26. " EP13RX_set/clr ,Endpoint 13. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0xC 25. 0x8 25. " EP12TX_set/clr ,Endpoint 12. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 24. 0xC 24. 0x8 24. " EP12RX_set/clr ,Endpoint 12. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0xC 23. 0x8 23. " EP11TX_set/clr ,Endpoint 11. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 22. 0xC 22. 0x8 22. " EP11RX_set/clr ,Endpoint 11, Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0xC 21. 0x8 21. " EP10TX_set/clr ,Endpoint 10. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 20. 0xC 20. 0x8 20. " EP10RX_set/clr ,Endpoint 10. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0xC 19. 0x8 19. " EP9TX_set/clr ,Endpoint 9. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 18. 0xC 18. 0x8 18. " EP9RX_set/clr ,Endpoint 9. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0xC 17. 0x8 17. " EP8TX_set/clr ,Endpoint 8. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 16. 0xC 16. 0x8 16. " EP8RX_set/clr ,Endpoint 8. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0xC 15. 0x8 15. " EP7TX_set/clr ,Endpoint 7. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0xC 14. 0x8 14. " EP7RX_set/clr ,Endpoint 7. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0xC 13. 0x8 13. " EP6TX_set/clr ,Endpoint 6. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 12. 0xC 12. 0x8 12. " EP6RX_set/clr ,Endpoint 6. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0xC 11. 0x8 11. " EP5TX_set/clr ,Endpoint 5. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0xC 10. 0x8 10. " EP5RX_set/clr ,Endpoint 5. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0xC 9. 0x8 9. " EP4TX_set/clr ,Endpoint 4. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0xC 8. 0x8 8. " EP4RX_set/clr ,Endpoint 4. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0xC 7. 0x8 7. " EP3TX_set/clr ,Endpoint 3. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0xC 6. 0x8 6. " EP3RX_set/clr ,Endpoint 3. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0xC 5. 0x8 5. " EP2TX_set/clr ,Endpoint 2. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0xC 4. 0x8 4. " EP2RX_set/clr ,Endpoint 2. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0xC 3. 0x8 3. " EP1TX_set/clr ,Endpoint 1. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0xC 2. 0x8 2. " EP1RX_set/clr ,Endpoint 1. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0xC 1. 0x8 1. " EP0TX_set/clr ,Endpoint 0. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0xC 0. 0x8 0. " EP0RX_set/clr ,Endpoint 0. Data Received Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "USBEpIntEn,USB Endpoint Interrupt Enable Register"
|
|
bitfld.long 0x4 31. " EP15TX ,Endpoint 15. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 30. " EP15RX ,Endpoint 15. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 29. " EP14TX ,Endpoint 14. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 28. " EP14RX ,Endpoint 14. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 27. " EP13TX ,Endpoint 13. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 26. " EP13RX ,Endpoint 13. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " EP12TX ,Endpoint 12. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 24. " EP12RX ,Endpoint 12. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 23. " EP11TX ,Endpoint 11. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 22. " EP11RX ,Endpoint 11, Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " EP10TX ,Endpoint 10. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " EP10RX ,Endpoint 10. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " EP9TX ,Endpoint 9. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " EP9RX ,Endpoint 9. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " EP8TX ,Endpoint 8. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16. " EP8RX ,Endpoint 8. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 15. " EP7TX ,Endpoint 7. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " EP7RX ,Endpoint 7. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " EP6TX ,Endpoint 6. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " EP6RX ,Endpoint 6. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 11. " EP5TX ,Endpoint 5. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 10. " EP5RX ,Endpoint 5. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 9. " EP4TX ,Endpoint 4. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " EP4RX ,Endpoint 4. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " EP3TX ,Endpoint 3. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " EP3RX ,Endpoint 3. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EP2TX ,Endpoint 2. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EP2RX ,Endpoint 2. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " EP1TX ,Endpoint 1. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " EP1RX ,Endpoint 1. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " EP0TX ,Endpoint 0. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " EP0RX ,Endpoint 0. Data Received Interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "USBEpIntPri,USB Endpoint Interrupt Priority Register"
|
|
bitfld.long 0x0 31. " EP15TX ,Endpoint 15. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 30. " EP15RX ,Endpoint 15. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 29. " EP14TX ,Endpoint 14. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 28. " EP14RX ,Endpoint 14. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 27. " EP13TX ,Endpoint 13. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 26. " EP13RX ,Endpoint 13. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EP12TX ,Endpoint 12. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 24. " EP12RX ,Endpoint 12. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 23. " EP11TX ,Endpoint 11. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 22. " EP11RX ,Endpoint 11, Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 21. " EP10TX ,Endpoint 10. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 20. " EP10RX ,Endpoint 10. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 19. " EP9TX ,Endpoint 9. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 18. " EP9RX ,Endpoint 9. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 17. " EP8TX ,Endpoint 8. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EP8RX ,Endpoint 8. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 15. " EP7TX ,Endpoint 7. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 14. " EP7RX ,Endpoint 7. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EP6TX ,Endpoint 6. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 12. " EP6RX ,Endpoint 6. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 11. " EP5TX ,Endpoint 5. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EP5RX ,Endpoint 5. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 9. " EP4TX ,Endpoint 4. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 8. " EP4RX ,Endpoint 4. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EP3TX ,Endpoint 3. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 6. " EP3RX ,Endpoint 3. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 5. " EP2TX ,Endpoint 2. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EP2RX ,Endpoint 2. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 3. " EP1TX ,Endpoint 1. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 2. " EP1RX ,Endpoint 1. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP0TX ,Endpoint 0. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 0. " EP0RX ,Endpoint 0. Data Received Interrupt" "Slow,Fast"
|
|
tree.end
|
|
tree "Realization, Transfer and Command Registers"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "USBReEp,USB Realize Endpoint Register"
|
|
bitfld.long 0x0 31. " EP31 ,Endpoint 31 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 30. " EP30 ,Endpoint 30 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 29. " EP29 ,Endpoint 29 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 28. " EP28 ,Endpoint 28 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 27. " EP27 ,Endpoint 27 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 26. " EP26 ,Endpoint 26 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EP25 ,Endpoint 25 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 24. " EP24 ,Endpoint 24 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 23. " EP23 ,Endpoint 23 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 22. " EP22 ,Endpoint 22 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 21. " EP21 ,Endpoint 21 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 20. " EP20 ,Endpoint 20 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 19. " EP19 ,Endpoint 19 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 18. " EP18 ,Endpoint 18 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 17. " EP17 ,Endpoint 17 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EP16 ,Endpoint 16 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 15. " EP15 ,Endpoint 15 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 14. " EP14 ,Endpoint 14 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EP13 ,Endpoint 13 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 12. " EP12 ,Endpoint 12 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 11. " EP11 ,Endpoint 11 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EP10 ,Endpoint 10 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 9. " EP9 ,Endpoint 9 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 8. " EP8 ,Endpoint 8 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EP7 ,Endpoint 7 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 6. " EP6 ,Endpoint 6 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 5. " EP5 ,Endpoint 5 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EP4 ,Endpoint 4 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 3. " EP3 ,Endpoint 3 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 2. " EP2 ,Endpoint 2 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP1 ,Endpoint 1 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 0. " EP0 ,Endpoint 0 realized" "Unrealized,Realized"
|
|
wgroup.long 0x48++0x3
|
|
line.long 0x0 "USBEpInd,USB Endpoint Index Register"
|
|
bitfld.long 0x0 0.--4. " PhyEndp ,Physical endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "USBMaxPSize,USB MaxPacketSize Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " MaxPacketSize ,Maximum packet size value"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "USBRxData,USB Receive Data Register"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "USBRxPLen,USB Receive Packet Length Register"
|
|
bitfld.long 0x0 11. " PKT_RDY ,Packet length field ready" "Not ready,Ready"
|
|
bitfld.long 0x0 10. " DV ,Data valid" "Invalid,Valid"
|
|
hexmask.long.word 0x0 0.--9. 1. " PKT_LNGTH ,Remaining amount of data in bytes still to be read from the RAM"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "USBTxData,USB Transmit Data Register"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "USBTxPLen,USB Transmit Packet Length Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " PKT_LNGTH ,Remaining amount of data in bytes to be written to the EP_RAM"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "USBCtrl,USB Control Register"
|
|
bitfld.long 0x0 2.--5. " LOG_ENDPOINT ,Logical Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 1. " WR_EN ,Write mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RD_EN ,Read mode enable" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "USBCmdCode,USB Command Code Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. " CMD_CODE ,Code for the command"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CMD_PHASE ,Command phase"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "USBCmdData,USB Command Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CMD_DATA ,Command Data"
|
|
tree.end
|
|
tree "DMA Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "USBDMARSt,USB DMA Request Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,Endpoint 31 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,Endpoint 30 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,Endpoint 29 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,Endpoint 28 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,Endpoint 27 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,Endpoint 26 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,Endpoint 25 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,Endpoint 24 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,Endpoint 23 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,Endpoint 22 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,Endpoint 21 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,Endpoint 20 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,Endpoint 19 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,Endpoint 18 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,Endpoint 17 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,Endpoint 16 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,Endpoint 15 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,Endpoint 14 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,Endpoint 13 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,Endpoint 12 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,Endpoint 11 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,Endpoint 10 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,Endpoint 9 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,Endpoint 8 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,Endpoint 7 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,Endpoint 6 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,Endpoint 5 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,Endpoint 4 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,Endpoint 3 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,Endpoint 2 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,Control endpoint IN" "Not requested,Requested"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,Control endpoint OUT" "Not requested,Requested"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "USBUDCAH,USB UDCA Head Register"
|
|
hexmask.long 0x0 7.--31. 0x80 " UDCAHeader ,Start address of the UDCA Header"
|
|
line.long 0x4 "USBEpDMASt,USB EP DMA Status Register"
|
|
setclrfld.long 0x4 31. 0x8 31. 0xC 31. " EP31_set/clr ,DMA for Endpoint 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 30. 0x8 30. 0xC 30. " EP30_set/clr ,DMA for Endpoint 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 29. 0x8 29. 0xC 29. " EP29_set/clr ,DMA for Endpoint 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 28. 0x8 28. 0xC 28. " EP28_set/clr ,DMA for Endpoint 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 27. 0x8 27. 0xC 27. " EP27_set/clr ,DMA for Endpoint 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 26. 0x8 26. 0xC 26. " EP26_set/clr ,DMA for Endpoint 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 25. 0x8 25. 0xC 25. " EP25_set/clr ,DMA for Endpoint 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 24. 0x8 24. 0xC 24. " EP24_set/clr ,DMA for Endpoint 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 23. 0x8 23. 0xC 23. " EP23_set/clr ,DMA for Endpoint 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 22. 0x8 22. 0xC 22. " EP22_set/clr ,DMA for Endpoint 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 21. 0x8 21. 0xC 21. " EP21_set/clr ,DMA for Endpoint 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 20. 0x8 20. 0xC 20. " EP20_set/clr ,DMA for Endpoint 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 19. 0x8 19. 0xC 19. " EP19_set/clr ,DMA for Endpoint 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 18. 0x8 18. 0xC 18. " EP18_set/clr ,DMA for Endpoint 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 17. 0x8 17. 0xC 17. " EP17_set/clr ,DMA for Endpoint 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 16. 0x8 16. 0xC 16. " EP16_set/clr ,DMA for Endpoint 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 15. 0x8 15. 0xC 15. " EP15_set/clr ,DMA for Endpoint 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 14. 0x8 14. 0xC 14. " EP14_set/clr ,DMA for Endpoint 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 13. 0x8 13. 0xC 13. " EP13_set/clr ,DMA for Endpoint 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 12. 0x8 12. 0xC 12. " EP12_set/clr ,DMA for Endpoint 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 11. 0x8 11. 0xC 11. " EP11_set/clr ,DMA for Endpoint 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 10. 0x8 10. 0xC 10. " EP10_set/clr ,DMA for Endpoint 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 9. 0x8 9. 0xC 9. " EP9_set/clr ,DMA for Endpoint 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 8. 0x8 8. 0xC 8. " EP8_set/clr ,DMA for Endpoint 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 7. 0x8 7. 0xC 7. " EP7_set/clr ,DMA for Endpoint 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 6. 0x8 6. 0xC 6. " EP6_set/clr ,DMA for Endpoint 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 5. 0x8 5. 0xC 5. " EP5_set/clr ,DMA for Endpoint 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 4. 0x8 4. 0xC 4. " EP4_set/clr ,DMA for Endpoint 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 3. 0x8 3. 0xC 3. " EP3_set/clr ,DMA for Endpoint 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 2. 0x8 2. 0xC 2. " EP2_set/clr ,DMA for Endpoint 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 1. 0x8 1. 0xC 1. " EP1_set/clr ,Control endpoint IN" "0,1"
|
|
setclrfld.long 0x4 0. 0x8 0. 0xC 0. " EP0_set/clr ,Control endpoint OUT" "0,1"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "USBDMAIntSt,USB DMA Interrupt Status Register"
|
|
bitfld.long 0x0 2. " SysErrInt ,System error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 1. " NewDDReqInt ,New DD Request Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 0. " EndOfTrInt ,End of Transfer Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "USBDMAIntEn,USB DMA Interrupt Enable Register"
|
|
bitfld.long 0x0 2. " SysErrInt ,System error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " NewDDReqInt ,New DD Request Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " EndOfTrInt ,End of Transfer Interrupt" "Disabled,Enabled"
|
|
group.long 0xAC++0x3
|
|
line.long 0x0 "USBNDDRIntSt,USB New DD Request Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,New DD Request for Endpoint 31" "Not requested,Requested"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,New DD Request for Endpoint 30" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,New DD Request for Endpoint 29" "Not requested,Requested"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,New DD Request for Endpoint 28" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,New DD Request for Endpoint 27" "Not requested,Requested"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,New DD Request for Endpoint 26" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,New DD Request for Endpoint 25" "Not requested,Requested"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,New DD Request for Endpoint 24" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,New DD Request for Endpoint 23" "Not requested,Requested"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,New DD Request for Endpoint 22" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,New DD Request for Endpoint 21" "Not requested,Requested"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,New DD Request for Endpoint 20" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,New DD Request for Endpoint 19" "Not requested,Requested"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,New DD Request for Endpoint 18" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,New DD Request for Endpoint 17" "Not requested,Requested"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,New DD Request for Endpoint 16" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,New DD Request for Endpoint 15" "Not requested,Requested"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,New DD Request for Endpoint 14" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,New DD Request for Endpoint 13" "Not requested,Requested"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,New DD Request for Endpoint 12" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,New DD Request for Endpoint 11" "Not requested,Requested"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,New DD Request for Endpoint 10" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,New DD Request for Endpoint 9" "Not requested,Requested"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,New DD Request for Endpoint 8" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,New DD Request for Endpoint 7" "Not requested,Requested"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,New DD Request for Endpoint 6" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,New DD Request for Endpoint 5" "Not requested,Requested"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,New DD Request for Endpoint 4" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,New DD Request for Endpoint 3" "Not requested,Requested"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,New DD Request for Endpoint 2" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,New DD Request for Endpoint 1" "Not requested,Requested"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,New DD Request for Endpoint 0" "Not requested,Requested"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "USBEoTIntSt,USB End Of Transfer Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,End of Transfer Interrupt request for Endpoint 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,End of Transfer Interrupt request for Endpoint 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,End of Transfer Interrupt request for Endpoint 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,End of Transfer Interrupt request for Endpoint 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,End of Transfer Interrupt request for Endpoint 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,End of Transfer Interrupt request for Endpoint 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,End of Transfer Interrupt request for Endpoint 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,End of Transfer Interrupt request for Endpoint 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,End of Transfer Interrupt request for Endpoint 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,End of Transfer Interrupt request for Endpoint 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,End of Transfer Interrupt request for Endpoint 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,End of Transfer Interrupt request for Endpoint 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,End of Transfer Interrupt request for Endpoint 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,End of Transfer Interrupt request for Endpoint 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,End of Transfer Interrupt request for Endpoint 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,End of Transfer Interrupt request for Endpoint 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,End of Transfer Interrupt request for Endpoint 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,End of Transfer Interrupt request for Endpoint 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,End of Transfer Interrupt request for Endpoint 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,End of Transfer Interrupt request for Endpoint 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,End of Transfer Interrupt request for Endpoint 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,End of Transfer Interrupt request for Endpoint 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,End of Transfer Interrupt request for Endpoint 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,End of Transfer Interrupt request for Endpoint 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,End of Transfer Interrupt request for Endpoint 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,End of Transfer Interrupt request for Endpoint 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,End of Transfer Interrupt request for Endpoint 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,End of Transfer Interrupt request for Endpoint 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,End of Transfer Interrupt request for Endpoint 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,End of Transfer Interrupt request for Endpoint 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,End of Transfer Interrupt request for Endpoint 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,End of Transfer Interrupt request for Endpoint 0" "No interrupt,Interrupt"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "USBSysErrIntSt,USB System Error Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,System Error Interrupt request for Endpoint 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,System Error Interrupt request for Endpoint 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,System Error Interrupt request for Endpoint 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,System Error Interrupt request for Endpoint 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,System Error Interrupt request for Endpoint 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,System Error Interrupt request for Endpoint 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,System Error Interrupt request for Endpoint 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,System Error Interrupt request for Endpoint 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,System Error Interrupt request for Endpoint 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,System Error Interrupt request for Endpoint 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,System Error Interrupt request for Endpoint 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,System Error Interrupt request for Endpoint 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,System Error Interrupt request for Endpoint 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,System Error Interrupt request for Endpoint 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,System Error Interrupt request for Endpoint 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,System Error Interrupt request for Endpoint 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,System Error Interrupt request for Endpoint 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,System Error Interrupt request for Endpoint 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,System Error Interrupt request for Endpoint 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,System Error Interrupt request for Endpoint 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,System Error Interrupt request for Endpoint 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,System Error Interrupt request for Endpoint 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,System Error Interrupt request for Endpoint 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,System Error Interrupt request for Endpoint 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,System Error Interrupt request for Endpoint 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,System Error Interrupt request for Endpoint 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,System Error Interrupt request for Endpoint 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,System Error Interrupt request for Endpoint 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,System Error Interrupt request for Endpoint 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,System Error Interrupt request for Endpoint 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,System Error Interrupt request for Endpoint 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,System Error Interrupt request for Endpoint 0" "No interrupt,Interrupt"
|
|
sif (cpu()=="LPC3180")
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "USBModId,USB Module ID Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " IP_Number ,USB Device Core IP number"
|
|
hexmask.long.byte 0x0 8.--15. 1. " VER ,Version Number"
|
|
hexmask.long.byte 0x0 0.--7. 1. " REV ,Reversion Number"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB Host (OHCI) Controller"
|
|
base ad:0x31020000
|
|
width 22.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x0 "HcRevision,BCD Representation Of The Version Of The HCI Specification Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " REV ,BCD Representation Of The Version Of The HCI Specification"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "HcControl,HC Operating Modes Register"
|
|
bitfld.long 0x0 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " RWC ,Remote Wakeup Connected" "Not connected,Connected"
|
|
bitfld.long 0x0 8. " IR ,Interrupt Routing" "Normal host bus,System Management"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x0 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--1. " CBSR ,Control Bulk Service Ratio" "1:1,2:1,3:1,4:1"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "HcCommandStatus,HC Status Register"
|
|
bitfld.long 0x0 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x0 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x0 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x0 0. " HCR ,Host Controller Reset" "No effect,Reset"
|
|
group.long 0x0c++0x3
|
|
line.long 0x0 "HcInterruptStatus,HC Interrupt Status Register"
|
|
bitfld.long 0x0 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "HcInterruptEn/Dis,HC Interrupt Enable/Disable Register"
|
|
setclrfld.long 0x0 31. 0x0 31. 0x4 31. " MIE_set/clr ,Master Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. 0x0 30. 0x4 30. " OCMIE_set/clr ,Ownership Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. 0x0 6. 0x4 6. " RHSCMIE_set/clr ,Root Hub Status Change" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. 0x0 5. 0x4 5. " FNOMIE_set/clr ,Frame Number Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. 0x0 4. 0x4 4. " UEMIE_set/clr ,Unrecoverable Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. 0x0 3. 0x4 3. " RDMIE_set/clr ,Resume Detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. 0x0 2. 0x4 2. " SFMIE_set/clr ,Start of Frame" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. 0x0 1. 0x4 1. " WDHMIE_set/clr ,Writeback Done Head" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. 0x0 0. 0x4 0. " SOMIE_set/clr ,Scheduling Overrun" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "HcHCCA,Host Controller Communication Area Physical Address Register"
|
|
hexmask.long 0x00 8.--31. 0x100 " HCCA ,Host Controller Communication Area Base Address"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "HcPeriodCurrentED,Current Isochronous Or Interrupt Endpoint Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " PCED ,Period Current ED"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "HcControlHeadED,First Endpoint Of The Control List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " CHED ,Control Head ED"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "HcControlCurrentED,Current Endpoint Of The Control List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " CCED ,Control Current ED"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "HcBulkHeadED,First Endpoint Of The Bulk List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "HcBulkCurrentED,Current Endpoint Of The Bulk List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HcDoneHead,Last Transfer Descriptor Added Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " DH ,Done Head"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "HcFmInterval,HC Frame Interval Register"
|
|
bitfld.long 0x0 31. " FIT ,Frame Interval Toggle" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x0 0.--13. 1. " FI ,Frame Interval"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "HcFmRemaining,HC Frame Remaining Register"
|
|
bitfld.long 0x0 31. " FRT ,Frame Remaining Toggle" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0 0.--13. 1. " FR ,Frame Remaining"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x0 "HcFmNumber,HC Frame Number Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HcPeriodicStart,HC Periodic Start Register"
|
|
hexmask.long.word 0x0 0.--13. 1. " PS ,Periodic Start"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "HcLSThreshold,HC LS Threshold Register"
|
|
hexmask.long.word 0x0 0.--11. 1. " LST ,LS Threshold"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "HcRhDescriptorA,HC Root Hub Descriptor A Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x0 12. " NOCP ,No Over Current Protection" "Protection,No protection"
|
|
bitfld.long 0x0 11. " OCPM ,Over Current Protection Mode" "Collectively,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DT ,Device Type" "Not compound,Compound"
|
|
bitfld.long 0x0 9. " PSM ,Power Switching Mode" "Global,Individual"
|
|
bitfld.long 0x0 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HcRhDescriptorB,HC Root Hub Descriptor B Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " PPCM ,Port Power Control Mask"
|
|
hexmask.long.word 0x0 0.--15. 1. " DR ,Device Removable"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "HcRhStatus,HC Root Hub Status Register"
|
|
bitfld.long 0x0 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Cleared"
|
|
eventfld.long 0x0 17. " OCIC ,Over Current Indicator Change" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 16. " LPSC ,Local Power Status Change/Set Global Power (read/write)" "Not supported/No effect,Not supported/Turn power on"
|
|
bitfld.long 0x0 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable (read/write)" "No wakeup/No effect,Wakeup/Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " OCI ,OverCurrent Indicator" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x0 0. " LPS ,Local Power Status/Clear Global Power (read/write)" "Not supported/No effect,Not supported/Turn power off"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "HcRhPortStatus[1],HC Root Hub Port Status 1 Register"
|
|
eventfld.long 0x0 20. " PRSC ,Port Reset Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 18. " PSSC ,Port Suspend Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0 9. " LSDA ,Low Speed Device Attached/Clear Port Power (read/write)" "Full speed/No effect,Low speed/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 8. " PPS ,Port Power Status/Set Port Power (read/write)" "Off/No effect,On/Set"
|
|
bitfld.long 0x0 4. " PRS ,Port Reset Status/Set Port Reset (read/write)" "Inactive/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " POCI ,Port Over Current Indicator/Clear Suspend Status (read/write)" "No overcurrent/No effect,Overcurrent/Clear"
|
|
bitfld.long 0x0 2. " PSS ,Port Suspend Status/Set Port Suspend (read/write)" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PES ,Port Enable Status/Set Port Enable (read/write)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x0 0. " CCS ,Current Connect Status/Clear Port Enable (read/write)" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "HcRhPortStatus[2],HC Root Hub Port Status 2 Register"
|
|
eventfld.long 0x0 20. " PRSC ,Port Reset Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 18. " PSSC ,Port Suspend Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0 9. " LSDA ,Low Speed Device Attached/Clear Port Power (read/write)" "Full speed/No effect,Low speed/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 8. " PPS ,Port Power Status/Set Port Power (read/write)" "Off/No effect,On/Set"
|
|
bitfld.long 0x0 4. " PRS ,Port Reset Status/Set Port Reset (read/write)" "Inactive/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " POCI ,Port Over Current Indicator/Clear Suspend Status (read/write)" "No overcurrent/No effect,Overcurrent/Clear"
|
|
bitfld.long 0x0 2. " PSS ,Port Suspend Status/Set Port Suspend (read/write)" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PES ,Port Enable Status/Set Port Enable (read/write)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x0 0. " CCS ,Current Connect Status/Clear Port Enable (read/write)" "Not connected/No effect,Connected/Clear"
|
|
sif (cpu()=="LPC3180"||cpuis("LPC293*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "Module_ID/Ver_Rev_ID,Module Version And Reversion ID Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB OTG (On-The-Go) Controller"
|
|
base ad:0x31020100
|
|
width 16.
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "OTG_int_status,OTG Interrupt Status Register"
|
|
setclrfld.long 0x0 3. 0x8 3. 0xC 3. " hnp_success_set/clr ,hnp_success interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 2. 0x8 2. 0xC 2. " hnp_failure_set/clr ,hnp_failure interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0xC 1. " remove_pullup_set/clr ,remove_pullup interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 0. 0x8 3. 0xC 3. " timer_interrupt_set/clr ,timer_interrupt interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "OTG_int_enable,OTG Interrupt Enable Register"
|
|
bitfld.long 0x4 3. " hnp_success ,hnp_success interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " hnp_failure ,hnp_failure interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " remove_pullup ,remove_pullup interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " timer_interrupt ,timer_interrupt interrupt" "Disabled,Enabled"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "OTG_status,OTG Status And Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " TimCountSt ,Timer count status"
|
|
bitfld.long 0x0 10. " Pullup_removed ,Pullup Removed" "Not removed,Removed"
|
|
textline " "
|
|
bitfld.long 0x0 9. " a_to_b_hnp_track ,A to B hnp track" "Not switched,Switched"
|
|
bitfld.long 0x0 8. " b_to_a_hnp_track ,B to A hnp track" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x0 7. " Transp_I2C_en ,Transparent I2C enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " Timer_reset ,Timer reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 5. " Timer_enable ,Timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " Timer_mode ,Timer mode" "Monoshot,Free running"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " Timer_scale ,Timer granularity selection" "10 us,100 us,1000 us,?..."
|
|
bitfld.long 0x0 0. " Host_En ,USB Host or Device selection" "Device,Host"
|
|
line.long 0x4 "OTG_timer,OTG Timer Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " TimerValue ,16-bit timer value to be counted"
|
|
base ad:0x31020F00
|
|
group.long 0xF4++0x7
|
|
line.long 0x0 "OTG_clock_ctrl,OTG Clock Control Register"
|
|
bitfld.long 0x0 4. " AHB_CLK_ON ,AHB clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " OTG_CLK_ON ,OTG clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " I2C_CLK_ON ,I2C clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " DEV_CLK_ON ,Device clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HOST_CLK_ON ,Host clock control" "Disabled,Enabled"
|
|
line.long 0x4 "OTG_clock_stat,OTG Clock Status Register"
|
|
bitfld.long 0x4 4. " AHB_CLK_ON ,AHB clock status" "Not available,Available"
|
|
bitfld.long 0x4 3. " OTG_CLK_ON ,OTG clock status" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x4 2. " I2C_CLK_ON ,I2C clock status" "Not available,Available"
|
|
bitfld.long 0x4 1. " DEV_CLK_ON ,Device clock status" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x4 0. " HOST_CLK_ON ,Host clock status" "Not available,Available"
|
|
sif (cpu()=="LPC3180")
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "OTG_module_id,OTG Module ID Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " IP_Number ,USB OTG IP number"
|
|
hexmask.long.byte 0x0 8.--15. 1. " VER ,Version Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " REV ,Reversion Number"
|
|
endif
|
|
base ad:0x31020300
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "I2C_RX/TX,I2C RX/TX Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "I2C_STS,I2C STS Register"
|
|
bitfld.long 0x0 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 10. " TFF ,Transmit FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 9. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x0 8. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 7. " SDA ,Value of the SDA signal" "Low,High"
|
|
bitfld.long 0x0 6. " SCL ,Value of the SCL signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " Active ,Bus Active" "Not active,Active"
|
|
bitfld.long 0x0 4. " DRSI ,Slave Data Request" "No request,Request"
|
|
bitfld.long 0x0 3. " DRMI ,Master Data Request" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NAI ,No Acknowledge" "Acknowledge,No acknowledge"
|
|
bitfld.long 0x0 1. " AFI ,Arbitration Failure" "Not occurred,Occurred"
|
|
bitfld.long 0x0 0. " TDI ,Transaction Done" "Undone,Done"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "I2C_CTL,I2C CTL Register"
|
|
bitfld.long 0x0 8. " SRST ,Soft reset" "No reset,Reset"
|
|
bitfld.long 0x0 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RFDAIE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RFFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DRSIE ,Slave Transmitter Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " DRMIE ,Master Transmitter Data Request Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " AFIE ,Transmitter Arbitration Failure Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x4 "I2C_CLKHI,I2C CLock High Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " CDHI ,Clock divisor high"
|
|
line.long 0x8 "I2C_CLKLO,I2C Clock Low Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " CDLO ,Clock divisor low"
|
|
width 0xB
|
|
tree.end
|
|
tree "SD (Secure Digital) Card Interface"
|
|
base ad:0x20098000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x0 "SD_Power,Power Control Register"
|
|
bitfld.long 0x0 6. " OpenDrain ,SDCMD output control" "Push-pull,Open drain"
|
|
bitfld.long 0x0 0.--1. " Ctrl ,Power mode control" "Power off,Reserved,Power up,Power on"
|
|
line.long 0x4 "SD_Clock,Clock Control Register"
|
|
bitfld.long 0x4 11. " WideBus ,Wide bus mode" "Standard,Wide"
|
|
bitfld.long 0x4 10. " Bypass ,Bypassing the clock divide logic (SDCLK)" "Not bypassed,Bypassed"
|
|
bitfld.long 0x4 9. " PwrSave ,Power save" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " Enable ,SD card clock enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " ClkDiv ,SD card clock period"
|
|
line.long 0x8 "SD_Argument,Argument Register"
|
|
line.long 0xC "SD_Command,Command Register"
|
|
bitfld.long 0xC 10. " Enable ,Command Path State Machine Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 9. " Pending ,Wait for CmdPend before sending the command" "Don't wait,Wait"
|
|
textline " "
|
|
bitfld.long 0xC 8. " Interrupt ,Disable the command timer and wait for a card interrupt" "No interrupt,Wait for interrupt"
|
|
bitfld.long 0xC 7. " LongRsp ,Long response" "Short (48-bit),Long (136-bit)"
|
|
textline " "
|
|
bitfld.long 0xC 6. " Response ,Response to a command require" "Not required,Required"
|
|
hexmask.long.byte 0xC 0.--5. 1. " CmdIndex ,Command Index"
|
|
rgroup.long 0x10++0x13
|
|
line.long 0x0 "SD_Respcmd,Command Response Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. " RespCmd ,Response Command Index"
|
|
if ((d.l(ad:0x20098000+0xC)&0x80)==0x80)
|
|
rgroup.long 0x14++0xF
|
|
line.long 0x00 "SD_Response0,Response register 0"
|
|
line.long 0x04 "SD_Response1,Response register 1"
|
|
line.long 0x08 "SD_Response2,Response register 2"
|
|
line.long 0x0C "SD_Response3,Response register 3"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SD_Response0,Response register 0"
|
|
endif
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "SD_DataTimer,Data Timer Register"
|
|
line.long 0x4 "SD_DataLength,Data Length Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " DataLength ,Data length value"
|
|
line.long 0x8 "SD_DataCtrl,Data Control Register"
|
|
bitfld.long 0x8 4.--7. " BlockSize ,Block Size" "1 byte,2 bytes,4 bytes,8 bytes,16 bytes,31 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,?..."
|
|
bitfld.long 0x8 3. " DMAEnable ,DMA Enbable" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " Mode ,Data transfer mode" "Block,Stream"
|
|
textline " "
|
|
bitfld.long 0x8 1. " Direction ,Direction" "Transmit,Receive"
|
|
bitfld.long 0x8 0. " Enable ,Data transfer enable" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SD_DataCnt,Data Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " DataCount ,Indicates the number of bytes remaining to transfer"
|
|
line.long 0x4 "SD_Status,Status Register"
|
|
bitfld.long 0x4 21. " RxDataAvlbl ,Data available in receive FIFO" "Unavailable,Available"
|
|
textline " "
|
|
bitfld.long 0x4 20. " TxDataAvlbl ,Data available in transmit FIFO" "Unavailable,Available"
|
|
textline " "
|
|
bitfld.long 0x4 19. " RxFifoEmpty ,Receive FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x4 18. " TxFifoEmpty ,Transmit FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x4 17. " RxFifoFull ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x4 16. " TxFifoFull ,Transmit FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x4 15. " RxFifoHalfFull ,Receive FIFO half full" "Not half-full,Half-full"
|
|
textline " "
|
|
bitfld.long 0x4 14. " TxFifoHalfEmpty ,Transmit FIFO half empty" "Not half-empty,Half-empty"
|
|
textline " "
|
|
bitfld.long 0x4 13. " RxActive ,Data receive active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x4 12. " TxActive ,Data transmit active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x4 11. " CmdActive ,Command transfer active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x4 10. " DataBlockEnd ,Data block sent/received (CRC check passed)" "Not sent/received,Sent/received"
|
|
textline " "
|
|
bitfld.long 0x4 9. " StartBitErr ,Start Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 8. " DataEnd ,Data end" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x4 7. " CmdSent ,Command sent (No response required)" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x4 6. " CmdRespEnd ,Command Response received (CRC check passed)" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RxOverrun ,Receive FIFO overrun" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x4 4. " TxUnderrun ,Transmit FIFO underrun" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x4 3. " DataTimeOut ,Data Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x4 2. " CmdTimeOut ,Command Response Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x4 1. " DataCrcFail ,Data block sent/received (CRC check failed)" "Not sent/received,Sent/received"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CmdCrcFail ,Command response received (CRC check failed)" "Not received,Received"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "SD_Clear,Clear Register"
|
|
bitfld.long 0x0 10. " DataBlockEndClr ,DataBlockEnd flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 9. " StartBitErrClr ,StartBitErr flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DataEndClr ,DataEnd flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " CmdSentClr ,CmdSent flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 6. " CmdRespEndClr ,CmdRespEnd flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 5. " RxOverrunClr ,RxOverrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TxUnderrunClr ,TxUnderrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 3. " DataTimeOutClr ,DataTimeOut flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 2. " CmdTimeOutClr ,CmdTimeOut flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 1. " DataCrcFailClr ,DataCrcFail flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CmdCrcFailClr ,CmdCrcFail flag clear" "No effect,Clear"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "SD_Mask0,Interrupt Mask 0 Register"
|
|
bitfld.long 0x0 21. " Mask21 ,RxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " Mask20 ,TxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 19. " Mask19 ,RxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " Mask18 ,TxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " Mask17 ,RxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " Mask16 ,TxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " Mask15 ,RxFifoHalfFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " Mask14 ,TxFifoHalfEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " Mask13 ,RxActive flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " Mask12 ,TxActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Mask11 ,CmdActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " Mask10 ,DataBlockEnd flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " Mask9 ,StartBitErr flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " Mask8 ,DataEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " Mask7 ,CmdSent flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " Mask6 ,CmdRespEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " Mask5 ,RxOverrun flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " Mask4 ,TxUnderrun flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " Mask3 ,DataTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " Mask2 ,CmdTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " Mask1 ,DataCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " Mask0 ,CmdCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
line.long 0x4 "SD_Mask1,Interrupt Mask 1 Register"
|
|
bitfld.long 0x4 21. " Mask21 ,RxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " Mask20 ,TxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 19. " Mask19 ,RxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 18. " Mask18 ,TxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " Mask17 ,RxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " Mask16 ,TxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 15. " Mask15 ,RxFifoHalfFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " Mask14 ,TxFifoHalfEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 13. " Mask13 ,RxActive flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 12. " Mask12 ,TxActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 11. " Mask11 ,CmdActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 10. " Mask10 ,DataBlockEnd flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " Mask9 ,StartBitErr flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " Mask8 ,DataEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 7. " Mask7 ,CmdSent flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 6. " Mask6 ,CmdRespEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " Mask5 ,RxOverrun flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " Mask4 ,TxUnderrun flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " Mask3 ,DataTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " Mask2 ,CmdTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " Mask1 ,DataCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0. " Mask0 ,CmdCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "SD_FIFO0,Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "SD_FIFO1,Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "SD_FIFO2,Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x00 "SD_FIFO3,Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x3
|
|
hide.long 0x00 "SD_FIFO4,Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "SD_FIFO5,Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "SD_FIFO6,Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "SD_FIFO7,Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "SD_FIFO8,Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "SD_FIFO9,Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "SD_FIFO10,Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "SD_FIFO11,Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "SD_FIFO12,Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "SD_FIFO13,Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "SD_FIFO14,Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "SD_FIFO15,Data FIFO Register 15"
|
|
in
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "SD_FIFOCnt,FIFO Counter Register"
|
|
hexmask.long.word 0x0 0.--14. 1. " DataCount ,Remaining data words to transfer"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "Standard UART 3"
|
|
base ad:0x40080000
|
|
width 11.
|
|
if (((d.b(ad:0x40080000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U3RBR/THR,UART 3 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U3IER,UART 3 Interrupt Enable Register"
|
|
bitfld.byte 0x0 3. " Modem_IE ,UART3 Modem Interrupt. Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U3DLL,UART 3 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U3DLM,UART 3 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U3IIR,UART 3 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 3 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 3 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Modem,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U3FCR,UART3 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 3 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 3 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
group.byte 0x10++0x3
|
|
line.byte 0x00 "U3_MSR,UART3 Modem Status Register"
|
|
bitfld.byte 0x00 4. " Loopback ,Loopback Mode Select" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,Control for modem output pin U3_RTS" "1,0"
|
|
bitfld.byte 0x00 0. " DTR ,Control for modem output pin U3_DTR" "1,0"
|
|
if (((d.b(ad:0x40080000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U3LCR,UART 3 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8 bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U3LCR,UART 3 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U3LSR,UART 3 Line Status Register"
|
|
in
|
|
hgroup.byte 0x18++0x3
|
|
hide.byte 0x00 "U3_MSR,UART3 Modem Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U3RXLEV,UART 3 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040D0
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U3_CLK,UART 3 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long.byte 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Standard UART 4"
|
|
base ad:0x40088000
|
|
width 11.
|
|
if (((d.b(ad:0x40088000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U4RBR/THR,UART 4 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U4IER,UART 4 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U4DLL,UART 4 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U4DLM,UART 4 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U4IIR,UART 4 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 4 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 4 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Modem,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U4FCR,UART4 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 4 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 4 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40088000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U4LCR,UART 4 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8 bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U4LCR,UART 4 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U4LSR,UART 4 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U4RXLEV,UART 4 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040D4
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U4_CLK,UART 4 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long.byte 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Standard UART 5"
|
|
base ad:0x40090000
|
|
width 11.
|
|
if (((d.b(ad:0x40090000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U5RBR/THR,UART 5 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U5IER,UART 5 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U5DLL,UART 5 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U5DLM,UART 5 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U5IIR,UART 5 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 5 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 5 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Modem,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U5FCR,UART5 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 5 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 5 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40090000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U5LCR,UART 5 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8 bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U5LCR,UART 5 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U5LSR,UART 5 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U5RXLEV,UART 5 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040D8
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U5_CLK,UART 5 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long.byte 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Standard UART 6"
|
|
base ad:0x40098000
|
|
width 11.
|
|
if (((d.b(ad:0x40098000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U6RBR/THR,UART 6 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U6IER,UART 6 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U6DLL,UART 6 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U6DLM,UART 6 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U6IIR,UART 6 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 6 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 6 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Modem,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U6FCR,UART6 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 6 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 6 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40098000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U6LCR,UART 6 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8 bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U6LCR,UART 6 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U6LSR,UART 6 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U6RXLEV,UART 6 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040DC
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U6_CLK,UART 6 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long.byte 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long.byte 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Fast UART 1"
|
|
base ad:0x40014000
|
|
width 12.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "HSU1_RX/TX,High Speed UART 1 Receiver/Transmitter FIFO Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "HSU1_LEVEL,High Speed UART 1 Level Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HSU_TX_LEV ,Current transmitter FIFO level"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HSU_RX_LEV ,Current receiver FIFO level"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "HSU1_IIR,High Speed UART 1 Interrupt Identification Register"
|
|
bitfld.long 0x0 6. " HSU_TX_INT_SET ,Transmit interrupt flag set" "No effect,Set"
|
|
textline " "
|
|
eventfld.long 0x0 5. " HSU_RX_OE ,Overrun error flag" "No overflow,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0 4. " HSU_BRK ,Break flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x0 3. " HSU_FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " HSU_RX_TIMEOUT ,Receiver timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSU_RX_TRIG ,Receiver trigger level" "Below,Above"
|
|
textline " "
|
|
eventfld.long 0x0 0. " HSU_TX ,Transmitter interrupt" "Inactive,Active"
|
|
line.long 0x4 "HSU1_CTRL,High Speed UART 1 Control Register"
|
|
bitfld.long 0x4 21. " HRTS_INV ,U1_HRTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 19.--20. " HRTS_TRIG ,Hardware RTS flow control trigger level control" "8 bytes,16 bytes,32 bytes,48 bytes"
|
|
textline " "
|
|
bitfld.long 0x4 18. " HRTS_EN ,Hardware RTS flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " TMO_CONFIG ,Receiver timeout interrupt configuration" "Disabled,4 characters,8 characters,16 characters"
|
|
textline " "
|
|
bitfld.long 0x4 15. " HCTS_INV ,Un_HCTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 14. " HCTS_EN ,Hardware CTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--13. " HSU_OFFSET ,First bit sampling point" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks"
|
|
bitfld.long 0x4 8. " HSU_BREAK ,Break on the transmit data line generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " HSU_ERR_INT_EN ,UART 1 error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " HSU_RX_INT_EN ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " HSU_TX_INT_EN ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--4. " HSU_RX_TRIG ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,16 bytes,32 bytes,48 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " HSU_TX_TRIG ,Transmitter FIFO trigger level" "Empty,4 bytes,8 bytes,16 bytes"
|
|
line.long 0x8 "HSU1_RATE,High Speed UART 1 Rate Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " HSU_RATE ,High speed UART clock divider"
|
|
width 0xB
|
|
tree.end
|
|
tree "Fast UART 2"
|
|
base ad:0x40018000
|
|
width 12.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "HSU2_RX/TX,High Speed UART 2 Receiver/Transmitter FIFO Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "HSU2_LEVEL,High Speed UART 2 Level Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HSU_TX_LEV ,Current transmitter FIFO level"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HSU_RX_LEV ,Current receiver FIFO level"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "HSU2_IIR,High Speed UART 2 Interrupt Identification Register"
|
|
bitfld.long 0x0 6. " HSU_TX_INT_SET ,Transmit interrupt flag set" "No effect,Set"
|
|
textline " "
|
|
eventfld.long 0x0 5. " HSU_RX_OE ,Overrun error flag" "No overflow,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0 4. " HSU_BRK ,Break flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x0 3. " HSU_FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " HSU_RX_TIMEOUT ,Receiver timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSU_RX_TRIG ,Receiver trigger level" "Below,Above"
|
|
textline " "
|
|
eventfld.long 0x0 0. " HSU_TX ,Transmitter interrupt" "Inactive,Active"
|
|
line.long 0x4 "HSU2_CTRL,High Speed UART 2 Control Register"
|
|
bitfld.long 0x4 21. " HRTS_INV ,U2_HRTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 19.--20. " HRTS_TRIG ,Hardware RTS flow control trigger level control" "8 bytes,16 bytes,32 bytes,48 bytes"
|
|
textline " "
|
|
bitfld.long 0x4 18. " HRTS_EN ,Hardware RTS flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " TMO_CONFIG ,Receiver timeout interrupt configuration" "Disabled,4 characters,8 characters,16 characters"
|
|
textline " "
|
|
bitfld.long 0x4 15. " HCTS_INV ,Un_HCTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 14. " HCTS_EN ,Hardware CTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--13. " HSU_OFFSET ,First bit sampling point" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks"
|
|
bitfld.long 0x4 8. " HSU_BREAK ,Break on the transmit data line generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " HSU_ERR_INT_EN ,UART 2 error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " HSU_RX_INT_EN ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " HSU_TX_INT_EN ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--4. " HSU_RX_TRIG ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,16 bytes,32 bytes,48 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " HSU_TX_TRIG ,Transmitter FIFO trigger level" "Empty,4 bytes,8 bytes,16 bytes"
|
|
line.long 0x8 "HSU2_RATE,High Speed UART 2 Rate Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " HSU_RATE ,High speed UART clock divider"
|
|
width 0xB
|
|
tree.end
|
|
tree "Fast UART 7"
|
|
base ad:0x4001C000
|
|
width 12.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "HSU7_RX/TX,High Speed UART 7 Receiver/Transmitter FIFO Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "HSU7_LEVEL,High Speed UART 7 Level Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HSU_TX_LEV ,Current transmitter FIFO level"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HSU_RX_LEV ,Current receiver FIFO level"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "HSU7_IIR,High Speed UART 7 Interrupt Identification Register"
|
|
bitfld.long 0x0 6. " HSU_TX_INT_SET ,Transmit interrupt flag set" "No effect,Set"
|
|
textline " "
|
|
eventfld.long 0x0 5. " HSU_RX_OE ,Overrun error flag" "No overflow,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0 4. " HSU_BRK ,Break flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x0 3. " HSU_FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " HSU_RX_TIMEOUT ,Receiver timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSU_RX_TRIG ,Receiver trigger level" "Below,Above"
|
|
textline " "
|
|
eventfld.long 0x0 0. " HSU_TX ,Transmitter interrupt" "Inactive,Active"
|
|
line.long 0x4 "HSU7_CTRL,High Speed UART 7 Control Register"
|
|
bitfld.long 0x4 21. " HRTS_INV ,U7_HRTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 19.--20. " HRTS_TRIG ,Hardware RTS flow control trigger level control" "8 bytes,16 bytes,32 bytes,48 bytes"
|
|
textline " "
|
|
bitfld.long 0x4 18. " HRTS_EN ,Hardware RTS flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " TMO_CONFIG ,Receiver timeout interrupt configuration" "Disabled,4 characters,8 characters,16 characters"
|
|
textline " "
|
|
bitfld.long 0x4 15. " HCTS_INV ,Un_HCTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 14. " HCTS_EN ,Hardware CTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--13. " HSU_OFFSET ,First bit sampling point" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks"
|
|
bitfld.long 0x4 8. " HSU_BREAK ,Break on the transmit data line generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " HSU_ERR_INT_EN ,UART 7 error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " HSU_RX_INT_EN ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " HSU_TX_INT_EN ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--4. " HSU_RX_TRIG ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,16 bytes,32 bytes,48 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " HSU_TX_TRIG ,Transmitter FIFO trigger level" "Empty,4 bytes,8 bytes,16 bytes"
|
|
line.long 0x8 "HSU7_RATE,High Speed UART 7 Rate Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " HSU_RATE ,High speed UART clock divider"
|
|
width 0xB
|
|
tree.end
|
|
tree "Additional Control Registers"
|
|
base ad:0x400040E0
|
|
width 14.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "IRDACLK,IrDA Clock Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long.byte 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
base ad:0x40054000
|
|
group.long 0x00++0xB
|
|
line.long 0x0 "UART_CTRL,UART Control Register"
|
|
sif (cpu()!="LPC3180")
|
|
bitfld.long 0x0 10. " UART3_MD_CTRL ,Modem control pins usage by UART3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 10. " HDPX_INV ,HDPX inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " HDPX_EN ,HDPX enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " UART6_IRDA ,UART6 of IRDA usage" "Used,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0 4. " IRTX6_INV ,IRTX6 pin inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IRRX6_INV ,IRRX6 pin inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 2. " IR_RxLength ,IRDA Rx pulses period expectation" "3/16 of selected bit,3/16 of 115.2 kbps"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IR_TxLength ,IRDA Tx pulses period usage" "3/16 of selected bit,3/16 of 115.2 kbps"
|
|
textline " "
|
|
bitfld.long 0x0 0. " UART5_MODE ,UART5 TX/RX function routing" "UART5,UART5+USB"
|
|
line.long 0x4 "UART_CLKMODE,UART Clock Mode Register"
|
|
bitfld.long 0x4 22. " CLK_STAT7 ,UART 7 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " CLK_STAT6 ,UART 6 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " CLK_STAT5 ,UART 5 clock status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " CLK_STAT4 ,UART 4 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " CLK_STAT3 ,UART 3 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " CLK_STAT2 ,UART 2 clock status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16. " CLK_STAT1 ,UART 1 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " CLK_STAT ,Some of UART clocks are running" "Stopped,Running"
|
|
bitfld.long 0x4 10.--11. " UART6_CLK ,Selects the clock mode for UART6" "Clock off,Clock on,Auto clock,Not used"
|
|
textline " "
|
|
bitfld.long 0x4 8.--9. " UART5_CLK ,Selects the clock mode for UART5" "Clock off,Clock on,Auto clock,Not used"
|
|
bitfld.long 0x4 6.--7. " UART4_CLK ,Selects the clock mode for UART4" "Clock off,Clock on,Auto clock,Not used"
|
|
bitfld.long 0x4 4.--5. " UART3_CLK ,Selects the clock mode for UART3" "Clock off,Clock on,Auto clock,Not used"
|
|
line.long 0x8 "UART_LOOP,UART Loopback Control Register"
|
|
bitfld.long 0x8 6. " LOOPBACK7 ,UART 7 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 5. " LOOPBACK6 ,UART 6 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 4. " LOOPBACK5 ,UART 5 loopback mode" "Turned off,Loopback"
|
|
textline " "
|
|
bitfld.long 0x8 3. " LOOPBACK4 ,UART 4 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 2. " LOOPBACK3 ,UART 3 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 1. " LOOPBACK2 ,UART 2 loopback mode" "Turned off,Loopback"
|
|
textline " "
|
|
bitfld.long 0x8 0. " LOOPBACK1 ,UART 1 loopback mode" "Turned off,Loopback"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 1"
|
|
base ad:0x20088000
|
|
width 16.
|
|
group.long 0x00++0xF
|
|
line.long 0x0 "SPI1_GLOBAL,SPI 1 Global Control Register"
|
|
bitfld.long 0x0 1. " RST ,SPI interface reset" "No effect,Reset"
|
|
bitfld.long 0x0 0. " ENABLE ,SPI interface enable" "Disabled,Enabled"
|
|
line.long 0x4 "SPI1_CON,SPI 1 Control Register"
|
|
bitfld.long 0x4 23. " UNIDIR ,Bidirectional or unidirectional usage of the SPIn_DATIO pin" "Bidirectional,Unidirectional"
|
|
bitfld.long 0x4 22. " BHALT ,Busy halt" "Not halted,Halted"
|
|
bitfld.long 0x4 21. " BPOL ,Busy polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x4 19. " MSB ,Order in which data bits are transferred" "MSB first,LSB first"
|
|
bitfld.long 0x4 16.--17. " MODE ,SPI mode selection" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
bitfld.long 0x4 15. " RXTX ,Direction of data transfer" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.long 0x4 14. " THR ,FIFO threshold control" "Disabled,Enabled"
|
|
bitfld.long 0x4 13. " SHIFT_OFF ,Generation of clock pulses on SPIn_CLK control" "Enabled,Disabled"
|
|
bitfld.long 0x4 9.--12. " BITNUM ,Number of bits to be transmitted or received in one block transfer" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
textline " "
|
|
bitfld.long 0x4 7. " MS ,SPI master mode enable" "Not supported,Master mode"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RATE ,SPI transfer rate"
|
|
line.long 0x8 "SPI1_FRM,SPI 1 Frame Count Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " SPIF ,SPI frame count"
|
|
line.long 0xC "SPI1_IER,SPI 1 Interrupt Enable Register"
|
|
bitfld.long 0xC 1. " INTEOT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " INTTHR ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x20088000+0x4))&0x8000)==0x0)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI1_STAT,SPI 1 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Below threshold,At or above threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI1_STAT,SPI 1 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Above threshold,At or below threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "SPI1_DAT,SPI 1 Data Buffer Register"
|
|
in
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "SPI1_TIM_CTRL,SPI1 Timer Control Register"
|
|
bitfld.long 0x0 2. " TIRQE ,Timed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " PIRQE ,Peripheral interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MODE ,Mode" "Timed interrupt,DMA time out"
|
|
line.long 0x4 "SPI1_TIM_COUNT,SPI 1 Timer Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " Count ,Timed interrupt period"
|
|
line.long 0x8 "SPI1_TIM_STAT,SPI 1 Timer Status Register"
|
|
eventfld.long 0x8 15. " TIRQSTAT ,Timed interrupt status flag" "Not pending,Pending"
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI 2"
|
|
base ad:0x20090000
|
|
width 16.
|
|
group.long 0x00++0xF
|
|
line.long 0x0 "SPI2_GLOBAL,SPI 2 Global Control Register"
|
|
bitfld.long 0x0 1. " RST ,SPI interface reset" "No effect,Reset"
|
|
bitfld.long 0x0 0. " ENABLE ,SPI interface enable" "Disabled,Enabled"
|
|
line.long 0x4 "SPI2_CON,SPI 2 Control Register"
|
|
bitfld.long 0x4 23. " UNIDIR ,Bidirectional or unidirectional usage of the SPIn_DATIO pin" "Bidirectional,Unidirectional"
|
|
bitfld.long 0x4 22. " BHALT ,Busy halt" "Not halted,Halted"
|
|
bitfld.long 0x4 21. " BPOL ,Busy polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x4 19. " MSB ,Order in which data bits are transferred" "MSB first,LSB first"
|
|
bitfld.long 0x4 16.--17. " MODE ,SPI mode selection" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
bitfld.long 0x4 15. " RXTX ,Direction of data transfer" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.long 0x4 14. " THR ,FIFO threshold control" "Disabled,Enabled"
|
|
bitfld.long 0x4 13. " SHIFT_OFF ,Generation of clock pulses on SPIn_CLK control" "Enabled,Disabled"
|
|
bitfld.long 0x4 9.--12. " BITNUM ,Number of bits to be transmitted or received in one block transfer" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
textline " "
|
|
bitfld.long 0x4 7. " MS ,SPI master mode enable" "Not supported,Master mode"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RATE ,SPI transfer rate"
|
|
line.long 0x8 "SPI2_FRM,SPI 2 Frame Count Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " SPIF ,SPI frame count"
|
|
line.long 0xC "SPI2_IER,SPI 2 Interrupt Enable Register"
|
|
bitfld.long 0xC 1. " INTEOT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " INTTHR ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x20090000+0x4))&0x8000)==0x0)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI2_STAT,SPI 2 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Below threshold,At or above threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI2_STAT,SPI 2 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Above threshold,At or below threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "SPI2_DAT,SPI 2 Data Buffer Register"
|
|
in
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "SPI2_TIM_CTRL,SPI2 Timer Control Register"
|
|
bitfld.long 0x0 2. " TIRQE ,Timed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " PIRQE ,Peripheral interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MODE ,Mode" "Timed interrupt,DMA time out"
|
|
line.long 0x4 "SPI2_TIM_COUNT,SPI 2 Timer Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " Count ,Timed interrupt period"
|
|
line.long 0x8 "SPI2_TIM_STAT,SPI 2 Timer Status Register"
|
|
eventfld.long 0x8 15. " TIRQSTAT ,Timed interrupt status flag" "Not pending,Pending"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "SSP (Synchronous Serial Port)"
|
|
tree "SSP 0"
|
|
base ad:0x20084000
|
|
width 11.
|
|
if ((d.l(ad:0x20084000)&0x30)==0x0)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock Out Phase" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " CPOL ,Clock Out Polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" "Reserved,Reserved,Reserved,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" "Reserved,Reserved,Reserved,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
endif
|
|
if ((d.l(ad:0x20084000+0x04)&0x4)==0x4)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
newline
|
|
bitfld.long 0x00 3. " SOD ,Slave Output Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "SSP0DR,SSP0 Data Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x0c++0x3
|
|
line.long 0x00 "SSP0SR,SSP0 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO Not Empty" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Not Full" "Full,Not Full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SSP0CPSR,SSP0 Clock Prescale Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CPSDVSR ,PCLK Divisor (even value between 2 and 254)"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SSP0IMSC,SSP0 Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Tx FIFO Half Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIM ,Rx FIFO Half Full Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "SSP0RIS,SSP0 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO Half Empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO Half Full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive Timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 0. " RORRIS ,Frame Received When RxFIFO Full" "Not received,Received"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "SSP0MIS,SSP0 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXMIS ,Tx FIFO Half Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXMIS ,Rx FIFO Half Full Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTMIS ,Receive Timeout Interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " RORMIS ,Frame Received When RxFIFO Full Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SSP0ICR,SSP0 Interrupt Clear Register"
|
|
bitfld.long 0x0 1. " RTIC ,Receive Timeout Clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RORIC ,Clear Frame Received When RxFIFO Full" "No effect,Clear"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SSP0DMACR,SSP0 DMA Control Register"
|
|
bitfld.long 0x0 1. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SSP 1"
|
|
base ad:0x2008C000
|
|
width 11.
|
|
if ((d.l(ad:0x2008C000)&0x30)==0x0)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP1CR0,SSP1 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock Out Phase" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " CPOL ,Clock Out Polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" "Reserved,Reserved,Reserved,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SSP1CR0,SSP1 Control Register 0"
|
|
hexmask.long.byte 0x0 8.--15. 1. " SCR ,Serial Clock Rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame Format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data Size Select" "Reserved,Reserved,Reserved,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
endif
|
|
if ((d.l(ad:0x2008C000+0x04)&0x4)==0x4)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
newline
|
|
bitfld.long 0x00 3. " SOD ,Slave Output Disable" "No,Yes"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 2. " MS ,Master/Slave Mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop Back Mode" "Normal,Loopback"
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "SSP1DR,SSP1 Data Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x0c++0x3
|
|
line.long 0x00 "SSP1SR,SSP1 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO Not Empty" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Not Full" "Full,Not Full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SSP1CPSR,SSP1 Clock Prescale Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CPSDVSR ,PCLK Divisor (even value between 2 and 254)"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SSP1IMSC,SSP1 Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Tx FIFO Half Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIM ,Rx FIFO Half Full Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "SSP1RIS,SSP1 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO Half Empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO Half Full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive Timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 0. " RORRIS ,Frame Received When RxFIFO Full" "Not received,Received"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "SSP1MIS,SSP1 Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXMIS ,Tx FIFO Half Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXMIS ,Rx FIFO Half Full Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTMIS ,Receive Timeout Interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " RORMIS ,Frame Received When RxFIFO Full Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SSP1ICR,SSP1 Interrupt Clear Register"
|
|
bitfld.long 0x0 1. " RTIC ,Receive Timeout Clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " RORIC ,Clear Frame Received When RxFIFO Full" "No effect,Clear"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SSP1DMACR,SSP1 DMA Control Register"
|
|
bitfld.long 0x0 1. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C 1"
|
|
base ad:0x400A0000
|
|
width 13.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "I2C1_RX/TX,I2C 1 RX/TX Data FIFO"
|
|
in
|
|
group.long 0x04++0x13
|
|
line.long 0x0 "I2C1_STAT,I2C 1 Status Register"
|
|
bitfld.long 0x00 13. " TFES ,Slave Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TFFS ,Slave Transmit FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TFF ,Transmit FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDA ,The current value of the SDA signal" "Low,High"
|
|
bitfld.long 0x00 6. " SCL ,The current value of the SCL signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ACTIVE ,Bus activity" "Idle,Busy"
|
|
bitfld.long 0x00 4. " DRSI ,Slave Data Request Interrupt" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRMI ,Master Data Request Interrupt" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " NAI ,No Acknowledge Interrupt" "Acknowledged,Not acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 1. " AFI ,Arbitration Failure Interrupt" "Not failed,Failed"
|
|
eventfld.long 0x00 0. " TDI ,Transaction Done Interrupt" "Not completed,Completed"
|
|
line.long 0x04 "I2C1_CTRL,I2C 1 Control Register"
|
|
bitfld.long 0x04 10. " TFFSIE ,Slave Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SEVEN ,Seven-bit slave address" "7-bit,10-bit"
|
|
textline " "
|
|
sif (cpuis("LPC313*"))
|
|
bitfld.long 0x04 8. " RESET ,Soft Reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x04 8. " RFF ,Soft Reset" "No effect,Reset"
|
|
endif
|
|
bitfld.long 0x04 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RFDAIE ,Receive FIFO Data Available Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RFFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DRSIE ,Data Request Slave Transmitter Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DRMIE ,Data Request Master Transmitter Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " AFIE ,Transmitter Arbitration Failure Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "I2C1_CLK_HI,I2C 1 Clock Divider High Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLK_DIV_HI ,Clock Divisor High"
|
|
line.long 0x0C "I2C1_CLK_LO,I2C 1 Clock Divider Low Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " CLK_DIV_LO ,Clock Divisor Low"
|
|
line.long 0x10 "I2C1_ADR, I2C 1 Slave Address"
|
|
hexmask.long.word 0x10 0.--9. 1. " ADR ,ADR is the I2C bus slave address"
|
|
group.long 0x18++0xF
|
|
line.long 0x00 "I2C1_RXFL,I2C 1 Receive FIFO level"
|
|
bitfld.long 0x00 0.--1. " RXFL , Receive FIFO level" "0,1,2,3"
|
|
line.long 0x04 "I2C1_TXFL,I2C 1 Transmit FIFO level"
|
|
bitfld.long 0x04 0.--1. " TXFL , Transmit FIFO level" "0,1,2,3"
|
|
line.long 0x08 "I2C1_RXB,I2Cn Receive byte count"
|
|
hexmask.long.word 0x08 0.--15. 1. " RXB ,Number of bytes received"
|
|
line.long 0x0C "I2C1_TXB,I2Cn Transmit byte count"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXB ,Number of bytes transmit"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "I2C1_S_TX,Slave Transmit FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXS ,Slave Transmit FIFO data bits 7:0"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "I2C1_S_TXFL, Slave Transmit FIFO level"
|
|
bitfld.long 0x00 0.--1. " TXFL , Slave Transmit FIFO level" "0,1,2,3"
|
|
width 0xB
|
|
tree.end
|
|
tree "I2C 2"
|
|
base ad:0x400A8000
|
|
width 13.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "I2C2_RX/TX,I2C 2 RX/TX Data FIFO"
|
|
in
|
|
group.long 0x04++0x13
|
|
line.long 0x0 "I2C2_STAT,I2C 2 Status Register"
|
|
bitfld.long 0x00 13. " TFES ,Slave Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TFFS ,Slave Transmit FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TFF ,Transmit FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDA ,The current value of the SDA signal" "Low,High"
|
|
bitfld.long 0x00 6. " SCL ,The current value of the SCL signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ACTIVE ,Bus activity" "Idle,Busy"
|
|
bitfld.long 0x00 4. " DRSI ,Slave Data Request Interrupt" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRMI ,Master Data Request Interrupt" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " NAI ,No Acknowledge Interrupt" "Acknowledged,Not acknowledged"
|
|
textline " "
|
|
eventfld.long 0x00 1. " AFI ,Arbitration Failure Interrupt" "Not failed,Failed"
|
|
eventfld.long 0x00 0. " TDI ,Transaction Done Interrupt" "Not completed,Completed"
|
|
line.long 0x04 "I2C2_CTRL,I2C 2 Control Register"
|
|
bitfld.long 0x04 10. " TFFSIE ,Slave Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SEVEN ,Seven-bit slave address" "7-bit,10-bit"
|
|
textline " "
|
|
sif (cpuis("LPC313*"))
|
|
bitfld.long 0x04 8. " RESET ,Soft Reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x04 8. " RFF ,Soft Reset" "No effect,Reset"
|
|
endif
|
|
bitfld.long 0x04 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " RFDAIE ,Receive FIFO Data Available Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RFFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DRSIE ,Data Request Slave Transmitter Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DRMIE ,Data Request Master Transmitter Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " AFIE ,Transmitter Arbitration Failure Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "I2C2_CLK_HI,I2C 2 Clock Divider High Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " CLK_DIV_HI ,Clock Divisor High"
|
|
line.long 0x0C "I2C2_CLK_LO,I2C 2 Clock Divider Low Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " CLK_DIV_LO ,Clock Divisor Low"
|
|
line.long 0x10 "I2C2_ADR, I2C 2 Slave Address"
|
|
hexmask.long.word 0x10 0.--9. 1. " ADR ,ADR is the I2C bus slave address"
|
|
group.long 0x18++0xF
|
|
line.long 0x00 "I2C2_RXFL,I2C 2 Receive FIFO level"
|
|
bitfld.long 0x00 0.--1. " RXFL , Receive FIFO level" "0,1,2,3"
|
|
line.long 0x04 "I2C2_TXFL,I2C 2 Transmit FIFO level"
|
|
bitfld.long 0x04 0.--1. " TXFL , Transmit FIFO level" "0,1,2,3"
|
|
line.long 0x08 "I2C2_RXB,I2Cn Receive byte count"
|
|
hexmask.long.word 0x08 0.--15. 1. " RXB ,Number of bytes received"
|
|
line.long 0x0C "I2C2_TXB,I2Cn Transmit byte count"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXB ,Number of bytes transmit"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "I2C2_S_TX,Slave Transmit FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXS ,Slave Transmit FIFO data bits 7:0"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "I2C2_S_TXFL, Slave Transmit FIFO level"
|
|
bitfld.long 0x00 0.--1. " TXFL , Slave Transmit FIFO level" "0,1,2,3"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2S (Inter-IC Sound)"
|
|
tree "I2S 0"
|
|
base ad:0x20094000
|
|
width 11.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2S0DAO,Digital Audio Output Register"
|
|
bitfld.long 0x00 15. " MUTE ,The transmit channel sends only zeroes" "Not muted,Muted"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,long select half period minus one"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WS_SEL ,Slave mode" "Master,Slave"
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " MONO ,Data of monaural format" "Stereo,Monaural"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,Reserved,32 bit"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "I2S0DAI,Digital Audio Input Register"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,long select half period minus one"
|
|
bitfld.long 0x00 5. " WS_SEL ,Slave mode" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONO ,Data of monaural format" "Stereo,Monaural"
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,Reserved,32 bit"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "I2S0TXFIFO,Transmit FIFO Register"
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x0 "I2S0RXFIFO,Receive FIFO Register"
|
|
in
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "I2S0STATE,Status Feedback Register"
|
|
bitfld.long 0x00 16.--19. " TX_LEVEL ,Current level of the Transmit FIFO" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " RX_LEVEL ,Current level of the Receive FIFO" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMA1 ,Presence of Receive or Transmit DMA Request 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DMA0 ,Presence of Receive or Transmit DMA Request 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRQ ,Presence of Receive Interrupt or Transmit Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "I2S0DMA0,DMA Configuration Register 1"
|
|
bitfld.long 0x00 16.--19. " TX_DEPTH_DMA0 ,Set the FIFO level that triggers a transmit DMA request on DMA0" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " RX_DEPTH_DMA0 ,FIFO level that triggers a receive DMA request on DMA0" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_DMA0_ENABLE ,Enables DMA0 for I2S 0 transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_DMA0_ENABLE ,Enables DMA0 for I2S 0 receive" "Disabled,Enabled"
|
|
line.long 0x4 "I2S0DMA1,DMA Configuration Register 2"
|
|
bitfld.long 0x04 16.--18. " TX_DEPTH_DMA1 ,FIFO level that triggers a transmit DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " RX_DEPTH_DMA1 ,FIFO level that triggers a receive DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX_DMA1_ENABLE ,Enables DMA1 for I2S 0 transmit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RX_DMA1_ENABLE ,Enables DMA1 for I2S 0 receive" "Disabled,Enabled"
|
|
line.long 0x8 "I2S0IRQ,Interrupt Request Control Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TX_DEPTH_IRQ ,FIFO level on which to create an irq request"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RX_DEPTH_IRQ ,FIFO level on which to create an irq request"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TX_IRQ_ENABLE ,Enables I2S 0 transmit interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RX_IRQ_ENABLE ,Enables I2S 0 receive interrupt" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "I2S0TXRATE,Transmit bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " X_DIVIDER ,I2S 0 transmit bit rate numerator"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Y_DIVIDER ,I2S 0 transmit bit rate denominator"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "I2S0RXRATE,Receive bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " X_DIVIDER ,I2S 0 receive bit rate numerator"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Y_DIVIDER ,I2S 0 receive bit rate denominator"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2S 1"
|
|
base ad:0x2009C000
|
|
width 11.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "I2S1DAO,Digital Audio Output Register"
|
|
bitfld.long 0x00 15. " MUTE ,The transmit channel sends only zeroes" "Not muted,Muted"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,long select half period minus one"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WS_SEL ,Slave mode" "Master,Slave"
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " MONO ,Data of monaural format" "Stereo,Monaural"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,Reserved,32 bit"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "I2S1DAI,Digital Audio Input Register"
|
|
hexmask.long.word 0x00 6.--14. 1. " WS_HALFPERIOD ,long select half period minus one"
|
|
bitfld.long 0x00 5. " WS_SEL ,Slave mode" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESET ,Asynchronously reset the transmit channel and FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 3. " STOP ,Disables accesses on FIFOs/places the transmit channel in mute mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONO ,Data of monaural format" "Stereo,Monaural"
|
|
bitfld.long 0x00 0.--1. " WORDWIDTH ,Selects the number of bytes in data" "8 bit,16 bit,Reserved,32 bit"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "I2S1TXFIFO,Transmit FIFO Register"
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x0 "I2S1RXFIFO,Receive FIFO Register"
|
|
in
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "I2S1STATE,Status Feedback Register"
|
|
bitfld.long 0x00 16.--19. " TX_LEVEL ,Current level of the Transmit FIFO" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " RX_LEVEL ,Current level of the Receive FIFO" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMA1 ,Presence of Receive or Transmit DMA Request 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " DMA0 ,Presence of Receive or Transmit DMA Request 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRQ ,Presence of Receive Interrupt or Transmit Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "I2S1DMA0,DMA Configuration Register 1"
|
|
bitfld.long 0x00 16.--19. " TX_DEPTH_DMA0 ,Set the FIFO level that triggers a transmit DMA request on DMA0" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " RX_DEPTH_DMA0 ,FIFO level that triggers a receive DMA request on DMA0" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_DMA0_ENABLE ,Enables DMA0 for I2S 1 transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_DMA0_ENABLE ,Enables DMA0 for I2S 1 receive" "Disabled,Enabled"
|
|
line.long 0x4 "I2S1DMA1,DMA Configuration Register 2"
|
|
bitfld.long 0x04 16.--18. " TX_DEPTH_DMA1 ,FIFO level that triggers a transmit DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " RX_DEPTH_DMA1 ,FIFO level that triggers a receive DMA request on DMA1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX_DMA1_ENABLE ,Enables DMA1 for I2S 1 transmit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RX_DMA1_ENABLE ,Enables DMA1 for I2S 1 receive" "Disabled,Enabled"
|
|
line.long 0x8 "I2S1IRQ,Interrupt Request Control Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TX_DEPTH_IRQ ,FIFO level on which to create an irq request"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RX_DEPTH_IRQ ,FIFO level on which to create an irq request"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TX_IRQ_ENABLE ,Enables I2S 1 transmit interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RX_IRQ_ENABLE ,Enables I2S 1 receive interrupt" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "I2S1TXRATE,Transmit bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " X_DIVIDER ,I2S 1 transmit bit rate numerator"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Y_DIVIDER ,I2S 1 transmit bit rate denominator"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "I2S1RXRATE,Receive bit (Clock) rate divider Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " X_DIVIDER ,I2S 1 receive bit rate numerator"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Y_DIVIDER ,I2S 1 receive bit rate denominator"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "Standard Timers"
|
|
tree "Timer 0"
|
|
base ad:0x40044000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "T0IR,Timer0 Interrupt Register"
|
|
eventfld.byte 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "T0TCR,Timer0 Timer Control Register"
|
|
bitfld.byte 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T0TC,Timer0 Timer Counter Register"
|
|
line.long 0x04 "T0PR,Timer0 Prescale Register"
|
|
line.long 0x08 "T0PC,Timer0 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T0MR0,Timer0 Match Register 0"
|
|
line.long 0x04 "T0MR1,Timer0 Match Register 1"
|
|
line.long 0x08 "T0MR2,Timer0 Match Register 2"
|
|
line.long 0x0C "T0MR3,Timer0 Match Register 3"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "T0MCR,Timer0 Match Control Register"
|
|
bitfld.word 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T0CR0,Timer0 Capture Register 0"
|
|
line.long 0x04 "T0CR1,Timer0 Capture Register 1"
|
|
line.long 0x08 "T0CR2,Timer0 Capture Register 2"
|
|
line.long 0x0C "T0CR3,Timer0 Capture Register 3"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "T0CCR,Timer0 Capture Control Register"
|
|
bitfld.word 0x00 11. " CAP3I ,Interrupt on CAP0.3 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CAP3FE ,Capture on CAP0.3 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CAP3RE ,Capture on CAP0.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CAP2I ,Interrupt on CAP0.2 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CAP2FE ,Capture on CAP0.2 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CAP2RE ,Capture on CAP0.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAP1I ,Interrupt on CAP0.1 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CAP1FE ,Capture on CAP0.1 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CAP1RE ,Capture on CAP0.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CAP0I ,Interrupt on CAP0.0 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CAP0FE ,Capture on CAP0.0 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CAP0RE ,Capture on CAP0.0 rising edge" "Disabled,Enabled"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "T0EMR,Timer0 External Match Register"
|
|
bitfld.word 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.word 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.word 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
if ((data.byte(ad:0x40044000+0x70)&0x3)==0x0)
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T0CTCR,Timer0 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T0CTCR,Timer0 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.byte 0x00 2.--3. " CIS ,Counter Input Select" "CAP0.0,CAP0.1,CAP0.2,CAP0.3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 1"
|
|
base ad:0x4004C000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "T1IR,Timer1 Interrupt Register"
|
|
eventfld.byte 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "T1TCR,Timer1 Timer Control Register"
|
|
bitfld.byte 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T1TC,Timer1 Timer Counter Register"
|
|
line.long 0x04 "T1PR,Timer1 Prescale Register"
|
|
line.long 0x08 "T1PC,Timer1 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T1MR0,Timer1 Match Register 0"
|
|
line.long 0x04 "T1MR1,Timer1 Match Register 1"
|
|
line.long 0x08 "T1MR2,Timer1 Match Register 2"
|
|
line.long 0x0C "T1MR3,Timer1 Match Register 3"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "T1MCR,Timer1 Match Control Register"
|
|
bitfld.word 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T1CR0,Timer1 Capture Register 0"
|
|
line.long 0x04 "T1CR1,Timer1 Capture Register 1"
|
|
line.long 0x08 "T1CR2,Timer1 Capture Register 2"
|
|
line.long 0x0C "T1CR3,Timer1 Capture Register 3"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "T1CCR,Timer1 Capture Control Register"
|
|
bitfld.word 0x00 11. " CAP3I ,Interrupt on CAP1.3 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CAP3FE ,Capture on CAP1.3 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CAP3RE ,Capture on CAP1.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CAP2I ,Interrupt on CAP1.2 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CAP2FE ,Capture on CAP1.2 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CAP2RE ,Capture on CAP1.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAP1I ,Interrupt on CAP1.1 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CAP1FE ,Capture on CAP1.1 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CAP1RE ,Capture on CAP1.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CAP0I ,Interrupt on CAP1.0 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CAP0FE ,Capture on CAP1.0 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CAP0RE ,Capture on CAP1.0 rising edge" "Disabled,Enabled"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "T1EMR,Timer1 External Match Register"
|
|
bitfld.word 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.word 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.word 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
if ((data.byte(ad:0x4004C000+0x70)&0x3)==0x0)
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T1CTCR,Timer1 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T1CTCR,Timer1 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.byte 0x00 2.--3. " CIS ,Counter Input Select" "CAP1.0,CAP1.1,CAP1.2,CAP1.3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 2"
|
|
base ad:0x40058000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "T2IR,Timer2 Interrupt Register"
|
|
eventfld.byte 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "T2TCR,Timer2 Timer Control Register"
|
|
bitfld.byte 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T2TC,Timer2 Timer Counter Register"
|
|
line.long 0x04 "T2PR,Timer2 Prescale Register"
|
|
line.long 0x08 "T2PC,Timer2 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T2MR0,Timer2 Match Register 0"
|
|
line.long 0x04 "T2MR1,Timer2 Match Register 1"
|
|
line.long 0x08 "T2MR2,Timer2 Match Register 2"
|
|
line.long 0x0C "T2MR3,Timer2 Match Register 3"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "T2MCR,Timer2 Match Control Register"
|
|
bitfld.word 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T2CR0,Timer2 Capture Register 0"
|
|
line.long 0x04 "T2CR1,Timer2 Capture Register 1"
|
|
line.long 0x08 "T2CR2,Timer2 Capture Register 2"
|
|
line.long 0x0C "T2CR3,Timer2 Capture Register 3"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "T2CCR,Timer2 Capture Control Register"
|
|
bitfld.word 0x00 11. " CAP3I ,Interrupt on CAP2.3 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CAP3FE ,Capture on CAP2.3 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CAP3RE ,Capture on CAP2.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CAP2I ,Interrupt on CAP2.2 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CAP2FE ,Capture on CAP2.2 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CAP2RE ,Capture on CAP2.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAP1I ,Interrupt on CAP2.1 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CAP1FE ,Capture on CAP2.1 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CAP1RE ,Capture on CAP2.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CAP0I ,Interrupt on CAP2.0 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CAP0FE ,Capture on CAP2.0 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CAP0RE ,Capture on CAP2.0 rising edge" "Disabled,Enabled"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "T2EMR,Timer2 External Match Register"
|
|
bitfld.word 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.word 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.word 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
if ((data.byte(ad:0x40058000+0x70)&0x3)==0x0)
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T2CTCR,Timer2 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T2CTCR,Timer2 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.byte 0x00 2.--3. " CIS ,Counter Input Select" "CAP2.0,CAP2.1,CAP2.2,CAP2.3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 3"
|
|
base ad:0x40060000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "T3IR,Timer3 Interrupt Register"
|
|
eventfld.byte 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "T3TCR,Timer3 Timer Control Register"
|
|
bitfld.byte 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T3TC,Timer3 Timer Counter Register"
|
|
line.long 0x04 "T3PR,Timer3 Prescale Register"
|
|
line.long 0x08 "T3PC,Timer3 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T3MR0,Timer3 Match Register 0"
|
|
line.long 0x04 "T3MR1,Timer3 Match Register 1"
|
|
line.long 0x08 "T3MR2,Timer3 Match Register 2"
|
|
line.long 0x0C "T3MR3,Timer3 Match Register 3"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "T3MCR,Timer3 Match Control Register"
|
|
bitfld.word 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "T3CR0,Timer3 Capture Register 0"
|
|
line.long 0x04 "T3CR1,Timer3 Capture Register 1"
|
|
line.long 0x08 "T3CR2,Timer3 Capture Register 2"
|
|
line.long 0x0C "T3CR3,Timer3 Capture Register 3"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "T3CCR,Timer3 Capture Control Register"
|
|
bitfld.word 0x00 11. " CAP3I ,Interrupt on CAP3.3 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CAP3FE ,Capture on CAP3.3 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CAP3RE ,Capture on CAP3.3 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CAP2I ,Interrupt on CAP3.2 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CAP2FE ,Capture on CAP3.2 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CAP2RE ,Capture on CAP3.2 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAP1I ,Interrupt on CAP3.1 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CAP1FE ,Capture on CAP3.1 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CAP1RE ,Capture on CAP3.1 rising edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CAP0I ,Interrupt on CAP3.0 event" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CAP0FE ,Capture on CAP3.0 falling edge" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CAP0RE ,Capture on CAP3.0 rising edge" "Disabled,Enabled"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "T3EMR,Timer3 External Match Register"
|
|
bitfld.word 0x00 10.--11. " EMC3 ,External Match Control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " EMC2 ,External Match Control 2" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " EMC1 ,External Match Control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " EMC0 ,External Match Control 0" "No operation,Cleared,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " EM3 ,External Match 3" "Low,High"
|
|
bitfld.word 0x00 2. " EM2 ,External Match 2" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EM1 ,External Match 1" "Low,High"
|
|
bitfld.word 0x00 0. " EM0 ,External Match 0" "Low,High"
|
|
if ((data.byte(ad:0x40060000+0x70)&0x3)==0x0)
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T3CTCR,Timer3 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T3CTCR,Timer3 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.byte 0x00 2.--3. " CIS ,Counter Input Select" "CAP3.0,CAP3.1,CAP3.2,CAP3.3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 4"
|
|
base ad:0x4002C000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "T4IR,Timer4 Interrupt Register"
|
|
eventfld.byte 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "T4TCR,Timer4 Timer Control Register"
|
|
bitfld.byte 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T4TC,Timer4 Timer Counter Register"
|
|
line.long 0x04 "T4PR,Timer4 Prescale Register"
|
|
line.long 0x08 "T4PC,Timer4 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T4MR0,Timer4 Match Register 0"
|
|
line.long 0x04 "T4MR1,Timer4 Match Register 1"
|
|
line.long 0x08 "T4MR2,Timer4 Match Register 2"
|
|
line.long 0x0C "T4MR3,Timer4 Match Register 3"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "T4MCR,Timer4 Match Control Register"
|
|
bitfld.word 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "T4CR0,Timer4 Capture Register 0"
|
|
if ((data.byte(ad:0x4002C000+0x70)&0x3)==0x0)
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T4CTCR,Timer4 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T4CTCR,Timer4 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.byte 0x00 2.--3. " CIS ,Counter Input Select" "CAP4.0,CAP4.1,CAP4.2,CAP4.3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 5"
|
|
base ad:0x40030000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "T5IR,Timer5 Interrupt Register"
|
|
eventfld.byte 0x00 7. " CR3INTERRUPT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " CR2INTERRUPT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " CR1INTERRUPT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 4. " CR0INTERRUPT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " MR3INTERRUPT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 2. " MR2INTERRUPT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " MR1INTERRUPT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 0. " MR0INTERRUPT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "T5TCR,Timer5 Timer Control Register"
|
|
bitfld.byte 0x00 1. " COUNTERRESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " COUNTERENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x08++0xb
|
|
line.long 0x00 "T5TC,Timer5 Timer Counter Register"
|
|
line.long 0x04 "T5PR,Timer5 Prescale Register"
|
|
line.long 0x08 "T5PC,Timer5 Prescale Counter Register"
|
|
group.long 0x18++0x0f
|
|
line.long 0x00 "T5MR0,Timer5 Match Register 0"
|
|
line.long 0x04 "T5MR1,Timer5 Match Register 1"
|
|
line.long 0x08 "T5MR2,Timer5 Match Register 2"
|
|
line.long 0x0C "T5MR3,Timer5 Match Register 3"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "T5MCR,Timer5 Match Control Register"
|
|
bitfld.word 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
if ((data.byte(ad:0x40030000+0x70)&0x3)==0x0)
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T5CTCR,Timer5 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
else
|
|
group.byte 0x70++0x0
|
|
line.byte 0x00 "T5CTCR,Timer5 Count Control Register"
|
|
bitfld.byte 0x00 0.--1. " CTM ,Counter/Timer Mode" "Every rising PCLK edge,Incremented on rising edge,Incremented on falling edge,Incremented on both edges"
|
|
bitfld.byte 0x00 2.--3. " CIS ,Counter Input Select" "CAP5.0,CAP5.1,CAP5.2,CAP5.3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "High Speed Timer"
|
|
base ad:0x40038000
|
|
width 15.
|
|
group.long 0x00++0x23
|
|
line.long 0x0 "HSTIM_INT,High Speed Timer Interrupt Status Register"
|
|
eventfld.long 0x0 5. " RTC_TICK ,RTC tick capture status" "Inactive,Active"
|
|
eventfld.long 0x0 4. " HSTIM_CAP ,HSTIM_CAP tick capture status" "Inactive,Active"
|
|
eventfld.long 0x0 2. " MATCH2_INT ,MATCH2 interrupt status" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 1. " MATCH1_INT ,MATCH1 interrupt status" "Inactive,Active"
|
|
eventfld.long 0x0 0. " MATCH0_INT ,MATCH0 interrupt status" "Inactive,Active"
|
|
line.long 0x4 "HSTIM_CTRL,High Speed Timer Control Register"
|
|
bitfld.long 0x4 2. " PAUSE_EN ,Pause enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " RESET_COUNT ,Timer counter reset" "No reset,Reset"
|
|
bitfld.long 0x4 0. " COUNT_ENAB ,Timer counter enable" "Stopped,Enabled"
|
|
line.long 0x8 "HSTIM_COUNTER,High Speed Timer Counter Value Register"
|
|
line.long 0xC "HSTIM_PMATCH,High Speed Timer Prescale Counter Match Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " PMATCH ,Prescale counter match value"
|
|
line.long 0x10 "HSTIM_PCOUNT,High Speed Timer Prescale Counter Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " HSTIM_PCOUNT ,Current value of the Prescale Counter"
|
|
line.long 0x14 "HSTIM_MCTRL,High Speed Timer Match Control Register"
|
|
bitfld.long 0x14 8. " STOP_COUNT2 ,Stop functionality on Match 2" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " RESET_COUNT2 ,Reset of Timer Counter on Match 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MR2_INT ,Interrupt on the Match 2 register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " STOP_COUNT1 ,Stop functionality on Match 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " RESET_COUNT1 ,Reset of Timer Counter on Match 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " MR1_INT ,Interrupt on the Match 1 register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " STOP_COUNT0 ,Stop functionality on Match 0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " RESET_COUNT0 ,Reset of Timer Counter on Match 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MR0_INT ,Interrupt on the Match 0 register enable" "Disabled,Enabled"
|
|
line.long 0x18 "HSTIM_MATCH0,High Speed Timer Match 0 Register"
|
|
line.long 0x1C "HSTIM_MATCH1,High Speed Timer Match 1 Register"
|
|
line.long 0x20 "HSTIM_MATCH2,High Speed Timer Match 2 Register"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "HSTIM_CCR,High Speed Timer Capture Control Register"
|
|
bitfld.long 0x0 5. " RTC_TICK_EVENT ,RTC tick evet capture" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RTC_TICK_FALL ,RTC tick falling edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RTC_TICK_RISE ,RTC tick rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " HSTIM_CAP_EVENT ,GPI_06 capture" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSTIM_CAP_FALL ,GPI_06 falling edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " HSTIM_CAP_RISE ,GPI_06 rising edge detection" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "HSTIM_CR0,High Speed Timer Capture 0 Register"
|
|
line.long 0x4 "HSTIM_CR1,High Speed Timer Capture 1 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Milisecond Timer"
|
|
base ad:0x40034000
|
|
width 15.
|
|
group.long 0x00++0xB
|
|
line.long 0x0 "MSTIM_INT,Millisecond Timer Interrupt Status Register"
|
|
eventfld.long 0x0 1. " MATCH1_INT ,MATCH 1 interrupt active" "Inactive,Active"
|
|
eventfld.long 0x0 0. " MATCH0_INT ,MATCH 0 interrupt active" "Inactive,Active"
|
|
line.long 0x4 "MSTIM_CTRL,Millisecond Timer Control Register"
|
|
bitfld.long 0x4 2. " PAUSE_EN ,Pause enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " RESET_COUNT ,Timer counter reset" "No reset,Reset"
|
|
bitfld.long 0x4 0. " COUNT_ENAB ,Timer counter enable" "Stopped,Enabled"
|
|
line.long 0x8 "MSTIM_COUNTER,Millisecond Timer Counter Value Register"
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "MSTIM_MCTRL,Millisecond Timer Match Control Register"
|
|
bitfld.long 0x0 5. " STOP_COUNT1 ,Stop functionality on Match 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RESET_COUNT1 ,Reset of Timer Counter on Match 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " MR1_INT ,Interrupt on the Match 1 register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " STOP_COUNT0 ,Stop functionality on Match 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " RESET_COUNT0 ,Reset of Timer Counter on Match 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MR0_INT ,Interrupt on the Match 0 register enable" "Disabled,Enabled"
|
|
line.long 0x4 "MSTIM_MATCH0,Millisecond Timer Match 0 Register"
|
|
line.long 0x8 "MSTIM_MATCH1,Millisecond Timer Match 1 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "RTC (Real Time Clock And Battery Ram)"
|
|
base ad:0x40024000
|
|
width 12.
|
|
group.long 0x00++0x1B
|
|
line.long 0x0 "RTC_UCOUNT,RTC Up Counter Value Register"
|
|
line.long 0x4 "RTC_DCOUNT,RTC Down Counter Value Register"
|
|
line.long 0x8 "RTC_MATCH0,RTC Match 0 Register"
|
|
line.long 0xC "RTC_MATCH1,RTC Match 1 Register"
|
|
line.long 0x10 "RTC_CTRL,RTC Control Register"
|
|
bitfld.long 0x10 10. " 32kHzOut ,Output from the 32 kHz oscillator" "Low,High"
|
|
bitfld.long 0x10 7. " ForceONSW ,RTC force ONSW high signal" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CountClkDis ,RTC counter clock disable" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x10 4. " SWRTCRes ,Software controlled RTC reset" "No reset,Reset"
|
|
bitfld.long 0x10 3. " M1ONSWCtrl ,Match 1 ONSW control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " M0ONSWCtrl ,Match 0 ONSW control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " M1IntEn ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " M0IntEn ,Match 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x14 "RTC_INTSTAT,RTC Interrupt Status Register"
|
|
eventfld.long 0x14 2. " ONSW_MSt ,ONSW Match status" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 1. " M1IntStat ,Match 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 0. " M0IntStat ,Match 0 interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x18 "RTC_KEY,RTC Key Register"
|
|
tree "Battery Ram"
|
|
group.long 0x80++0x7F
|
|
line.long 0x0 "RTC_SRAM0,Battery RAM 0"
|
|
line.long 0x4 "RTC_SRAM1,Battery RAM 1"
|
|
line.long 0x8 "RTC_SRAM2,Battery RAM 2"
|
|
line.long 0xC "RTC_SRAM3,Battery RAM 3"
|
|
line.long 0x10 "RTC_SRAM4,Battery RAM 4"
|
|
line.long 0x14 "RTC_SRAM5,Battery RAM 5"
|
|
line.long 0x18 "RTC_SRAM6,Battery RAM 6"
|
|
line.long 0x1C "RTC_SRAM7,Battery RAM 7"
|
|
line.long 0x20 "RTC_SRAM8,Battery RAM 8"
|
|
line.long 0x24 "RTC_SRAM9,Battery RAM 9"
|
|
line.long 0x28 "RTC_SRAM10,Battery RAM 10"
|
|
line.long 0x2C "RTC_SRAM11,Battery RAM 11"
|
|
line.long 0x30 "RTC_SRAM12,Battery RAM 12"
|
|
line.long 0x34 "RTC_SRAM13,Battery RAM 13"
|
|
line.long 0x38 "RTC_SRAM14,Battery RAM 14"
|
|
line.long 0x3C "RTC_SRAM15,Battery RAM 15"
|
|
line.long 0x40 "RTC_SRAM16,Battery RAM 16"
|
|
line.long 0x44 "RTC_SRAM17,Battery RAM 17"
|
|
line.long 0x48 "RTC_SRAM18,Battery RAM 18"
|
|
line.long 0x4C "RTC_SRAM19,Battery RAM 19"
|
|
line.long 0x50 "RTC_SRAM20,Battery RAM 20"
|
|
line.long 0x54 "RTC_SRAM21,Battery RAM 21"
|
|
line.long 0x58 "RTC_SRAM22,Battery RAM 22"
|
|
line.long 0x5C "RTC_SRAM23,Battery RAM 23"
|
|
line.long 0x60 "RTC_SRAM24,Battery RAM 24"
|
|
line.long 0x64 "RTC_SRAM25,Battery RAM 25"
|
|
line.long 0x68 "RTC_SRAM26,Battery RAM 26"
|
|
line.long 0x6C "RTC_SRAM27,Battery RAM 27"
|
|
line.long 0x70 "RTC_SRAM28,Battery RAM 28"
|
|
line.long 0x74 "RTC_SRAM29,Battery RAM 29"
|
|
line.long 0x78 "RTC_SRAM30,Battery RAM 30"
|
|
line.long 0x7C "RTC_SRAM31,Battery RAM 31"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x4003C000
|
|
width 15.
|
|
group.long 0x00++0x1F
|
|
line.long 0x0 "WDTIM_INT,Watchdog Timer Interrupt Status Register"
|
|
eventfld.long 0x0 0. " MATCH_INT ,Match 0 interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x4 "WDTIM_CTRL,Watchdog Timer Control Register"
|
|
bitfld.long 0x4 2. " PAUSE_EN ,Pause enable (debug mode on)" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " RESET_COUNT ,Timer counter reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " COUNT_ENAB ,Timer counter enable" "Stopped,Enabled"
|
|
line.long 0x8 "WDTIM_COUNTER,Watchdog Timer Counter Value Register"
|
|
line.long 0xC "WDTIM_MCTRL,Watchdog Timer Match Control Register"
|
|
bitfld.long 0xC 6. " RESFRC2 ,WDOG_RESET2 signal active force" "Not forced,Forced"
|
|
bitfld.long 0xC 5. " RESFRC1 ,RESOUT_N signal active force" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0xC 4. " M_RES2 ,Match output to generate active WDOG_RESET2 signal" "No effect,Reset"
|
|
bitfld.long 0xC 3. " M_RES1 ,Match output to generate internal device reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 2. " STOP_COUNT0 ,Stop functionality on Match 0" "Disabled,Enabled"
|
|
bitfld.long 0xC 1. " RESET_COUNT0 ,Reset of Timer Counter on Match 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0. " MR0_INT ,Interrupt on the Match 0 enable" "Disabled,Enabled"
|
|
line.long 0x10 "WDTIM_MATCH0,Watchdog Timer Match 0 Register"
|
|
line.long 0x14 "WDTIM_EMR,Watchdog Timer External Match Control Register"
|
|
bitfld.long 0x14 4.--5. " MATCH_CTRL ,External Match Control" "No operation,Reserved,Output high on match,?..."
|
|
bitfld.long 0x14 0. " EXT_MATCH0 ,Value of the match output signal" "Low,High"
|
|
line.long 0x18 "WDTIM_PULSE,Watchdog Timer Reset Pulse Length Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " PULSE ,This register gives the RESET pulse length"
|
|
line.long 0x1C "WDTIM_RES,Watchdog Timer Reset Source Register"
|
|
bitfld.long 0x1C 0. " LastRes ,Last reset source" "RESET_N,Watchdog"
|
|
width 0xB
|
|
tree.end
|
|
tree "MCPWM (Motor Control Pulse Width Modulators)"
|
|
base ad:0x400E8000
|
|
width 11.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "MCCON,MCPWM control register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " DCMODE_set/clr ,3-phase DC mode select" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " ACMODE_set/clr ,3-phase AC mode select" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " INVBDC_set/clr ,Invert MCOB outputs for channels 0 to 2." "Not inverted,Inverted"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " DISUP2_set/clr ,Enable/disable updates of functional registers, channel 2" "Updated,Not updated"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " DTE2_set/clr ,Dead-time, channel 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " POLA2_set/clr ,Selects polarity of the MCOA2 and MCOB2 pins" "Active High,Active Low"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " CENTER2_set/clr ,Edge/center aligned operation, channel 2" "Edge,Center"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " RUN2_set/clr ,Stops/starts the timer, channel 2" "Stop,Run"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DISUP1_set/clr ,Enable/disable updates of functional registers, channel 1" "Updated,Not updated"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DTE1_set/clr ,Controls the dead-time feature for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " POLA1_set/clr ,Selects polarity of the MCOA1 and MCOB1 pins" "Active High,Active Low"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CENTER1_set/clr ,Edge/center aligned operation, channel 1" "Edge,Center"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " RUN1_set/clr ,Stops/starts the timer, channel 1" "Stop,Run"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DISUP0_set/clr ,Enable/disable updates of functional registers, channel 0" "Updated,Not updated"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DTE0_set/clr ,Controls the dead-time feature for channel 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " POLA0_set/clr ,Selects polarity of the MCOA0 and MCOB0 pins" "Active High,Active Low"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CENTER0_set/clr ,Edge/center aligned operation, channel 0" "Edge,Center"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RUN0_set/clr ,Stops/starts the timer, channel 0" "Stop,Run"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "MCCAPCON,MCPWM Capture control register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " HNFCAP2_set/clr ,Enable hardware noise filter" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " HNFCAP1_set/clr ,Enable hardware noise filter" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " HNFCAP0_set/clr ,Enable hardware noise filter" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " RT2_set/clr ,Reset MCTC2 register for any enabled capture event on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " RT1_set/clr ,Reset MCTC1 register for any enabled capture event on channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " RT0_set/clr ,Reset MCTC0 register for any enabled capture event on channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " CAP2MCI2_FE_set/clr ,Enable capture event on channel 2 on the falling edge of the MCI2 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " CAP2MCI2_RE_set/clr ,Enable capture event on channel 2 on the rising edge of the MCI2 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CAP2MCI1_FE_set/clr ,Enable capture event on channel 2 on the falling edge of the MCI1 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " CAP2MCI1_RE_set/clr ,Enable capture event on channel 2 on the rising edge of the MCI1 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " CAP2MCI0_FE_set/clr ,Enable capture event on channel 2 on the falling edge of the MCI0 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CAP2MCI0_RE_set/clr ,Enable capture event on channel 2 on the rising edge of the MCI0 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " CAP1MCI2_FE_set/clr ,Enable capture event on channel 1 on the falling edge of the MCI2 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " CAP1MCI2_RE_set/clr ,Enable capture event on channel 1 on the rising edge of the MCI2 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CAP1MCI1_FE_set/clr ,Enable capture event on channel 1 on the falling edge of the MCI1 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " CAP1MCI1_RE_set/clr ,Enable capture event on channel 1 on the rising edge of the MCI1 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CAP1MCI0_FE_set/clr ,Enable capture event on channel 1 on the falling edge of the MCI0 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CAP1MCI0_RE_set/clr ,Enable capture event on channel 1 on the rising edge of the MCI0 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CAP0MCI2_FE_set/clr ,Enable capture event on channel 0 on the falling edge of the MCI2 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CAP0MCI2_RE_set/clr ,Enable capture event on channel 0 on the rising edge of the MCI2 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CAP0MCI1_FE_set/clr ,Enable capture event on channel 0 on the falling edge of the MCI1 input." "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CAP0MCI1_RE_set/clr ,Enable capture event on channel 0 on the rising edge of the MCI1 input" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CAP0MCI0_FE_set/clr ,Enable capture event on channel 0 on the falling edge of the MCI0 input" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CAP0MCI0_RE_set/clr ,Enable capture event on channel 0 on the rising edge of the MCI0 input" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "MCINTEN,MCPWM interrupt enable register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " ABORT_set/clr ,Fast abort interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICAP2_set/clr ,Capture interrupt for channels 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " IMAT2_set/clr ,Match interrupt for channels 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ILIM2_set/clr ,Limit interrupt for channels 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ICAP1_set/clr ,Capture interrupt for channels 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " IMAT1_set/clr ,Match interrupt for channels 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ILIM1_set/clr ,Limit interrupt for channels 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ICAP0_set/clr ,Capture interrupt for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IMAT0_set/clr ,Match interrupt for channel 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ILIM0_set/clr ,Limit interrupt for channel 0" "Disabled,Enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "MCINTFLAG,MCPWM interrupt flags register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " ABORT_set/clr ,Fast abort interrupt" "Cleared,Set"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ICAP2_set/clr ,Capture interrupt for channels 2" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " IMAT2_set/clr ,Match interrupt for channels 2" "Cleared,Set"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ILIM2_set/clr ,Limit interrupt for channels 2" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ICAP1_set/clr ,Capture interrupt for channels 1" "Cleared,Set"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " IMAT1_set/clr ,Match interrupt for channels 1" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ILIM1_set/clr ,Limit interrupt for channels 1" "Cleared,Set"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ICAP0_set/clr ,Capture interrupt for channel 0" "Cleared,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " IMAT0_set/clr ,Match interrupt for channel 0" "Cleared,Set"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ILIM0_set/clr ,Limit interrupt for channel 0" "Cleared,Set"
|
|
group.long 0x18++0x23
|
|
line.long 0x00 "MCTC0,MCPWM Timer value registers 0"
|
|
line.long 0x04 "MCTC1,MCPWM Timer value registers 1"
|
|
line.long 0x08 "MCTC2,MCPWM Timer value registers 2"
|
|
line.long 0x0C "MCLIM0,MCPWM Limit value register 0"
|
|
line.long 0x10 "MCLIM1,MCPWM Limit value register 1"
|
|
line.long 0x14 "MCLIM2,MCPWM Limit value register 2"
|
|
line.long 0x18 "MCMAT0,MCPWM Match value register 0"
|
|
line.long 0x1C "MCMAT1,MCPWM Match value register 1"
|
|
line.long 0x20 "MCMAT2,MCPWM Match value register 2"
|
|
if ((d.l(ad:0x400E8000)&0x40000000)==0x0)
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "MCDT,MCPWM Dead-time register"
|
|
hexmask.long.word 0x00 20.--29. 1. " DT2 ,Dead time for channel 2"
|
|
hexmask.long.word 0x00 10.--19. 1. " DT1 ,Dead time for channel 1"
|
|
hexmask.long.word 0x00 0.--9. 1. " DT0 ,Dead time for channel 0"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "MCDT,MCPWM Dead-time register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DT0 ,Dead time for all three channels"
|
|
endif
|
|
if ((d.l(ad:0x400E8000)&0x80000000)==0x80000000)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "MCCP,MCPWM Communication pattern register"
|
|
bitfld.long 0x00 5. " CCPB2 ,MCO2B control" "Off,Tracks MCOA0"
|
|
bitfld.long 0x00 4. " CCPA2 ,MCO2A control" "Off,Tracks MCOA0"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CCPB1 ,MCO1B control" "Off,Tracks MCOA0"
|
|
bitfld.long 0x00 2. " CCPA1 ,MCO1A control" "Off,Tracks MCOA0"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CCPB0 ,MCO0B control" "Off,Tracks MCOA0"
|
|
bitfld.long 0x00 0. " CCPA0 ,MCO0A control" "Off,Active"
|
|
else
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "MCCP,MCPWM Communication pattern register"
|
|
endif
|
|
rgroup.long 0x44++0xB
|
|
line.long 0x00 "MCCAP0,TC value at a capture event for channel 0"
|
|
line.long 0x04 "MCCAP1,TC value at a capture event for channel 1"
|
|
line.long 0x08 "MCCAP2,TC value at a capture event for channel 2"
|
|
wgroup.long 0x74++0x3
|
|
line.long 0x00 "MCCAP_CLR,MCPWM Capture register"
|
|
bitfld.long 0x00 2. " CAP_CLR2 ,Clears the MCCAP2 register" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CAP_CLR1 ,Clears the MCCAP1 register" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CAP_CLR0 ,Clears the MCCAP0 register" "No effect,Clear"
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulators)"
|
|
base ad:0x4005C000
|
|
width 11.
|
|
group.long 0x00++0x3 "PWM1"
|
|
line.long 0x0 "PWM1_CTRL,PWM1 Control Register"
|
|
bitfld.long 0x0 31. " PWM1_EN ,PWM1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " PWM1_PIN_LEVEL ,PWM_OUT1 pin state" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PWM1_RELOADV ,Reload value for the PWM output frequency"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PWM1_DUTY ,Output duty cycle"
|
|
group.long 0x04++0x3 "PWM2"
|
|
line.long 0x0 "PWM2_CTRL,PWM2 Control Register"
|
|
bitfld.long 0x0 31. " PWM2_EN ,PWM2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " PWM2_PIN_LEVEL ,PWM_OUT2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " PWM2_INT ,PWM_OUT2 functionality" "Normal,Interrupt Status"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PWM1_RELOADV ,Reload value for the PWM output frequency"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " PWM1_DUTY ,Output duty cycle"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
base ad:0x40028000
|
|
width 14.
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
tree "Port 0"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "P0_INP_STATE,P0 Input Pin State register"
|
|
bitfld.long 0x00 7. " P0.7/I2S0TX_WS|(LCDVD[13]) ,State of the P0.7/I2S0TX_WS|(LCDVD[13]) pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P0.6/I2S0TX_CLK|(LCDVD[12]) ,State of the P0.6/I2S0TX_CLK|(LCDVD[12]) pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P0.5/I2S0TX_SDA|(LCDVD[7]) ,State of the P0.5/I2S0TX_SDA|(LCDVD[7])pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P0.4/I2S0RX_WS|(LCDVD[6]) ,State of the P0.4/I2S0RX_WS|(LCDVD[6]) pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0.3/I2S0RX_CLK|(LCDVD[5]) ,State of the P0.3/I2S0RX_CLK|(LCDVD[5]) pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P0.2/I2S0RX_SDA|(LCDVD[4]) ,State of the P0.2/I2S0RX_SDA|(LCDVD[4]) pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P0.1/I2S1RX_WS ,State of the P0.1/I2S1RX_WS pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0.0/I2S1RX_CLK ,State of the P0.0/I2S1RX_CLK pin" "Low,High"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "P0_OUTP_STATE,P0 Output Pin Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7/I2S0TX_WS|(LCDVD[13])_set/clr , The state of the P0.7/I2S0TX_WS|(LCDVD[13]) pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6/I2S0TX_CLK|(LCDVD[12])_set/clr , The state of the P0.6/I2S0TX_CLK|(LCDVD[12]) pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5/I2S0TX_SDA_set/clr ,State of the P0.5/I2S0TX_SDA|(LCDVD[7])pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4/I2S0RX_WS|(LCDVD[6])_set/clr , The state of the P0.4/I2S0RX_WS|(LCDVD[6]) pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3/I2S0RX_CLK|(LCDVD[5])_set/clr ,State of the P0.3/I2S0RX_CLK|(LCDVD[5]) pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2/I2S0RX_SDA|(LCDVD[4])_set/clr ,State of the P0.2/I2S0RX_SDA|(LCDVD[4]) pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1/I2S1RX_WS_set/clr ,State of the P0.1/I2S1RX_WS pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0/I2S1RX_CLK_set/clr ,State of the P0.0/I2S1RX_CLK pin" "Low,High"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "P0_DIR_STATE,P0 Direction Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7/I2S0TX_WS|(LCDVD[13])_set/clr ,Direction of the P0.7/I2S0TX_WS|(LCDVD[13]) pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6/I2S0TX_CLK|(LCDVD[12])_set/clr ,Direction of the P0.6/I2S0TX_CLK|(LCDVD[12]) pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5/I2S0TX_SDA_set/clr ,Direction of the P0.5/I2S0TX_SDA|(LCDVD[7])pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4/I2S0RX_WS|(LCDVD[6])_set/clr ,Direction of the P0.4/I2S0RX_WS|(LCDVD[6]) pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3/I2S0RX_CLK|(LCDVD[5])_set/clr ,Direction of the P0.3/I2S0RX_CLK|(LCDVD[5]) pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2/I2S0RX_SDA|(LCDVD[4])_set/clr ,Direction of the P0.2/I2S0RX_SDA|(LCDVD[4]) pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1/I2S1RX_WS_set/clr ,Direction of the P0.1/I2S1RX_WS pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0/I2S1RX_CLK_set/clr ,Direction of the P0.0/I2S1RX_CLK pin" "Input,Output"
|
|
tree.end
|
|
tree "Port 1"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "P1_INP_STATE,P1 Input Pin Register for EMC Address pins"
|
|
bitfld.long 0x00 23. " EMC_A[23]/P1.23_set/clr , The state of the P1.23 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMC_A[22]/P1.22_set/clr , The state of the P1.22 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMC_A[21]/P1.21_set/clr , The state of the P1.21 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EMC_A[20]/P1.20_set/clr , The state of the P1.20 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EMC_A[19]/P1.19_set/clr , The state of the P1.19 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EMC_A[18]/P1.18_set/clr , The state of the P1.18 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMC_A[17]/P1.17_set/clr , The state of the P1.17 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EMC_A[16]/P1.16_set/clr , The state of the P1.16 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EMC_A[15]/P1.15_set/clr , The state of the P1.15 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EMC_A[14]/P1.14_set/clr , The state of the P1.14 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EMC_A[13]/P1.13_set/clr , The state of the P1.13 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EMC_A[12]/P1.12_set/clr , The state of the P1.12 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EMC_A[11]/P1.11_set/clr , The state of the P1.11 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMC_A[10]/P1.10_set/clr , The state of the P1.10 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC_A[9]/P1.9_set/clr , The state of the P1.9 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMC_A[8]/P1.8_set/clr , The state of the P1.8 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC_A[7]/P1.7_set/clr , The state of the P1.7 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EMC_A[6]/P1.6_set/clr , The state of the P1.6 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC_A[5]/P1.5_set/clr , The state of the P1.5 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMC_A[4]/P1.4_set/clr , The state of the P1.4 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC_A[3]/P1.3_set/clr , The state of the P1.3 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EMC_A[2]/P1.2_set/clr , The state of the P1.2 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC_A[1]/P1.1_set/clr , The state of the P1.1 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMC_A[0]/P1.0_set/clr , The state of the P1.0 pin" "Low,High"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "P1_OUTP_STATE,P1 Output Pin Register for EMC address pins"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EMC_A[23]/P1.23_set/clr , The state of the P1.23 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EMC_A[22]/P1.22_set/clr , The state of the P1.22 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EMC_A[21]/P1.21_set/clr , The state of the P1.21 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EMC_A[20]/P1.20_set/clr , The state of the P1.20 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EMC_A[19]/P1.19_set/clr , The state of the P1.19 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EMC_A[18]/P1.18_set/clr , The state of the P1.18 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EMC_A[17]/P1.17_set/clr , The state of the P1.17 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EMC_A[16]/P1.16_set/clr , The state of the P1.16 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EMC_A[15]/P1.15_set/clr , The state of the P1.15 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EMC_A[14]/P1.14_set/clr , The state of the P1.14 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EMC_A[13]/P1.13_set/clr , The state of the P1.13 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_A[12]/P1.12_set/clr , The state of the P1.12 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_A[11]/P1.11_set/clr , The state of the P1.11 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_A[10]/P1.10_set/clr , The state of the P1.10 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_A[9]/P1.9_set/clr , The state of the P1.9 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_A[8]/P1.8_set/clr , The state of the P1.8 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_A[7]/P1.7_set/clr , The state of the P1.7 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_A[6]/P1.6_set/clr , The state of the P1.6 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_A[5]/P1.5_set/clr , The state of the P1.5 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_A[4]/P1.4_set/clr , The state of the P1.4 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_A[3]/P1.3_set/clr , The state of the P1.3 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_A[2]/P1.2_set/clr , The state of the P1.2 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_A[1]/P1.1_set/clr , The state of the P1.1 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_A[0]/P1.0_set/clr , The state of the P1.0 pin" "Low,High"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "P1_DIR_STATE,P1 Direction Register"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EMC_A[23]/P1.23_set/clr , Direction of the P1.23 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EMC_A[22]/P1.22_set/clr , Direction of the P1.22 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EMC_A[21]/P1.21_set/clr , Direction of the P1.21 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EMC_A[20]/P1.20_set/clr , Direction of the P1.20 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EMC_A[19]/P1.19_set/clr , Direction of the P1.19 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EMC_A[18]/P1.18_set/clr , Direction of the P1.18 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EMC_A[17]/P1.17_set/clr , Direction of the P1.17 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EMC_A[16]/P1.16_set/clr , Direction of the P1.16 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EMC_A[15]/P1.15_set/clr , Direction of the P1.15 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EMC_A[14]/P1.14_set/clr , Direction of the P1.14 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EMC_A[13]/P1.13_set/clr , Direction of the P1.13 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_A[12]/P1.12_set/clr , Direction of the P1.12 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_A[11]/P1.11_set/clr , Direction of the P1.11 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_A[10]/P1.10_set/clr , Direction of the P1.10 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_A[9]/P1.9_set/clr , Direction of the P1.9 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_A[8]/P1.8_set/clr , Direction of the P1.8 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_A[7]/P1.7_set/clr , Direction of the P1.7 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_A[6]/P1.6_set/clr , Direction of the P1.6 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_A[5]/P1.5_set/clr , Direction of the P1.5 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_A[4]/P1.4_set/clr , Direction of the P1.4 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_A[3]/P1.3_set/clr , Direction of the P1.3 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_A[2]/P1.2_set/clr , Direction of the P1.2 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_A[1]/P1.1_set/clr , Direction of the P1.1 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_A[0]/P1.0_set/clr , Direction of the P1.0 pin" "Input,Output"
|
|
tree.end
|
|
tree "Port 2"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "P2_INP_STATE,P2 Input Pin State register for EMC data pins"
|
|
bitfld.long 0x00 12. " EMC_D[31]/P2.12_set/clr , The state of the P2.12 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EMC_D[30]/P2.11_set/clr , The state of the P2.11 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMC_D[29]/P2.10_set/clr , The state of the P2.10 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC_D[28]/P2.9_set/clr , The state of the P2.9 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMC_D[27]/P2.8_set/clr , The state of the P2.8 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC_D[26]/P2.7_set/clr , The state of the P2.7 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EMC_D[25]/P2.6_set/clr , The state of the P2.6 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC_D[24]/P2.5_set/clr , The state of the P2.5 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMC_D[23]/P2.4_set/clr , The state of the P2.4 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC_D[22]/P2.3_set/clr , The state of the P2.3 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EMC_D[21]/P2.2_set/clr , The state of the P2.2 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC_D[20]/P2.1_set/clr , The state of the P2.1 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMC_D[19]/P2.0_set/clr , The state of the P2.0 pin" "Low,High"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x00 "P2_OUTP_SET,P2 Output Pin Set register for EMC pins"
|
|
bitfld.long 0x00 12. " EMC_D[31]/P2.12 , The state of the P2.12 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EMC_D[30]/P2.11 , The state of the P2.11 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMC_D[29]/P2.10 , The state of the P2.10 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC_D[28]/P2.9 , The state of the P2.9 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMC_D[27]/P2.8 , The state of the P2.8 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC_D[26]/P2.7 , The state of the P2.7 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EMC_D[25]/P2.6 , The state of the P2.6 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC_D[24]/P2.5 , The state of the P2.5 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMC_D[23]/P2.4 , The state of the P2.4 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC_D[22]/P2.3 , The state of the P2.3 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EMC_D[21]/P2.2 , The state of the P2.2 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC_D[20]/P2.1 , The state of the P2.1 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMC_D[19]/P2.0 , The state of the P2.0 pin" "No effect,Set High"
|
|
line.long 0x04 "P2_OUTP_CLR,P2 Output Pin Clear register for EMD data pins"
|
|
bitfld.long 0x04 12. " EMC_D[31]/P2.12 , The state of the P2.12 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EMC_D[30]/P2.11 , The state of the P2.11 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 10. " EMC_D[29]/P2.10 , The state of the P2.10 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EMC_D[28]/P2.9 , The state of the P2.9 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EMC_D[27]/P2.8 , The state of the P2.8 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EMC_D[26]/P2.7 , The state of the P2.7 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EMC_D[25]/P2.6 , The state of the P2.6 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EMC_D[24]/P2.5 , The state of the P2.5 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMC_D[23]/P2.4 , The state of the P2.4 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EMC_D[22]/P2.3 , The state of the P2.3 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMC_D[21]/P2.2 , The state of the P2.2 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EMC_D[20]/P2.1 , The state of the P2.1 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EMC_D[19]/P2.0 , The state of the P2.0 pin" "No effect,Set Low"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "P2_DIR_STATE,Port2 and Port3 Direction Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " GPIO_05_set/clr , Direction of the general purpose I/O pin GPIO_05[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " GPIO_04_set/clr , Direction of the general purpose I/O pin GPIO_04[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " GPIO_03_set/clr , Direction of the general purpose I/O pin GPIO_03[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " GPIO_02_set/clr , Direction of the general purpose I/O pin GPIO_02[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " GPIO_01_set/clr , Direction of the general purpose I/O pin GPIO_01[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GPIO_00_set/clr , Direction of the general purpose I/O pin GPIO_00" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_D[12]/P2.12_set/clr , Direction of the P2.12 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_D[11]/P2.11_set/clr , Direction of the P2.11 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_D[10]/P2.10_set/clr , Direction of the P2.10 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_D[9]/P2.9_set/clr , Direction of the P2.9 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_D[8]/P2.8_set/clr , Direction of the P2.8 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_D[7]/P2.7_set/clr , Direction of the P2.7 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_D[6]/P2.6_set/clr , Direction of the P2.6 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_D[5]/P2.5_set/clr , Direction of the P2.5 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_D[4]/P2.4_set/clr , Direction of the P2.4 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_D[3]/P2.3_set/clr , Direction of the P2.3 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_D[2]/P2.2_set/clr , Direction of the P2.2 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_D[1]/P2.1_set/clr , Direction of the P2.1 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_D[0]/P2.0_set/clr , Direction of the P2.0 pin" "Input,Output"
|
|
tree.end
|
|
tree "Port 3"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "P3_INP_STATE,P2 Input Pin State register for EMC data pins"
|
|
bitfld.long 0x00 28. " GPI_28/U3_RI , The state of the input pin GPI_28/U3_RI" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " GPI_27/SPI2_DATIN/MISO1|(LCDVD[21]) , The state of the input pin GPI_27/SPI2_DATIN" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPI_25/SPI1_DATIN/MISO0/MCFB2 , The state of the input pin GPI_25/SPI1_DATIN/MISO0/MCFB2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPIO_05/SSEL0/MCFB0 , The state of the input pin GPIO_05/SSEL0/MCFB0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPI_23/U7_RX/CAP0.0|(LCDVD[10]) , The state of the input pin GPI_23/U7_RX/CAP0.0|(LCDVD[10])" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPI_22/U7_HCTS/CAP0.1|(LCDCLKIN) , The state of the input pin GPI_22/U7_HCTS/CAP0.1|(LCDCLKIN)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPI_21/U6_IRRX , The state of the input pin GPI_21/U6_IRRX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPI_20/U5_RX , The state of the input pin GPI_20/U5_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPI_19/U4_RX , The state of the input pin GPI_19/U4_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPI_18/U3_RX , The state of the input pin GPI_18/U3_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPI_17/U2_RX|(U3_DSR) , The state of the input pin GPI_17/U2_RX|(U3_DSR)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPI_16/U2_HCTS|(U3_CTS) , The state of the input pin GPI_16/U2_HCTS|(U3_CTS)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPI_15/U1_RX|(CAP1.0) , The state of the input pin GPI_15/U1_RX|(CAP1.0)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " GPIO_04/SSEL1|(LCDVD[22]) , The state of the input pin GPIO_04/SSEL1|(LCDVD[22])" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3250")
|
|
bitfld.long 0x00 13. " GPIO_03/KEY_ROW7|(ENET_MDIO) , The state of the input pin GPIO_03/KEY_ROW7|(ENET_MDIO)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " GPIO_02/KEY_ROW6|(ENET_MDC) , The state of the input pin GPIO_02/KEY_ROW6|(ENET_MDC)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " GPIO_03/KEY_ROW7 , The state of the input pin GPIO_03/KEY_ROW7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " GPIO_02/KEY_ROW6 , The state of the input pin GPIO_02/KEY_ROW6" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_01 , The state of the input pin GPIO_01" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GPIO_00 , The state of the input pin GPIO_00" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3250")
|
|
bitfld.long 0x00 9. " GPI_09/KEY_COL7|(ENET_COL) , The state of the input pin GPI_09/KEY_COL7|(ENET_COL)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPI_08/KEY_COL6/SPI2_BUSY|(ENET_RX_DV) , The state of the input pin GPI_08/KEY_COL6/SPI2_BUSY|(ENET_RX_DV)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 9. " GPI_09/KEY_COL7 , The state of the input pin GPI_09/KEY_COL7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPI_08/KEY_COL6/SPI2_BUSY , The state of the input pin GPI_08/KEY_COL6/SPI2_BUSY" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " GPI_07 , The state of the input pin GPI_07" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3250")
|
|
bitfld.long 0x00 6. " GPI_06/HSTIM_CAP|(ENET_RXD2) , The state of the input pin GPI_06/HSTIM_CAP|(ENET_RXD2)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " GPI_06/HSTIM_CAP , The state of the input pin GPI_06/HSTIM_CAP" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " GPI_05/U3_DCD , The state of the input pin GPI_05/U3_DCD" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPI_04/SPI1_BUSY , The state of the input pin GPI_04/SPI1_BUSY" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GPI_03 , The state of the input pin GPI_03" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3250")
|
|
bitfld.long 0x00 2. " GPI_02/CAP2.0|(ENET_RXD3) , The state of the input pin GPI_02/CAP2.0|(ENET_RXD3)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 2. " GPI_02/CAP2.0 , The state of the input pin GPI_02/CAP2.0" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPI_01/SERVICE_N , The state of the input pin GPI_01/SERVICE_N" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPI_00/I2S1RX_SDA , The state of the input pin GPI_00/I2S1RX_SDA" "Low,High"
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "P3_OUTP_STATE,P3 Output Pin State Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " GPIO_05/SSEL0/MCFB0_set/clr , The state of general purpose I/0 pin GPIO_05" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " GPIO_04/SSEL1|(LCDVD[22])_set/clr , The state of general purpose I/0 pin GPIO_04" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3250")
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " GPIO_03/KEY_ROW7|(ENET_MDIO)_set/clr , The state of general purpose I/0 pin GPIO_03" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " GPIO_02/KEY_ROW6|(ENET_MDC)_set/clr , The state of general purpose I/0 pin GPIO_02" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " GPIO_03/KEY_ROW7_set/clr , The state of general purpose I/0 pin GPIO_03" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " GPIO_02/KEY_ROW6_set/clr , The state of general purpose I/0 pin GPIO_02" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " GPIO_01_set/clr , The state of general purpose I/0 pin GPIO_01" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GPIO_00_set/clr , The state of general purpose I/0 pin GPIO_00" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " GPO_23/U2_HRTS|(U3_RTS)_set/clr , The state of general purpose output pin GPO_23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " GPO_22/U7_HRTS/LCDVD[14]_set/clr , The state of general purpose output pin GPO_22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " GPO_21/U4_TX|(LCDVD[3])_set/clr , The state of general purpose output pin GPO_21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " GPO_20_set/clr , The state of general purpose output pin GPO_20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " GPO_19_set/clr , The state of general purpose output pin GPO_19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " GPO_18/MC0A|LCDLP_set/clr , The state of general purpose output pin GPO_18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " GPO_17_set/clr , The state of general purpose output pin GPO_17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " GPO_16/MC0B|(LCDENAB/LCDM)_set/clr , The state of general purpose output pin GPO_16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " GPO_15/MC1A|(LCDFP)_set/clr , The state of general purpose output pin GPO_15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " GPO_14_set/clr , The state of general purpose output pin GPO_14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " GPO_13/MC1B|(LCDDCLK)_set/clr , The state of general purpose output pin GPO_13" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " GPO_12/MC2A|(LCDLE)_set/clr , The state of general purpose output pin GPO_12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " GPO_11_set/clr , The state of general purpose output pin GPO_11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " GPO_10/MC2B|(LCDPWR)_set/clr , The state of general purpose output pin GPO_10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " GPO_09|(LCDVD[9])_set/clr , The state of general purpose output pin GPO_9" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " GPO_08|(LCDVD[8])_set/clr , The state of general purpose output pin GPO_8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " GPO_07|(LCDVD[2])_set/clr , The state of general purpose output pin GPO_7" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " GPO_06|(LCDVD[18])_set/clr , The state of general purpose output pin GPO_6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GPO_05_set/clr , The state of general purpose output pin GPO_5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " GPO_04_set/clr , The state of general purpose output pin GPO_4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " GPO_03|(LCDVD[1])_set/clr , The state of general purpose output pin GPO_3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " GPO_02/T1_MAT.0|(LCDVD[0])_set/clr , The state of general purpose output pin GPO_2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " GPO_01_set/clr , The state of general purpose output pin GPO_1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " GPO_00|(TST_CLK1)_set/clr , The state of general purpose output pin GPO_0" "Low,High"
|
|
tree.end
|
|
else
|
|
tree "Port 0"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "P0_INP_STATE,P0 Input Pin State register"
|
|
bitfld.long 0x00 7. " P0.7/I2S0TX_WS ,State of the P0.7/I2S0TX_WS pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P0.6/I2S0TX_CLK ,State of the P0.6/I2S0TX_CLK pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P0.5/I2S0TX_SDA ,State of the P0.5/I2S0TX_SDA pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P0.4/I2S0RX_WS ,State of the P0.4/I2S0RX_WS pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P0.3/I2S0RX_CLK ,State of the P0.3/I2S0RX_CLK pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P0.2/I2S0RX_SDA ,State of the P0.2/I2S0RX_SDA pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P0.1/I2S1RX_WS ,State of the P0.1/I2S1RX_WS pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0.0/I2S1RX_CLK ,State of the P0.0/I2S1RX_CLK pin" "Low,High"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "P0_OUTP_STATE,P0 Output Pin Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7/I2S0TX_WS_set/clr , The state of the P0.7/I2S0TX_WS pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6/I2S0TX_CLK_set/clr , The state of the P0.6/I2S0TX_CLK pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5/I2S0TX_SDA_set/clr ,State of the P0.5/I2S0TX_SDA pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4/I2S0RX_WS_set/clr , The state of the P0.4/I2S0RX_WS pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3/I2S0RX_CLK_set/clr ,State of the P0.3/I2S0RX_CLK pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2/I2S0RX_SDA_set/clr ,State of the P0.2/I2S0RX_SDA pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1/I2S1RX_WS_set/clr ,State of the P0.1/I2S1RX_WS pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0/I2S1RX_CLK_set/clr ,State of the P0.0/I2S1RX_CLK pin" "Low,High"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "P0_DIR_STATE,P0 Direction Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7/I2S0TX_WS_set/clr ,Direction of the P0.7/I2S0TX_WS pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6/I2S0TX_CLK_set/clr ,Direction of the P0.6/I2S0TX_CLK pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5/I2S0TX_SDA_set/clr ,Direction of the P0.5/I2S0TX_SDApin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4/I2S0RX_WS_set/clr ,Direction of the P0.4/I2S0RX_WS pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3/I2S0RX_CLK_set/clr ,Direction of the P0.3/I2S0RX_CLK pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2/I2S0RX_SDA_set/clr ,Direction of the P0.2/I2S0RX_SDA pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1/I2S1RX_WS_set/clr ,Direction of the P0.1/I2S1RX_WS pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0/I2S1RX_CLK_set/clr ,Direction of the P0.0/I2S1RX_CLK pin" "Input,Output"
|
|
tree.end
|
|
tree "Port 1"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "P1_INP_STATE,P1 Input Pin Register for EMC Address pins"
|
|
bitfld.long 0x00 23. " EMC_A[23]/P1.23_set/clr , The state of the P1.23 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMC_A[22]/P1.22_set/clr , The state of the P1.22 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EMC_A[21]/P1.21_set/clr , The state of the P1.21 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EMC_A[20]/P1.20_set/clr , The state of the P1.20 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EMC_A[19]/P1.19_set/clr , The state of the P1.19 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EMC_A[18]/P1.18_set/clr , The state of the P1.18 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMC_A[17]/P1.17_set/clr , The state of the P1.17 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EMC_A[16]/P1.16_set/clr , The state of the P1.16 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EMC_A[15]/P1.15_set/clr , The state of the P1.15 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EMC_A[14]/P1.14_set/clr , The state of the P1.14 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EMC_A[13]/P1.13_set/clr , The state of the P1.13 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EMC_A[12]/P1.12_set/clr , The state of the P1.12 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EMC_A[11]/P1.11_set/clr , The state of the P1.11 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMC_A[10]/P1.10_set/clr , The state of the P1.10 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC_A[9]/P1.9_set/clr , The state of the P1.9 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMC_A[8]/P1.8_set/clr , The state of the P1.8 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC_A[7]/P1.7_set/clr , The state of the P1.7 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EMC_A[6]/P1.6_set/clr , The state of the P1.6 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC_A[5]/P1.5_set/clr , The state of the P1.5 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMC_A[4]/P1.4_set/clr , The state of the P1.4 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC_A[3]/P1.3_set/clr , The state of the P1.3 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EMC_A[2]/P1.2_set/clr , The state of the P1.2 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC_A[1]/P1.1_set/clr , The state of the P1.1 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMC_A[0]/P1.0_set/clr , The state of the P1.0 pin" "Low,High"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "P1_OUTP_STATE,P1 Output Pin Register for EMC address pins"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EMC_A[23]/P1.23_set/clr , The state of the P1.23 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EMC_A[22]/P1.22_set/clr , The state of the P1.22 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EMC_A[21]/P1.21_set/clr , The state of the P1.21 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EMC_A[20]/P1.20_set/clr , The state of the P1.20 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EMC_A[19]/P1.19_set/clr , The state of the P1.19 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EMC_A[18]/P1.18_set/clr , The state of the P1.18 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EMC_A[17]/P1.17_set/clr , The state of the P1.17 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EMC_A[16]/P1.16_set/clr , The state of the P1.16 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EMC_A[15]/P1.15_set/clr , The state of the P1.15 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EMC_A[14]/P1.14_set/clr , The state of the P1.14 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EMC_A[13]/P1.13_set/clr , The state of the P1.13 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_A[12]/P1.12_set/clr , The state of the P1.12 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_A[11]/P1.11_set/clr , The state of the P1.11 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_A[10]/P1.10_set/clr , The state of the P1.10 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_A[9]/P1.9_set/clr , The state of the P1.9 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_A[8]/P1.8_set/clr , The state of the P1.8 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_A[7]/P1.7_set/clr , The state of the P1.7 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_A[6]/P1.6_set/clr , The state of the P1.6 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_A[5]/P1.5_set/clr , The state of the P1.5 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_A[4]/P1.4_set/clr , The state of the P1.4 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_A[3]/P1.3_set/clr , The state of the P1.3 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_A[2]/P1.2_set/clr , The state of the P1.2 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_A[1]/P1.1_set/clr , The state of the P1.1 pin" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_A[0]/P1.0_set/clr , The state of the P1.0 pin" "Low,High"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "P1_DIR_STATE,P1 Direction Register"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EMC_A[23]/P1.23_set/clr , Direction of the P1.23 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EMC_A[22]/P1.22_set/clr , Direction of the P1.22 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EMC_A[21]/P1.21_set/clr , Direction of the P1.21 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EMC_A[20]/P1.20_set/clr , Direction of the P1.20 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EMC_A[19]/P1.19_set/clr , Direction of the P1.19 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EMC_A[18]/P1.18_set/clr , Direction of the P1.18 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EMC_A[17]/P1.17_set/clr , Direction of the P1.17 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EMC_A[16]/P1.16_set/clr , Direction of the P1.16 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EMC_A[15]/P1.15_set/clr , Direction of the P1.15 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EMC_A[14]/P1.14_set/clr , Direction of the P1.14 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EMC_A[13]/P1.13_set/clr , Direction of the P1.13 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_A[12]/P1.12_set/clr , Direction of the P1.12 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_A[11]/P1.11_set/clr , Direction of the P1.11 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_A[10]/P1.10_set/clr , Direction of the P1.10 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_A[9]/P1.9_set/clr , Direction of the P1.9 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_A[8]/P1.8_set/clr , Direction of the P1.8 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_A[7]/P1.7_set/clr , Direction of the P1.7 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_A[6]/P1.6_set/clr , Direction of the P1.6 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_A[5]/P1.5_set/clr , Direction of the P1.5 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_A[4]/P1.4_set/clr , Direction of the P1.4 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_A[3]/P1.3_set/clr , Direction of the P1.3 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_A[2]/P1.2_set/clr , Direction of the P1.2 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_A[1]/P1.1_set/clr , Direction of the P1.1 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_A[0]/P1.0_set/clr , Direction of the P1.0 pin" "Input,Output"
|
|
tree.end
|
|
tree "Port 2"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "P2_INP_STATE,P2 Input Pin State register for EMC data pins"
|
|
bitfld.long 0x00 12. " EMC_D[31]/P2.12_set/clr , The state of the P2.12 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EMC_D[30]/P2.11_set/clr , The state of the P2.11 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMC_D[29]/P2.10_set/clr , The state of the P2.10 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC_D[28]/P2.9_set/clr , The state of the P2.9 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMC_D[27]/P2.8_set/clr , The state of the P2.8 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC_D[26]/P2.7_set/clr , The state of the P2.7 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EMC_D[25]/P2.6_set/clr , The state of the P2.6 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC_D[24]/P2.5_set/clr , The state of the P2.5 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMC_D[23]/P2.4_set/clr , The state of the P2.4 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC_D[22]/P2.3_set/clr , The state of the P2.3 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EMC_D[21]/P2.2_set/clr , The state of the P2.2 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC_D[20]/P2.1_set/clr , The state of the P2.1 pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMC_D[19]/P2.0_set/clr , The state of the P2.0 pin" "Low,High"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x00 "P2_OUTP_SET,P2 Output Pin Set register for EMC pins"
|
|
bitfld.long 0x00 12. " EMC_D[31]/P2.12 , The state of the P2.12 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EMC_D[30]/P2.11 , The state of the P2.11 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EMC_D[29]/P2.10 , The state of the P2.10 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC_D[28]/P2.9 , The state of the P2.9 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EMC_D[27]/P2.8 , The state of the P2.8 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC_D[26]/P2.7 , The state of the P2.7 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EMC_D[25]/P2.6 , The state of the P2.6 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC_D[24]/P2.5 , The state of the P2.5 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMC_D[23]/P2.4 , The state of the P2.4 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC_D[22]/P2.3 , The state of the P2.3 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EMC_D[21]/P2.2 , The state of the P2.2 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC_D[20]/P2.1 , The state of the P2.1 pin" "No effect,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMC_D[19]/P2.0 , The state of the P2.0 pin" "No effect,Set High"
|
|
line.long 0x04 "P2_INP_STATE,P2 Output Pin Clear register for EMD data pins"
|
|
bitfld.long 0x04 12. " EMC_D[31]/P2.12 , The state of the P2.12 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EMC_D[30]/P2.11 , The state of the P2.11 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 10. " EMC_D[29]/P2.10 , The state of the P2.10 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EMC_D[28]/P2.9 , The state of the P2.9 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EMC_D[27]/P2.8 , The state of the P2.8 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EMC_D[26]/P2.7 , The state of the P2.7 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EMC_D[25]/P2.6 , The state of the P2.6 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EMC_D[24]/P2.5 , The state of the P2.5 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMC_D[23]/P2.4 , The state of the P2.4 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EMC_D[22]/P2.3 , The state of the P2.3 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMC_D[21]/P2.2 , The state of the P2.2 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EMC_D[20]/P2.1 , The state of the P2.1 pin" "No effect,Set Low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EMC_D[19]/P2.0 , The state of the P2.0 pin" "No effect,Set Low"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "P2_DIR_STATE,Port2 and Port3 Direction Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " GPIO_05_set/clr , Direction of the general purpose I/O pin GPIO_05[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " GPIO_04_set/clr , Direction of the general purpose I/O pin GPIO_04[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " GPIO_03_set/clr , Direction of the general purpose I/O pin GPIO_03[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " GPIO_02_set/clr , Direction of the general purpose I/O pin GPIO_02[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " GPIO_01_set/clr , Direction of the general purpose I/O pin GPIO_01[" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GPIO_00_set/clr , Direction of the general purpose I/O pin GPIO_00" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_D[12]/P2.12_set/clr , Direction of the P2.12 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_D[11]/P2.11_set/clr , Direction of the P2.11 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_D[10]/P2.10_set/clr , Direction of the P2.10 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_D[9]/P2.9_set/clr , Direction of the P2.9 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_D[8]/P2.8_set/clr , Direction of the P2.8 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_D[7]/P2.7_set/clr , Direction of the P2.7 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_D[6]/P2.6_set/clr , Direction of the P2.6 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_D[5]/P2.5_set/clr , Direction of the P2.5 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_D[4]/P2.4_set/clr , Direction of the P2.4 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_D[3]/P2.3_set/clr , Direction of the P2.3 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_D[2]/P2.2_set/clr , Direction of the P2.2 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_D[1]/P2.1_set/clr , Direction of the P2.1 pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_D[0]/P2.0_set/clr , Direction of the P2.0 pin" "Input,Output"
|
|
tree.end
|
|
tree "Port 3"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "P3_INP_STATE,P2 Input Pin State register for EMC data pins"
|
|
bitfld.long 0x00 31. " GPI_28/U3_RI , The state of the input pin GPI_28/U3_RI" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GPI_28/U3_RI , The state of the input pin GPI_28/U3_RI" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " GPI_27/SPI2_DATIN/MISO1 , The state of the input pin GPI_27/SPI2_DATIN" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPI_25/SPI1_DATIN/MISO0/MCFB2 , The state of the input pin GPI_25/SPI1_DATIN/MISO0/MCFB2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPIO_05/SSEL0/MCFB0 , The state of the input pin GPIO_05/SSEL0/MCFB0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPI_23/U7_RX/CAP0.0 , The state of the input pin GPI_23/U7_RX/CAP0.0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPI_22/U7_HCTS/CAP0.1 , The state of the input pin GPI_22/U7_HCTS/CAP0.1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPI_21/U6_IRRX , The state of the input pin GPI_21/U6_IRRX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPI_20/U5_RX , The state of the input pin GPI_20/U5_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPI_19/U4_RX , The state of the input pin GPI_19/U4_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPI_18/U3_RX , The state of the input pin GPI_18/U3_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPI_17/U2_RX|(U3_DSR) , The state of the input pin GPI_17/U2_RX|(U3_DSR)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPI_16/U2_HCTS|(U3_CTS) , The state of the input pin GPI_16/U2_HCTS|(U3_CTS)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPI_15/U1_RX|(CAP1.0) , The state of the input pin GPI_15/U1_RX|(CAP1.0)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " GPIO_04/SSEL1 , The state of the input pin GPIO_04/SSEL1" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3240")
|
|
bitfld.long 0x00 13. " GPIO_03/KEY_ROW7|(ENET_MDIO) , The state of the input pin GPIO_03/KEY_ROW7|(ENET_MDIO)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " GPIO_02/KEY_ROW6|(ENET_MDC) , The state of the input pin GPIO_02/KEY_ROW6|(ENET_MDC)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 13. " GPIO_03/KEY_ROW7 , The state of the input pin GPIO_03/KEY_ROW7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " GPIO_02/KEY_ROW6 , The state of the input pin GPIO_02/KEY_ROW6" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_01 , The state of the input pin GPIO_01" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GPIO_00 , The state of the input pin GPIO_00" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3240")
|
|
bitfld.long 0x00 9. " GPI_09/KEY_COL7|(ENET_COL) , The state of the input pin GPI_09/KEY_COL7|(ENET_COL)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPI_08/KEY_COL6/SPI2_BUSY|(ENET_RX_DV) , The state of the input pin GPI_08/KEY_COL6/SPI2_BUSY|(ENET_RX_DV)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 9. " GPI_09/KEY_COL7 , The state of the input pin GPI_09/KEY_COL7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPI_08/KEY_COL6/SPI2_BUSY , The state of the input pin GPI_08/KEY_COL6/SPI2_BUSY" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " GPI_07 , The state of the input pin GPI_07" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3240")
|
|
bitfld.long 0x00 6. " GPI_06/HSTIM_CAP|(ENET_RXD2) , The state of the input pin GPI_06/HSTIM_CAP|(ENET_RXD2)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. " GPI_06/HSTIM_CAP , The state of the input pin GPI_06/HSTIM_CAP" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " GPI_05/U3_DCD , The state of the input pin GPI_05/U3_DCD" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPI_04/SPI1_BUSY , The state of the input pin GPI_04/SPI1_BUSY" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GPI_03 , The state of the input pin GPI_03" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3240")
|
|
bitfld.long 0x00 2. " GPI_02/CAP2.0|(ENET_RXD3) , The state of the input pin GPI_02/CAP2.0|(ENET_RXD3)" "Low,High"
|
|
else
|
|
bitfld.long 0x00 2. " GPI_02/CAP2.0 , The state of the input pin GPI_02/CAP2.0" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPI_01/SERVICE_N , The state of the input pin GPI_01/SERVICE_N" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPI_00/I2S1RX_SDA , The state of the input pin GPI_00/I2S1RX_SDA" "Low,High"
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "P3_OUTP_STATE,P3 Output Pin State Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " GPIO_05/SSEL0/MCFB0_set/clr , The state of general purpose I/0 pin GPIO_05" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " GPIO_04/SSEL1_set/clr , The state of general purpose I/0 pin GPIO_04" "Low,High"
|
|
textline " "
|
|
sif (cpu()=="LPC3240")
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " GPIO_03/KEY_ROW7|(ENET_MDIO)_set/clr , The state of general purpose I/0 pin GPIO_03" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " GPIO_02/KEY_ROW6|(ENET_MDC)_set/clr , The state of general purpose I/0 pin GPIO_02" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " GPIO_03/KEY_ROW7_set/clr , The state of general purpose I/0 pin GPIO_03" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " GPIO_02/KEY_ROW6_set/clr , The state of general purpose I/0 pin GPIO_02" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " GPIO_01_set/clr , The state of general purpose I/0 pin GPIO_01" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GPIO_00_set/clr , The state of general purpose I/0 pin GPIO_00" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " GPO_23/U2_HRTS|(U3_RTS)_set/clr , The state of general purpose output pin GPO_23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " GPO_22/U7_HRTS_set/clr , The state of general purpose output pin GPO_22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " GPO_21/U4_TX_set/clr , The state of general purpose output pin GPO_21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " GPO_20_set/clr , The state of general purpose output pin GPO_20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " GPO_19_set/clr , The state of general purpose output pin GPO_19" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " GPO_18/MC0A|LCDLP_set/clr , The state of general purpose output pin GPO_18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " GPO_17_set/clr , The state of general purpose output pin GPO_17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " GPO_16/MC0B_set/clr , The state of general purpose output pin GPO_16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " GPO_15/MC1A_set/clr , The state of general purpose output pin GPO_15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " GPO_14_set/clr , The state of general purpose output pin GPO_14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " GPO_13/MC1B_set/clr , The state of general purpose output pin GPO_13" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " GPO_12/MC2A_set/clr , The state of general purpose output pin GPO_12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " GPO_11_set/clr , The state of general purpose output pin GPO_11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " GPO_10/MC2B_set/clr , The state of general purpose output pin GPO_10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " GPO_09_set/clr , The state of general purpose output pin GPO_9" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " GPO_08_set/clr , The state of general purpose output pin GPO_8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " GPO_07_set/clr , The state of general purpose output pin GPO_7" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " GPO_06_set/clr , The state of general purpose output pin GPO_6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GPO_05_set/clr , The state of general purpose output pin GPO_5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " GPO_04_set/clr , The state of general purpose output pin GPO_4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " GPO_03_set/clr , The state of general purpose output pin GPO_3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " GPO_02/T1_MAT.0_set/clr , The state of general purpose output pin GPO_2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " GPO_01_set/clr , The state of general purpose output pin GPO_1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " GPO_00_set/clr , The state of general purpose output pin GPO_0" "Low,High"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "PINMUX (Pin Multiplexing)"
|
|
base ad:0x40028100
|
|
width 14.
|
|
sif (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
tree "Peripheral MUX"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "P_MUX_STATE,Peripheral multiplexer State register"
|
|
bitfld.long 0x00 20. " (MS_DIO0)|MAT0.0 , Pin function status" "MAT0.0(MS_DIO0),?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " (MS_DIO1)|MAT0.1 , Pin function status" "MAT0.1(MS_DIO1),?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " (MS_DIO2)|MAT0.2 , Pin function status" "MAT0.2(MS_DIO2),?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " (MS_DIO3)|MAT0.3 , Pin function status" "MAT0.3(MS_DIO3),?..."
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " U7_TX/MAT1.1|(LCDVD[11])_set/clr , Pin function selection (Overriden by LCDVD[11] if LCD enabled)" "U7_TX,MAT1.1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " (MS_SCLK)|MAT2.0 , Pin function status" "MAT2.0(MS_SCLK),?..."
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SPI1_CLK/SCK0_set/clr , Pin function selection" "SPI1_CLK,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SPI1_DATIN/MISO0/MCFB2_set/clr , Pin function selection" "SPI1_DATIN,MISO0(MCFB2)"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ESPI1_DATIO/MOSI0/MCFB1_set/clr , Pin function selection" "SPI1_DATI,MOSI0(MCFB1)"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SPI2_CLK/SCK1|(LCDVD[23])_set/clr , Pin function selection (Overriden by LCDVD[23] if LCD enabled)" "SPI2_CLK,SCK1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " SPI2_DATIN/MISO1|(LCDVD[21])_set/clr , Pin function selection (Overriden by LCDVD[21] if LCD enabled)" "SPI2_DATIN,MISO1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " SPI2_DATIO/MOSI1|(LCDVD[20])_set/clr , Pin function selection (Overriden by LCDVD[20] if LCD enabled)" "SPI2_DATIO,MOSI1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " I2S1TX_WS/CAP3.0_set/clr , Pin function selection" "I2S1TX_WS,CAP3.0"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " I2S1TX_CLK/MAT3.0_set/clr , Pin function selection" "I2S1TX_CLK,MAT3.0"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " I2S1TX_SDA/MAT3.1_set/clr , Pin function selection" "I2S1TX_SDA,MAT3.1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x00 "P_MUX_CLR,Peripheral multiplexer Clear register"
|
|
bitfld.long 0x00 20. " (MS_DIO0)|MAT0.0 , Pin function selection" "No effect,MAT0.0(MS_DIO0)"
|
|
bitfld.long 0x00 19. " (MS_DIO1)|MAT0.1 , Pin function selection" "No effect,MAT0.1(MS_DIO1)"
|
|
textline " "
|
|
bitfld.long 0x00 18. " (MS_DIO2)|MAT0.2 , Pin function selection" "No effect,MAT0.2(MS_DIO2)"
|
|
bitfld.long 0x00 17. " (MS_DIO3)|MAT0.3 , Pin function selection" "No effect,MAT0.3(MS_DIO3)"
|
|
textline " "
|
|
bitfld.long 0x00 14. " (MS_SCLK)|MAT2.0 , Pin function selection" "No effect,MAT2.0(MS_SCLK)"
|
|
tree.end
|
|
tree "Port 0"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "P0_MUX_STATE,Port 0 multiplexer register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7/I2S0TX_WS|(LCDVD[13])_set/clr , Function selection of the P0.7/I2S0TX_WS pin (Overriden by LCDVD[13] if LCD enabled)" "P0.7,I2S0TX_WS"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6/I2S0TX_CLK|(LCDVD[12])_set/clr , Function selection of the P0.6/I2S0TX_CLK pin (Overriden by LCDVD[12] if LCD enabled)" "P0.6,I2S0TX_CLK"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5/I2S0TX_SDA_set/clr ,Function selection of the P0.5/I2S0TX_SDA|(LCDVD[7])pin (Overriden by LCDVD[7] if LCD enabled)" "P0.5,I2S0TX_SDA"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4/I2S0RX_WS|(LCDVD[6])_set/clr , Function selection of the P0.4/I2S0RX_WS pin (Overriden by LCDVD[6] if LCD enabled)" "P0.4,I2S0RX_WS"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3/I2S0RX_CLK|(LCDVD[5])_set/clr ,Function selection of the P0.3/I2S0RX_CLK pin (Overriden by LCDVD[5] if LCD enabled)" "P0.3,I2S0RX_CLK"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2/I2S0RX_SDA|(LCDVD[4])_set/clr ,Function selection of the P0.2/I2S0RX_SDA pin (Overriden by LCDVD[4] if LCD enabled)" "P0.2,I2S0RX_SDA"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1/I2S1RX_WS_set/clr ,Function selection of the P0.1/I2S1RX_WS pin " "P0.1,I2S1RX_WS"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0/I2S1RX_CLK_set/clr ,Function selection of the P0.0/I2S1RX_CLK pin" "P0.0,I2S1RX_CLK"
|
|
tree.end
|
|
tree "Port 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "P1_MUX_STATE,Port 1 multiplexer register"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EMC_A[23]/P1.23_set/clr , Function selection of the P1.23 pin" "EMC_A[23],P1.23"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EMC_A[22]/P1.22_set/clr , Function selection of the P1.22 pin" "EMC_A[22],P1.22"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EMC_A[21]/P1.21_set/clr , Function selection of the P1.21 pin" "EMC_A[21],P1.21"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EMC_A[20]/P1.20_set/clr , Function selection of the P1.20 pin" "EMC_A[20],P1.20"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EMC_A[19]/P1.19_set/clr , Function selection of the P1.19 pin" "EMC_A[19],P1.19"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EMC_A[18]/P1.18_set/clr , Function selection of the P1.18 pin" "EMC_A[18],P1.18"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EMC_A[17]/P1.17_set/clr , Function selection of the P1.17 pin" "EMC_A[17],P1.17"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EMC_A[16]/P1.16_set/clr , Function selection of the P1.16 pin" "EMC_A[16],P1.16"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EMC_A[15]/P1.15_set/clr , Function selection of the P1.15 pin" "EMC_A[15],P1.15"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EMC_A[14]/P1.14_set/clr , Function selection of the P1.14 pin" "EMC_A[14],P1.14"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EMC_A[13]/P1.13_set/clr , Function selection of the P1.13 pin" "EMC_A[13],P1.13"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_A[12]/P1.12_set/clr , Function selection of the P1.12 pin" "EMC_A[12],P1.12"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_A[11]/P1.11_set/clr , Function selection of the P1.11 pin" "EMC_A[11],P1.11"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_A[10]/P1.10_set/clr , Function selection of the P1.10 pin" "EMC_A[10],P1.10"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_A[9]/P1.9_set/clr , Function selection of the P1.9 pin" "EMC_A[9],P1.9"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_A[8]/P1.8_set/clr , Function selection of the P1.8 pin" "EMC_A[8],P1.8"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_A[7]/P1.7_set/clr , Function selection of the P1.7 pin" "EMC_A[7],P1.7"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_A[6]/P1.6_set/clr , Function selection of the P1.6 pin" "LEMC_A[6],P1.6"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_A[5]/P1.5_set/clr , Function selection of the P1.5 pin" "EMC_A[5],P1.5"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_A[4]/P1.4_set/clr , Function selection of the P1.4 pin" "EMC_A[4],P1.4"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_A[3]/P1.3_set/clr , Function selection of the P1.3 pin" "EMC_A[3],P1.3"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_A[2]/P1.2_set/clr , Function selection of the P1.2 pin" "EMC_A[2],P1.2"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_A[1]/P1.1_set/clr , Function selection of the P1.1 pin" "EMC_A[1],P1.1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_A[0]/P1.0_set/clr , Function selection of the P1.0 pin" "EMC_A[0],P1.0"
|
|
tree.end
|
|
tree "Port 2"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "P2_MUX_STATE,Port 2 multiplexer register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GPIO_05/SSEL0/MCFB0_set/clr , Function selection of the P2.5 pin" "GPIO_05,SSEL0"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " GPIO_04/SSEL1|(LCDVD[22])_set/clr , Function selection of the P2.4 pin (Overriden by LCDVD[22] if LCD enabled)" "GPIO_04,SSEL1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_D_SEL_set/clr , Function selection of the EMC_D[31:19] pins" "SDRAM controller,GPIO block"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " GPO_21/U4_TX|(LCDVD[3])_set/clr , Function selection of the P2.2 pin (Overriden by LCDVD[3] if LCD enabled)" "GPO_21,U4_TX"
|
|
textline " "
|
|
sif (cpu()=="LPC3250")
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " GPIO_03/KEY_ROW7|(ENET_MDIO)_set/clr , Function selection of the P2.1 pin (Overriden by ENET_MDIO if ETHERNET enabled)" "GPIO_03,KeyScan Row[7]"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " GPIO_02/KEY_ROW6|(ENET_MDC)_set/clr , Function selection of the P2.0 pin (Overriden by ENET_MDC if ETHERNET enabled)" "GPIO_02,KeyScan Row[6]"
|
|
else
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " GPIO_03/KEY_ROW7_set/clr , Function selection of the P2.1 pin" "GPIO_03,KeyScan Row[7]"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " GPIO_02/KEY_ROW6_set/clr , Function selection of the P2.0 pin" "GPIO_02,KeyScan Row[6]"
|
|
endif
|
|
tree.end
|
|
tree "Port 3"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "P3_MUX_STATE,Port 3 Multiplexer register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " GPO_18/MC0A|LCDLP_set/clr , Function selection of general purpose output pin GPO_18 (Overriden by LCDLP if LCD enabled)" "GPO_18,MC0A"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " GPO_16/MC0B|(LCDENAB/LCDM)_set/clr , Function selection of general purpose output pin GPO_16 (Overriden by LCDENAB/LCDM if LCD enabled)" "GPO_16,MC0B"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " GPO_15/MC1A|(LCDFP)_set/clr , Function selection of general purpose output pin GPO_15 (Overriden by LCDFP if LCD enabled)" "GPO_15,MC1A"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " GPO_13/MC1B|(LCDDCLK)_set/clr , Function selection of general purpose output pin GPO_13 (Overriden by LCDDCLK if LCD enabled)" "GPO_13,MC1B"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " GPO_12/MC2A|(LCDLE)_set/clr , Function selection of general purpose output pin GPO_12 (Overriden by LCDLE if LCD enabled)" "GPO_12,MC2A"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " GPO_10/MC2B|(LCDPWR)_set/clr , Function selection of general purpose output pin GPO_10 (Overriden by LCDPWR if LCD enabled)" "GPO_10,MC2B"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " GPO_09|(LCDVD[9])_set/clr , Function selection of general purpose output pin GPO_9 (Overriden by LCDVD[9] if LCD enabled)" "GPO_9,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " GPO_08|(LCDVD[8])_set/clr , Function selection of general purpose output pin GPO_8 (Overriden by LCDVD[8] if LCD enabled)" "GPO_8,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " GPO_06|(LCDVD[18])_set/clr , Function selection of general purpose output pin GPO_6 (Overriden by LCDVD[18] if LCD enabled)" "GPO_6,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " GPO_02/T1_MAT.0|(LCDVD[0])_set/clr , Function selection of general purpose output pin GPO_2 (Overriden by LCDVD[0] if LCD enabled)" "GPO_2,MAT1.0"
|
|
tree.end
|
|
else
|
|
tree "Peripheral MUX"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "P_MUX_STATE,Peripheral multiplexer State register"
|
|
bitfld.long 0x00 20. " (MS_DIO0)|MAT0.0 , Pin function status" "MAT0.0(MS_DIO0),?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " (MS_DIO1)|MAT0.1 , Pin function status" "MAT0.1(MS_DIO1),?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " (MS_DIO2)|MAT0.2 , Pin function status" "MAT0.2(MS_DIO2),?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " (MS_DIO3)|MAT0.3 , Pin function status" "MAT0.3(MS_DIO3),?..."
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " U7_TX/MAT1.1_set/clr , Pin function selection" "U7_TX,MAT1.1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " (MS_SCLK)|MAT2.0 , Pin function status" "MAT2.0(MS_SCLK),?..."
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SPI1_CLK/SCK0_set/clr , Pin function selection" "SPI1_CLK,SCK0"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SPI1_DATIN/MISO0/MCFB2_set/clr , Pin function selection" "SPI1_DATIN,MISO0(MCFB2)"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ESPI1_DATIO/MOSI0/MCFB1_set/clr , Pin function selection" "SPI1_DATI,MOSI0(MCFB1)"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SPI2_CLK/SCK1_set/clr , Pin function selection" "SPI2_CLK,SCK1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " SPI2_DATIN/MISO1_set/clr , Pin function selection" "SPI2_DATIN,MISO1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " SPI2_DATIO/MOSI1_set/clr , Pin function selection" "SPI2_DATIO,MOSI1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " I2S1TX_WS/CAP3.0_set/clr , Pin function selection" "I2S1TX_WS,CAP3.0"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " I2S1TX_CLK/MAT3.0_set/clr , Pin function selection" "I2S1TX_CLK,MAT3.0"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " I2S1TX_SDA/MAT3.1_set/clr , Pin function selection" "I2S1TX_SDA,MAT3.1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x00 "P_MUX_CLR,Peripheral multiplexer Clear register"
|
|
bitfld.long 0x00 20. " (MS_DIO0)|MAT0.0 , Pin function selection" "No effect,MAT0.0(MS_DIO0)"
|
|
bitfld.long 0x00 19. " (MS_DIO1)|MAT0.1 , Pin function selection" "No effect,MAT0.1(MS_DIO1)"
|
|
textline " "
|
|
bitfld.long 0x00 18. " (MS_DIO2)|MAT0.2 , Pin function selection" "No effect,MAT0.2(MS_DIO2)"
|
|
bitfld.long 0x00 17. " (MS_DIO3)|MAT0.3 , Pin function selection" "No effect,MAT0.3(MS_DIO3)"
|
|
textline " "
|
|
bitfld.long 0x00 14. " (MS_SCLK)|MAT2.0 , Pin function selection" "No effect,MAT2.0(MS_SCLK)"
|
|
tree.end
|
|
tree "Port 0"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "P0_MUX_STATE,Port 0 multiplexer register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7/I2S0TX_WS_set/clr , Function selection of the P0.7/I2S0TX_WS pin" "P0.7,I2S0TX_WS"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6/I2S0TX_CLK_set/clr , Function selection of the P0.6/I2S0TX_CLK pin" "P0.6,I2S0TX_CLK"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5/I2S0TX_SDA_set/clr ,Function selection of the P0.5/I2S0TX_SDA pin" "P0.5,I2S0TX_SDA"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4/I2S0RX_WS_set/clr , Function selection of the P0.4/I2S0RX_WS pin" "P0.4,I2S0RX_WS"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3/I2S0RX_CLK_set/clr ,Function selection of the P0.3/I2S0RX_CLK pin" "P0.3,I2S0RX_CLK"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2/I2S0RX_SDA_set/clr ,Function selection of the P0.2/I2S0RX_SDA pin" "P0.2,I2S0RX_SDA"
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textline " "
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setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1/I2S1RX_WS_set/clr ,Function selection of the P0.1/I2S1RX_WS pin" "P0.1,I2S1RX_WS"
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textline " "
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setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0/I2S1RX_CLK_set/clr ,Function selection of the P0.0/I2S1RX_CLK pin" "P0.0,I2S1RX_CLK"
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tree.end
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tree "Port 1"
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group.long 0x38++0x3
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line.long 0x00 "P1_MUX_STATE,Port 1 multiplexer register"
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setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EMC_A[23]/P1.23_set/clr , Function selection of the P1.23 pin" "EMC_A[23],P1.23"
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textline " "
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setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EMC_A[22]/P1.22_set/clr , Function selection of the P1.22 pin" "EMC_A[22],P1.22"
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textline " "
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setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EMC_A[21]/P1.21_set/clr , Function selection of the P1.21 pin" "EMC_A[21],P1.21"
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textline " "
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setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EMC_A[20]/P1.20_set/clr , Function selection of the P1.20 pin" "EMC_A[20],P1.20"
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textline " "
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setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EMC_A[19]/P1.19_set/clr , Function selection of the P1.19 pin" "EMC_A[19],P1.19"
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textline " "
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setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EMC_A[18]/P1.18_set/clr , Function selection of the P1.18 pin" "EMC_A[18],P1.18"
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|
textline " "
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setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EMC_A[17]/P1.17_set/clr , Function selection of the P1.17 pin" "EMC_A[17],P1.17"
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textline " "
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setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EMC_A[16]/P1.16_set/clr , Function selection of the P1.16 pin" "EMC_A[16],P1.16"
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|
textline " "
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setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EMC_A[15]/P1.15_set/clr , Function selection of the P1.15 pin" "EMC_A[15],P1.15"
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|
textline " "
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setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EMC_A[14]/P1.14_set/clr , Function selection of the P1.14 pin" "EMC_A[14],P1.14"
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|
textline " "
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EMC_A[13]/P1.13_set/clr , Function selection of the P1.13 pin" "EMC_A[13],P1.13"
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|
textline " "
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setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMC_A[12]/P1.12_set/clr , Function selection of the P1.12 pin" "EMC_A[12],P1.12"
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|
textline " "
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setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EMC_A[11]/P1.11_set/clr , Function selection of the P1.11 pin" "EMC_A[11],P1.11"
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|
textline " "
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMC_A[10]/P1.10_set/clr , Function selection of the P1.10 pin" "EMC_A[10],P1.10"
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|
textline " "
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setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EMC_A[9]/P1.9_set/clr , Function selection of the P1.9 pin" "EMC_A[9],P1.9"
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|
textline " "
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setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EMC_A[8]/P1.8_set/clr , Function selection of the P1.8 pin" "EMC_A[8],P1.8"
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textline " "
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EMC_A[7]/P1.7_set/clr , Function selection of the P1.7 pin" "EMC_A[7],P1.7"
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|
textline " "
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setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EMC_A[6]/P1.6_set/clr , Function selection of the P1.6 pin" "LEMC_A[6],P1.6"
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|
textline " "
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setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EMC_A[5]/P1.5_set/clr , Function selection of the P1.5 pin" "EMC_A[5],P1.5"
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|
textline " "
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setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EMC_A[4]/P1.4_set/clr , Function selection of the P1.4 pin" "EMC_A[4],P1.4"
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|
textline " "
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setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_A[3]/P1.3_set/clr , Function selection of the P1.3 pin" "EMC_A[3],P1.3"
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|
textline " "
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setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EMC_A[2]/P1.2_set/clr , Function selection of the P1.2 pin" "EMC_A[2],P1.2"
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|
textline " "
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|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EMC_A[1]/P1.1_set/clr , Function selection of the P1.1 pin" "EMC_A[1],P1.1"
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|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EMC_A[0]/P1.0_set/clr , Function selection of the P1.0 pin" "EMC_A[0],P1.0"
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tree.end
|
|
tree "Port 2"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "P2_MUX_STATE,Port 2 multiplexer register"
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|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GPIO_05/SSEL0/MCFB0_set/clr , Function selection of the P2.5 pin" "GPIO_05,SSEL0"
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|
textline " "
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|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " GPIO_04/SSEL1_set/clr , Function selection of the P2.4 pin" "GPIO_04,SSEL1"
|
|
textline " "
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setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EMC_D_SEL_set/clr , Function selection of the EMC_D[31:19] pins" "SDRAM controller,GPIO block"
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|
textline " "
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|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " GPO_21/U4_TX_set/clr , Function selection of the P2.2 pin" "GPO_21,U4_TX"
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|
textline " "
|
|
sif (cpu()=="LPC3240")
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " GPIO_03/KEY_ROW7|(ENET_MDIO)_set/clr , Function selection of the P2.1 pin (Overriden by ENET_MDIO if ETHERNET enabled)" "GPIO_03,KeyScan Row[7]"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " GPIO_02/KEY_ROW6|(ENET_MDC)_set/clr , Function selection of the P2.0 pin (Overriden by ENET_MDC if ETHERNET enabled)" "GPIO_02,KeyScan Row[6]"
|
|
else
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " GPIO_03/KEY_ROW7_set/clr , Function selection of the P2.1 pin" "GPIO_03,KeyScan Row[7]"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " GPIO_02/KEY_ROW6_set/clr , Function selection of the P2.0 pin" "GPIO_02,KeyScan Row[6]"
|
|
endif
|
|
tree.end
|
|
tree "Port 3"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "P3_MUX_STATE,Port 3 Multiplexer register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " GPO_18/MC0A_set/clr , Function selection of general purpose output pin GPO_18" "GPO_18,MC0A"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " GPO_16/MC0B_set/clr , Function selection of general purpose output pin GPO_16" "GPO_16,MC0B"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " GPO_15/MC1A_set/clr , Function selection of general purpose output pin GPO_15" "GPO_15,MC1A"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " GPO_13/MC1B_set/clr , Function selection of general purpose output pin GPO_13" "GPO_13,MC1B"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " GPO_12/MC2A_set/clr , Function selection of general purpose output pin GPO_12" "GPO_12,MC2A"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " GPO_10/MC2B_set/clr , Function selection of general purpose output pin GPO_10" "GPO_10,MC2B"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " GPO_09_set/clr , Function selection of general purpose output pin GPO_9" "GPO_9,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " GPO_08_set/clr , Function selection of general purpose output pin GPO_8" "GPO_8,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " GPO_06_set/clr , Function selection of general purpose output pin GPO_6" "GPO_6,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " GPO_02/T1_MAT.0_set/clr , Function selection of general purpose output pin " "GPO_2,MAT1.0"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "DEBUG"
|
|
base ad:0x40040000
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DEBUG_CTRL,Debug Control Register"
|
|
bitfld.long 0x00 4. " VFP9_CLKEN ,Controls VFP9 GCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VFP_BIGEND ,Controls endianess of VFP" "As ARM926,Force Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARMDBG_DIS ,Debug Logic Disable" "No,Yes"
|
|
line.long 0x04 "DEBUG_GRANT,Master Grant Debug Mode Register"
|
|
bitfld.long 0x04 7. " USB_MASTER ,Forces GRANT inactive in ARM debug mode" "Not forced,Forced"
|
|
bitfld.long 0x04 1. " DMA_M1_MASTER ,Forces GRANT inactive in ARM debug mode" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DMA_M0_MASTER ,Forces GRANT inactive in ARM debug mode" "Not forced,Forced"
|
|
width 0xB
|
|
tree.end
|
|
textline ""
|