24386 lines
1.9 MiB
24386 lines
1.9 MiB
; --------------------------------------------------------------------------------
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; @Title: LPC15xx On-Chip Peripherals
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; @Props: Released
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; @Author: MKK, LSD
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; @Changelog: 2016-06-07 LSD
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: UM10736.pdf (Rev.1 2014-02)
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; LPC15XX.pdf (Rev.1 2014-02)
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; @Core: Cortex-M3
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; @Chip: LPC1517, LPC1518, LPC1519
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; LPC1547, LPC1548, LPC1549
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perlpc15xx.per 17736 2024-04-08 09:26:07Z kwisniewski $
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base ad:0x0
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "PID3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SYSCON (System Control)"
|
|
base ad:0x40074000
|
|
width 16.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SYSMEMREMAP,System memory remap"
|
|
bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,?..."
|
|
group.long 0x0c++0xb
|
|
line.long 0x00 "AHBBUFEN0,AHB-to-APB bridge 0 write buffering control"
|
|
bitfld.long 0x00 29. " SYSCON_BUF ,SYSCON AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " QEI_BUF ,QEI AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " I2C0_BUF ,I2C0 AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPI1_BUF ,SPI1 AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI0_BUF ,SPI0 AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UART1_BUF ,USART1 AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " UART0_BUF ,USART0 AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PMU_BUF ,PMU AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SWM_BUF ,SWM AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WWDT_BUF ,WWDT AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RTC_BUF ,RTC AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INPUTMUX_BUF ,INPUT MUX AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACMP_BUF ,ACMP AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DAC_BUF ,DAC AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADC0_BUF ,ADC AHB-APB write buffering" "Disabled,Enabled"
|
|
line.long 0x04 "AHBBUFEN1,AHB-to-APB bridge 1 write buffering control"
|
|
bitfld.long 0x04 31. " EEPROM_BUF ,EEPROM AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " IOCON_BUF ,IOCON AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " CCAN_BUF ,CCAN AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " UART2_BUF ,UART2 AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " FMC_BUF ,FMC AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SCTIPU_BUF ,SCTIPU AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RIT_BUF ,RIT AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " GINT1_BUF ,GINT1 AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " GINT0_BUF ,GINT0 AHB-APB write buffering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PINT_BUF ,PINT AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " MRT_BUF ,MRT AHB-APB write buffering" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ADC1_BUF ,ADC1 AHB-APB write buffering" "Disabled,Enabled"
|
|
line.long 0x08 "SYSTCKCAL,System tick counter calibration"
|
|
hexmask.long 0x08 0.--25. 1. " CAL ,System tick timer calibration value"
|
|
if (((per.l((ad:0x40074000+0x1c)))&0x80000000)==0x80000000)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "NMISRC,NMI Source Control"
|
|
bitfld.long 0x00 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--5. " IRQN ,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "NMISRC,NMI Source Control"
|
|
bitfld.long 0x00 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "SYSRSTSTAT,System reset status register"
|
|
bitfld.long 0x00 4. " SYSRST ,Status of the software system reset" "No reset,Reset"
|
|
bitfld.long 0x00 3. " BOD ,Status of the Brown-out detect reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " WDT ,Status of the Watchdog reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EXTRST ,External reset status" "No reset,Reset"
|
|
bitfld.long 0x00 0. " POR ,POR reset status" "No reset,Reset"
|
|
line.long 0x04 "PRESETCTRL0,Peripheral reset control 0"
|
|
eventfld.long 0x04 30. " ACMP_RST ,Analog Comparator (ACMP) reset control for all in the block" "Cleared,Asserted"
|
|
eventfld.long 0x04 28. " ADC1_RST ,ADC1 reset control" "Cleared,Asserted"
|
|
eventfld.long 0x04 27. " ADC0_RST ,ADC0 reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x04 21. " CRC_RST ,CRC generator reset control" "Cleared,Asserted"
|
|
eventfld.long 0x04 20. " DMA_RST ,DMA reset control" "Cleared,Asserted"
|
|
eventfld.long 0x04 19. " GINT_RST ,Grouped interrupt (GINT) reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x04 18. " PINT_RST ,Pin interrupt (PINT) reset control" "Cleared,Asserted"
|
|
eventfld.long 0x04 13. " IOCON_RST ,IOCON reset control" "Cleared,Asserted"
|
|
eventfld.long 0x04 11. " MUX_RST ,Input mux reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x04 9. " EEPROM_RST ,EEPROM controller reset control" "Cleared,Asserted"
|
|
eventfld.long 0x04 7. " FLASH_RST ,Flash controller reset control" "Cleared,Asserted"
|
|
line.long 0x08 "PRESETCTRL1,Peripheral reset control 1"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
eventfld.long 0x08 23. " USB_RST ,USB reset control" "Cleared,Asserted"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x08 21. " QEI_RST ,QEI reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 19. " UART2_RST ,USART2 reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 18. " UART1_RST ,USART1 reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x08 17. " UART0_RST ,USART0 reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 13. " I2C0_RST ,I2C0 reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 10. " SPI1_RST ,SPI1 reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x08 9. " SPI0_RST ,SPI0 reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 7. " CCAN_RST ,CCAN reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 6. " SCTIPU_RST ,State configurable timer IPU (SCTIPU) reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x08 5. " SCT3_RST ,State configurable timer 3 (SCT3) reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 4. " SCT2_RST ,State configurable timer 2 (SCT2) reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 3. " SCT1_RST ,State configurable timer 1 (SCT1) reset control" "Cleared,Asserted"
|
|
textline " "
|
|
eventfld.long 0x08 2. " SCT0_RST ,State configurable timer 0 (SCT0) reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 1. " RIT_RST ,Repetitive interrupt timer (RIT) reset control" "Cleared,Asserted"
|
|
eventfld.long 0x08 0. " MRT_RST ,Multi-rate timer (MRT) reset control" "Cleared,Asserted"
|
|
rgroup.long 0x4c++0xb
|
|
line.long 0x00 "PIOPORCAP0,POR captured PIO status 0"
|
|
line.long 0x04 "PIOPORCAP1,POR captured PIO status 1"
|
|
line.long 0x08 "PIOPORCAP2,POR captured PIO status 2"
|
|
hexmask.long.word 0x08 0.--11. 1. " PIOSTAT ,State of PIO2_11 through PIO2_0 at power-on reset"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "MAINCLKSELA,Main clock source select A"
|
|
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock source selector A" "IRC Oscillator,System oscillator,Watchdog oscillator,?..."
|
|
line.long 0x04 "MAINCLKSELB,Main clock source select B"
|
|
bitfld.long 0x04 0.--1. " SEL ,Clock source for main clock source selector B" "MAINCLKSELA src,System PLL input,System PLL output,RTC oscillator 32 kHz output"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "USBCLKSEL,USB clock source select"
|
|
bitfld.long 0x00 0.--1. " SEL ,USB clock source" "IRC Oscillator,System oscillator,USB PLL out,Main clock"
|
|
line.long 0x04 "ADCASYNCCLKSEL,ADC asynchronous clock source select"
|
|
bitfld.long 0x04 0.--1. " SEL ,ADC clock source" "IRC Oscillator,System PLL output,USB PLL output,SCT PLL output"
|
|
else
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "ADCASYNCCLKSEL,ADC asynchronous clock source select"
|
|
bitfld.long 0x00 0.--1. " SEL ,ADC clock source" "IRC Oscillator,System PLL output,,SCT PLL output"
|
|
endif
|
|
group.long 0x94++0x7
|
|
line.long 0x00 "CLKOUTSELA,CLKOUT clock source select A"
|
|
bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC Oscillator,Crystal(SYSOSC),Watchdog oscillator,Main clock"
|
|
line.long 0x04 "CLKOUTSELB,CLKOUT clock source select B"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x04 0.--1. " SEL ,CLKOUT clock source" "CLKOUTSELA src,USB PLL output,SCT PLL output,RTC 32 kHz output"
|
|
else
|
|
bitfld.long 0x04 0.--1. " SEL ,CLKOUT clock source" "CLKOUTSELA src,,SCT PLL output,RTC 32 kHz output"
|
|
endif
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
group.long 0xA0++0xb
|
|
line.long 0x00 "SYSPLLCLKSEL,System PLL clock source select"
|
|
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC Oscillator,Crystal(SYSOSC),?..."
|
|
line.long 0x04 "USBPLLCLKSEL,USB PLL clock source select"
|
|
bitfld.long 0x04 0.--1. " SEL ,USB PLL clock source" "IRC Oscillator,System oscillator,?..."
|
|
line.long 0x08 "SCTPLLCLKSEL,SCT PLL clock source select"
|
|
bitfld.long 0x08 0.--1. " SEL ,SCT PLL clock source" "IRC Oscillator,System oscillator,?..."
|
|
else
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "SYSPLLCLKSEL,System PLL clock source select"
|
|
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC Oscillator,Crystal(SYSOSC),?..."
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "SCTPLLCLKSEL,SCT PLL clock source select"
|
|
bitfld.long 0x00 0.--1. " SEL ,SCT PLL clock source" "IRC Oscillator,System oscillator,?..."
|
|
endif
|
|
group.long 0xC0++0x1b
|
|
line.long 0x00 "SYSAHBCLKDIV,System clock divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,System AHB clock divider values. 0 - System clock disabled"
|
|
line.long 0x04 "SYSAHBCLKCTRL0,System clock control 0"
|
|
bitfld.long 0x04 30. " ACMP ,Enables clock to analog comparator block" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DAC ,Enables clock for DAC" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " ADC1 ,Enables clock for ADC1 register interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ADC0 ,Enables clock for ADC0 register interface" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " RTC ,Enables clock for RTC" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " WWDT ,Enables clock for WWDT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " CRC ,Enables clock for CRC" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " DMA ,Enables clock for DMA" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " GINT ,Enables clock for grouped pin interrupt block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " PINT ,Enables clock for pin interrupt block" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " GPIO2 ,Enables clock for GPIO2 port registers" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " GPIO1 ,Enables clock for GPIO1 port registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " GPIO0 ,Enables clock for GPIO0 port registers" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " SWM ,Enables clock for IOCON block" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " SWM ,Enables clock for switch matrix" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MUX ,Enables clock for input MUX" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EEPROM ,Enables clock for EEPROM controller" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " FLASH ,Enables clock for flash controller" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SRAM2 ,Enables clock for SRAM2" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SRAM1 ,Enables clock for SRAM1" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ROM ,Enables clock for ROM" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " SYS ,AHB/APB/Cortex-M3/SYSCON/reset/SRAM0/PMU clocks configuration" "Disabled,Enabled"
|
|
line.long 0x08 "SYSAHBCLKCTRL1,System clock control 1"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x08 23. " USB ,Enables clock for USB register interface" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21. " QEI ,Enables clock for QEI" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " UART2 ,Enables clock for USART2" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " UART1 ,Enables clock for USART1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " UART0 ,Enables clock for USART0" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " I2C0 ,Enables clock for I2C0" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SPI1 ,Enables clock for input SPI1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SPI0 ,Enables clock for SPI0" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CCAN ,Enables clock for CCAN" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " SCTIPU ,Enables clock for SCTIPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SCT3 ,Enables clock for SCT3" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " SCT2 ,Enables clock for SCT2" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SCT1 ,Enables clock for SCT1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SCT0 ,Enables clock for SCT0" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RIT ,Enables clock for repetitive interrupt timer" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " MRT ,Enables clock for multi-rate timer" "Disabled,Enabled"
|
|
line.long 0x0c "SYSTICKCLKDIV,SYSTICK clock divider"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DIV ,SYSTICK clock divider values"
|
|
line.long 0x10 "UARTCLKDIV,USART clock divider"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DIV ,USART clock divider values"
|
|
line.long 0x14 "IOCONCLKDIV,Peripheral clock to the IOCON block"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DIV ,IOCON clock divider values"
|
|
line.long 0x18 "TRACECLKDIV,ARM trace clock divider"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DIV ,ARM trace clock divider values"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "USBCLKDIV,USB clock divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,USB clock divider values"
|
|
endif
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "ADCASYNCCLKDIV,Asynchronous ADC clock divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,ADC clock divider values"
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "CLKOUTDIV,Asynchronous CLKOUT clock divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,CLKOUT clock divider values"
|
|
group.long 0x120++0xb
|
|
line.long 0x00 "FREQMECTRL,Frequency measure register"
|
|
bitfld.long 0x00 31. " PROG ,Frequency measurement cycle initiate" "Not initiated,Initiated"
|
|
hexmask.long.word 0x00 0.--13. 1. " CAPVAL ,Stores the capture result which is used to calculate the frequency of the target clock"
|
|
line.long 0x04 "FLASHCFG,Flash waitstates configuration register"
|
|
bitfld.long 0x04 12.--13. " FLASHTIM ,Flash memory access time" "1 clock cycle,2 clock cycles,3 clock cycles,?..."
|
|
line.long 0x08 "FRGCTRL,USART fractional baud rate generation control register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " MULT ,Numerator of the fractional divider"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,Denominator of the fractional divider"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
group.long 0x12C++0x7
|
|
line.long 0x00 "USBCLKCTRL,USB clock control register"
|
|
bitfld.long 0x00 1. " POL_CLK ,USB need_clock polarity for triggering the USB wake-up interrupt" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 0. " AP_CLK ,USB need_clock signal control" "HW control,Forced HIGH"
|
|
line.long 0x04 "USBCLKST,USB clock status register"
|
|
bitfld.long 0x04 0. " NEED_CLKST ,USB need_clock signal status" "LOW,HIGH"
|
|
endif
|
|
group.long 0x180++0xb
|
|
line.long 0x00 "BODCTRL,Brown-Out Detect"
|
|
bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",,Level 2,Level 3"
|
|
bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" ",,Level 2,Level 3"
|
|
line.long 0x04 "IRCCTRL,IRC trim value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TRIM ,Trim value"
|
|
line.long 0x08 "SYSOSCCTRL,System oscillator control"
|
|
bitfld.long 0x08 1. " FREQRANGE ,Determines frequency range for system oscillator" "1-20MHz(low),15-25MHz(high)"
|
|
bitfld.long 0x08 0. " BYPASS ,Bypass system oscillator" "Not bypassed,Bypassed"
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "RTCOSCCTRL,RTC oscillator 32 kHz output control"
|
|
bitfld.long 0x00 0. " EN ,RTC 32 kHz clock enable" "Disabled,Enabled"
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "SYSPLLCTRL,System PLL control"
|
|
bitfld.long 0x00 6.--7. " PSEL ,Post divider ratio P" "1,2,4,8"
|
|
bitfld.long 0x00 0.--5. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x19c++0x3
|
|
line.long 0x00 "SYSPLLSTAT,System PLL status"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Unlocked,Locked"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "USBPLLCTRL,USB PLL control"
|
|
bitfld.long 0x00 6.--7. " PSEL ,Post divider ratio P" "1,2,4,8"
|
|
bitfld.long 0x00 0.--5. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x1A4++0x3
|
|
line.long 0x00 "USBPLLSTAT,USB PLL status"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Unlocked,Locked"
|
|
endif
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "SCTPLLCTRL,SCT PLL control"
|
|
bitfld.long 0x00 6.--7. " PSEL ,Post divider ratio P" "1,2,4,8"
|
|
bitfld.long 0x00 0.--5. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long 0x1Ac++0x3
|
|
line.long 0x00 "SCTPLLSTAT,SCT PLL status"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Unlocked,Locked"
|
|
group.long 0x204++0x7
|
|
line.long 0x00 "PDAWAKECFG,Power-down states for wake-up from deep-sleep"
|
|
bitfld.long 0x00 24. " SCTPLL_PD ,SCT PLL wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 23. " USBPLL_PD ,USB PLL wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 22. " SYSPLL_PD ,System PLL wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 21. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 20. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VDDADIV_PD ,VDDA divider wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 18. " TS_PD ,Temperature sensor wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 17. " IREF_PD ,Internal voltage reference wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ACMP3_PD ,Analog comparator 3 wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 15. " ACMP2_PD ,Analog comparator 2 wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 14. " ACMP1_PD ,Analog comparator 1 wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACMP0_PD ,Analog comparator 0 wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 12. " DAC_PD ,DAC wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 11. " ADC1_PD ,ADC1 wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ADC0_PD ,ADC0 wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 9. " USBPHY_PD ,USBPHY wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " BOD_PD ,BOD wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 6. " EEPROM ,EEPROM wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 5. " FLASH ,FLASH memory wake-up configuration" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRC ,IRC oscillator wake-up configuration" "Powered up,Powered down"
|
|
bitfld.long 0x00 3. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered up,Powered down"
|
|
line.long 0x04 "PDRUNCFG,Power configuration register"
|
|
bitfld.long 0x04 24. " SCTPLL_PD ,SCT PLL" "Powered up,Powered down"
|
|
textline " "
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x04 23. " USBPLL_PD ,USB PLL" "Powered up,Powered down"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " SYSPLL_PD ,System PLL" "Powered up,Powered down"
|
|
bitfld.long 0x04 21. " SYSOSC_PD ,System oscillator" "Powered up,Powered down"
|
|
bitfld.long 0x04 20. " WDTOSC_PD ,Watchdog oscillator" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 19. " VDDADIV_PD ,VDDA divider" "Powered up,Powered down"
|
|
bitfld.long 0x04 18. " TS_PD ,Temperature sensor" "Powered up,Powered down"
|
|
bitfld.long 0x04 17. " IREF_PD ,Internal voltage reference" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ACMP3_PD ,Analog comparator 3" "Powered up,Powered down"
|
|
bitfld.long 0x04 15. " ACMP2_PD ,Analog comparator 2" "Powered up,Powered down"
|
|
bitfld.long 0x04 14. " ACMP1_PD ,Analog comparator 1" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACMP0_PD ,Analog comparator 0" "Powered up,Powered down"
|
|
bitfld.long 0x04 12. " DAC_PD ,DAC" "Powered up,Powered down"
|
|
bitfld.long 0x04 11. " ADC1_PD ,ADC1" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ADC0_PD ,ADC0" "Powered up,Powered down"
|
|
textline " "
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x04 9. " USBPHY_PD ,USBPHY" "Powered up,Powered down"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " BOD_PD ,BOD" "Powered up,Powered down"
|
|
bitfld.long 0x04 6. " EEPROM ,EEPROM" "Powered up,Powered down"
|
|
bitfld.long 0x04 5. " FLASH ,FLASH memory" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x04 4. " IRC ,IRC oscillator" "Powered up,Powered down"
|
|
bitfld.long 0x04 3. " IRCOUT_PD ,IRC oscillator output" "Powered up,Powered down"
|
|
group.long 0x218++0x7
|
|
line.long 0x00 "STARTERP0,Start logic 0 wake-up enable register"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 30. " USB_WAKEUP ,USB need_clock signal wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " SPI1 ,SPI1 interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SPI0 ,SPI0 interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " I2C ,I2C interrupt wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " USART2 ,USART2 interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " USART1 ,USART1 interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " USART0 ,USART0 interrupt wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PINT7 ,GPIO pin interrupt 7 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PINT6 ,GPIO pin interrupt 6 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PINT5 ,GPIO pin interrupt 5 wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PINT4 ,GPIO pin interrupt 4 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PINT3 ,GPIO pin interrupt 3 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINT2 ,GPIO pin interrupt 2 wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PINT1 ,GPIO pin interrupt 1 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PINT0 ,GPIO pin interrupt 0 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GINT1 ,Group interrupt 1 wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GINT0 ,Group interrupt 0 wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOD ,BOD interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WWDT ,WWDT interrupt wake-up" "Disabled,Enabled"
|
|
line.long 0x04 "STARTERP1,Start logic 1 wake-up enable register"
|
|
bitfld.long 0x04 14. " RTCWAKE ,RTC wake-up interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RTCALARM ,RTC alarm interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ACMP3 ,Analog comparator 3 interrupt wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ACMP2 ,Analog comparator 2 interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ACMP1 ,Analog comparator 1 interrupt wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ACMP0 ,Analog comparator 0 interrupt wake-up" "Disabled,Enabled"
|
|
rgroup.long 0x3F4++0xb
|
|
line.long 0x00 "JTAG_IDCODE,JTAG ID code register"
|
|
line.long 0x04 "DEVICE_ID0,Part ID register"
|
|
line.long 0x08 "DEVICE_ID1,Boot ROM and die revision register"
|
|
width 0xb
|
|
tree.end
|
|
tree "PMU (Power Management Unit)"
|
|
base ad:0x4003C000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCON,Power Control Register"
|
|
sif cpuis("LPC11U*")
|
|
eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " NODPD ,No deep-power-down mode flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep-power down,?..."
|
|
else
|
|
bitfld.long 0x00 11. " DPDFLAG ,Deep power-down mode entry prevention" "Not prevented,Prevented"
|
|
eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not set,Set"
|
|
eventfld.long 0x00 3. " NODPD ,Sleep mode flag" "Not set,Set"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPREG0,General Purpose Register 0"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPREG2,General Purpose Register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG3,General Purpose Register 3"
|
|
sif cpuis("LPC11U*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register 4"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register 4/WAKEUP pad control"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. " DATA ,Data retained during Deep power-down mode"
|
|
bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes"
|
|
bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "IOCON (I/O pin configuration)"
|
|
base ad:0x400F8000
|
|
width 9.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PIO0_0,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_0"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PIO0_1,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_1"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PIO0_2,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_2"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PIO0_3,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_3"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PIO0_4,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_4"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PIO0_5,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_5"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO0_6,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_6"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PIO0_7,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_7"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PIO0_8,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_8"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PIO0_9,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_9"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO0_10,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_10"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PIO0_11,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_11"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PIO0_12,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_12"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PIO0_13,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_13"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO0_14,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_14"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PIO0_15,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_15"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO0_16,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_16"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PIO0_17,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_17"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO0_18,Digital I/O control - without glitch filter - for port 0 pin PIO0_18"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PIO0_19,Digital I/O control - without glitch filter - for port 0 pin PIO0_19"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PIO0_20,Digital I/O control - without glitch filter - for port 0 pin PIO0_20"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO0_21,Digital I/O control - without glitch filter - for port 0 pin PIO0_21"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x58++0x0b
|
|
line.long 0x00 "PIO0_22,I/O control for open-drain pin PIO0_22(I2C-bus SCL function)"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode" "Standard Fast I2C,Digital I/O func,Fast-Plus I2C,?..."
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x04 "PIO0_23,I/O control for open-drain pin PIO0_23(I2C-bus SDA function)"
|
|
bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x04 8.--9. " I2CMODE ,I2C mode" "Standard Fast I2C,Digital I/O func,Fast-Plus I2C,?..."
|
|
bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
line.long 0x08 "PIO0_24,Digital I/O - control without glitch filter - for port 0 pins PIO0_24"
|
|
bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PIO0_25,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_25"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO0_26,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_26"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PIO0_27,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_27"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PIO0_28,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_28"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PIO0_29,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_29"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PIO0_30,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_30"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PIO0_31,Digital I/O control - with analog function and glitch filter - for port 0 pin PIO0_31"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PIO1_0,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_0"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PIO1_1,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_1"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO1_2,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_2"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO1_3,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_3"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PIO1_4,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_4"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PIO1_5,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_5"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO1_6,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_6"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PIO1_7,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_7"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PIO1_8,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_8"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PIO1_9,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_9"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO1_10,Digital I/O control - with analog function and glitch filter - for port 1 pin PIO1_10"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FILTR ,10 ns input glitch filter disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PIO1_11,Digital I/O control - without glitch filter - for port 1 pin PIO1_11"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PIO1_12,Digital I/O control - without glitch filter - for port 1 pin PIO1_12"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PIO1_13,Digital I/O control - without glitch filter - for port 1 pin PIO1_13"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO1_14,Digital I/O control - without glitch filter - for port 1 pin PIO1_14"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PIO1_15,Digital I/O control - without glitch filter - for port 1 pin PIO1_15"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PIO1_16,Digital I/O control - without glitch filter - for port 1 pin PIO1_16"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PIO1_17,Digital I/O control - without glitch filter - for port 1 pin PIO1_17"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO1_18,Digital I/O control - without glitch filter - for port 1 pin PIO1_18"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "PIO1_19,Digital I/O control - without glitch filter - for port 1 pin PIO1_19"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "PIO1_20,Digital I/O control - without glitch filter - for port 1 pin PIO1_20"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PIO1_21,Digital I/O control - without glitch filter - for port 1 pin PIO1_21"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO1_22,Digital I/O control - without glitch filter - for port 1 pin PIO1_22"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PIO1_23,Digital I/O control - without glitch filter - for port 1 pin PIO1_23"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PIO1_24,Digital I/O control - without glitch filter - for port 1 pin PIO1_24"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO1_25,Digital I/O control - without glitch filter - for port 1 pin PIO1_25"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PIO1_26,Digital I/O control - without glitch filter - for port 1 pin PIO1_26"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PIO1_27,Digital I/O control - without glitch filter - for port 1 pin PIO1_27"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PIO1_28,Digital I/O control - without glitch filter - for port 1 pin PIO1_28"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PIO1_29,Digital I/O control - without glitch filter - for port 1 pin PIO1_29"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PIO1_30,Digital I/O control - without glitch filter - for port 1 pin PIO1_30"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PIO1_31,Digital I/O control - without glitch filter - for port 1 pin PIO1_31"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PIO1_11,Digital I/O control - without glitch filter - for port 1 pin PIO1_11"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
endif
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO2_11,Digital I/O control - without glitch filter - for port 2 pin PIO2_11"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PIO2_12,Digital I/O control - without glitch filter - for port 2 pin PIO2_12"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PIO2_13,Digital I/O control - without glitch filter - for port 2 pin PIO2_13"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PIO2_14,Digital I/O control - without glitch filter - for port 2 pin PIO2_14"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIO2_15,Digital I/O control - without glitch filter - for port 2 pin PIO2_15"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PIO2_16,Digital I/O control - without glitch filter - for port 2 pin PIO2_16"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PIO2_17,Digital I/O control - without glitch filter - for port 2 pin PIO2_17"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PIO2_18,Digital I/O control - without glitch filter - for port 2 pin PIO2_18"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PIO2_19,Digital I/O control - without glitch filter - for port 2 pin PIO2_19"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PIO2_20,Digital I/O control - without glitch filter - for port 2 pin PIO2_20"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PIO2_21,Digital I/O control - without glitch filter - for port 2 pin PIO2_21"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PIO2_22,Digital I/O control - without glitch filter - for port 2 pin PIO2_22"
|
|
bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock IOCONCLKDIV" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypass,Less than 1 cycle,Less than 2 cycles,Less than 3 cycles"
|
|
bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Function mode" "Inactive,Pull-down resistor,Pull-up resistor,Repeater"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "SWM (Switch Matrix)"
|
|
base ad:0x40038000
|
|
width 13.
|
|
group.long 0x00++0x3f
|
|
line.long 0x00 "PINASSIGN0,Pin assign register 0"
|
|
decmask.long.byte 0x00 24.--31. 1. " UART0_CTS_I ,UART0_CTS function assignment"
|
|
decmask.long.byte 0x00 16.--23. 1. " UART0_RTS_O ,UART0_RTS function assignment"
|
|
decmask.long.byte 0x00 8.--15. 1. " UART0_RXD_I ,UART0_RXD function assignment"
|
|
decmask.long.byte 0x00 0.--7. 1. " UART0_TXD_O ,UART0_TXD function assignment"
|
|
line.long 0x04 "PINASSIGN1,Pin assign register 1"
|
|
decmask.long.byte 0x04 24.--31. 1. " UART1_RTS_O ,UART1_RTS function assignment"
|
|
decmask.long.byte 0x04 16.--23. 1. " UART1_RXD_I ,UART1_RXD function assignment"
|
|
decmask.long.byte 0x04 8.--15. 1. " UART1_TXD_O ,UART1_TXD function assignment"
|
|
decmask.long.byte 0x04 0.--7. 1. " UART0_SCLK_IO ,UART0_SCLK function assignment"
|
|
line.long 0x08 "PINASSIGN2,Pin assign register 2"
|
|
decmask.long.byte 0x08 24.--31. 1. " UART2_RXD_I ,UART2_RXD function assignment"
|
|
decmask.long.byte 0x08 16.--23. 1. " UART2_TXD_O ,UART2_TXD function assignment"
|
|
decmask.long.byte 0x08 8.--15. 1. " UART1_SCLK_IO ,UART1_SCLK function assignment"
|
|
decmask.long.byte 0x08 0.--7. 1. " UART1_CTS_I ,UART1_CTS function assignment"
|
|
line.long 0x0c "PINASSIGN3,Pin assign register 3"
|
|
decmask.long.byte 0x0c 24.--31. 1. " SPI0_MISO_IO ,SPI0_MISO function assignment"
|
|
decmask.long.byte 0x0c 16.--23. 1. " SPI0_MOSI_IO ,SPI0_MOSI function assignment"
|
|
decmask.long.byte 0x0c 8.--15. 1. " SPI0_SCK_IO ,SPI0_SCK function assignment"
|
|
decmask.long.byte 0x0c 0.--7. 1. " UART2_SCLK_IO ,UART2_SCLK function assignment"
|
|
line.long 0x10 "PINASSIGN4,Pin assign register 4"
|
|
decmask.long.byte 0x10 24.--31. 1. " SPI0_SSELSN_3_IO ,SPI0_SSELSN_3 function assignment"
|
|
decmask.long.byte 0x10 16.--23. 1. " SPI0_SSELSN_2_IO ,SPI0_SSELSN_2 function assignment"
|
|
decmask.long.byte 0x10 8.--15. 1. " SPI0_SSELSN_1_IO ,SPI0_SSELSN_1 function assignment"
|
|
decmask.long.byte 0x10 0.--7. 1. " SPI0_SSELSN_0_IO ,SPI0_SSELSN_0 function assignment"
|
|
line.long 0x14 "PINASSIGN5,Pin assign register 5"
|
|
decmask.long.byte 0x14 24.--31. 1. " SPI1_SSELSN_0_IO ,SPI1_SSELSN_0 function assignment"
|
|
decmask.long.byte 0x14 16.--23. 1. " SPI1_MISO_IO ,SPI1_MISO function assignment"
|
|
decmask.long.byte 0x14 8.--15. 1. " SPI1_MOSI_IO ,SPI1_MOSI function assignment"
|
|
decmask.long.byte 0x14 0.--7. 1. " SPI1_SCK_IO ,SPI1_SCK function assignment"
|
|
line.long 0x18 "PINASSIGN6,Pin assign register 6"
|
|
decmask.long.byte 0x18 16.--23. 1. " CAN_RD1_I ,CAN_RD1 function assignment"
|
|
decmask.long.byte 0x18 8.--15. 1. " CAN_TD1_O ,CAN_TD1 function assignment"
|
|
decmask.long.byte 0x18 0.--7. 1. " SPI1_SSELSN_1_IO ,SPI1_SSELSN_1 function assignment"
|
|
line.long 0x1c "PINASSIGN7,Pin assign register 7"
|
|
decmask.long.byte 0x1c 24.--31. 1. " SCT0_OUT2_O ,SCT0_OUT2 function assignment"
|
|
decmask.long.byte 0x1c 16.--23. 1. " SCT0_OUT1_O ,SCT0_OUT1 function assignment"
|
|
decmask.long.byte 0x1c 8.--15. 1. " SCT0_OUT0_O ,SCT0_OUT0 function assignment"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
decmask.long.byte 0x1c 0.--7. 1. " USB_VBUS_I ,USB_VBUS function assignment"
|
|
endif
|
|
line.long 0x20 "PINASSIGN8,Pin assign register 8"
|
|
decmask.long.byte 0x20 24.--31. 1. " SCT2_OUT0_O ,SCT2_OUT0 function assignment"
|
|
decmask.long.byte 0x20 16.--23. 1. " SCT1_OUT2_O ,SCT1_OUT2 function assignment"
|
|
decmask.long.byte 0x20 8.--15. 1. " SCT1_OUT1_O ,SCT1_OUT1 function assignment"
|
|
decmask.long.byte 0x20 0.--7. 1. " SCT1_OUT0_O ,SCT1_OUT0 function assignment"
|
|
line.long 0x24 "PINASSIGN9,Pin assign register 9"
|
|
decmask.long.byte 0x24 24.--31. 1. " SCT3_OUT1_O ,SCT3_OUT1 function assignment"
|
|
decmask.long.byte 0x24 16.--23. 1. " SCT3_OUT0_O ,SCT3_OUT0 function assignment"
|
|
decmask.long.byte 0x24 8.--15. 1. " SCT2_OUT2_O ,SCT2_OUT2 function assignment"
|
|
decmask.long.byte 0x24 0.--7. 1. " SCT2_OUT1_O ,SCT2_OUT1 function assignment"
|
|
line.long 0x28 "PINASSIGN10,Pin assign register 10"
|
|
decmask.long.byte 0x28 24.--31. 1. " ADC0_PIN_TRIG0_I ,ADC0_PIN_TRIG0 function assignment"
|
|
decmask.long.byte 0x28 16.--23. 1. " SCT_ABORT1_I ,SCT_ABORT1 function assignment"
|
|
decmask.long.byte 0x28 8.--15. 1. " SCT_ABORT0_I ,SCT_ABORT0 function assignment"
|
|
decmask.long.byte 0x28 0.--7. 1. " SCT3_OUT2_O ,SCT3_OUT2 function assignment"
|
|
line.long 0x2c "PINASSIGN11,Pin assign register 11"
|
|
decmask.long.byte 0x2c 24.--31. 1. " DAC_PIN_TRIG_I ,DAC_PIN_TRIG function assignment"
|
|
decmask.long.byte 0x2c 16.--23. 1. " ADC1_PIN_TRIG1_I ,ADC1_PIN_TRIG1 function assignment"
|
|
decmask.long.byte 0x2c 8.--15. 1. " ADC1_PIN_TRIG0_I ,ADC1_PIN_TRIG0 function assignment"
|
|
decmask.long.byte 0x2c 0.--7. 1. " ADC0_PIN_TRIG1_I ,ADC0_PIN_TRIG1 function assignment"
|
|
line.long 0x30 "PINASSIGN12,Pin assign register 12"
|
|
decmask.long.byte 0x30 24.--31. 1. " ACMP2_OUT_O ,ACMP2_OUT function assignment"
|
|
decmask.long.byte 0x30 16.--23. 1. " ACMP1_OUT_O ,ACMP1_OUT function assignment"
|
|
decmask.long.byte 0x30 8.--15. 1. " ACMP0_OUT_O ,ACMP0_OUT function assignment"
|
|
decmask.long.byte 0x30 0.--7. 1. " DAC_SHUTOFF_I ,DAC_SHUTOFF function assignment"
|
|
line.long 0x34 "PINASSIGN13,Pin assign register 13"
|
|
decmask.long.byte 0x34 24.--31. 1. " ROSC_RST0_I ,ROSC_RST0 function assignment"
|
|
decmask.long.byte 0x34 16.--23. 1. " ROSC0_O ,ROSC0 function assignment"
|
|
decmask.long.byte 0x34 8.--15. 1. " CLK_OUT_O ,CLK_OUT function assignment"
|
|
decmask.long.byte 0x34 0.--7. 1. " ACMP3_OUT_O ,ACMP3_OUT function assignment"
|
|
line.long 0x38 "PINASSIGN14,Pin assign register 14"
|
|
decmask.long.byte 0x38 24.--31. 1. " QEI0_IDX_I ,QEI0_IDX function assignment"
|
|
decmask.long.byte 0x38 16.--23. 1. " QEI0_PHB_I ,QEI0_PHB function assignment"
|
|
decmask.long.byte 0x38 8.--15. 1. " QEI0_PHA_I ,QEI0_PHA function assignment"
|
|
sif (cpuis("LPC1547")||cpuis("LPC1549")||cpuis("LPC1548"))
|
|
decmask.long.byte 0x38 0.--7. 1. " USB_FRAME_TOG_O ,USB_FRAME_TOG function assignment"
|
|
endif
|
|
line.long 0x3c "PINASSIGN15,Pin assign register 15"
|
|
decmask.long.byte 0x3c 8.--15. 1. " SWO_O ,SWO function assignment"
|
|
decmask.long.byte 0x3c 0.--7. 1. " GPIO_INT_BMATCH_O ,GPIO_INT_BMATCH function assignment"
|
|
textline " "
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "PINENABLE0,Pin enable register 0"
|
|
bitfld.long 0x00 31. " ACMP2_I3 ,Analog comparator 2 input 3 function enable(PIO0_29)" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACMP1_I4 ,Analog comparator 1 input 4 function enable(PIO1_10)" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ACMP1_I3 ,Analog comparator 1 input 3 function enable(PIO0_28)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ACMP0_I4 ,Analog comparator 0 input 4 function enable(PIO0_25)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ACMP0_I3 ,Analog comparator 0 input 3 function enable(PIO0_26)" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ACMP_I2 ,ACMP input 2 (common input) function enable(PIO1_6)" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ACMP_I1 ,ACMP input 1 (common input) function enable(PIO0_27)" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DAC_OUT ,DAC_OUT function enable(PIO0_12)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ADC1_11 ,ADC1_11 function enable(PIO1_5)" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ADC1_10 ,ADC1_10 function enable(PIO1_4)" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ADC1_9 ,ADC1_9 function enable(PIO0_16)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ADC1_8 ,ADC1_8 function enable(PIO0_15)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADC1_7 ,ADC1_7 function enable(PIO0_14)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ADC1_6 ,ADC1_6 function enable(PIO0_13)" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ADC1_5 ,ADC1_5 function enable(PIO1_3)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ADC1_4 ,ADC1_4 function enable(PIO1_2)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ADC1_3 ,ADC1_3 function enable(PIO0_11)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADC1_2 ,ADC1_2 function enable(PIO0_10)" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ADC1_1 ,ADC1_1 function enable(PIO0_9)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ADC1_0 ,ADC1_0 function enable(PIO1_1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADC0_11 ,ADC0_11 function enable(PIO0_30)" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ADC0_10 ,ADC0_10 function enable(PIO0_0)" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADC0_9 ,ADC0_9 function enable(PIO0_31)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ADC0_8 ,ADC0_8 function enable(PIO1_0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADC0_7 ,ADC0_7 function enable(PIO0_1)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ADC0_6 ,ADC0_6 function enable(PIO0_2)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ADC0_5 ,ADC0_5 function enable(PIO0_3)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ADC0_4 ,ADC0_4 function enable(PIO0_4)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADC0_3 ,ADC0_3 function enable(PIO0_5)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADC0_2 ,ADC0_2 function enable(PIO0_6)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ADC0_1 ,ADC0_1 function enable(PIO0_7)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADC0_0 ,ADC0_0 function enable(PIO0_8)" "Disabled,Enabled"
|
|
line.long 0x04 "PINENABLE1,Pin enable register 1"
|
|
bitfld.long 0x04 23. " SWDIO ,SWDIO function enable(PIO0_20)" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SWCLK ,SWCLK function enable(PIO0_19)" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " RESETN ,RESET function enable(PIO0_21)" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SCT3_OUT5 ,SCT3_OUT5 function enable(PIO1_24)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SCT3_OUT4 ,SCT3_OUT4 function enable(PIO1_8)" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " SCT3_OUT3 ,SCT3_OUT3 function enable(PIO0_26)" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " SCT2_OUT5 ,SCT2_OUT5 function enable(PIO1_20)" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " SCT2_OUT4 ,SCT2_OUT4 function enable(PIO0_29)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SCT2_OUT3 ,SCT2_OUT3 function enable(PIO0_6)" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SCT1_OUT7 ,SCT1_OUT7 function enable(PIO1_17)" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " SCT1_OUT6 ,SCT1_OUT6 function enable(PIO0_20)" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " SCT1_OUT5 ,SCT1_OUT5 function enable(PIO0_14)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SCT1_OUT4 ,SCT1_OUT4 function enable(PIO0_3)" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " SCT1_OUT3 ,SCT1_OUT3 function enable(PIO0_2)" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SCT0_OUT7 ,SCT0_OUT7 function enable(PIO1_14)" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " SCT0_OUT6 ,SCT0_OUT6 function enable(PIO0_24)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SCT0_OUT5 ,SCT0_OUT5 function enable(PIO0_18)" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " SCT0_OUT4 ,SCT0_OUT4 function enable(PIO0_1)" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " SCT0_OUT3 ,SCT0_OUT3 function enable(PIO0_0)" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " I2C0_SCL ,I2C0_SCL function enable(PIO0_22)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " I2C0_SDA ,I2C0_SDA function enable(PIO0_23)" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ACMP3_I4 ,Analog comparator 3 input 4 function enable(PIO1_7)" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ACMP3_I3 ,Analog comparator 3 input 3 function enable(PIO1_8)" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ACMP2_I4 ,Analog comparator 2 input 4 function enable(PIO1_9)" "Disabled,Enabled"
|
|
width 0x0b
|
|
tree.end
|
|
tree "INPUT MUX (Input multiplexing)"
|
|
base ad:0x40014000
|
|
width 20.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SCT0_INMUX0,Input mux register for SCT0 input 0"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SCT0_INMUX1,Input mux register for SCT0 input 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SCT0_INMUX2,Input mux register for SCT0 input 2"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SCT0_INMUX3,Input mux register for SCT0 input 3"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 3 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 3 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCT0_INMUX4,Input mux register for SCT0 input 4"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 4 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 4 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCT0_INMUX5,Input mux register for SCT0 input 5"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 5 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 5 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SCT0_INMUX6,Input mux register for SCT0 input 6"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 6 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,PIO1_12,PIO1_13,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 6 to SCT0 inputs 0 to 6" "PIO0_2,PIO0_3,PIO0_17,PIO0_30,PIO1_6,PIO1_7,,,SCT1_OUT4,SCT2_OUT4,SCT2_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCT1_INMUX0,Input mux register for SCT1 input 0"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCT1_INMUX1,Input mux register for SCT1 input 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SCT1_INMUX2,Input mux register for SCT1 input 2"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCT1_INMUX3,Input mux register for SCT1 input 3"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 3 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 3 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SCT1_INMUX4,Input mux register for SCT1 input 4"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 4 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 4 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SCT1_INMUX5,Input mux register for SCT1 input 5"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 5 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 5 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCT1_INMUX6,Input mux register for SCT1 input 6"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 6 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,PIO1_15,PIO1_16,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 6 to SCT1 inputs 0 to 6" "PIO0_15,PIO0_16,PIO0_21,PIO0_31,PIO1_4,PIO1_5,,,SCT0_OUT4,SCT3_OUT4,SCT3_OUT5,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SCT2_INMUX0,Input mux register for SCT2 input 0"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,PIO1_18,PIO1_19,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,PIO1_18,PIO1_19,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,,,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,,,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SCT2_INMUX1,Input mux register for SCT2 input 1"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,PIO1_18,PIO1_19,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,PIO1_18,PIO1_19,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,,,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,,,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCT2_INMUX2,Input mux register for SCT2 input 2"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,PIO1_18,PIO1_19,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,PIO1_18,PIO1_19,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,,,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number (decimal value) to SCT2 inputs 0 to 2" "PIO0_4,PIO0_27,,,SCT0_OUT4,SCT0_OUT5,SCT0_OUT7,SCT0_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SCT3_INMUX0,Input mux register for SCT3 input 0"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,PIO1_21,PIO1_22,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,PIO1_21,PIO1_22,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,,,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 0 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,,,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SCT3_INMUX1,Input mux register for SCT3 input 1"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,PIO1_21,PIO1_22,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,PIO1_21,PIO1_22,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,,,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 1 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,,,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SCT3_INMUX2,Input mux register for SCT3 input 2"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,PIO1_21,PIO1_22,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,PIO1_21,PIO1_22,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,,,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,USB_FRAME_TOGGLE,DEBUG_HALTED,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " INP_N ,Input number 2 to SCT3 inputs 0 to 2" "PIO0_7,PIO1_11,,,SCT1_OUT4,SCT1_OUT5,SCT1_OUT7,SCT1_OUT8,ADC0_THCMP_IRQ,ADC1_THCMP_IRQ,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,SCTIPU_ABORT3,SCTIPU_SAMPLE0,SCTIPU_SAMPLE1,SCTIPU_SAMPLE2,SCTIPU_SAMPLE3,,DEBUG_HALTED,?..."
|
|
endif
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0xC0++0xf
|
|
line.long 0x00 "PINTSEL0,Pin interrupt select register 0"
|
|
bitfld.long 0x00 7. " PIO0_[7] ,Pin number 7 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " PIO0_[6] ,Pin number 6 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " PIO0_[5] ,Pin number 5 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " PIO0_[4] ,Pin number 4 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIO0_[3] ,Pin number 3 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " PIO0_[2] ,Pin number 2 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " PIO0_[1] ,Pin number 1 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " PIO0_[0] ,Pin number 0 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x04 "PINTSEL1,Pin interrupt select register 1"
|
|
bitfld.long 0x04 7. " PIO0_[15] ,Pin number 15 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 6. " PIO0_[14] ,Pin number 14 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " PIO0_[13] ,Pin number 13 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 4. " PIO0_[12] ,Pin number 12 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PIO0_[11] ,Pin number 11 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " PIO0_[10] ,Pin number 10 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " PIO0_[9] ,Pin number 9 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 0. " PIO0_[8] ,Pin number 8 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x08 "PINTSEL2,Pin interrupt select register 2"
|
|
bitfld.long 0x08 7. " PIO0_[23] ,Pin number 23 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 6. " PIO0_[22] ,Pin number 22 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 5. " PIO0_[21] ,Pin number 21 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 4. " PIO0_[20] ,Pin number 20 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PIO0_[19] ,Pin number 19 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 2. " PIO0_[18] ,Pin number 18 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 1. " PIO0_[17] ,Pin number 17 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 0. " PIO0_[16] ,Pin number 16 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x0c "PINTSEL3,Pin interrupt select register 3"
|
|
bitfld.long 0x0c 7. " PIO0_[31] ,Pin number 31 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 6. " PIO0_[30] ,Pin number 30 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 5. " PIO0_[29] ,Pin number 29 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 4. " PIO0_[28] ,Pin number 28 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " PIO0_[27] ,Pin number 27 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 2. " PIO0_[26] ,Pin number 26 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 1. " PIO0_[25] ,Pin number 25 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 0. " PIO0_[24] ,Pin number 24 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
group.long 0xD0++0xf
|
|
line.long 0x00 "PINTSEL5,Pin interrupt select register 5"
|
|
bitfld.long 0x00 7. " PIO1_[39] ,Pin number 39 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " PIO1_[38] ,Pin number 38 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " PIO1_[37] ,Pin number 37 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " PIO1_[36] ,Pin number 36 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIO1_[35] ,Pin number 35 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " PIO1_[34] ,Pin number 34 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " PIO1_[33] ,Pin number 33 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " PIO1_[32] ,Pin number 32 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x04 "PINTSEL6,Pin interrupt select register 6"
|
|
bitfld.long 0x04 7. " PIO1_[47] ,Pin number 47 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 6. " PIO1_[46] ,Pin number 46 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " PIO1_[45] ,Pin number 45 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 4. " PIO1_[44] ,Pin number 44 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PIO1_[43] ,Pin number 43 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " PIO1_[42] ,Pin number 42 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " PIO1_[41] ,Pin number 41 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 0. " PIO1_[40] ,Pin number 40 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x08 "PINTSEL7,Pin interrupt select register 7"
|
|
bitfld.long 0x08 7. " PIO1_[55] ,Pin number 55 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 6. " PIO1_[54] ,Pin number 54 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 5. " PIO1_[53] ,Pin number 53 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 4. " PIO1_[52] ,Pin number 52 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PIO1_[51] ,Pin number 51 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 2. " PIO1_[50] ,Pin number 50 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 1. " PIO1_[49] ,Pin number 49 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 0. " PIO1_[48] ,Pin number 48 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x0c "PINTSEL8,Pin interrupt select register 8"
|
|
bitfld.long 0x0c 7. " PIO1_[63] ,Pin number 63 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 6. " PIO1_[62] ,Pin number 62 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 5. " PIO1_[61] ,Pin number 61 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 4. " PIO1_[60] ,Pin number 60 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " PIO1_[59] ,Pin number 59 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 2. " PIO1_[58] ,Pin number 58 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 1. " PIO1_[57] ,Pin number 57 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 0. " PIO1_[56] ,Pin number 56 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
elif cpuis("LPC15?7")
|
|
group.long 0xC0++0xf
|
|
line.long 0x00 "PINTSEL0,Pin interrupt select register 0"
|
|
bitfld.long 0x00 7. " PIO0_[7] ,Pin number 7 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " PIO0_[6] ,Pin number 6 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " PIO0_[5] ,Pin number 5 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " PIO0_[4] ,Pin number 4 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIO0_[3] ,Pin number 3 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " PIO0_[2] ,Pin number 2 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " PIO0_[1] ,Pin number 1 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " PIO0_[0] ,Pin number 0 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x04 "PINTSEL1,Pin interrupt select register 1"
|
|
bitfld.long 0x04 7. " PIO0_[15] ,Pin number 15 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 6. " PIO0_[14] ,Pin number 14 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " PIO0_[13] ,Pin number 13 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 4. " PIO0_[12] ,Pin number 12 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PIO0_[11] ,Pin number 11 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " PIO0_[10] ,Pin number 10 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " PIO0_[9] ,Pin number 9 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 0. " PIO0_[8] ,Pin number 8 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x08 "PINTSEL2,Pin interrupt select register 2"
|
|
bitfld.long 0x08 7. " PIO0_[23] ,Pin number 23 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 6. " PIO0_[22] ,Pin number 22 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 5. " PIO0_[21] ,Pin number 21 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 4. " PIO0_[20] ,Pin number 20 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PIO0_[19] ,Pin number 19 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 2. " PIO0_[18] ,Pin number 18 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 1. " PIO0_[17] ,Pin number 17 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x08 0. " PIO0_[16] ,Pin number 16 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x0c "PINTSEL3,Pin interrupt select register 3"
|
|
bitfld.long 0x0c 7. " PIO0_[31] ,Pin number 31 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 6. " PIO0_[30] ,Pin number 30 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 5. " PIO0_[29] ,Pin number 29 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 4. " PIO0_[28] ,Pin number 28 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " PIO0_[27] ,Pin number 27 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 2. " PIO0_[26] ,Pin number 26 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 1. " PIO0_[25] ,Pin number 25 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x0c 0. " PIO0_[24] ,Pin number 24 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
group.long 0xD0++0x07
|
|
line.long 0x00 "PINTSEL4,Pin interrupt select register 4"
|
|
bitfld.long 0x00 7. " PIO1_[7] ,Pin number 7 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " PIO1_[6] ,Pin number 6 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " PIO1_[5] ,Pin number 5 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " PIO1_[4] ,Pin number 4 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIO1_[3] ,Pin number 3 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " PIO1_[2] ,Pin number 2 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " PIO1_[1] ,Pin number 1 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " PIO1_[0] ,Pin number 0 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
line.long 0x04 "PINTSEL5,Pin interrupt select register 5"
|
|
bitfld.long 0x04 3. " PIO1_[11] ,Pin number 11 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " PIO1_[10] ,Pin number 10 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " PIO1_[9] ,Pin number 9 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
bitfld.long 0x04 0. " PIO1_[8] ,Pin number 8 select for pin interrupt or pattern match engine input" "Not selected,Selected"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX0,Input mux register for trigger input 0 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 0 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX1,Input mux register for trigger input 1 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 1 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX2,Input mux register for trigger input 2 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 2 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX3,Input mux register for trigger input 3 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 3 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX4,Input mux register for trigger input 4 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 4 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX5,Input mux register for trigger input 5 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 5 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX6,Input mux register for trigger input 6 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 6 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX7,Input mux register for trigger input 7 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 7 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX8,Input mux register for trigger input 8 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 8 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX9,Input mux register for trigger input 9 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 9 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX10,Input mux register for trigger input 10 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 10 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX11,Input mux register for trigger input 11 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 11 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX12,Input mux register for trigger input 12 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 12 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX13,Input mux register for trigger input 13 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 13 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX14,Input mux register for trigger input 14 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 14 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX15,Input mux register for trigger input 15 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 15 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX16,Input mux register for trigger input 16 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 16 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DRAM_ITRIG_INMUX17,Input mux register for trigger input 17 connected to DMA channel 0"
|
|
bitfld.long 0x00 0.--4. " INP ,Trigger input number 17 for DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,ADC1_SEQA_IRQ,ADC1_SEQB_IRQ,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,SCT2_DMA0,SCT2_DMA1,SCT3_DMA0,SCT3_DMA1,ACMP0_OUT,ACMP1_OUT,ACMP2_OUT,ACMP3_OUT,DMA_INMUX_INMUX0,DMA_INMUX_INMUX1,DMA_INMUX_INMUX2,DMA_INMUX_INMUX3,?..."
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DMA_INMUX_INMUX0,Input mux register for DMA trigger input 20"
|
|
bitfld.long 0x00 0.--4. " INP ,DMA trigger output number 0 for DMA channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DMA_INMUX_INMUX1,Input mux register for DMA trigger input 21"
|
|
bitfld.long 0x00 0.--4. " INP ,DMA trigger output number 1 for DMA channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DMA_INMUX_INMUX2,Input mux register for DMA trigger input 22"
|
|
bitfld.long 0x00 0.--4. " INP ,DMA trigger output number 2 for DMA channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DMA_INMUX_INMUX3,Input mux register for DMA trigger input 23"
|
|
bitfld.long 0x00 0.--4. " INP ,DMA trigger output number 3 for DMA channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x160++0x7
|
|
line.long 0x00 "FREQMEAS_REF,Clock selection for frequency measurement function reference clock"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x00 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,USB_FTOGGLE,PIO0_5,PIO0_19,PIO0_30,PIO1_27,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x00 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,USB_FTOGGLE,PIO0_5,PIO0_19,PIO0_30,,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x00 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,,PIO0_5,PIO0_19,PIO0_30,PIO1_27,?..."
|
|
elif cpuis("LPC1517")
|
|
bitfld.long 0x00 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,,PIO0_5,PIO0_19,PIO0_30,,?..."
|
|
endif
|
|
line.long 0x04 "FREQMEAS_TARGET,Clock selection for frequency measurement function target clock"
|
|
sif (cpuis("LPC1549")||cpuis("LPC1548"))
|
|
bitfld.long 0x04 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,USB_FTOGGLE,PIO0_5,PIO0_19,PIO0_30,PIO1_27,?..."
|
|
elif cpuis("LPC1547")
|
|
bitfld.long 0x04 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,USB_FTOGGLE,PIO0_5,PIO0_19,PIO0_30,,?..."
|
|
elif (cpuis("LPC1519")||cpuis("LPC1518"))
|
|
bitfld.long 0x04 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,,PIO0_5,PIO0_19,PIO0_30,PIO1_27,?..."
|
|
elif cpuis("LPC1517")
|
|
bitfld.long 0x04 0.--3. " CLKIN ,Clock source number for frequency measure function target clock" "MAIN_OSC,IRC,WDOSC,32KHZOSC,,PIO0_5,PIO0_19,PIO0_30,,?..."
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x1C000000
|
|
width 7.
|
|
tree "Pin-state registers"
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "B0,Byte pin PIO0_0 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_0" "Low,High"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "B1,Byte pin PIO0_1 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_1" "Low,High"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "B2,Byte pin PIO0_2 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_2" "Low,High"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "B3,Byte pin PIO0_3 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_3" "Low,High"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "B4,Byte pin PIO0_4 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_4" "Low,High"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "B5,Byte pin PIO0_5 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_5" "Low,High"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "B6,Byte pin PIO0_6 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_6" "Low,High"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "B7,Byte pin PIO0_7 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_7" "Low,High"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "B8,Byte pin PIO0_8 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_8" "Low,High"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "B9,Byte pin PIO0_9 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_9" "Low,High"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "B10,Byte pin PIO0_10 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_10" "Low,High"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "B11,Byte pin PIO0_11 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_11" "Low,High"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "B12,Byte pin PIO0_12 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_12" "Low,High"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "B13,Byte pin PIO0_13 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_13" "Low,High"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "B14,Byte pin PIO0_14 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_14" "Low,High"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "B15,Byte pin PIO0_15 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_15" "Low,High"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "B16,Byte pin PIO0_16 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_16" "Low,High"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "B17,Byte pin PIO0_17 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_17" "Low,High"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "B18,Byte pin PIO0_18 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_18" "Low,High"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "B19,Byte pin PIO0_19 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_19" "Low,High"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "B20,Byte pin PIO0_20 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_20" "Low,High"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "B21,Byte pin PIO0_21 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_21" "Low,High"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "B22,Byte pin PIO0_22 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_22" "Low,High"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "B23,Byte pin PIO0_23 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_23" "Low,High"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "B24,Byte pin PIO0_24 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_24" "Low,High"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "B25,Byte pin PIO0_25 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_25" "Low,High"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "B26,Byte pin PIO0_26 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_26" "Low,High"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "B27,Byte pin PIO0_27 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_27" "Low,High"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "B28,Byte pin PIO0_28 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_28" "Low,High"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "B29,Byte pin PIO0_29 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_29" "Low,High"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "B30,Byte pin PIO0_30 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_30" "Low,High"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "B31,Byte pin PIO0_31 register for port 0"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_31" "Low,High"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "B32,Byte pin PIO1_0 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_0" "Low,High"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "B33,Byte pin PIO1_1 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_1" "Low,High"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "B34,Byte pin PIO1_2 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_2" "Low,High"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "B35,Byte pin PIO1_3 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_3" "Low,High"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "B36,Byte pin PIO1_4 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_4" "Low,High"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "B37,Byte pin PIO1_5 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_5" "Low,High"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "B38,Byte pin PIO1_6 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_6" "Low,High"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "B39,Byte pin PIO1_7 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_7" "Low,High"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "B40,Byte pin PIO1_8 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_8" "Low,High"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "B41,Byte pin PIO1_9 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_9" "Low,High"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "B42,Byte pin PIO1_10 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_10" "Low,High"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "B43,Byte pin PIO1_11 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_11" "Low,High"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "B44,Byte pin PIO1_12 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_12" "Low,High"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "B45,Byte pin PIO1_13 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "B46,Byte pin PIO1_14 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_14" "Low,High"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "B47,Byte pin PIO1_15 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_15" "Low,High"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "B48,Byte pin PIO1_16 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_16" "Low,High"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "B49,Byte pin PIO1_17 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_17" "Low,High"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "B50,Byte pin PIO1_18 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_18" "Low,High"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "B51,Byte pin PIO1_19 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "B52,Byte pin PIO1_20 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_20" "Low,High"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "B53,Byte pin PIO1_21 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_21" "Low,High"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "B54,Byte pin PIO1_22 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_22" "Low,High"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "B55,Byte pin PIO1_23 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_23" "Low,High"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "B56,Byte pin PIO1_24 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_24" "Low,High"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "B57,Byte pin PIO1_25 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_25" "Low,High"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "B58,Byte pin PIO1_26 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_26" "Low,High"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "B59,Byte pin PIO1_27 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_27" "Low,High"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "B60,Byte pin PIO1_28 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_28" "Low,High"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "B61,Byte pin PIO1_29 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_29" "Low,High"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "B62,Byte pin PIO1_30 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_30" "Low,High"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "B63,Byte pin PIO1_31 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_31" "Low,High"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "B64,Byte pin PIO2_0 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_0" "Low,High"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "B65,Byte pin PIO2_1 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_1" "Low,High"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "B66,Byte pin PIO2_2 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_2" "Low,High"
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "B67,Byte pin PIO2_3 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_3" "Low,High"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "B68,Byte pin PIO2_4 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_4" "Low,High"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "B69,Byte pin PIO2_5 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_5" "Low,High"
|
|
group.byte 0x46++0x00
|
|
line.byte 0x00 "B70,Byte pin PIO2_6 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_6" "Low,High"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "B71,Byte pin PIO2_7 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_7" "Low,High"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "B72,Byte pin PIO2_8 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_8" "Low,High"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "B73,Byte pin PIO2_9 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_9" "Low,High"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "B74,Byte pin PIO2_10 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_10" "Low,High"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "B75,Byte pin PIO2_11 register for port 2"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_11" "Low,High"
|
|
else
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "B32,Byte pin PIO1_0 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_0" "Low,High"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "B33,Byte pin PIO1_1 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_1" "Low,High"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "B34,Byte pin PIO1_2 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_2" "Low,High"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "B35,Byte pin PIO1_3 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_3" "Low,High"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "B36,Byte pin PIO1_4 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_4" "Low,High"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "B37,Byte pin PIO1_5 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_5" "Low,High"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "B38,Byte pin PIO1_6 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_6" "Low,High"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "B39,Byte pin PIO1_7 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_7" "Low,High"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "B40,Byte pin PIO1_8 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_8" "Low,High"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "B41,Byte pin PIO1_9 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_9" "Low,High"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "B42,Byte pin PIO1_10 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_10" "Low,High"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "B43,Byte pin PIO1_11 register for port 1"
|
|
bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_11" "Low,High"
|
|
endif
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "W0,Word pin PIO0_0 register for port 0"
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "W1,Word pin PIO0_1 register for port 0"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "W2,Word pin PIO0_2 register for port 0"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "W3,Word pin PIO0_3 register for port 0"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "W4,Word pin PIO0_4 register for port 0"
|
|
group.long 0x1014++0x03
|
|
line.long 0x00 "W5,Word pin PIO0_5 register for port 0"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "W6,Word pin PIO0_6 register for port 0"
|
|
group.long 0x101C++0x03
|
|
line.long 0x00 "W7,Word pin PIO0_7 register for port 0"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "W8,Word pin PIO0_8 register for port 0"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "W9,Word pin PIO0_9 register for port 0"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "W10,Word pin PIO0_10 register for port 0"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "W11,Word pin PIO0_11 register for port 0"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "W12,Word pin PIO0_12 register for port 0"
|
|
group.long 0x1034++0x03
|
|
line.long 0x00 "W13,Word pin PIO0_13 register for port 0"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "W14,Word pin PIO0_14 register for port 0"
|
|
group.long 0x103C++0x03
|
|
line.long 0x00 "W15,Word pin PIO0_15 register for port 0"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "W16,Word pin PIO0_16 register for port 0"
|
|
group.long 0x1044++0x03
|
|
line.long 0x00 "W17,Word pin PIO0_17 register for port 0"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "W18,Word pin PIO0_18 register for port 0"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "W19,Word pin PIO0_19 register for port 0"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "W20,Word pin PIO0_20 register for port 0"
|
|
group.long 0x1054++0x03
|
|
line.long 0x00 "W21,Word pin PIO0_21 register for port 0"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "W22,Word pin PIO0_22 register for port 0"
|
|
group.long 0x105C++0x03
|
|
line.long 0x00 "W23,Word pin PIO0_23 register for port 0"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "W24,Word pin PIO0_24 register for port 0"
|
|
group.long 0x1064++0x03
|
|
line.long 0x00 "W25,Word pin PIO0_25 register for port 0"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "W26,Word pin PIO0_26 register for port 0"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "W27,Word pin PIO0_27 register for port 0"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "W28,Word pin PIO0_28 register for port 0"
|
|
group.long 0x1074++0x03
|
|
line.long 0x00 "W29,Word pin PIO0_29 register for port 0"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "W30,Word pin PIO0_30 register for port 0"
|
|
group.long 0x107C++0x03
|
|
line.long 0x00 "W31,Word pin PIO0_31 register for port 0"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "W32,Word pin PIO1_0 register for port 1"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "W33,Word pin PIO1_1 register for port 1"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "W34,Word pin PIO1_2 register for port 1"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "W35,Word pin PIO1_3 register for port 1"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "W36,Word pin PIO1_4 register for port 1"
|
|
group.long 0x1094++0x03
|
|
line.long 0x00 "W37,Word pin PIO1_5 register for port 1"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "W38,Word pin PIO1_6 register for port 1"
|
|
group.long 0x109C++0x03
|
|
line.long 0x00 "W39,Word pin PIO1_7 register for port 1"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "W40,Word pin PIO1_8 register for port 1"
|
|
group.long 0x10A4++0x03
|
|
line.long 0x00 "W41,Word pin PIO1_9 register for port 1"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "W42,Word pin PIO1_10 register for port 1"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "W43,Word pin PIO1_11 register for port 1"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "W44,Word pin PIO1_12 register for port 1"
|
|
group.long 0x10B4++0x03
|
|
line.long 0x00 "W45,Word pin PIO1_13 register for port 1"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "W46,Word pin PIO1_14 register for port 1"
|
|
group.long 0x10BC++0x03
|
|
line.long 0x00 "W47,Word pin PIO1_15 register for port 1"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "W48,Word pin PIO1_16 register for port 1"
|
|
group.long 0x10C4++0x03
|
|
line.long 0x00 "W49,Word pin PIO1_17 register for port 1"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "W50,Word pin PIO1_18 register for port 1"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "W51,Word pin PIO1_19 register for port 1"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "W52,Word pin PIO1_20 register for port 1"
|
|
group.long 0x10D4++0x03
|
|
line.long 0x00 "W53,Word pin PIO1_21 register for port 1"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "W54,Word pin PIO1_22 register for port 1"
|
|
group.long 0x10DC++0x03
|
|
line.long 0x00 "W55,Word pin PIO1_23 register for port 1"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "W56,Word pin PIO1_24 register for port 1"
|
|
group.long 0x10E4++0x03
|
|
line.long 0x00 "W57,Word pin PIO1_25 register for port 1"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "W58,Word pin PIO1_26 register for port 1"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "W59,Word pin PIO1_27 register for port 1"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "W60,Word pin PIO1_28 register for port 1"
|
|
group.long 0x10F4++0x03
|
|
line.long 0x00 "W61,Word pin PIO1_29 register for port 1"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "W62,Word pin PIO1_30 register for port 1"
|
|
group.long 0x10FC++0x03
|
|
line.long 0x00 "W63,Word pin PIO1_31 register for port 1"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "W64,Word pin PIO2_0 register for port 2"
|
|
group.long 0x1104++0x03
|
|
line.long 0x00 "W65,Word pin PIO2_1 register for port 2"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "W66,Word pin PIO2_2 register for port 2"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "W67,Word pin PIO2_3 register for port 2"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "W68,Word pin PIO2_4 register for port 2"
|
|
group.long 0x1114++0x03
|
|
line.long 0x00 "W69,Word pin PIO2_5 register for port 2"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "W70,Word pin PIO2_6 register for port 2"
|
|
group.long 0x111C++0x03
|
|
line.long 0x00 "W71,Word pin PIO2_7 register for port 2"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "W72,Word pin PIO2_8 register for port 2"
|
|
group.long 0x1124++0x03
|
|
line.long 0x00 "W73,Word pin PIO2_9 register for port 2"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "W74,Word pin PIO2_10 register for port 2"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "W75,Word pin PIO2_11 register for port 2"
|
|
else
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "W32,Word pin PIO1_0 register for port 1"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "W33,Word pin PIO1_1 register for port 1"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "W34,Word pin PIO1_2 register for port 1"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "W35,Word pin PIO1_3 register for port 1"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "W36,Word pin PIO1_4 register for port 1"
|
|
group.long 0x1094++0x03
|
|
line.long 0x00 "W37,Word pin PIO1_5 register for port 1"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "W38,Word pin PIO1_6 register for port 1"
|
|
group.long 0x109C++0x03
|
|
line.long 0x00 "W39,Word pin PIO1_7 register for port 1"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "W40,Word pin PIO1_8 register for port 1"
|
|
group.long 0x10A4++0x03
|
|
line.long 0x00 "W41,Word pin PIO1_9 register for port 1"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "W42,Word pin PIO1_10 register for port 1"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "W43,Word pin PIO1_11 register for port 1"
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
group.long 0x2000++0x07
|
|
line.long 0x00 "DIR0,Direction register for port 0"
|
|
bitfld.long 0x00 31. " DIRP[31] ,Selects direction for pin PIO0_31" "Input,Output"
|
|
bitfld.long 0x00 30. " DIRP[30] ,Selects direction for pin PIO0_30" "Input,Output"
|
|
bitfld.long 0x00 29. " DIRP[29] ,Selects direction for pin PIO0_29" "Input,Output"
|
|
bitfld.long 0x00 28. " DIRP[28] ,Selects direction for pin PIO0_28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIRP[27] ,Selects direction for pin PIO0_27" "Input,Output"
|
|
bitfld.long 0x00 26. " DIRP[26] ,Selects direction for pin PIO0_26" "Input,Output"
|
|
bitfld.long 0x00 25. " DIRP[25] ,Selects direction for pin PIO0_25" "Input,Output"
|
|
bitfld.long 0x00 24. " DIRP[24] ,Selects direction for pin PIO0_24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DIRP[23] ,Selects direction for pin PIO0_23" "Input,Output"
|
|
bitfld.long 0x00 22. " DIRP[22] ,Selects direction for pin PIO0_22" "Input,Output"
|
|
bitfld.long 0x00 21. " DIRP[21] ,Selects direction for pin PIO0_21" "Input,Output"
|
|
bitfld.long 0x00 20. " DIRP[20] ,Selects direction for pin PIO0_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIRP[19] ,Selects direction for pin PIO0_19" "Input,Output"
|
|
bitfld.long 0x00 18. " DIRP[18] ,Selects direction for pin PIO0_18" "Input,Output"
|
|
bitfld.long 0x00 17. " DIRP[17] ,Selects direction for pin PIO0_17" "Input,Output"
|
|
bitfld.long 0x00 16. " DIRP[16] ,Selects direction for pin PIO0_16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIRP[15] ,Selects direction for pin PIO0_15" "Input,Output"
|
|
bitfld.long 0x00 14. " DIRP[14] ,Selects direction for pin PIO0_14" "Input,Output"
|
|
bitfld.long 0x00 13. " DIRP[13] ,Selects direction for pin PIO0_13" "Input,Output"
|
|
bitfld.long 0x00 12. " DIRP[12] ,Selects direction for pin PIO0_12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIRP[11] ,Selects direction for pin PIO0_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP[10] ,Selects direction for pin PIO0_10" "Input,Output"
|
|
bitfld.long 0x00 9. " DIRP[9] ,Selects direction for pin PIO0_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP[8] ,Selects direction for pin PIO0_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP[7] ,Selects direction for pin PIO0_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP[6] ,Selects direction for pin PIO0_6" "Input,Output"
|
|
bitfld.long 0x00 5. " DIRP[5] ,Selects direction for pin PIO0_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP[4] ,Selects direction for pin PIO0_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP[3] ,Selects direction for pin PIO0_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP[2] ,Selects direction for pin PIO0_2" "Input,Output"
|
|
bitfld.long 0x00 1. " DIRP[1] ,Selects direction for pin PIO0_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP[0] ,Selects direction for pin PIO0_0" "Input,Output"
|
|
line.long 0x04 "DIR1,Direction register for port 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " DIRP[31] ,Selects direction for pin PIO1_31" "Input,Output"
|
|
bitfld.long 0x04 30. " DIRP[30] ,Selects direction for pin PIO1_30" "Input,Output"
|
|
bitfld.long 0x04 29. " DIRP[29] ,Selects direction for pin PIO1_29" "Input,Output"
|
|
bitfld.long 0x04 28. " DIRP[28] ,Selects direction for pin PIO1_28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DIRP[27] ,Selects direction for pin PIO1_27" "Input,Output"
|
|
bitfld.long 0x04 26. " DIRP[26] ,Selects direction for pin PIO1_26" "Input,Output"
|
|
bitfld.long 0x04 25. " DIRP[25] ,Selects direction for pin PIO1_25" "Input,Output"
|
|
bitfld.long 0x04 24. " DIRP[24] ,Selects direction for pin PIO1_24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DIRP[23] ,Selects direction for pin PIO1_23" "Input,Output"
|
|
bitfld.long 0x04 22. " DIRP[22] ,Selects direction for pin PIO1_22" "Input,Output"
|
|
bitfld.long 0x04 21. " DIRP[21] ,Selects direction for pin PIO1_21" "Input,Output"
|
|
bitfld.long 0x04 20. " DIRP[20] ,Selects direction for pin PIO1_20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DIRP[19] ,Selects direction for pin PIO1_19" "Input,Output"
|
|
bitfld.long 0x04 18. " DIRP[18] ,Selects direction for pin PIO1_18" "Input,Output"
|
|
bitfld.long 0x04 17. " DIRP[17] ,Selects direction for pin PIO1_17" "Input,Output"
|
|
bitfld.long 0x04 16. " DIRP[16] ,Selects direction for pin PIO1_16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " DIRP[15] ,Selects direction for pin PIO1_15" "Input,Output"
|
|
bitfld.long 0x04 14. " DIRP[14] ,Selects direction for pin PIO1_14" "Input,Output"
|
|
bitfld.long 0x04 13. " DIRP[13] ,Selects direction for pin PIO1_13" "Input,Output"
|
|
bitfld.long 0x04 12. " DIRP[12] ,Selects direction for pin PIO1_12" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " DIRP[11] ,Selects direction for pin PIO1_11" "Input,Output"
|
|
bitfld.long 0x04 10. " DIRP[10] ,Selects direction for pin PIO1_10" "Input,Output"
|
|
bitfld.long 0x04 9. " DIRP[9] ,Selects direction for pin PIO1_9" "Input,Output"
|
|
bitfld.long 0x04 8. " DIRP[8] ,Selects direction for pin PIO1_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DIRP[7] ,Selects direction for pin PIO1_7" "Input,Output"
|
|
bitfld.long 0x04 6. " DIRP[6] ,Selects direction for pin PIO1_6" "Input,Output"
|
|
bitfld.long 0x04 5. " DIRP[5] ,Selects direction for pin PIO1_5" "Input,Output"
|
|
bitfld.long 0x04 4. " DIRP[4] ,Selects direction for pin PIO1_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DIRP[3] ,Selects direction for pin PIO1_3" "Input,Output"
|
|
bitfld.long 0x04 2. " DIRP[2] ,Selects direction for pin PIO1_2" "Input,Output"
|
|
bitfld.long 0x04 1. " DIRP[1] ,Selects direction for pin PIO1_1" "Input,Output"
|
|
bitfld.long 0x04 0. " DIRP[0] ,Selects direction for pin PIO1_0" "Input,Output"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x2008++0x03
|
|
line.long 0x00 "DIR2,Direction register for port 2"
|
|
bitfld.long 0x00 11. " DIRP[11] ,Selects direction for pin PIO2_11" "Input,Output"
|
|
bitfld.long 0x00 10. " DIRP[10] ,Selects direction for pin PIO2_10" "Input,Output"
|
|
bitfld.long 0x00 9. " DIRP[9] ,Selects direction for pin PIO2_9" "Input,Output"
|
|
bitfld.long 0x00 8. " DIRP[8] ,Selects direction for pin PIO2_8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIRP[7] ,Selects direction for pin PIO2_7" "Input,Output"
|
|
bitfld.long 0x00 6. " DIRP[6] ,Selects direction for pin PIO2_6" "Input,Output"
|
|
bitfld.long 0x00 5. " DIRP[5] ,Selects direction for pin PIO2_5" "Input,Output"
|
|
bitfld.long 0x00 4. " DIRP[4] ,Selects direction for pin PIO2_4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIRP[3] ,Selects direction for pin PIO2_3" "Input,Output"
|
|
bitfld.long 0x00 2. " DIRP[2] ,Selects direction for pin PIO2_2" "Input,Output"
|
|
bitfld.long 0x00 1. " DIRP[1] ,Selects direction for pin PIO2_1" "Input,Output"
|
|
bitfld.long 0x00 0. " DIRP[0] ,Selects direction for pin PIO2_0" "Input,Output"
|
|
endif
|
|
textline " "
|
|
group.long 0x2080++0x07
|
|
line.long 0x00 "MASK0,Mask register for port 0"
|
|
bitfld.long 0x00 31. " MASKP[31] ,Masks pin PIO0_31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " MASKP[30] ,Masks pin PIO0_30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " MASKP[29] ,Masks pin PIO0_29" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " MASKP[28] ,Masks pin PIO0_28" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MASKP[27] ,Masks pin PIO0_27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MASKP[26] ,Masks pin PIO0_26" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " MASKP[25] ,Masks pin PIO0_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MASKP[24] ,Masks pin PIO0_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MASKP[23] ,Masks pin PIO0_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MASKP[22] ,Masks pin PIO0_22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " MASKP[21] ,Masks pin PIO0_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MASKP[20] ,Masks pin PIO0_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MASKP[19] ,Masks pin PIO0_19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MASKP[18] ,Masks pin PIO0_18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " MASKP[17] ,Masks pin PIO0_17" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MASKP[16] ,Masks pin PIO0_16" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MASKP[15] ,Masks pin PIO0_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MASKP[14] ,Masks pin PIO0_14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " MASKP[13] ,Masks pin PIO0_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MASKP[12] ,Masks pin PIO0_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MASKP[11] ,Masks pin PIO0_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP[10] ,Masks pin PIO0_10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " MASKP[9] ,Masks pin PIO0_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP[8] ,Masks pin PIO0_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP[7] ,Masks pin PIO0_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP[6] ,Masks pin PIO0_6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MASKP[5] ,Masks pin PIO0_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP[4] ,Masks pin PIO0_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP[3] ,Masks pin PIO0_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP[2] ,Masks pin PIO0_2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " MASKP[1] ,Masks pin PIO0_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP[0] ,Masks pin PIO0_0" "Not masked,Masked"
|
|
line.long 0x04 "MASK1,Mask register for port 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " MASKP[31] ,Masks pin PIO1_31" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " MASKP[30] ,Masks pin PIO1_30" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " MASKP[29] ,Masks pin PIO1_29" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " MASKP[28] ,Masks pin PIO1_28" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MASKP[27] ,Masks pin PIO1_27" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " MASKP[26] ,Masks pin PIO1_26" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " MASKP[25] ,Masks pin PIO1_25" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " MASKP[24] ,Masks pin PIO1_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MASKP[23] ,Masks pin PIO1_23" "Not masked,Masked"
|
|
bitfld.long 0x04 22. " MASKP[22] ,Masks pin PIO1_22" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " MASKP[21] ,Masks pin PIO1_21" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " MASKP[20] ,Masks pin PIO1_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MASKP[19] ,Masks pin PIO1_19" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " MASKP[18] ,Masks pin PIO1_18" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " MASKP[17] ,Masks pin PIO1_17" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " MASKP[16] ,Masks pin PIO1_16" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MASKP[15] ,Masks pin PIO1_15" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " MASKP[14] ,Masks pin PIO1_14" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " MASKP[13] ,Masks pin PIO1_13" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " MASKP[12] ,Masks pin PIO1_12" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " MASKP[11] ,Masks pin PIO1_11" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " MASKP[10] ,Masks pin PIO1_10" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " MASKP[9] ,Masks pin PIO1_9" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " MASKP[8] ,Masks pin PIO1_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MASKP[7] ,Masks pin PIO1_7" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " MASKP[6] ,Masks pin PIO1_6" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " MASKP[5] ,Masks pin PIO1_5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " MASKP[4] ,Masks pin PIO1_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MASKP[3] ,Masks pin PIO1_3" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " MASKP[2] ,Masks pin PIO1_2" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " MASKP[1] ,Masks pin PIO1_1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " MASKP[0] ,Masks pin PIO1_0" "Not masked,Masked"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x2088++0x03
|
|
line.long 0x00 "MASK2,Mask register for port 2"
|
|
bitfld.long 0x00 11. " MASKP[11] ,Masks pin PIO2_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MASKP[10] ,Masks pin PIO2_10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " MASKP[9] ,Masks pin PIO2_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MASKP[8] ,Masks pin PIO2_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MASKP[7] ,Masks pin PIO2_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MASKP[6] ,Masks pin PIO2_6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MASKP[5] ,Masks pin PIO2_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MASKP[4] ,Masks pin PIO2_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MASKP[3] ,Masks pin PIO2_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MASKP[2] ,Masks pin PIO2_2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " MASKP[1] ,Masks pin PIO2_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MASKP[0] ,Masks pin PIO2_0" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
group.long 0x2100++0x07
|
|
line.long 0x00 "PIN0,Port pin register for port 0"
|
|
bitfld.long 0x00 31. " PORT[31] ,State of pin PIO0_31" "Low,High"
|
|
bitfld.long 0x00 30. " PORT[30] ,State of pin PIO0_30" "Low,High"
|
|
bitfld.long 0x00 29. " PORT[29] ,State of pin PIO0_29" "Low,High"
|
|
bitfld.long 0x00 28. " PORT[28] ,State of pin PIO0_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PORT[27] ,State of pin PIO0_27" "Low,High"
|
|
bitfld.long 0x00 26. " PORT[26] ,State of pin PIO0_26" "Low,High"
|
|
bitfld.long 0x00 25. " PORT[25] ,State of pin PIO0_25" "Low,High"
|
|
bitfld.long 0x00 24. " PORT[24] ,State of pin PIO0_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PORT[23] ,State of pin PIO0_23" "Low,High"
|
|
bitfld.long 0x00 22. " PORT[22] ,State of pin PIO0_22" "Low,High"
|
|
bitfld.long 0x00 21. " PORT[21] ,State of pin PIO0_21" "Low,High"
|
|
bitfld.long 0x00 20. " PORT[20] ,State of pin PIO0_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORT[19] ,State of pin PIO0_19" "Low,High"
|
|
bitfld.long 0x00 18. " PORT[18] ,State of pin PIO0_18" "Low,High"
|
|
bitfld.long 0x00 17. " PORT[17] ,State of pin PIO0_17" "Low,High"
|
|
bitfld.long 0x00 16. " PORT[16] ,State of pin PIO0_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PORT[15] ,State of pin PIO0_15" "Low,High"
|
|
bitfld.long 0x00 14. " PORT[14] ,State of pin PIO0_14" "Low,High"
|
|
bitfld.long 0x00 13. " PORT[13] ,State of pin PIO0_13" "Low,High"
|
|
bitfld.long 0x00 12. " PORT[12] ,State of pin PIO0_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PORT[11] ,State of pin PIO0_11" "Low,High"
|
|
bitfld.long 0x00 10. " PORT[10] ,State of pin PIO0_10" "Low,High"
|
|
bitfld.long 0x00 9. " PORT[9] ,State of pin PIO0_9" "Low,High"
|
|
bitfld.long 0x00 8. " PORT[8] ,State of pin PIO0_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT[7] ,State of pin PIO0_7" "Low,High"
|
|
bitfld.long 0x00 6. " PORT[6] ,State of pin PIO0_6" "Low,High"
|
|
bitfld.long 0x00 5. " PORT[5] ,State of pin PIO0_5" "Low,High"
|
|
bitfld.long 0x00 4. " PORT[4] ,State of pin PIO0_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT[3] ,State of pin PIO0_3" "Low,High"
|
|
bitfld.long 0x00 2. " PORT[2] ,State of pin PIO0_2" "Low,High"
|
|
bitfld.long 0x00 1. " PORT[1] ,State of pin PIO0_1" "Low,High"
|
|
bitfld.long 0x00 0. " PORT[0] ,State of pin PIO0_0" "Low,High"
|
|
line.long 0x04 "PIN1,Port pin register for port 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " PORT[31] ,State of pin PIO1_31" "Low,High"
|
|
bitfld.long 0x04 30. " PORT[30] ,State of pin PIO1_30" "Low,High"
|
|
bitfld.long 0x04 29. " PORT[29] ,State of pin PIO1_29" "Low,High"
|
|
bitfld.long 0x04 28. " PORT[28] ,State of pin PIO1_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PORT[27] ,State of pin PIO1_27" "Low,High"
|
|
bitfld.long 0x04 26. " PORT[26] ,State of pin PIO1_26" "Low,High"
|
|
bitfld.long 0x04 25. " PORT[25] ,State of pin PIO1_25" "Low,High"
|
|
bitfld.long 0x04 24. " PORT[24] ,State of pin PIO1_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PORT[23] ,State of pin PIO1_23" "Low,High"
|
|
bitfld.long 0x04 22. " PORT[22] ,State of pin PIO1_22" "Low,High"
|
|
bitfld.long 0x04 21. " PORT[21] ,State of pin PIO1_21" "Low,High"
|
|
bitfld.long 0x04 20. " PORT[20] ,State of pin PIO1_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PORT[19] ,State of pin PIO1_19" "Low,High"
|
|
bitfld.long 0x04 18. " PORT[18] ,State of pin PIO1_18" "Low,High"
|
|
bitfld.long 0x04 17. " PORT[17] ,State of pin PIO1_17" "Low,High"
|
|
bitfld.long 0x04 16. " PORT[16] ,State of pin PIO1_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PORT[15] ,State of pin PIO1_15" "Low,High"
|
|
bitfld.long 0x04 14. " PORT[14] ,State of pin PIO1_14" "Low,High"
|
|
bitfld.long 0x04 13. " PORT[13] ,State of pin PIO1_13" "Low,High"
|
|
bitfld.long 0x04 12. " PORT[12] ,State of pin PIO1_12" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " PORT[11] ,State of pin PIO1_11" "Low,High"
|
|
bitfld.long 0x04 10. " PORT[10] ,State of pin PIO1_10" "Low,High"
|
|
bitfld.long 0x04 9. " PORT[9] ,State of pin PIO1_9" "Low,High"
|
|
bitfld.long 0x04 8. " PORT[8] ,State of pin PIO1_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PORT[7] ,State of pin PIO1_7" "Low,High"
|
|
bitfld.long 0x04 6. " PORT[6] ,State of pin PIO1_6" "Low,High"
|
|
bitfld.long 0x04 5. " PORT[5] ,State of pin PIO1_5" "Low,High"
|
|
bitfld.long 0x04 4. " PORT[4] ,State of pin PIO1_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PORT[3] ,State of pin PIO1_3" "Low,High"
|
|
bitfld.long 0x04 2. " PORT[2] ,State of pin PIO1_2" "Low,High"
|
|
bitfld.long 0x04 1. " PORT[1] ,State of pin PIO1_1" "Low,High"
|
|
bitfld.long 0x04 0. " PORT[0] ,State of pin PIO1_0" "Low,High"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "PIN2,Port pin register for port 2"
|
|
bitfld.long 0x00 11. " PORT[11] ,State of pin PIO2_11" "Low,High"
|
|
bitfld.long 0x00 10. " PORT[10] ,State of pin PIO2_10" "Low,High"
|
|
bitfld.long 0x00 9. " PORT[9] ,State of pin PIO2_9" "Low,High"
|
|
bitfld.long 0x00 8. " PORT[8] ,State of pin PIO2_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PORT[7] ,State of pin PIO2_7" "Low,High"
|
|
bitfld.long 0x00 6. " PORT[6] ,State of pin PIO2_6" "Low,High"
|
|
bitfld.long 0x00 5. " PORT[5] ,State of pin PIO2_5" "Low,High"
|
|
bitfld.long 0x00 4. " PORT[4] ,State of pin PIO2_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PORT[3] ,State of pin PIO2_3" "Low,High"
|
|
bitfld.long 0x00 2. " PORT[2] ,State of pin PIO2_2" "Low,High"
|
|
bitfld.long 0x00 1. " PORT[1] ,State of pin PIO2_1" "Low,High"
|
|
bitfld.long 0x00 0. " PORT[0] ,State of pin PIO2_0" "Low,High"
|
|
endif
|
|
textline " "
|
|
group.long 0x2180++0x07
|
|
line.long 0x00 "MPIN0,Masked port register for port 0"
|
|
bitfld.long 0x00 31. " MPORTP[31] ,Masked port on pin PIO0_31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " MPORTP[30] ,Masked port on pin PIO0_30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " MPORTP[29] ,Masked port on pin PIO0_29" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " MPORTP[28] ,Masked port on pin PIO0_28" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MPORTP[27] ,Masked port on pin PIO0_27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MPORTP[26] ,Masked port on pin PIO0_26" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " MPORTP[25] ,Masked port on pin PIO0_25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " MPORTP[24] ,Masked port on pin PIO0_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MPORTP[23] ,Masked port on pin PIO0_23" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " MPORTP[22] ,Masked port on pin PIO0_22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " MPORTP[21] ,Masked port on pin PIO0_21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " MPORTP[20] ,Masked port on pin PIO0_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MPORTP[19] ,Masked port on pin PIO0_19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " MPORTP[18] ,Masked port on pin PIO0_18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " MPORTP[17] ,Masked port on pin PIO0_17" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " MPORTP[16] ,Masked port on pin PIO0_16" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MPORTP[15] ,Masked port on pin PIO0_15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " MPORTP[14] ,Masked port on pin PIO0_14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " MPORTP[13] ,Masked port on pin PIO0_13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " MPORTP[12] ,Masked port on pin PIO0_12" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MPORTP[11] ,Masked port on pin PIO0_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MPORTP[10] ,Masked port on pin PIO0_10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " MPORTP[9] ,Masked port on pin PIO0_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MPORTP[8] ,Masked port on pin PIO0_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP[7] ,Masked port on pin PIO0_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MPORTP[6] ,Masked port on pin PIO0_6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MPORTP[5] ,Masked port on pin PIO0_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MPORTP[4] ,Masked port on pin PIO0_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP[3] ,Masked port on pin PIO0_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MPORTP[2] ,Masked port on pin PIO0_2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " MPORTP[1] ,Masked port on pin PIO0_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MPORTP[0] ,Masked port on pin PIO0_0" "Not masked,Masked"
|
|
line.long 0x04 "MPIN1,Masked port register for port 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " MPORTP[31] ,Masked port on pin PIO1_31" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " MPORTP[30] ,Masked port on pin PIO1_30" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " MPORTP[29] ,Masked port on pin PIO1_29" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " MPORTP[28] ,Masked port on pin PIO1_28" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MPORTP[27] ,Masked port on pin PIO1_27" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " MPORTP[26] ,Masked port on pin PIO1_26" "Not masked,Masked"
|
|
bitfld.long 0x04 25. " MPORTP[25] ,Masked port on pin PIO1_25" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " MPORTP[24] ,Masked port on pin PIO1_24" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MPORTP[23] ,Masked port on pin PIO1_23" "Not masked,Masked"
|
|
bitfld.long 0x04 22. " MPORTP[22] ,Masked port on pin PIO1_22" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " MPORTP[21] ,Masked port on pin PIO1_21" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " MPORTP[20] ,Masked port on pin PIO1_20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MPORTP[19] ,Masked port on pin PIO1_19" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " MPORTP[18] ,Masked port on pin PIO1_18" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " MPORTP[17] ,Masked port on pin PIO1_17" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " MPORTP[16] ,Masked port on pin PIO1_16" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MPORTP[15] ,Masked port on pin PIO1_15" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " MPORTP[14] ,Masked port on pin PIO1_14" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " MPORTP[13] ,Masked port on pin PIO1_13" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " MPORTP[12] ,Masked port on pin PIO1_12" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " MPORTP[11] ,Masked port on pin PIO1_11" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " MPORTP[10] ,Masked port on pin PIO1_10" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " MPORTP[9] ,Masked port on pin PIO1_9" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " MPORTP[8] ,Masked port on pin PIO1_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MPORTP[7] ,Masked port on pin PIO1_7" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " MPORTP[6] ,Masked port on pin PIO1_6" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " MPORTP[5] ,Masked port on pin PIO1_5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " MPORTP[4] ,Masked port on pin PIO1_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MPORTP[3] ,Masked port on pin PIO1_3" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " MPORTP[2] ,Masked port on pin PIO1_2" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " MPORTP[1] ,Masked port on pin PIO1_1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " MPORTP[0] ,Masked port on pin PIO1_0" "Not masked,Masked"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x2188++0x03
|
|
line.long 0x00 "MPIN2,Masked port register for port 2"
|
|
bitfld.long 0x00 11. " MPORTP[11] ,Masked port on pin PIO2_11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " MPORTP[10] ,Masked port on pin PIO2_10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " MPORTP[9] ,Masked port on pin PIO2_9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MPORTP[8] ,Masked port on pin PIO2_8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MPORTP[7] ,Masked port on pin PIO2_7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " MPORTP[6] ,Masked port on pin PIO2_6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MPORTP[5] ,Masked port on pin PIO2_5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " MPORTP[4] ,Masked port on pin PIO2_4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MPORTP[3] ,Masked port on pin PIO2_3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " MPORTP[2] ,Masked port on pin PIO2_2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " MPORTP[1] ,Masked port on pin PIO2_1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MPORTP[0] ,Masked port on pin PIO2_0" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
group.long 0x2200++0x07
|
|
line.long 0x00 "SET0,Set register for port 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SETP[31]_set/clr ,Set pin PIO0_31" "Clear,Set"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SETP[30]_set/clr ,Set pin PIO0_30" "Clear,Set"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SETP[29]_set/clr ,Set pin PIO0_29" "Clear,Set"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SETP[28]_set/clr ,Set pin PIO0_28" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SETP[27]_set/clr ,Set pin PIO0_27" "Clear,Set"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SETP[26]_set/clr ,Set pin PIO0_26" "Clear,Set"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SETP[25]_set/clr ,Set pin PIO0_25" "Clear,Set"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SETP[24]_set/clr ,Set pin PIO0_24" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SETP[23]_set/clr ,Set pin PIO0_23" "Clear,Set"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SETP[22]_set/clr ,Set pin PIO0_22" "Clear,Set"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SETP[21]_set/clr ,Set pin PIO0_21" "Clear,Set"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SETP[20]_set/clr ,Set pin PIO0_20" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SETP[19]_set/clr ,Set pin PIO0_19" "Clear,Set"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SETP[18]_set/clr ,Set pin PIO0_18" "Clear,Set"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SETP[17]_set/clr ,Set pin PIO0_17" "Clear,Set"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SETP[16]_set/clr ,Set pin PIO0_16" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SETP[15]_set/clr ,Set pin PIO0_15" "Clear,Set"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SETP[14]_set/clr ,Set pin PIO0_14" "Clear,Set"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SETP[13]_set/clr ,Set pin PIO0_13" "Clear,Set"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SETP[12]_set/clr ,Set pin PIO0_12" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SETP[11]_set/clr ,Set pin PIO0_11" "Clear,Set"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SETP[10]_set/clr ,Set pin PIO0_10" "Clear,Set"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SETP[9]_set/clr ,Set pin PIO0_9" "Clear,Set"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SETP[8]_set/clr ,Set pin PIO0_8" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SETP[7]_set/clr ,Set pin PIO0_7" "Clear,Set"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SETP[6]_set/clr ,Set pin PIO0_6" "Clear,Set"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SETP[5]_set/clr ,Set pin PIO0_5" "Clear,Set"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SETP[4]_set/clr ,Set pin PIO0_4" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SETP[3]_set/clr ,Set pin PIO0_3" "Clear,Set"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SETP[2]_set/clr ,Set pin PIO0_2" "Clear,Set"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SETP[1]_set/clr ,Set pin PIO0_1" "Clear,Set"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SETP[0]_set/clr ,Set pin PIO0_0" "Clear,Set"
|
|
line.long 0x04 "SET1,Set register for port 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " SETP[31]_set/clr ,Set pin PIO1_31" "Clear,Set"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " SETP[30]_set/clr ,Set pin PIO1_30" "Clear,Set"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " SETP[29]_set/clr ,Set pin PIO1_29" "Clear,Set"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " SETP[28]_set/clr ,Set pin PIO1_28" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " SETP[27]_set/clr ,Set pin PIO1_27" "Clear,Set"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " SETP[26]_set/clr ,Set pin PIO1_26" "Clear,Set"
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " SETP[25]_set/clr ,Set pin PIO1_25" "Clear,Set"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " SETP[24]_set/clr ,Set pin PIO1_24" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " SETP[23]_set/clr ,Set pin PIO1_23" "Clear,Set"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " SETP[22]_set/clr ,Set pin PIO1_22" "Clear,Set"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " SETP[21]_set/clr ,Set pin PIO1_21" "Clear,Set"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " SETP[20]_set/clr ,Set pin PIO1_20" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " SETP[19]_set/clr ,Set pin PIO1_19" "Clear,Set"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " SETP[18]_set/clr ,Set pin PIO1_18" "Clear,Set"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " SETP[17]_set/clr ,Set pin PIO1_17" "Clear,Set"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " SETP[16]_set/clr ,Set pin PIO1_16" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " SETP[15]_set/clr ,Set pin PIO1_15" "Clear,Set"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " SETP[14]_set/clr ,Set pin PIO1_14" "Clear,Set"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " SETP[13]_set/clr ,Set pin PIO1_13" "Clear,Set"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " SETP[12]_set/clr ,Set pin PIO1_12" "Clear,Set"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " SETP[11]_set/clr ,Set pin PIO1_11" "Clear,Set"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " SETP[10]_set/clr ,Set pin PIO1_10" "Clear,Set"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " SETP[9]_set/clr ,Set pin PIO1_9" "Clear,Set"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " SETP[8]_set/clr ,Set pin PIO1_8" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " SETP[7]_set/clr ,Set pin PIO1_7" "Clear,Set"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " SETP[6]_set/clr ,Set pin PIO1_6" "Clear,Set"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " SETP[5]_set/clr ,Set pin PIO1_5" "Clear,Set"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " SETP[4]_set/clr ,Set pin PIO1_4" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " SETP[3]_set/clr ,Set pin PIO1_3" "Clear,Set"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " SETP[2]_set/clr ,Set pin PIO1_2" "Clear,Set"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " SETP[1]_set/clr ,Set pin PIO1_1" "Clear,Set"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " SETP[0]_set/clr ,Set pin PIO1_0" "Clear,Set"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x2208++0x03
|
|
line.long 0x00 "SET2,Set register for port 2"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SETP[11]_set/clr ,Set pin PIO2_11" "Clear,Set"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SETP[10]_set/clr ,Set pin PIO2_10" "Clear,Set"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SETP[9]_set/clr ,Set pin PIO2_9" "Clear,Set"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SETP[8]_set/clr ,Set pin PIO2_8" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SETP[7]_set/clr ,Set pin PIO2_7" "Clear,Set"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SETP[6]_set/clr ,Set pin PIO2_6" "Clear,Set"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SETP[5]_set/clr ,Set pin PIO2_5" "Clear,Set"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SETP[4]_set/clr ,Set pin PIO2_4" "Clear,Set"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SETP[3]_set/clr ,Set pin PIO2_3" "Clear,Set"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SETP[2]_set/clr ,Set pin PIO2_2" "Clear,Set"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SETP[1]_set/clr ,Set pin PIO2_1" "Clear,Set"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SETP[0]_set/clr ,Set pin PIO2_0" "Clear,Set"
|
|
endif
|
|
textline " "
|
|
wgroup.long 0x2300++0x07
|
|
line.long 0x00 "NOT0,Toggle register for port 0"
|
|
bitfld.long 0x00 31. " NOTP[31] ,Toggle pin PIO0_31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. " NOTP[30] ,Toggle pin PIO0_30" "No effect,Toggle"
|
|
bitfld.long 0x00 29. " NOTP[29] ,Toggle pin PIO0_29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. " NOTP[28] ,Toggle pin PIO0_28" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NOTP[27] ,Toggle pin PIO0_27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. " NOTP[26] ,Toggle pin PIO0_26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. " NOTP[25] ,Toggle pin PIO0_25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. " NOTP[24] ,Toggle pin PIO0_24" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NOTP[23] ,Toggle pin PIO0_23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. " NOTP[22] ,Toggle pin PIO0_22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. " NOTP[21] ,Toggle pin PIO0_21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. " NOTP[20] ,Toggle pin PIO0_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NOTP[19] ,Toggle pin PIO0_19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. " NOTP[18] ,Toggle pin PIO0_18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. " NOTP[17] ,Toggle pin PIO0_17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. " NOTP[16] ,Toggle pin PIO0_16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NOTP[15] ,Toggle pin PIO0_15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. " NOTP[14] ,Toggle pin PIO0_14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. " NOTP[13] ,Toggle pin PIO0_13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. " NOTP[12] ,Toggle pin PIO0_12" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NOTP[11] ,Toggle pin PIO0_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP[10] ,Toggle pin PIO0_10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " NOTP[9] ,Toggle pin PIO0_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP[8] ,Toggle pin PIO0_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP[7] ,Toggle pin PIO0_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP[6] ,Toggle pin PIO0_6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " NOTP[5] ,Toggle pin PIO0_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP[4] ,Toggle pin PIO0_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP[3] ,Toggle pin PIO0_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP[2] ,Toggle pin PIO0_2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " NOTP[1] ,Toggle pin PIO0_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP[0] ,Toggle pin PIO0_0" "No effect,Toggle"
|
|
line.long 0x04 "NOT1,Toggle register for port 1"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " NOTP[31] ,Toggle pin PIO1_31" "No effect,Toggle"
|
|
bitfld.long 0x04 30. " NOTP[30] ,Toggle pin PIO1_30" "No effect,Toggle"
|
|
bitfld.long 0x04 29. " NOTP[29] ,Toggle pin PIO1_29" "No effect,Toggle"
|
|
bitfld.long 0x04 28. " NOTP[28] ,Toggle pin PIO1_28" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x04 27. " NOTP[27] ,Toggle pin PIO1_27" "No effect,Toggle"
|
|
bitfld.long 0x04 26. " NOTP[26] ,Toggle pin PIO1_26" "No effect,Toggle"
|
|
bitfld.long 0x04 25. " NOTP[25] ,Toggle pin PIO1_25" "No effect,Toggle"
|
|
bitfld.long 0x04 24. " NOTP[24] ,Toggle pin PIO1_24" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NOTP[23] ,Toggle pin PIO1_23" "No effect,Toggle"
|
|
bitfld.long 0x04 22. " NOTP[22] ,Toggle pin PIO1_22" "No effect,Toggle"
|
|
bitfld.long 0x04 21. " NOTP[21] ,Toggle pin PIO1_21" "No effect,Toggle"
|
|
bitfld.long 0x04 20. " NOTP[20] ,Toggle pin PIO1_20" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NOTP[19] ,Toggle pin PIO1_19" "No effect,Toggle"
|
|
bitfld.long 0x04 18. " NOTP[18] ,Toggle pin PIO1_18" "No effect,Toggle"
|
|
bitfld.long 0x04 17. " NOTP[17] ,Toggle pin PIO1_17" "No effect,Toggle"
|
|
bitfld.long 0x04 16. " NOTP[16] ,Toggle pin PIO1_16" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x04 15. " NOTP[15] ,Toggle pin PIO1_15" "No effect,Toggle"
|
|
bitfld.long 0x04 14. " NOTP[14] ,Toggle pin PIO1_14" "No effect,Toggle"
|
|
bitfld.long 0x04 13. " NOTP[13] ,Toggle pin PIO1_13" "No effect,Toggle"
|
|
bitfld.long 0x04 12. " NOTP[12] ,Toggle pin PIO1_12" "No effect,Toggle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " NOTP[11] ,Toggle pin PIO1_11" "No effect,Toggle"
|
|
bitfld.long 0x04 10. " NOTP[10] ,Toggle pin PIO1_10" "No effect,Toggle"
|
|
bitfld.long 0x04 9. " NOTP[9] ,Toggle pin PIO1_9" "No effect,Toggle"
|
|
bitfld.long 0x04 8. " NOTP[8] ,Toggle pin PIO1_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x04 7. " NOTP[7] ,Toggle pin PIO1_7" "No effect,Toggle"
|
|
bitfld.long 0x04 6. " NOTP[6] ,Toggle pin PIO1_6" "No effect,Toggle"
|
|
bitfld.long 0x04 5. " NOTP[5] ,Toggle pin PIO1_5" "No effect,Toggle"
|
|
bitfld.long 0x04 4. " NOTP[4] ,Toggle pin PIO1_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x04 3. " NOTP[3] ,Toggle pin PIO1_3" "No effect,Toggle"
|
|
bitfld.long 0x04 2. " NOTP[2] ,Toggle pin PIO1_2" "No effect,Toggle"
|
|
bitfld.long 0x04 1. " NOTP[1] ,Toggle pin PIO1_1" "No effect,Toggle"
|
|
bitfld.long 0x04 0. " NOTP[0] ,Toggle pin PIO1_0" "No effect,Toggle"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
wgroup.long 0x2308++0x03
|
|
line.long 0x00 "NOT2,Toggle register for port 2"
|
|
bitfld.long 0x00 11. " NOTP[11] ,Toggle pin PIO2_11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. " NOTP[10] ,Toggle pin PIO2_10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. " NOTP[9] ,Toggle pin PIO2_9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. " NOTP[8] ,Toggle pin PIO2_8" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NOTP[7] ,Toggle pin PIO2_7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. " NOTP[6] ,Toggle pin PIO2_6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. " NOTP[5] ,Toggle pin PIO2_5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. " NOTP[4] ,Toggle pin PIO2_4" "No effect,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NOTP[3] ,Toggle pin PIO2_3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. " NOTP[2] ,Toggle pin PIO2_2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. " NOTP[1] ,Toggle pin PIO2_1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. " NOTP[0] ,Toggle pin PIO2_0" "No effect,Toggle"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree.open "GINT (Group GPIO input interrupt)"
|
|
tree "GINT0"
|
|
base ad:0x400A8000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,GPIO grouped interrupt control register"
|
|
bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level"
|
|
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR func,AND func"
|
|
bitfld.long 0x00 0. " INT ,Group interrupt status" "Inactive,Active"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "PORT_POL0,GPIO grouped interrupt port 0 polarity register"
|
|
bitfld.long 0x00 31. " POL[31] ,Polarity of pin PIO0_31" "Low,High"
|
|
bitfld.long 0x00 30. " POL[30] ,Polarity of pin PIO0_30" "Low,High"
|
|
bitfld.long 0x00 29. " POL[29] ,Polarity of pin PIO0_29" "Low,High"
|
|
bitfld.long 0x00 28. " POL[28] ,Polarity of pin PIO0_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " POL[27] ,Polarity of pin PIO0_27" "Low,High"
|
|
bitfld.long 0x00 26. " POL[26] ,Polarity of pin PIO0_26" "Low,High"
|
|
bitfld.long 0x00 25. " POL[25] ,Polarity of pin PIO0_25" "Low,High"
|
|
bitfld.long 0x00 24. " POL[24] ,Polarity of pin PIO0_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " POL[23] ,Polarity of pin PIO0_23" "Low,High"
|
|
bitfld.long 0x00 22. " POL[22] ,Polarity of pin PIO0_22" "Low,High"
|
|
bitfld.long 0x00 21. " POL[21] ,Polarity of pin PIO0_21" "Low,High"
|
|
bitfld.long 0x00 20. " POL[20] ,Polarity of pin PIO0_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL[19] ,Polarity of pin PIO0_19" "Low,High"
|
|
bitfld.long 0x00 18. " POL[18] ,Polarity of pin PIO0_18" "Low,High"
|
|
bitfld.long 0x00 17. " POL[17] ,Polarity of pin PIO0_17" "Low,High"
|
|
bitfld.long 0x00 16. " POL[16] ,Polarity of pin PIO0_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL[15] ,Polarity of pin PIO0_15" "Low,High"
|
|
bitfld.long 0x00 14. " POL[14] ,Polarity of pin PIO0_14" "Low,High"
|
|
bitfld.long 0x00 13. " POL[13] ,Polarity of pin PIO0_13" "Low,High"
|
|
bitfld.long 0x00 12. " POL[12] ,Polarity of pin PIO0_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " POL[11] ,Polarity of pin PIO0_11" "Low,High"
|
|
bitfld.long 0x00 10. " POL[10] ,Polarity of pin PIO0_10" "Low,High"
|
|
bitfld.long 0x00 9. " POL[9] ,Polarity of pin PIO0_9" "Low,High"
|
|
bitfld.long 0x00 8. " POL[8] ,Polarity of pin PIO0_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL[7] ,Polarity of pin PIO0_7" "Low,High"
|
|
bitfld.long 0x00 6. " POL[6] ,Polarity of pin PIO0_6" "Low,High"
|
|
bitfld.long 0x00 5. " POL[5] ,Polarity of pin PIO0_5" "Low,High"
|
|
bitfld.long 0x00 4. " POL[4] ,Polarity of pin PIO0_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL[3] ,Polarity of pin PIO0_3" "Low,High"
|
|
bitfld.long 0x00 2. " POL[2] ,Polarity of pin PIO0_2" "Low,High"
|
|
bitfld.long 0x00 1. " POL[1] ,Polarity of pin PIO0_1" "Low,High"
|
|
bitfld.long 0x00 0. " POL[0] ,Polarity of pin PIO0_0" "Low,High"
|
|
line.long 0x04 "PORT_POL1,GPIO grouped interrupt port 1 polarity register"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " POL[31] ,Polarity of pin PIO1_31" "Low,High"
|
|
bitfld.long 0x04 30. " POL[30] ,Polarity of pin PIO1_30" "Low,High"
|
|
bitfld.long 0x04 29. " POL[29] ,Polarity of pin PIO1_29" "Low,High"
|
|
bitfld.long 0x04 28. " POL[28] ,Polarity of pin PIO1_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " POL[27] ,Polarity of pin PIO1_27" "Low,High"
|
|
bitfld.long 0x04 26. " POL[26] ,Polarity of pin PIO1_26" "Low,High"
|
|
bitfld.long 0x04 25. " POL[25] ,Polarity of pin PIO1_25" "Low,High"
|
|
bitfld.long 0x04 24. " POL[24] ,Polarity of pin PIO1_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " POL[23] ,Polarity of pin PIO1_23" "Low,High"
|
|
bitfld.long 0x04 22. " POL[22] ,Polarity of pin PIO1_22" "Low,High"
|
|
bitfld.long 0x04 21. " POL[21] ,Polarity of pin PIO1_21" "Low,High"
|
|
bitfld.long 0x04 20. " POL[20] ,Polarity of pin PIO1_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " POL[19] ,Polarity of pin PIO1_19" "Low,High"
|
|
bitfld.long 0x04 18. " POL[18] ,Polarity of pin PIO1_18" "Low,High"
|
|
bitfld.long 0x04 17. " POL[17] ,Polarity of pin PIO1_17" "Low,High"
|
|
bitfld.long 0x04 16. " POL[16] ,Polarity of pin PIO1_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " POL[15] ,Polarity of pin PIO1_15" "Low,High"
|
|
bitfld.long 0x04 14. " POL[14] ,Polarity of pin PIO1_14" "Low,High"
|
|
bitfld.long 0x04 13. " POL[13] ,Polarity of pin PIO1_13" "Low,High"
|
|
bitfld.long 0x04 12. " POL[12] ,Polarity of pin PIO1_12" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " POL[11] ,Polarity of pin PIO1_11" "Low,High"
|
|
bitfld.long 0x04 10. " POL[10] ,Polarity of pin PIO1_10" "Low,High"
|
|
bitfld.long 0x04 9. " POL[9] ,Polarity of pin PIO1_9" "Low,High"
|
|
bitfld.long 0x04 8. " POL[8] ,Polarity of pin PIO1_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " POL[7] ,Polarity of pin PIO1_7" "Low,High"
|
|
bitfld.long 0x04 6. " POL[6] ,Polarity of pin PIO1_6" "Low,High"
|
|
bitfld.long 0x04 5. " POL[5] ,Polarity of pin PIO1_5" "Low,High"
|
|
bitfld.long 0x04 4. " POL[4] ,Polarity of pin PIO1_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " POL[3] ,Polarity of pin PIO1_3" "Low,High"
|
|
bitfld.long 0x04 2. " POL[2] ,Polarity of pin PIO1_2" "Low,High"
|
|
bitfld.long 0x04 1. " POL[1] ,Polarity of pin PIO1_1" "Low,High"
|
|
bitfld.long 0x04 0. " POL[0] ,Polarity of pin PIO1_0" "Low,High"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PORT_POL2,GPIO grouped interrupt port 2 polarity register"
|
|
bitfld.long 0x00 11. " POL[11] ,Polarity of pin PIO2_11" "Low,High"
|
|
bitfld.long 0x00 10. " POL[10] ,Polarity of pin PIO2_10" "Low,High"
|
|
bitfld.long 0x00 9. " POL[9] ,Polarity of pin PIO2_9" "Low,High"
|
|
bitfld.long 0x00 8. " POL[8] ,Polarity of pin PIO2_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL[7] ,Polarity of pin PIO2_7" "Low,High"
|
|
bitfld.long 0x00 6. " POL[6] ,Polarity of pin PIO2_6" "Low,High"
|
|
bitfld.long 0x00 5. " POL[5] ,Polarity of pin PIO2_5" "Low,High"
|
|
bitfld.long 0x00 4. " POL[4] ,Polarity of pin PIO2_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL[3] ,Polarity of pin PIO2_3" "Low,High"
|
|
bitfld.long 0x00 2. " POL[2] ,Polarity of pin PIO2_2" "Low,High"
|
|
bitfld.long 0x00 1. " POL[1] ,Polarity of pin PIO2_1" "Low,High"
|
|
bitfld.long 0x00 0. " POL[0] ,Polarity of pin PIO2_0" "Low,High"
|
|
endif
|
|
textline ""
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "PORT_ENA0,GPIO grouped interrupt port 0 enable register"
|
|
bitfld.long 0x00 31. " ENA[31] ,Enable of pin PIO0_31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENA[30] ,Enable of pin PIO0_30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENA[29] ,Enable of pin PIO0_29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ENA[28] ,Enable of pin PIO0_28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENA[27] ,Enable of pin PIO0_27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA[26] ,Enable of pin PIO0_26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ENA[25] ,Enable of pin PIO0_25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA[24] ,Enable of pin PIO0_24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENA[23] ,Enable of pin PIO0_23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA[22] ,Enable of pin PIO0_22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA[21] ,Enable of pin PIO0_21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENA[20] ,Enable of pin PIO0_20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENA[19] ,Enable of pin PIO0_19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA[18] ,Enable of pin PIO0_18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENA[17] ,Enable of pin PIO0_17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENA[16] ,Enable of pin PIO0_16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENA[15] ,Enable of pin PIO0_15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA[14] ,Enable of pin PIO0_14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA[13] ,Enable of pin PIO0_13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA[12] ,Enable of pin PIO0_12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA[11] ,Enable of pin PIO0_11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA[10] ,Enable of pin PIO0_10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA[9] ,Enable of pin PIO0_9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA[8] ,Enable of pin PIO0_8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA[7] ,Enable of pin PIO0_7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA[6] ,Enable of pin PIO0_6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA[5] ,Enable of pin PIO0_5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA[4] ,Enable of pin PIO0_4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA[3] ,Enable of pin PIO0_3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA[2] ,Enable of pin PIO0_2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA[1] ,Enable of pin PIO0_1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA[0] ,Enable of pin PIO0_0" "Disabled,Enabled"
|
|
line.long 0x04 "PORT_ENA1,GPIO grouped interrupt port 1 enable register"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " ENA[31] ,Enable of pin PIO1_31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENA[30] ,Enable of pin PIO1_30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " ENA[29] ,Enable of pin PIO1_29" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " ENA[28] ,Enable of pin PIO1_28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ENA[27] ,Enable of pin PIO1_27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " ENA[26] ,Enable of pin PIO1_26" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " ENA[25] ,Enable of pin PIO1_25" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " ENA[24] ,Enable of pin PIO1_24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " ENA[23] ,Enable of pin PIO1_23" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ENA[22] ,Enable of pin PIO1_22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " ENA[21] ,Enable of pin PIO1_21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " ENA[20] ,Enable of pin PIO1_20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ENA[19] ,Enable of pin PIO1_19" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ENA[18] ,Enable of pin PIO1_18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " ENA[17] ,Enable of pin PIO1_17" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " ENA[16] ,Enable of pin PIO1_16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " ENA[15] ,Enable of pin PIO1_15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ENA[14] ,Enable of pin PIO1_14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " ENA[13] ,Enable of pin PIO1_13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " ENA[12] ,Enable of pin PIO1_12" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " ENA[11] ,Enable of pin PIO1_11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ENA[10] ,Enable of pin PIO1_10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ENA[9] ,Enable of pin PIO1_9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ENA[8] ,Enable of pin PIO1_8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ENA[7] ,Enable of pin PIO1_7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ENA[6] ,Enable of pin PIO1_6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ENA[5] ,Enable of pin PIO1_5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ENA[4] ,Enable of pin PIO1_4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENA[3] ,Enable of pin PIO1_3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ENA[2] ,Enable of pin PIO1_2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ENA[1] ,Enable of pin PIO1_1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ENA[0] ,Enable of pin PIO1_0" "Disabled,Enabled"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PORT_ENA2,GPIO grouped interrupt port 2 enable register"
|
|
bitfld.long 0x00 11. " ENA[11] ,Enable of pin PIO2_11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA[10] ,Enable of pin PIO2_10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA[9] ,Enable of pin PIO2_9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA[8] ,Enable of pin PIO2_8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA[7] ,Enable of pin PIO2_7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA[6] ,Enable of pin PIO2_6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA[5] ,Enable of pin PIO2_5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA[4] ,Enable of pin PIO2_4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA[3] ,Enable of pin PIO2_3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA[2] ,Enable of pin PIO2_2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA[1] ,Enable of pin PIO2_1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA[0] ,Enable of pin PIO2_0" "Disabled,Enabled"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "GINT1"
|
|
base ad:0x400AC000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,GPIO grouped interrupt control register"
|
|
bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level"
|
|
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR func,AND func"
|
|
bitfld.long 0x00 0. " INT ,Group interrupt status" "Inactive,Active"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "PORT_POL0,GPIO grouped interrupt port 0 polarity register"
|
|
bitfld.long 0x00 31. " POL[31] ,Polarity of pin PIO0_31" "Low,High"
|
|
bitfld.long 0x00 30. " POL[30] ,Polarity of pin PIO0_30" "Low,High"
|
|
bitfld.long 0x00 29. " POL[29] ,Polarity of pin PIO0_29" "Low,High"
|
|
bitfld.long 0x00 28. " POL[28] ,Polarity of pin PIO0_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " POL[27] ,Polarity of pin PIO0_27" "Low,High"
|
|
bitfld.long 0x00 26. " POL[26] ,Polarity of pin PIO0_26" "Low,High"
|
|
bitfld.long 0x00 25. " POL[25] ,Polarity of pin PIO0_25" "Low,High"
|
|
bitfld.long 0x00 24. " POL[24] ,Polarity of pin PIO0_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " POL[23] ,Polarity of pin PIO0_23" "Low,High"
|
|
bitfld.long 0x00 22. " POL[22] ,Polarity of pin PIO0_22" "Low,High"
|
|
bitfld.long 0x00 21. " POL[21] ,Polarity of pin PIO0_21" "Low,High"
|
|
bitfld.long 0x00 20. " POL[20] ,Polarity of pin PIO0_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " POL[19] ,Polarity of pin PIO0_19" "Low,High"
|
|
bitfld.long 0x00 18. " POL[18] ,Polarity of pin PIO0_18" "Low,High"
|
|
bitfld.long 0x00 17. " POL[17] ,Polarity of pin PIO0_17" "Low,High"
|
|
bitfld.long 0x00 16. " POL[16] ,Polarity of pin PIO0_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL[15] ,Polarity of pin PIO0_15" "Low,High"
|
|
bitfld.long 0x00 14. " POL[14] ,Polarity of pin PIO0_14" "Low,High"
|
|
bitfld.long 0x00 13. " POL[13] ,Polarity of pin PIO0_13" "Low,High"
|
|
bitfld.long 0x00 12. " POL[12] ,Polarity of pin PIO0_12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " POL[11] ,Polarity of pin PIO0_11" "Low,High"
|
|
bitfld.long 0x00 10. " POL[10] ,Polarity of pin PIO0_10" "Low,High"
|
|
bitfld.long 0x00 9. " POL[9] ,Polarity of pin PIO0_9" "Low,High"
|
|
bitfld.long 0x00 8. " POL[8] ,Polarity of pin PIO0_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL[7] ,Polarity of pin PIO0_7" "Low,High"
|
|
bitfld.long 0x00 6. " POL[6] ,Polarity of pin PIO0_6" "Low,High"
|
|
bitfld.long 0x00 5. " POL[5] ,Polarity of pin PIO0_5" "Low,High"
|
|
bitfld.long 0x00 4. " POL[4] ,Polarity of pin PIO0_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL[3] ,Polarity of pin PIO0_3" "Low,High"
|
|
bitfld.long 0x00 2. " POL[2] ,Polarity of pin PIO0_2" "Low,High"
|
|
bitfld.long 0x00 1. " POL[1] ,Polarity of pin PIO0_1" "Low,High"
|
|
bitfld.long 0x00 0. " POL[0] ,Polarity of pin PIO0_0" "Low,High"
|
|
line.long 0x04 "PORT_POL1,GPIO grouped interrupt port 1 polarity register"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " POL[31] ,Polarity of pin PIO1_31" "Low,High"
|
|
bitfld.long 0x04 30. " POL[30] ,Polarity of pin PIO1_30" "Low,High"
|
|
bitfld.long 0x04 29. " POL[29] ,Polarity of pin PIO1_29" "Low,High"
|
|
bitfld.long 0x04 28. " POL[28] ,Polarity of pin PIO1_28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " POL[27] ,Polarity of pin PIO1_27" "Low,High"
|
|
bitfld.long 0x04 26. " POL[26] ,Polarity of pin PIO1_26" "Low,High"
|
|
bitfld.long 0x04 25. " POL[25] ,Polarity of pin PIO1_25" "Low,High"
|
|
bitfld.long 0x04 24. " POL[24] ,Polarity of pin PIO1_24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " POL[23] ,Polarity of pin PIO1_23" "Low,High"
|
|
bitfld.long 0x04 22. " POL[22] ,Polarity of pin PIO1_22" "Low,High"
|
|
bitfld.long 0x04 21. " POL[21] ,Polarity of pin PIO1_21" "Low,High"
|
|
bitfld.long 0x04 20. " POL[20] ,Polarity of pin PIO1_20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " POL[19] ,Polarity of pin PIO1_19" "Low,High"
|
|
bitfld.long 0x04 18. " POL[18] ,Polarity of pin PIO1_18" "Low,High"
|
|
bitfld.long 0x04 17. " POL[17] ,Polarity of pin PIO1_17" "Low,High"
|
|
bitfld.long 0x04 16. " POL[16] ,Polarity of pin PIO1_16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " POL[15] ,Polarity of pin PIO1_15" "Low,High"
|
|
bitfld.long 0x04 14. " POL[14] ,Polarity of pin PIO1_14" "Low,High"
|
|
bitfld.long 0x04 13. " POL[13] ,Polarity of pin PIO1_13" "Low,High"
|
|
bitfld.long 0x04 12. " POL[12] ,Polarity of pin PIO1_12" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " POL[11] ,Polarity of pin PIO1_11" "Low,High"
|
|
bitfld.long 0x04 10. " POL[10] ,Polarity of pin PIO1_10" "Low,High"
|
|
bitfld.long 0x04 9. " POL[9] ,Polarity of pin PIO1_9" "Low,High"
|
|
bitfld.long 0x04 8. " POL[8] ,Polarity of pin PIO1_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " POL[7] ,Polarity of pin PIO1_7" "Low,High"
|
|
bitfld.long 0x04 6. " POL[6] ,Polarity of pin PIO1_6" "Low,High"
|
|
bitfld.long 0x04 5. " POL[5] ,Polarity of pin PIO1_5" "Low,High"
|
|
bitfld.long 0x04 4. " POL[4] ,Polarity of pin PIO1_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " POL[3] ,Polarity of pin PIO1_3" "Low,High"
|
|
bitfld.long 0x04 2. " POL[2] ,Polarity of pin PIO1_2" "Low,High"
|
|
bitfld.long 0x04 1. " POL[1] ,Polarity of pin PIO1_1" "Low,High"
|
|
bitfld.long 0x04 0. " POL[0] ,Polarity of pin PIO1_0" "Low,High"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PORT_POL2,GPIO grouped interrupt port 2 polarity register"
|
|
bitfld.long 0x00 11. " POL[11] ,Polarity of pin PIO2_11" "Low,High"
|
|
bitfld.long 0x00 10. " POL[10] ,Polarity of pin PIO2_10" "Low,High"
|
|
bitfld.long 0x00 9. " POL[9] ,Polarity of pin PIO2_9" "Low,High"
|
|
bitfld.long 0x00 8. " POL[8] ,Polarity of pin PIO2_8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL[7] ,Polarity of pin PIO2_7" "Low,High"
|
|
bitfld.long 0x00 6. " POL[6] ,Polarity of pin PIO2_6" "Low,High"
|
|
bitfld.long 0x00 5. " POL[5] ,Polarity of pin PIO2_5" "Low,High"
|
|
bitfld.long 0x00 4. " POL[4] ,Polarity of pin PIO2_4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POL[3] ,Polarity of pin PIO2_3" "Low,High"
|
|
bitfld.long 0x00 2. " POL[2] ,Polarity of pin PIO2_2" "Low,High"
|
|
bitfld.long 0x00 1. " POL[1] ,Polarity of pin PIO2_1" "Low,High"
|
|
bitfld.long 0x00 0. " POL[0] ,Polarity of pin PIO2_0" "Low,High"
|
|
endif
|
|
textline ""
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "PORT_ENA0,GPIO grouped interrupt port 0 enable register"
|
|
bitfld.long 0x00 31. " ENA[31] ,Enable of pin PIO0_31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENA[30] ,Enable of pin PIO0_30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENA[29] ,Enable of pin PIO0_29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ENA[28] ,Enable of pin PIO0_28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENA[27] ,Enable of pin PIO0_27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENA[26] ,Enable of pin PIO0_26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ENA[25] ,Enable of pin PIO0_25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENA[24] ,Enable of pin PIO0_24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ENA[23] ,Enable of pin PIO0_23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENA[22] ,Enable of pin PIO0_22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ENA[21] ,Enable of pin PIO0_21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENA[20] ,Enable of pin PIO0_20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENA[19] ,Enable of pin PIO0_19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENA[18] ,Enable of pin PIO0_18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENA[17] ,Enable of pin PIO0_17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENA[16] ,Enable of pin PIO0_16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENA[15] ,Enable of pin PIO0_15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENA[14] ,Enable of pin PIO0_14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENA[13] ,Enable of pin PIO0_13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENA[12] ,Enable of pin PIO0_12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENA[11] ,Enable of pin PIO0_11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA[10] ,Enable of pin PIO0_10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA[9] ,Enable of pin PIO0_9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA[8] ,Enable of pin PIO0_8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA[7] ,Enable of pin PIO0_7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA[6] ,Enable of pin PIO0_6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA[5] ,Enable of pin PIO0_5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA[4] ,Enable of pin PIO0_4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA[3] ,Enable of pin PIO0_3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA[2] ,Enable of pin PIO0_2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA[1] ,Enable of pin PIO0_1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA[0] ,Enable of pin PIO0_0" "Disabled,Enabled"
|
|
line.long 0x04 "PORT_ENA1,GPIO grouped interrupt port 1 enable register"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
bitfld.long 0x04 31. " ENA[31] ,Enable of pin PIO1_31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ENA[30] ,Enable of pin PIO1_30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " ENA[29] ,Enable of pin PIO1_29" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " ENA[28] ,Enable of pin PIO1_28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ENA[27] ,Enable of pin PIO1_27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " ENA[26] ,Enable of pin PIO1_26" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " ENA[25] ,Enable of pin PIO1_25" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " ENA[24] ,Enable of pin PIO1_24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " ENA[23] ,Enable of pin PIO1_23" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ENA[22] ,Enable of pin PIO1_22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " ENA[21] ,Enable of pin PIO1_21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " ENA[20] ,Enable of pin PIO1_20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ENA[19] ,Enable of pin PIO1_19" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ENA[18] ,Enable of pin PIO1_18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " ENA[17] ,Enable of pin PIO1_17" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " ENA[16] ,Enable of pin PIO1_16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " ENA[15] ,Enable of pin PIO1_15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ENA[14] ,Enable of pin PIO1_14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " ENA[13] ,Enable of pin PIO1_13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " ENA[12] ,Enable of pin PIO1_12" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " ENA[11] ,Enable of pin PIO1_11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ENA[10] ,Enable of pin PIO1_10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ENA[9] ,Enable of pin PIO1_9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ENA[8] ,Enable of pin PIO1_8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ENA[7] ,Enable of pin PIO1_7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ENA[6] ,Enable of pin PIO1_6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ENA[5] ,Enable of pin PIO1_5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ENA[4] ,Enable of pin PIO1_4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENA[3] ,Enable of pin PIO1_3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ENA[2] ,Enable of pin PIO1_2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ENA[1] ,Enable of pin PIO1_1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ENA[0] ,Enable of pin PIO1_0" "Disabled,Enabled"
|
|
sif (cpuis("LPC15?9")||cpuis("LPC15?8"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PORT_ENA2,GPIO grouped interrupt port 2 enable register"
|
|
bitfld.long 0x00 11. " ENA[11] ,Enable of pin PIO2_11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENA[10] ,Enable of pin PIO2_10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENA[9] ,Enable of pin PIO2_9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENA[8] ,Enable of pin PIO2_8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENA[7] ,Enable of pin PIO2_7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA[6] ,Enable of pin PIO2_6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA[5] ,Enable of pin PIO2_5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENA[4] ,Enable of pin PIO2_4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA[3] ,Enable of pin PIO2_3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA[2] ,Enable of pin PIO2_2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA[1] ,Enable of pin PIO2_1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENA[0] ,Enable of pin PIO2_0" "Disabled,Enabled"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree "PINT (Pin interrupt and pattern match)"
|
|
base ad:0x400A4000
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ISEL,Pin Interrupt Mode Register"
|
|
bitfld.long 0x00 7. " PMODE[7] ,Interrupt mode for pin 7" "Edge,Level"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt mode for pin 6" "Edge,Level"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt mode for pin 5" "Edge,Level"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt mode for pin 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Interrupt mode for pin 3" "Edge,Level"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt mode for pin 2" "Edge,Level"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt mode for pin 1" "Edge,Level"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt mode for pin 0" "Edge,Level"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IENR_SET/CLR,Pin Interrupt Level Or Rising Edge Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENRL[7] ,Interrupt for pin 7 enable level/rising" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt for pin 6 enable level/rising" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt for pin 5 enable level/rising" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt for pin 4 enable level/rising" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt for pin 3 enable level/rising" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt for pin 2 enable level/rising" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt for pin 1 enable level/rising" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt for pin 0 enable level/rising" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IENF_SET/CLR,Pin Interrupt Active Level Or Falling Edge Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENAF[7] ,Interrupt for pin 7 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt for pin 6 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt for pin 5 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt for pin 4 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt for pin 3 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt for pin 2 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt for pin 1 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt for pin 0 enable falling/level" "Disabled/LOW,Enabled/HIGH"
|
|
group.long 0x1C++0x17
|
|
line.long 0x00 "RISE,Pin Interrupt Rising Edge Register"
|
|
eventfld.long 0x00 7. " RDET[7] ,Rising edge detect for pin 7" "No effect,Cleared"
|
|
eventfld.long 0x00 6. " [6] ,Rising edge detect for pin 6" "No effect,Cleared"
|
|
eventfld.long 0x00 5. " [5] ,Rising edge detect for pin 5" "No effect,Cleared"
|
|
eventfld.long 0x00 4. " [4] ,Rising edge detect for pin 4" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Rising edge detect for pin 3" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " [2] ,Rising edge detect for pin 2" "No effect,Cleared"
|
|
eventfld.long 0x00 1. " [1] ,Rising edge detect for pin 1" "No effect,Cleared"
|
|
eventfld.long 0x00 0. " [0] ,Rising edge detect for pin 0" "No effect,Cleared"
|
|
line.long 0x04 "FALL,Pin Interrupt Falling Edge Register"
|
|
eventfld.long 0x04 7. " FDET[7] ,Falling edge detect for pin 7" "No effect,Cleared"
|
|
eventfld.long 0x04 6. " [6] ,Falling edge detect for pin 6" "No effect,Cleared"
|
|
eventfld.long 0x04 5. " [5] ,Falling edge detect for pin 5" "No effect,Cleared"
|
|
eventfld.long 0x04 4. " [4] ,Falling edge detect for pin 4" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " [3] ,Falling edge detect for pin 3" "No effect,Cleared"
|
|
eventfld.long 0x04 2. " [2] ,Falling edge detect for pin 2" "No effect,Cleared"
|
|
eventfld.long 0x04 1. " [1] ,Falling edge detect for pin 1" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " [0] ,Falling edge detect for pin 0" "No effect,Cleared"
|
|
line.long 0x08 "IST,Pin Interrupt Status Register"
|
|
eventfld.long 0x08 7. " PSTAT[7] ,Pin interrupt status for pin 7" "No effect,Cleared"
|
|
eventfld.long 0x08 6. " [6] ,Pin interrupt status for pin 6" "No effect,Cleared"
|
|
eventfld.long 0x08 5. " [5] ,Pin interrupt status for pin 5" "No effect,Cleared"
|
|
eventfld.long 0x08 4. " [4] ,Pin interrupt status for pin 4" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,Pin interrupt status for pin 3" "No effect,Cleared"
|
|
eventfld.long 0x08 2. " [2] ,Pin interrupt status for pin 2" "No effect,Cleared"
|
|
eventfld.long 0x08 1. " [1] ,Pin interrupt status for pin 1" "No effect,Cleared"
|
|
eventfld.long 0x08 0. " [0] ,Pin interrupt status for pin 0" "No effect,Cleared"
|
|
newline
|
|
sif !cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PMCTRL,Pattern Match Interrupt Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PMAT ,This field displays the current state of pattern matches"
|
|
bitfld.long 0x00 1. " ENA_RXEV ,Enables the RXEV output to the ARM cpu and/or to a GPIO output under conditions" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEL_PMATCH ,Specifies 8 pin interrupts function" "Pin,Pattern"
|
|
newline
|
|
line.long 0x04 "PMSRC,Pattern Match Interrupt Bit-Slice Source Register"
|
|
bitfld.long 0x04 29.--31. " SRC[7] ,Selects the input source for bit slice 7" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
bitfld.long 0x04 26.--28. " [6] ,Selects the input source for bit slice 6" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
bitfld.long 0x04 23.--25. " [5] ,Selects the input source for bit slice 5" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
bitfld.long 0x04 20.--22. " [4] ,Selects the input source for bit slice 4" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " [3] ,Selects the input source for bit slice 3" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
bitfld.long 0x04 14.--16. " [2] ,Selects the input source for bit slice 2" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
bitfld.long 0x04 11.--13. " [1] ,Selects the input source for bit slice 1" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
bitfld.long 0x04 8.--10. " [0] ,Selects the input source for bit slice 0" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7"
|
|
line.long 0x08 "PMCFG,Pattern Match Interrupt Bit Slice Configuration Register"
|
|
bitfld.long 0x08 29.--31. " CFG[7] ,Specifies the match contribution condition for bit slice 7" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
bitfld.long 0x08 26.--28. " [6] ,Specifies the match contribution condition for bit slice 6" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
bitfld.long 0x08 23.--25. " [5] ,Specifies the match contribution condition for bit slice 5" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
bitfld.long 0x08 20.--22. " [4] ,Specifies the match contribution condition for bit slice 4" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " [3] ,Specifies the match contribution condition for bit slice 3" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
bitfld.long 0x08 14.--16. " [2] ,Specifies the match contribution condition for bit slice 2" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
bitfld.long 0x08 11.--13. " [1] ,Specifies the match contribution condition for bit slice 1" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
bitfld.long 0x08 8.--10. " [0] ,Specifies the match contribution condition for bit slice 0" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PROD_ENDPTS[6] ,Determines whether slice 6 is an endpoint" "Not endpoint,Endpoint"
|
|
bitfld.long 0x08 5. " [5] ,Determines whether slice 5 is an endpoint" "Not endpoint,Endpoint"
|
|
bitfld.long 0x08 4. " [4] ,Determines whether slice 4 is an endpoint" "Not endpoint,Endpoint"
|
|
bitfld.long 0x08 3. " [3] ,Determines whether slice 3 is an endpoint" "Not endpoint,Endpoint"
|
|
textline " "
|
|
bitfld.long 0x08 2. " [2] ,Determines whether slice 2 is an endpoint" "Not endpoint,Endpoint"
|
|
bitfld.long 0x08 1. " [1] ,Determines whether slice 1 is an endpoint" "Not endpoint,Endpoint"
|
|
bitfld.long 0x08 0. " [0] ,Determines whether slice 0 is an endpoint" "Not endpoint,Endpoint"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA controller"
|
|
base ad:0x1C004000
|
|
width 12.
|
|
group.long 0x00++0x03 "Global control and status registers"
|
|
line.long 0x00 "CTRL,DMA control"
|
|
bitfld.long 0x00 0. " ENABLE ,DMA controller master enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt status"
|
|
bitfld.long 0x00 2. " ACTIVEERRINT ,Summarizes whether any error interrupts are pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " ACTIVEINT ,Summarizes whether any enabled interrupts are pending" "Not pending,Pending"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table"
|
|
hexmask.long.tbyte 0x00 9.--31. 0x02 " OFFSET ,Address bits 31:9 of the beginning of the DMA descriptor table"
|
|
group.long 0x20++0x03 "Shared registers"
|
|
line.long 0x00 "ENABLESET0,Channel Enable read and Set for all DMA channels"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " ENA[17]_set/clr ,Enable for DMA channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " ENA[16]_set/clr ,Enable for DMA channel 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " ENA[15]_set/clr ,Enable for DMA channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " ENA[14]_set/clr ,Enable for DMA channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " ENA[13]_set/clr ,Enable for DMA channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " ENA[12]_set/clr ,Enable for DMA channel 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " ENA[11]_set/clr ,Enable for DMA channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " ENA[10]_set/clr ,Enable for DMA channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ENA[9]_set/clr ,Enable for DMA channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " ENA[8]_set/clr ,Enable for DMA channel 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " ENA[7]_set/clr ,Enable for DMA channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " ENA[6]_set/clr ,Enable for DMA channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " ENA[5]_set/clr ,Enable for DMA channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " ENA[4]_set/clr ,Enable for DMA channel 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " ENA[3]_set/clr ,Enable for DMA channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " ENA[2]_set/clr ,Enable for DMA channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " ENA[1]_set/clr ,Enable for DMA channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " ENA[0]_set/clr ,Enable for DMA channel 0" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels"
|
|
bitfld.long 0x00 17. " ACT[17] ,Active flag for DMA channel 17" "Inactive,Active"
|
|
bitfld.long 0x00 16. " ACT[16] ,Active flag for DMA channel 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " ACT[15] ,Active flag for DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " ACT[14] ,Active flag for DMA channel 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACT[13] ,Active flag for DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " ACT[12] ,Active flag for DMA channel 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " ACT[11] ,Active flag for DMA channel 11" "Inactive,Active"
|
|
bitfld.long 0x00 10. " ACT[10] ,Active flag for DMA channel 10" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACT[9] ,Active flag for DMA channel 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " ACT[8] ,Active flag for DMA channel 8" "Inactive,Active"
|
|
bitfld.long 0x00 7. " ACT[7] ,Active flag for DMA channel 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " ACT[6] ,Active flag for DMA channel 6" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ACT[5] ,Active flag for DMA channel 5" "Inactive,Active"
|
|
bitfld.long 0x00 4. " ACT[4] ,Active flag for DMA channel 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " ACT[3] ,Active flag for DMA channel 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " ACT[2] ,Active flag for DMA channel 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACT[1] ,Active flag for DMA channel 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " ACT[0] ,Active flag for DMA channel 0" "Inactive,Active"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "BUSY0,Channel Busy status for all DMA channels"
|
|
bitfld.long 0x00 17. " BSY[17] ,Busy flag for DMA channel 17" "Idle,Busy"
|
|
bitfld.long 0x00 16. " BSY[16] ,Busy flag for DMA channel 16" "Idle,Busy"
|
|
bitfld.long 0x00 15. " BSY[15] ,Busy flag for DMA channel 15" "Idle,Busy"
|
|
bitfld.long 0x00 14. " BSY[14] ,Busy flag for DMA channel 14" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BSY[13] ,Busy flag for DMA channel 13" "Idle,Busy"
|
|
bitfld.long 0x00 12. " BSY[12] ,Busy flag for DMA channel 12" "Idle,Busy"
|
|
bitfld.long 0x00 11. " BSY[11] ,Busy flag for DMA channel 11" "Idle,Busy"
|
|
bitfld.long 0x00 10. " BSY[10] ,Busy flag for DMA channel 10" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BSY[9] ,Busy flag for DMA channel 9" "Idle,Busy"
|
|
bitfld.long 0x00 8. " BSY[8] ,Busy flag for DMA channel 8" "Idle,Busy"
|
|
bitfld.long 0x00 7. " BSY[7] ,Busy flag for DMA channel 7" "Idle,Busy"
|
|
bitfld.long 0x00 6. " BSY[6] ,Busy flag for DMA channel 6" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BSY[5] ,Busy flag for DMA channel 5" "Idle,Busy"
|
|
bitfld.long 0x00 4. " BSY[4] ,Busy flag for DMA channel 4" "Idle,Busy"
|
|
bitfld.long 0x00 3. " BSY[3] ,Busy flag for DMA channel 3" "Idle,Busy"
|
|
bitfld.long 0x00 2. " BSY[2] ,Busy flag for DMA channel 2" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BSY[1] ,Busy flag for DMA channel 1" "Idle,Busy"
|
|
bitfld.long 0x00 0. " BSY[0] ,Busy flag for DMA channel 0" "Idle,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels"
|
|
bitfld.long 0x00 17. " ERR[17] ,Error Interrupt flag for DMA channel 17" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR[16] ,Error Interrupt flag for DMA channel 16" "No error,Error"
|
|
bitfld.long 0x00 15. " ERR[15] ,Error Interrupt flag for DMA channel 15" "No error,Error"
|
|
bitfld.long 0x00 14. " ERR[14] ,Error Interrupt flag for DMA channel 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERR[13] ,Error Interrupt flag for DMA channel 13" "No error,Error"
|
|
bitfld.long 0x00 12. " ERR[12] ,Error Interrupt flag for DMA channel 12" "No error,Error"
|
|
bitfld.long 0x00 11. " ERR[11] ,Error Interrupt flag for DMA channel 11" "No error,Error"
|
|
bitfld.long 0x00 10. " ERR[10] ,Error Interrupt flag for DMA channel 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERR[9] ,Error Interrupt flag for DMA channel 9" "No error,Error"
|
|
bitfld.long 0x00 8. " ERR[8] ,Error Interrupt flag for DMA channel 8" "No error,Error"
|
|
bitfld.long 0x00 7. " ERR[7] ,Error Interrupt flag for DMA channel 7" "No error,Error"
|
|
bitfld.long 0x00 6. " ERR[6] ,Error Interrupt flag for DMA channel 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERR[5] ,Error Interrupt flag for DMA channel 5" "No error,Error"
|
|
bitfld.long 0x00 4. " ERR[4] ,Error Interrupt flag for DMA channel 4" "No error,Error"
|
|
bitfld.long 0x00 3. " ERR[3] ,Error Interrupt flag for DMA channel 3" "No error,Error"
|
|
bitfld.long 0x00 2. " ERR[2] ,Error Interrupt flag for DMA channel 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERR[1] ,Error Interrupt flag for DMA channel 1" "No error,Error"
|
|
bitfld.long 0x00 0. " ERR[0] ,Error Interrupt flag for DMA channel 0" "No error,Error"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " INTEN[17]_set/clr ,Interrupt Enable for DMA channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " INTEN[16]_set/clr ,Interrupt Enable for DMA channel 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " INTEN[15]_set/clr ,Interrupt Enable for DMA channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " INTEN[14]_set/clr ,Interrupt Enable for DMA channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " INTEN[13]_set/clr ,Interrupt Enable for DMA channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " INTEN[12]_set/clr ,Interrupt Enable for DMA channel 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " INTEN[11]_set/clr ,Interrupt Enable for DMA channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " INTEN[10]_set/clr ,Interrupt Enable for DMA channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " INTEN[9]_set/clr ,Interrupt Enable for DMA channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " INTEN[8]_set/clr ,Interrupt Enable for DMA channel 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " INTEN[7]_set/clr ,Interrupt Enable for DMA channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " INTEN[6]_set/clr ,Interrupt Enable for DMA channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " INTEN[5]_set/clr ,Interrupt Enable for DMA channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " INTEN[4]_set/clr ,Interrupt Enable for DMA channel 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " INTEN[3]_set/clr ,Interrupt Enable for DMA channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " INTEN[2]_set/clr ,Interrupt Enable for DMA channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " INTEN[1]_set/clr ,Interrupt Enable for DMA channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " INTEN[0]_set/clr ,Interrupt Enable for DMA channel 0" "Disabled,Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "INTA0,Interrupt A status for all DMA channels"
|
|
bitfld.long 0x00 17. " IA[17] ,Interrupt A status for DMA channel 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IA[16] ,Interrupt A status for DMA channel 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " IA[15] ,Interrupt A status for DMA channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IA[14] ,Interrupt A status for DMA channel 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IA[13] ,Interrupt A status for DMA channel 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IA[12] ,Interrupt A status for DMA channel 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " IA[11] ,Interrupt A status for DMA channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IA[10] ,Interrupt A status for DMA channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IA[9] ,Interrupt A status for DMA channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IA[8] ,Interrupt A status for DMA channel 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " IA[7] ,Interrupt A status for DMA channel 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IA[6] ,Interrupt A status for DMA channel 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IA[5] ,Interrupt A status for DMA channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IA[4] ,Interrupt A status for DMA channel 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " IA[3] ,Interrupt A status for DMA channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IA[2] ,Interrupt A status for DMA channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IA[1] ,Interrupt A status for DMA channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IA[0] ,Interrupt A status for DMA channel 0" "No interrupt,Interrupt"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "INTB0,Interrupt B status for all DMA channels"
|
|
bitfld.long 0x00 17. " IB[17] ,Interrupt B status for DMA channel 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IB[16] ,Interrupt B status for DMA channel 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " IB[15] ,Interrupt B status for DMA channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IB[14] ,Interrupt B status for DMA channel 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IB[13] ,Interrupt B status for DMA channel 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IB[12] ,Interrupt B status for DMA channel 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " IB[11] ,Interrupt B status for DMA channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IB[10] ,Interrupt B status for DMA channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IB[9] ,Interrupt B status for DMA channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IB[8] ,Interrupt B status for DMA channel 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " IB[7] ,Interrupt B status for DMA channel 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IB[6] ,Interrupt B status for DMA channel 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IB[5] ,Interrupt B status for DMA channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IB[4] ,Interrupt B status for DMA channel 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " IB[3] ,Interrupt B status for DMA channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IB[2] ,Interrupt B status for DMA channel 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IB[1] ,Interrupt B status for DMA channel 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IB[0] ,Interrupt B status for DMA channel 0" "No interrupt,Interrupt"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "SETVALID0,Set Valid/Pending control bits for all DMA channels"
|
|
bitfld.long 0x00 17. " SV[17] ,SETVALID control for DMA channel 17" "No effect,Set"
|
|
bitfld.long 0x00 16. " SV[16] ,SETVALID control for DMA channel 16" "No effect,Set"
|
|
bitfld.long 0x00 15. " SV[15] ,SETVALID control for DMA channel 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SV[14] ,SETVALID control for DMA channel 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SV[13] ,SETVALID control for DMA channel 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SV[12] ,SETVALID control for DMA channel 12" "No effect,Set"
|
|
bitfld.long 0x00 11. " SV[11] ,SETVALID control for DMA channel 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " SV[10] ,SETVALID control for DMA channel 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SV[9] ,SETVALID control for DMA channel 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " SV[8] ,SETVALID control for DMA channel 8" "No effect,Set"
|
|
bitfld.long 0x00 7. " SV[7] ,SETVALID control for DMA channel 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " SV[6] ,SETVALID control for DMA channel 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SV[5] ,SETVALID control for DMA channel 5" "No effect,Set"
|
|
bitfld.long 0x00 4. " SV[4] ,SETVALID control for DMA channel 4" "No effect,Set"
|
|
bitfld.long 0x00 3. " SV[3] ,SETVALID control for DMA channel 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " SV[2] ,SETVALID control for DMA channel 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SV[1] ,SETVALID control for DMA channel 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " SV[0] ,SETVALID control for DMA channel 0" "No effect,Set"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels"
|
|
bitfld.long 0x00 17. " TRIG[17] ,Set Trigger control bit for DMA channel 17" "No effect,Set"
|
|
bitfld.long 0x00 16. " TRIG[16] ,Set Trigger control bit for DMA channel 16" "No effect,Set"
|
|
bitfld.long 0x00 15. " TRIG[15] ,Set Trigger control bit for DMA channel 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " TRIG[14] ,Set Trigger control bit for DMA channel 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TRIG[13] ,Set Trigger control bit for DMA channel 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " TRIG[12] ,Set Trigger control bit for DMA channel 12" "No effect,Set"
|
|
bitfld.long 0x00 11. " TRIG[11] ,Set Trigger control bit for DMA channel 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " TRIG[10] ,Set Trigger control bit for DMA channel 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRIG[9] ,Set Trigger control bit for DMA channel 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " TRIG[8] ,Set Trigger control bit for DMA channel 8" "No effect,Set"
|
|
bitfld.long 0x00 7. " TRIG[7] ,Set Trigger control bit for DMA channel 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " TRIG[6] ,Set Trigger control bit for DMA channel 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TRIG[5] ,Set Trigger control bit for DMA channel 5" "No effect,Set"
|
|
bitfld.long 0x00 4. " TRIG[4] ,Set Trigger control bit for DMA channel 4" "No effect,Set"
|
|
bitfld.long 0x00 3. " TRIG[3] ,Set Trigger control bit for DMA channel 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " TRIG[2] ,Set Trigger control bit for DMA channel 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRIG[1] ,Set Trigger control bit for DMA channel 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " TRIG[0] ,Set Trigger control bit for DMA channel 0" "No effect,Set"
|
|
wgroup.long 0x78++0x03
|
|
line.long 0x00 "SETABORT0,Channel Abort control for all DMA channels"
|
|
bitfld.long 0x00 17. " ABORTCTRL[17] ,Abort control for DMA channel 17" "No effect,Abort"
|
|
bitfld.long 0x00 16. " ABORTCTRL[16] ,Abort control for DMA channel 16" "No effect,Abort"
|
|
bitfld.long 0x00 15. " ABORTCTRL[15] ,Abort control for DMA channel 15" "No effect,Abort"
|
|
bitfld.long 0x00 14. " ABORTCTRL[14] ,Abort control for DMA channel 14" "No effect,Abort"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ABORTCTRL[13] ,Abort control for DMA channel 13" "No effect,Abort"
|
|
bitfld.long 0x00 12. " ABORTCTRL[12] ,Abort control for DMA channel 12" "No effect,Abort"
|
|
bitfld.long 0x00 11. " ABORTCTRL[11] ,Abort control for DMA channel 11" "No effect,Abort"
|
|
bitfld.long 0x00 10. " ABORTCTRL[10] ,Abort control for DMA channel 10" "No effect,Abort"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ABORTCTRL[9] ,Abort control for DMA channel 9" "No effect,Abort"
|
|
bitfld.long 0x00 8. " ABORTCTRL[8] ,Abort control for DMA channel 8" "No effect,Abort"
|
|
bitfld.long 0x00 7. " ABORTCTRL[7] ,Abort control for DMA channel 7" "No effect,Abort"
|
|
bitfld.long 0x00 6. " ABORTCTRL[6] ,Abort control for DMA channel 6" "No effect,Abort"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ABORTCTRL[5] ,Abort control for DMA channel 5" "No effect,Abort"
|
|
bitfld.long 0x00 4. " ABORTCTRL[4] ,Abort control for DMA channel 4" "No effect,Abort"
|
|
bitfld.long 0x00 3. " ABORTCTRL[3] ,Abort control for DMA channel 3" "No effect,Abort"
|
|
bitfld.long 0x00 2. " ABORTCTRL[2] ,Abort control for DMA channel 2" "No effect,Abort"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ABORTCTRL[1] ,Abort control for DMA channel 1" "No effect,Abort"
|
|
bitfld.long 0x00 0. " ABORTCTRL[0] ,Abort control for DMA channel 0" "No effect,Abort"
|
|
tree "Channels registers"
|
|
group.long 0x400++0x03 "Channel 0 registers"
|
|
line.long 0x00 "CFG0,Configuration register for DMA channel 0"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x400+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT0,Control and status register for DMA channel 0"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x400+0x8)++0x03
|
|
line.long 0x00 "XFERCFG0,Transfer configuration register for DMA channel 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x410++0x03 "Channel 1 registers"
|
|
line.long 0x00 "CFG1,Configuration register for DMA channel 1"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x410+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT1,Control and status register for DMA channel 1"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x410+0x8)++0x03
|
|
line.long 0x00 "XFERCFG1,Transfer configuration register for DMA channel 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x420++0x03 "Channel 2 registers"
|
|
line.long 0x00 "CFG2,Configuration register for DMA channel 2"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x420+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT2,Control and status register for DMA channel 2"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x420+0x8)++0x03
|
|
line.long 0x00 "XFERCFG2,Transfer configuration register for DMA channel 2"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x430++0x03 "Channel 3 registers"
|
|
line.long 0x00 "CFG3,Configuration register for DMA channel 3"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x430+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT3,Control and status register for DMA channel 3"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x430+0x8)++0x03
|
|
line.long 0x00 "XFERCFG3,Transfer configuration register for DMA channel 3"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x440++0x03 "Channel 4 registers"
|
|
line.long 0x00 "CFG4,Configuration register for DMA channel 4"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x440+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT4,Control and status register for DMA channel 4"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x440+0x8)++0x03
|
|
line.long 0x00 "XFERCFG4,Transfer configuration register for DMA channel 4"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x450++0x03 "Channel 5 registers"
|
|
line.long 0x00 "CFG5,Configuration register for DMA channel 5"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x450+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT5,Control and status register for DMA channel 5"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x450+0x8)++0x03
|
|
line.long 0x00 "XFERCFG5,Transfer configuration register for DMA channel 5"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x460++0x03 "Channel 6 registers"
|
|
line.long 0x00 "CFG6,Configuration register for DMA channel 6"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x460+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT6,Control and status register for DMA channel 6"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x460+0x8)++0x03
|
|
line.long 0x00 "XFERCFG6,Transfer configuration register for DMA channel 6"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x470++0x03 "Channel 7 registers"
|
|
line.long 0x00 "CFG7,Configuration register for DMA channel 7"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x470+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT7,Control and status register for DMA channel 7"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x470+0x8)++0x03
|
|
line.long 0x00 "XFERCFG7,Transfer configuration register for DMA channel 7"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x480++0x03 "Channel 8 registers"
|
|
line.long 0x00 "CFG8,Configuration register for DMA channel 8"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x480+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT8,Control and status register for DMA channel 8"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x480+0x8)++0x03
|
|
line.long 0x00 "XFERCFG8,Transfer configuration register for DMA channel 8"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x490++0x03 "Channel 9 registers"
|
|
line.long 0x00 "CFG9,Configuration register for DMA channel 9"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x490+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT9,Control and status register for DMA channel 9"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x490+0x8)++0x03
|
|
line.long 0x00 "XFERCFG9,Transfer configuration register for DMA channel 9"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x4A0++0x03 "Channel 10 registers"
|
|
line.long 0x00 "CFG10,Configuration register for DMA channel 10"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x4A0+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT10,Control and status register for DMA channel 10"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x4A0+0x8)++0x03
|
|
line.long 0x00 "XFERCFG10,Transfer configuration register for DMA channel 10"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x4B0++0x03 "Channel 11 registers"
|
|
line.long 0x00 "CFG11,Configuration register for DMA channel 11"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x4B0+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT11,Control and status register for DMA channel 11"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x4B0+0x8)++0x03
|
|
line.long 0x00 "XFERCFG11,Transfer configuration register for DMA channel 11"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x4C0++0x03 "Channel 12 registers"
|
|
line.long 0x00 "CFG12,Configuration register for DMA channel 12"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x4C0+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT12,Control and status register for DMA channel 12"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x4C0+0x8)++0x03
|
|
line.long 0x00 "XFERCFG12,Transfer configuration register for DMA channel 12"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x4D0++0x03 "Channel 13 registers"
|
|
line.long 0x00 "CFG13,Configuration register for DMA channel 13"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x4D0+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT13,Control and status register for DMA channel 13"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x4D0+0x8)++0x03
|
|
line.long 0x00 "XFERCFG13,Transfer configuration register for DMA channel 13"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x4E0++0x03 "Channel 14 registers"
|
|
line.long 0x00 "CFG14,Configuration register for DMA channel 14"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x4E0+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT14,Control and status register for DMA channel 14"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x4E0+0x8)++0x03
|
|
line.long 0x00 "XFERCFG14,Transfer configuration register for DMA channel 14"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x4F0++0x03 "Channel 15 registers"
|
|
line.long 0x00 "CFG15,Configuration register for DMA channel 15"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x4F0+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT15,Control and status register for DMA channel 15"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x4F0+0x8)++0x03
|
|
line.long 0x00 "XFERCFG15,Transfer configuration register for DMA channel 15"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x500++0x03 "Channel 16 registers"
|
|
line.long 0x00 "CFG16,Configuration register for DMA channel 16"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x500+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT16,Control and status register for DMA channel 16"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x500+0x8)++0x03
|
|
line.long 0x00 "XFERCFG16,Transfer configuration register for DMA channel 16"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
group.long 0x510++0x03 "Channel 17 registers"
|
|
line.long 0x00 "CFG17,Configuration register for DMA channel 17"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source Burst Wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst Power" "1,2,4,8,16,32,64,128,256,512,1024,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRIGBURST ,Trigger Burst Transfer" "Single,Burst"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Trigger Type" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Trigger Polarity" "Low/Falling,High/Rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware Triggering Enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request Enable" "Disabled,Enabled"
|
|
rgroup.long (0x510+0x4)++0x03
|
|
line.long 0x00 "CTLSTAT17,Control and status register for DMA channel 17"
|
|
bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid"
|
|
group.long (0x510+0x8)++0x03
|
|
line.long 0x00 "XFERCFG17,Transfer configuration register for DMA channel 17"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1 x width,2 x width,4 x width"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " SETINTB ,Set Interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set Interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear Trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration Valid flag" "Invalid,Valid"
|
|
tree.end
|
|
width 0x0b
|
|
tree.end
|
|
tree "SCTIPU (SCT Input Processing Unit)"
|
|
base ad:0x400B8000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,SCTIPU sample control register"
|
|
bitfld.long 0x00 15. " LATCHEN3 ,Enable latch for output channel 3" "Transparent,Latched"
|
|
bitfld.long 0x00 14. " LATCHEN2 ,Enable latch for output channel 2" "Transparent,Latched"
|
|
bitfld.long 0x00 13. " LATCHEN1 ,Enable latch for output channel 1" "Transparent,Latched"
|
|
bitfld.long 0x00 12. " LATCHEN0 ,Enable latch for output channel 0" "Transparent,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SAMPLE_EN3SEL ,Select the sample enable input as the latch/sample-enable control for the Sample_Output(3) latch" "Enable_A,Enable_B,Enable_C,Enable_D"
|
|
bitfld.long 0x00 8.--9. " SAMPLE_EN2SEL ,Select the sample enable input as the latch/sample-enable control for the Sample_Output(2) latch" "Enable_A,Enable_B,Enable_C,Enable_D"
|
|
bitfld.long 0x00 6.--7. " SAMPLE_EN1SEL ,Select the sample enable input as the latch/sample-enable control for the Sample_Output(1) latch" "Enable_A,Enable_B,Enable_C,Enable_D"
|
|
bitfld.long 0x00 4.--5. " SAMPLE_EN0SEL ,Select the sample enable input as the latch/sample-enable control for the Sample_Output(0) latch" "Enable_A,Enable_B,Enable_C,Enable_D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IN3SEL ,Select SCTIPU input source for output channel 3" "SAMPLE_IN_A3,SAMPLE_IN_B3"
|
|
bitfld.long 0x00 2. " IN2SEL ,Select SCTIPU input source for output channel 2" "SAMPLE_IN_A2,SAMPLE_IN_B2"
|
|
bitfld.long 0x00 1. " IN1SEL ,Select SCTIPU input source for output channel 1" "SAMPLE_IN_A1,SAMPLE_IN_B1"
|
|
bitfld.long 0x00 0. " IN0SEL ,Select SCTIPU input source for output channel 0" "SAMPLE_IN_A0,SAMPLE_IN_B0"
|
|
textline ""
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "ABORT_ENABLE0,SCTIPU abort enable 0 register"
|
|
bitfld.long 0x00 8. " ENA8 ,Enable abort source ACMP3_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA7 ,Enable abort source ACMP2_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA6 ,Enable abort source ACMP1_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA5 ,Enable abort source ACMP0_O output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA4 ,Enable abort source ADC1_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA3 ,Enable abort source ADC0_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA2 ,Enable abort source SCT0_OUT9" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA1 ,Enable abort source SCT_ABORT1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA0 ,Enable abort source SCT_ABORT0" "Disabled,Enabled"
|
|
line.long 0x04 "ABORT_SOURCE0,SCTIPU abort source 0 register"
|
|
bitfld.long 0x04 8. " ACT8 ,Activate source ACMP3_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 7. " ACT7 ,Activate source ACMP2_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 6. " ACT6 ,Activate source ACMP1_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 5. " ACT5 ,Activate source ACMP0_O output" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACT4 ,Activate source ADC1_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 3. " ACT3 ,Activate source ADC0_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 2. " ACT2 ,Activate source SCT0_OUT9" "Not activated,Activated"
|
|
bitfld.long 0x04 1. " ACT1 ,Activate source SCT_ABORT1" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACT0 ,Activate source SCT_ABORT0" "Not activated,Activated"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "ABORT_ENABLE1,SCTIPU abort enable 1 register"
|
|
bitfld.long 0x00 8. " ENA8 ,Enable abort source ACMP3_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA7 ,Enable abort source ACMP2_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA6 ,Enable abort source ACMP1_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA5 ,Enable abort source ACMP0_O output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA4 ,Enable abort source ADC1_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA3 ,Enable abort source ADC0_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA2 ,Enable abort source SCT0_OUT9" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA1 ,Enable abort source SCT_ABORT1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA0 ,Enable abort source SCT_ABORT0" "Disabled,Enabled"
|
|
line.long 0x04 "ABORT_SOURCE1,SCTIPU abort source 1 register"
|
|
bitfld.long 0x04 8. " ACT8 ,Activate source ACMP3_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 7. " ACT7 ,Activate source ACMP2_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 6. " ACT6 ,Activate source ACMP1_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 5. " ACT5 ,Activate source ACMP0_O output" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACT4 ,Activate source ADC1_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 3. " ACT3 ,Activate source ADC0_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 2. " ACT2 ,Activate source SCT0_OUT9" "Not activated,Activated"
|
|
bitfld.long 0x04 1. " ACT1 ,Activate source SCT_ABORT1" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACT0 ,Activate source SCT_ABORT0" "Not activated,Activated"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "ABORT_ENABLE2,SCTIPU abort enable 2 register"
|
|
bitfld.long 0x00 8. " ENA8 ,Enable abort source ACMP3_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA7 ,Enable abort source ACMP2_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA6 ,Enable abort source ACMP1_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA5 ,Enable abort source ACMP0_O output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA4 ,Enable abort source ADC1_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA3 ,Enable abort source ADC0_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA2 ,Enable abort source SCT0_OUT9" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA1 ,Enable abort source SCT_ABORT1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA0 ,Enable abort source SCT_ABORT0" "Disabled,Enabled"
|
|
line.long 0x04 "ABORT_SOURCE2,SCTIPU abort source 2 register"
|
|
bitfld.long 0x04 8. " ACT8 ,Activate source ACMP3_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 7. " ACT7 ,Activate source ACMP2_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 6. " ACT6 ,Activate source ACMP1_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 5. " ACT5 ,Activate source ACMP0_O output" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACT4 ,Activate source ADC1_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 3. " ACT3 ,Activate source ADC0_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 2. " ACT2 ,Activate source SCT0_OUT9" "Not activated,Activated"
|
|
bitfld.long 0x04 1. " ACT1 ,Activate source SCT_ABORT1" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACT0 ,Activate source SCT_ABORT0" "Not activated,Activated"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "ABORT_ENABLE3,SCTIPU abort enable 3 register"
|
|
bitfld.long 0x00 8. " ENA8 ,Enable abort source ACMP3_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENA7 ,Enable abort source ACMP2_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENA6 ,Enable abort source ACMP1_O output" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENA5 ,Enable abort source ACMP0_O output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENA4 ,Enable abort source ADC1_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENA3 ,Enable abort source ADC0_THCMP_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENA2 ,Enable abort source SCT0_OUT9" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENA1 ,Enable abort source SCT_ABORT1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENA0 ,Enable abort source SCT_ABORT0" "Disabled,Enabled"
|
|
line.long 0x04 "ABORT_SOURCE3,SCTIPU abort source 3 register"
|
|
bitfld.long 0x04 8. " ACT8 ,Activate source ACMP3_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 7. " ACT7 ,Activate source ACMP2_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 6. " ACT6 ,Activate source ACMP1_O output" "Not activated,Activated"
|
|
bitfld.long 0x04 5. " ACT5 ,Activate source ACMP0_O output" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACT4 ,Activate source ADC1_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 3. " ACT3 ,Activate source ADC0_THCMP_IRQ" "Not activated,Activated"
|
|
bitfld.long 0x04 2. " ACT2 ,Activate source SCT0_OUT9" "Not activated,Activated"
|
|
bitfld.long 0x04 1. " ACT1 ,Activate source SCT_ABORT1" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACT0 ,Activate source SCT_ABORT0" "Not activated,Activated"
|
|
width 0x0b
|
|
tree.end
|
|
tree.open "Large SCTimers"
|
|
tree "SCTimer 0"
|
|
base ad:0x1C018000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,SCT configuration register"
|
|
bitfld.long 0x00 18. " AUTOLIMIT_H ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " NORELOAD_H ,Prevent the higher match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
bitfld.long 0x00 7. " NORELOAD_L ,Prevent the lower match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input (0:7)" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,Rising 4,Falling 4,Rising 5,Falling 5,Rising 6,Falling 6,Rising 7,Falling 7"
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System,Prescaled system,SCT input,Prescaled SCT input"
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operate as unified 32-bit counter" "Not unified,Unified"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "CTRL,SCT control register"
|
|
hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock"
|
|
bitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down"
|
|
line.long 0x04 "LIMIT,SCT limit register"
|
|
bitfld.long 0x04 15. " LIMMSK[15] ,Event 15 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 14. " LIMMSK[14] ,Event 14 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 13. " LIMMSK[13] ,Event 13 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 12. " LIMMSK[12] ,Event 12 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LIMMSK[11] ,Event 11 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 10. " LIMMSK[10] ,Event 10 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 9. " LIMMSK[9] ,Event 9 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 8. " LIMMSK[8] ,Event 8 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LIMMSK[7] ,Event 7 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 6. " LIMMSK[6] ,Event 6 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 5. " LIMMSK[5] ,Event 5 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 4. " LIMMSK[4] ,Event 4 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LIMMSK[3] ,Event 3 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 2. " LIMMSK[2] ,Event 2 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 1. " LIMMSK[1] ,Event 1 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 0. " LIMMSK[0] ,Event 0 use as counter limit for unified counter" "Not used,Used"
|
|
line.long 0x08 "HALT,SCT halt condition register"
|
|
bitfld.long 0x08 15. " HALTMSK[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 14. " HALTMSK[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 13. " HALTMSK[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 12. " HALTMSK[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HALTMSK[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 10. " HALTMSK[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 9. " HALTMSK[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 8. " HALTMSK[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HALTMSK[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 6. " HALTMSK[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 5. " HALTMSK[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 4. " HALTMSK[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HALTMSK[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 2. " HALTMSK[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 1. " HALTMSK[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 0. " HALTMSK[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x0C "STOP,SCT stop condition register"
|
|
bitfld.long 0x0C 15. " STOPMSK[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 14. " STOPMSK[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 13. " STOPMSK[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 12. " STOPMSK[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " STOPMSK[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 10. " STOPMSK[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 9. " STOPMSK[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 8. " STOPMSK[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " STOPMSK[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 6. " STOPMSK[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 5. " STOPMSK[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 4. " STOPMSK[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " STOPMSK[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 2. " STOPMSK[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 1. " STOPMSK[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 0. " STOPMSK[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x10 "START,SCT start condition register"
|
|
bitfld.long 0x10 15. " STARTMSK[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 14. " STARTMSK[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 13. " STARTMSK[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 12. " STARTMSK[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 11. " STARTMSK[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 10. " STARTMSK[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 9. " STARTMSK[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 8. " STARTMSK[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 7. " STARTMSK[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 6. " STARTMSK[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 5. " STARTMSK[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 4. " STARTMSK[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 3. " STARTMSK[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 2. " STARTMSK[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 1. " STARTMSK[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 0. " STARTMSK[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
line.long 0x14 "DITHER,SCT dither condition register"
|
|
bitfld.long 0x14 15. " DITHMSK[15] ,Event 15 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 14. " DITHMSK[14] ,Event 14 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 13. " DITHMSK[13] ,Event 13 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 12. " DITHMSK[12] ,Event 12 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DITHMSK[11] ,Event 11 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 10. " DITHMSK[10] ,Event 10 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 9. " DITHMSK[9] ,Event 9 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 8. " DITHMSK[8] ,Event 8 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DITHMSK[7] ,Event 7 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 6. " DITHMSK[6] ,Event 6 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 5. " DITHMSK[5] ,Event 5 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 4. " DITHMSK[4] ,Event 4 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DITHMSK[3] ,Event 3 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 2. " DITHMSK[2] ,Event 2 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 1. " DITHMSK[1] ,Event 1 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 0. " DITHMSK[0] ,Event 0 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "COUNT,SCT counter register"
|
|
line.long 0x04 "STATE,SCT state register"
|
|
bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 23. " SIN7 ,Input 7 state" "Low,High"
|
|
bitfld.long 0x00 22. " SIN6 ,Input 6 state" "Low,High"
|
|
bitfld.long 0x00 21. " SIN5 ,Input 5 state" "Low,High"
|
|
bitfld.long 0x00 20. " SIN4 ,Input 4 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AIN7 ,Input 7 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 6. " AIN6 ,Input 6 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 5. " AIN5 ,Input 5 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 4. " AIN4 ,Input 4 state(Direct read)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT match/capture registers mode register"
|
|
bitfld.long 0x00 15. " REGMOD[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 14. " REGMOD[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 13. " REGMOD[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 12. " REGMOD[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REGMOD[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 10. " REGMOD[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 9. " REGMOD[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 8. " REGMOD[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REGMOD[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 6. " REGMOD[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 5. " REGMOD[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 4. " REGMOD[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REGMOD[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 2. " REGMOD[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 1. " REGMOD[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 0. " REGMOD[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
else
|
|
group.word 0x04++0x17
|
|
line.word 0x00 "CTRL_L,SCT control lower 16-bit register"
|
|
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock"
|
|
bitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down"
|
|
line.word 0x02 "CTRL_H,SCT control higher 16-bit register"
|
|
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock"
|
|
bitfld.word 0x02 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x02 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x02 2. " HALT_H ,H counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x02 1. " STOP_H ,H counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x02 0. " DOWN_H ,H counter counting down" "Counting up,Counting down"
|
|
line.word 0x04 "LIMIT_L,SCT limit higher 16-bit register"
|
|
bitfld.word 0x04 15. " LIMMSK_L[15] ,Event 15 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 14. " LIMMSK_L[14] ,Event 14 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 13. " LIMMSK_L[13] ,Event 13 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 12. " LIMMSK_L[12] ,Event 12 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 11. " LIMMSK_L[11] ,Event 11 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 10. " LIMMSK_L[10] ,Event 10 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 9. " LIMMSK_L[9] ,Event 9 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 8. " LIMMSK_L[8] ,Event 8 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 7. " LIMMSK_L[7] ,Event 7 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 6. " LIMMSK_L[6] ,Event 6 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 5. " LIMMSK_L[5] ,Event 5 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 4. " LIMMSK_L[4] ,Event 4 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 3. " LIMMSK_L[3] ,Event 3 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 2. " LIMMSK_L[2] ,Event 2 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 1. " LIMMSK_L[1] ,Event 1 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 0. " LIMMSK_L[0] ,Event 0 use as counter limit for L counter" "Not used,Used"
|
|
line.word 0x06 "LIMIT_H,SCT limit lower 16-bit register"
|
|
bitfld.word 0x06 15. " LIMMSK_H[15] ,Event 15 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 14. " LIMMSK_H[14] ,Event 14 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 13. " LIMMSK_H[13] ,Event 13 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 12. " LIMMSK_H[12] ,Event 12 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 11. " LIMMSK_H[11] ,Event 11 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 10. " LIMMSK_H[10] ,Event 10 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 9. " LIMMSK_H[9] ,Event 9 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 8. " LIMMSK_H[8] ,Event 8 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 7. " LIMMSK_H[7] ,Event 7 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 6. " LIMMSK_H[6] ,Event 6 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 5. " LIMMSK_H[5] ,Event 5 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 4. " LIMMSK_H[4] ,Event 4 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 3. " LIMMSK_H[3] ,Event 3 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 2. " LIMMSK_H[2] ,Event 2 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 1. " LIMMSK_H[1] ,Event 1 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 0. " LIMMSK_H[0] ,Event 0 use as counter limit for H counter" "Not used,Used"
|
|
line.word 0x08 "HALT_L,SCT halt condition lower 16-bit register"
|
|
bitfld.word 0x08 15. " HALTMSK_L[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 14. " HALTMSK_L[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 13. " HALTMSK_L[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 12. " HALTMSK_L[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 11. " HALTMSK_L[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 10. " HALTMSK_L[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 9. " HALTMSK_L[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 8. " HALTMSK_L[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 7. " HALTMSK_L[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 6. " HALTMSK_L[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 5. " HALTMSK_L[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 4. " HALTMSK_L[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 3. " HALTMSK_L[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 2. " HALTMSK_L[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 1. " HALTMSK_L[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 0. " HALTMSK_L[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0A "HALT_H,SCT halt condition higher 16-bit register"
|
|
bitfld.word 0x0A 15. " HALTMSK_H[15] ,Event 15 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 14. " HALTMSK_H[14] ,Event 14 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 13. " HALTMSK_H[13] ,Event 13 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 12. " HALTMSK_H[12] ,Event 12 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 11. " HALTMSK_H[11] ,Event 11 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 10. " HALTMSK_H[10] ,Event 10 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 9. " HALTMSK_H[9] ,Event 9 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 8. " HALTMSK_H[8] ,Event 8 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 7. " HALTMSK_H[7] ,Event 7 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 6. " HALTMSK_H[6] ,Event 6 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 5. " HALTMSK_H[5] ,Event 5 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 4. " HALTMSK_H[4] ,Event 4 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 3. " HALTMSK_H[3] ,Event 3 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 2. " HALTMSK_H[2] ,Event 2 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 1. " HALTMSK_H[1] ,Event 1 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 0. " HALTMSK_H[0] ,Event 0 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x0C "STOP_L,SCT stop condition lower 16-bit register"
|
|
bitfld.word 0x0C 15. " STOPMSK_L[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 14. " STOPMSK_L[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 13. " STOPMSK_L[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 12. " STOPMSK_L[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 11. " STOPMSK_L[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 10. " STOPMSK_L[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 9. " STOPMSK_L[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 8. " STOPMSK_L[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 7. " STOPMSK_L[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 6. " STOPMSK_L[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 5. " STOPMSK_L[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 4. " STOPMSK_L[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 3. " STOPMSK_L[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 2. " STOPMSK_L[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 1. " STOPMSK_L[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 0. " STOPMSK_L[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0E "STOP_H,SCT stop condition higher 16-bit register"
|
|
bitfld.word 0x0E 15. " STOPMSK_H[15] ,Event 15 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 14. " STOPMSK_H[14] ,Event 14 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 13. " STOPMSK_H[13] ,Event 13 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 12. " STOPMSK_H[12] ,Event 12 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 11. " STOPMSK_H[11] ,Event 11 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 10. " STOPMSK_H[10] ,Event 10 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 9. " STOPMSK_H[9] ,Event 9 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 8. " STOPMSK_H[8] ,Event 8 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 7. " STOPMSK_H[7] ,Event 7 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 6. " STOPMSK_H[6] ,Event 6 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 5. " STOPMSK_H[5] ,Event 5 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 4. " STOPMSK_H[4] ,Event 4 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 3. " STOPMSK_H[3] ,Event 3 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 2. " STOPMSK_H[2] ,Event 2 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 1. " STOPMSK_H[1] ,Event 1 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 0. " STOPMSK_H[0] ,Event 0 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x10 "START_L,SCT start condition lower 16-bit register"
|
|
bitfld.word 0x10 15. " STARTMSK_L[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 14. " STARTMSK_L[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 13. " STARTMSK_L[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 12. " STARTMSK_L[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 11. " STARTMSK_L[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 10. " STARTMSK_L[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 9. " STARTMSK_L[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 8. " STARTMSK_L[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 7. " STARTMSK_L[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 6. " STARTMSK_L[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 5. " STARTMSK_L[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 4. " STARTMSK_L[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 3. " STARTMSK_L[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 2. " STARTMSK_L[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 1. " STARTMSK_L[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 0. " STARTMSK_L[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
line.word 0x12 "START_H,SCT start condition higher 16-bit register"
|
|
bitfld.word 0x12 15. " STARTMSK_H[15] ,Event 15 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 14. " STARTMSK_H[14] ,Event 14 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 13. " STARTMSK_H[13] ,Event 13 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 12. " STARTMSK_H[12] ,Event 12 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 11. " STARTMSK_H[11] ,Event 11 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 10. " STARTMSK_H[10] ,Event 10 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 9. " STARTMSK_H[9] ,Event 9 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 8. " STARTMSK_H[8] ,Event 8 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 7. " STARTMSK_H[7] ,Event 7 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 6. " STARTMSK_H[6] ,Event 6 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 5. " STARTMSK_H[5] ,Event 5 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 4. " STARTMSK_H[4] ,Event 4 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 3. " STARTMSK_H[3] ,Event 3 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 2. " STARTMSK_H[2] ,Event 2 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 1. " STARTMSK_H[1] ,Event 1 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 0. " STARTMSK_H[0] ,Event 0 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
line.word 0x14 "DITHER_L,SCT dither condition lower 16-bit register"
|
|
bitfld.word 0x14 15. " DITHMSK_L[15] ,Event 15 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 14. " DITHMSK_L[14] ,Event 14 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 13. " DITHMSK_L[13] ,Event 13 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 12. " DITHMSK_L[12] ,Event 12 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x14 11. " DITHMSK_L[11] ,Event 11 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 10. " DITHMSK_L[10] ,Event 10 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 9. " DITHMSK_L[9] ,Event 9 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 8. " DITHMSK_L[8] ,Event 8 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x14 7. " DITHMSK_L[7] ,Event 7 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 6. " DITHMSK_L[6] ,Event 6 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 5. " DITHMSK_L[5] ,Event 5 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 4. " DITHMSK_L[4] ,Event 4 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x14 3. " DITHMSK_L[3] ,Event 3 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 2. " DITHMSK_L[2] ,Event 2 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 1. " DITHMSK_L[1] ,Event 1 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 0. " DITHMSK_L[0] ,Event 0 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
line.word 0x16 "DITHER_H,SCT dither condition higher 16-bit register"
|
|
bitfld.word 0x16 15. " DITHMSK_H[15] ,Event 15 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 14. " DITHMSK_H[14] ,Event 14 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 13. " DITHMSK_H[13] ,Event 13 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 12. " DITHMSK_H[12] ,Event 12 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x16 11. " DITHMSK_H[11] ,Event 11 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 10. " DITHMSK_H[10] ,Event 10 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 9. " DITHMSK_H[9] ,Event 9 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 8. " DITHMSK_H[8] ,Event 8 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x16 7. " DITHMSK_H[7] ,Event 7 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 6. " DITHMSK_H[6] ,Event 6 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 5. " DITHMSK_H[5] ,Event 5 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 4. " DITHMSK_H[4] ,Event 4 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x16 3. " DITHMSK_H[3] ,Event 3 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 2. " DITHMSK_H[2] ,Event 2 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 1. " DITHMSK_H[1] ,Event 1 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 0. " DITHMSK_H[0] ,Event 0 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
group.word 0x40++0x7
|
|
line.word 0x00 "COUNT_L,SCT counter register low counter 16-bit"
|
|
line.word 0x02 "COUNT_H,SCT counter register high counter 16-bit"
|
|
line.word 0x04 "STATE_L,SCT state register low counter 16-bit"
|
|
bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x06 "STATE_L,SCT state register high counter 16-bit"
|
|
bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 23. " SIN7 ,Input 7 state" "Low,High"
|
|
bitfld.long 0x00 22. " SIN6 ,Input 6 state" "Low,High"
|
|
bitfld.long 0x00 21. " SIN5 ,Input 5 state" "Low,High"
|
|
bitfld.long 0x00 20. " SIN4 ,Input 4 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AIN7 ,Input 7 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 6. " AIN6 ,Input 6 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 5. " AIN5 ,Input 5 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 4. " AIN4 ,Input 4 state(Direct read)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.word 0x4C++0x03
|
|
line.word 0x00 "REGMODE_L,SCT match/capture registers mode register low counter 16-bit"
|
|
bitfld.word 0x00 15. " REGMOD_L[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 14. " REGMOD_L[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 13. " REGMOD_L[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 12. " REGMOD_L[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 11. " REGMOD_L[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 10. " REGMOD_L[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 9. " REGMOD_L[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 8. " REGMOD_L[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 7. " REGMOD_L[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 6. " REGMOD_L[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 5. " REGMOD_L[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 4. " REGMOD_L[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 3. " REGMOD_L[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 2. " REGMOD_L[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 1. " REGMOD_L[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 0. " REGMOD_L[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
line.word 0x02 "REGMODE_H,SCT match/capture registers mode register high counter 16-bit"
|
|
bitfld.word 0x02 15. " REGMOD_H[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 14. " REGMOD_H[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 13. " REGMOD_H[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 12. " REGMOD_H[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 11. " REGMOD_H[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 10. " REGMOD_H[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 9. " REGMOD_H[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 8. " REGMOD_H[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 7. " REGMOD_H[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 6. " REGMOD_H[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 5. " REGMOD_H[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 4. " REGMOD_H[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 3. " REGMOD_H[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 2. " REGMOD_H[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 1. " REGMOD_H[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 0. " REGMOD_H[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT output register"
|
|
bitfld.long 0x00 9. " OUT[9] ,Set high on output 9" "Low,High"
|
|
bitfld.long 0x00 8. " OUT[8] ,Set high on output 8" "Low,High"
|
|
bitfld.long 0x00 7. " OUT[7] ,Set high on output 7" "Low,High"
|
|
bitfld.long 0x00 6. " OUT[6] ,Set high on output 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OUT[5] ,Set high on output 5" "Low,High"
|
|
bitfld.long 0x00 4. " OUT[4] ,Set high on output 4" "Low,High"
|
|
bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT[2] ,Set high on output 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT[1] ,Set high on output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT[0] ,Set high on output 0" "Low,High"
|
|
line.long 0x04 "OUTPUTDIRCTRL,SCT output counter direction control register"
|
|
bitfld.long 0x04 18.--19. " SETCLR9 ,Set/clear operation on output 9 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 16.--17. " SETCLR8 ,Set/clear operation on output 8 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 14.--15. " SETCLR7 ,Set/clear operation on output 7 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 12.--13. " SETCLR6 ,Set/clear operation on output 6 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " SETCLR5 ,Set/clear operation on output 5 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 8.--9. " SETCLR4 ,Set/clear operation on output 4 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 6.--7. " SETCLR3 ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 4.--5. " SETCLR2 ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SETCLR1 ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 0.--1. " SETCLR0 ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
line.long 0x08 "RES,SCT conflict resolution register"
|
|
bitfld.long 0x08 18.--19. " O9RES ,Effect of simultaneous set and clear on output 9" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 16.--17. " O8RES ,Effect of simultaneous set and clear on output 8" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 14.--15. " O7RES ,Effect of simultaneous set and clear on output 7" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 12.--13. " O6RES ,Effect of simultaneous set and clear on output 6" "No change,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle"
|
|
line.long 0x0c "DMAREQ0,SCT DMA request 0 register"
|
|
rbitfld.long 0x0c 31. " DRQ0 ,Indicates the state of DMA Request 0" "Low,High"
|
|
bitfld.long 0x0c 30. " DRL0 ,SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x0c 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 14. " DEV_0[14] ,Event 14 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " DEV_0[13] ,Event 13 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 12. " DEV_0[12] ,Event 12 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 11. " DEV_0[11] ,Event 11 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 10. " DEV_0[10] ,Event 10 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " DEV_0[9] ,Event 9 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 8. " DEV_0[8] ,Event 8 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 7. " DEV_0[7] ,Event 7 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 6. " DEV_0[6] ,Event 6 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 4. " DEV_0[4] ,Event 4 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 3. " DEV_0[3] ,Event 3 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 2. " DEV_0[2] ,Event 2 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " DEV_0[1] ,Event 1 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 0. " DEV_0[0] ,Event 0 sets DMA request 0" "Not set,Set"
|
|
line.long 0x10 "DMAREQ1,SCT DMA request 1 register"
|
|
rbitfld.long 0x10 31. " DRQ1 ,Indicates the state of DMA Request 1" "Low,High"
|
|
bitfld.long 0x10 30. " DRL1 ,SCT set DMA request 1 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x10 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 14. " DEV_1[14] ,Event 14 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DEV_1[13] ,Event 13 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 12. " DEV_1[12] ,Event 12 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 11. " DEV_1[11] ,Event 11 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 10. " DEV_1[10] ,Event 10 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DEV_1[9] ,Event 9 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 8. " DEV_1[8] ,Event 8 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 7. " DEV_1[7] ,Event 7 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 6. " DEV_1[6] ,Event 6 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 4. " DEV_1[4] ,Event 4 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 3. " DEV_1[3] ,Event 3 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 2. " DEV_1[2] ,Event 2 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DEV_1[1] ,Event 1 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 0. " DEV_1[0] ,Event 0 sets DMA request 1" "Not set,Set"
|
|
group.long 0xF0++0xf
|
|
line.long 0x00 "EVEN,SCT event enable register"
|
|
bitfld.long 0x00 15. " IEN[15] ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IEN[14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IEN[13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IEN[12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IEN[11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IEN[10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVFLAG,SCT event flag register"
|
|
bitfld.long 0x04 15. " FLAG[15] ,Event 15 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " FLAG[14] ,Event 14 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " FLAG[13] ,Event 13 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " FLAG[12] ,Event 12 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FLAG[11] ,Event 11 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " FLAG[10] ,Event 10 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " FLAG[9] ,Event 9 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " FLAG[8] ,Event 8 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FLAG[7] ,Event 7 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " FLAG[6] ,Event 6 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " FLAG[4] ,Event 4 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLAG[3] ,Event 3 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " FLAG[2] ,Event 2 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " FLAG[1] ,Event 1 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " FLAG[0] ,Event 0 occurred flag" "Not occurred,Occurred"
|
|
line.long 0x08 "CONEN,SCT conflict enable register"
|
|
bitfld.long 0x08 9. " NCEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NCEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " NCEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NCEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NCEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NCEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " NCEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NCEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NCEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NCEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CONFLAG,SCT conflict flag register"
|
|
bitfld.long 0x0c 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the Output register when the H counter was not halted" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 30. " BUSERRL ,Error writing CTR L/Unified STATE L/Unified MATCH L/Unified or the Output register when the L/U counter was not halted" "No error,Error"
|
|
bitfld.long 0x0c 9. " NCFLAG[9] ,No-change event occurred on output 9 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 8. " NCFLAG[8] ,No-change event occurred on output 8 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " NCFLAG[7] ,No-change event occurred on output 7 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 6. " NCFLAG[6] ,No-change event occurred on output 6 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 5. " NCFLAG[5] ,No-change event occurred on output 5 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 4. " NCFLAG[4] ,No-change event occurred on output 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 2. " NCFLAG[2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 1. " NCFLAG[1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 0. " NCFLAG[0] ,No-change event occurred on output 0 flag" "Not occurred,Occurred"
|
|
tree "Match value and capture registers"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT match value register of match channel 0"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT capture register of capture channel 0"
|
|
else
|
|
group.word 0x100++0x03
|
|
line.word 0x00 "MATCH0_L,SCT match value register of match channel 0 low counter 16-bit"
|
|
line.word 0x02 "MATCH0_H,SCT match value register of match channel 0 high counter 16-bit"
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "CAP0_L,SCT capture register of capture channel 0 low counter 16-bit"
|
|
line.word 0x02 "CAP0_H,SCT capture register of capture channel 0 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT match value register of match channel 1"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT capture register of capture channel 1"
|
|
else
|
|
group.word 0x104++0x03
|
|
line.word 0x00 "MATCH1_L,SCT match value register of match channel 1 low counter 16-bit"
|
|
line.word 0x02 "MATCH1_H,SCT match value register of match channel 1 high counter 16-bit"
|
|
rgroup.word 0x104++0x03
|
|
line.word 0x00 "CAP1_L,SCT capture register of capture channel 1 low counter 16-bit"
|
|
line.word 0x02 "CAP1_H,SCT capture register of capture channel 1 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT match value register of match channel 2"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT capture register of capture channel 2"
|
|
else
|
|
group.word 0x108++0x03
|
|
line.word 0x00 "MATCH2_L,SCT match value register of match channel 2 low counter 16-bit"
|
|
line.word 0x02 "MATCH2_H,SCT match value register of match channel 2 high counter 16-bit"
|
|
rgroup.word 0x108++0x03
|
|
line.word 0x00 "CAP2_L,SCT capture register of capture channel 2 low counter 16-bit"
|
|
line.word 0x02 "CAP2_H,SCT capture register of capture channel 2 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT match value register of match channel 3"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT capture register of capture channel 3"
|
|
else
|
|
group.word 0x10C++0x03
|
|
line.word 0x00 "MATCH3_L,SCT match value register of match channel 3 low counter 16-bit"
|
|
line.word 0x02 "MATCH3_H,SCT match value register of match channel 3 high counter 16-bit"
|
|
rgroup.word 0x10C++0x03
|
|
line.word 0x00 "CAP3_L,SCT capture register of capture channel 3 low counter 16-bit"
|
|
line.word 0x02 "CAP3_H,SCT capture register of capture channel 3 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT match value register of match channel 4"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT capture register of capture channel 4"
|
|
else
|
|
group.word 0x110++0x03
|
|
line.word 0x00 "MATCH4_L,SCT match value register of match channel 4 low counter 16-bit"
|
|
line.word 0x02 "MATCH4_H,SCT match value register of match channel 4 high counter 16-bit"
|
|
rgroup.word 0x110++0x03
|
|
line.word 0x00 "CAP4_L,SCT capture register of capture channel 4 low counter 16-bit"
|
|
line.word 0x02 "CAP4_H,SCT capture register of capture channel 4 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT match value register of match channel 5"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT capture register of capture channel 5"
|
|
else
|
|
group.word 0x114++0x03
|
|
line.word 0x00 "MATCH5_L,SCT match value register of match channel 5 low counter 16-bit"
|
|
line.word 0x02 "MATCH5_H,SCT match value register of match channel 5 high counter 16-bit"
|
|
rgroup.word 0x114++0x03
|
|
line.word 0x00 "CAP5_L,SCT capture register of capture channel 5 low counter 16-bit"
|
|
line.word 0x02 "CAP5_H,SCT capture register of capture channel 5 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT match value register of match channel 6"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT capture register of capture channel 6"
|
|
else
|
|
group.word 0x118++0x03
|
|
line.word 0x00 "MATCH6_L,SCT match value register of match channel 6 low counter 16-bit"
|
|
line.word 0x02 "MATCH6_H,SCT match value register of match channel 6 high counter 16-bit"
|
|
rgroup.word 0x118++0x03
|
|
line.word 0x00 "CAP6_L,SCT capture register of capture channel 6 low counter 16-bit"
|
|
line.word 0x02 "CAP6_H,SCT capture register of capture channel 6 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT match value register of match channel 7"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT capture register of capture channel 7"
|
|
else
|
|
group.word 0x11C++0x03
|
|
line.word 0x00 "MATCH7_L,SCT match value register of match channel 7 low counter 16-bit"
|
|
line.word 0x02 "MATCH7_H,SCT match value register of match channel 7 high counter 16-bit"
|
|
rgroup.word 0x11C++0x03
|
|
line.word 0x00 "CAP7_L,SCT capture register of capture channel 7 low counter 16-bit"
|
|
line.word 0x02 "CAP7_H,SCT capture register of capture channel 7 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MATCH8,SCT match value register of match channel 8"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CAP8,SCT capture register of capture channel 8"
|
|
else
|
|
group.word 0x120++0x03
|
|
line.word 0x00 "MATCH8_L,SCT match value register of match channel 8 low counter 16-bit"
|
|
line.word 0x02 "MATCH8_H,SCT match value register of match channel 8 high counter 16-bit"
|
|
rgroup.word 0x120++0x03
|
|
line.word 0x00 "CAP8_L,SCT capture register of capture channel 8 low counter 16-bit"
|
|
line.word 0x02 "CAP8_H,SCT capture register of capture channel 8 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MATCH9,SCT match value register of match channel 9"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CAP9,SCT capture register of capture channel 9"
|
|
else
|
|
group.word 0x124++0x03
|
|
line.word 0x00 "MATCH9_L,SCT match value register of match channel 9 low counter 16-bit"
|
|
line.word 0x02 "MATCH9_H,SCT match value register of match channel 9 high counter 16-bit"
|
|
rgroup.word 0x124++0x03
|
|
line.word 0x00 "CAP9_L,SCT capture register of capture channel 9 low counter 16-bit"
|
|
line.word 0x02 "CAP9_H,SCT capture register of capture channel 9 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MATCH10,SCT match value register of match channel 10"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CAP10,SCT capture register of capture channel 10"
|
|
else
|
|
group.word 0x128++0x03
|
|
line.word 0x00 "MATCH10_L,SCT match value register of match channel 10 low counter 16-bit"
|
|
line.word 0x02 "MATCH10_H,SCT match value register of match channel 10 high counter 16-bit"
|
|
rgroup.word 0x128++0x03
|
|
line.word 0x00 "CAP10_L,SCT capture register of capture channel 10 low counter 16-bit"
|
|
line.word 0x02 "CAP10_H,SCT capture register of capture channel 10 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MATCH11,SCT match value register of match channel 11"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "CAP11,SCT capture register of capture channel 11"
|
|
else
|
|
group.word 0x12C++0x03
|
|
line.word 0x00 "MATCH11_L,SCT match value register of match channel 11 low counter 16-bit"
|
|
line.word 0x02 "MATCH11_H,SCT match value register of match channel 11 high counter 16-bit"
|
|
rgroup.word 0x12C++0x03
|
|
line.word 0x00 "CAP11_L,SCT capture register of capture channel 11 low counter 16-bit"
|
|
line.word 0x02 "CAP11_H,SCT capture register of capture channel 11 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MATCH12,SCT match value register of match channel 12"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CAP12,SCT capture register of capture channel 12"
|
|
else
|
|
group.word 0x130++0x03
|
|
line.word 0x00 "MATCH12_L,SCT match value register of match channel 12 low counter 16-bit"
|
|
line.word 0x02 "MATCH12_H,SCT match value register of match channel 12 high counter 16-bit"
|
|
rgroup.word 0x130++0x03
|
|
line.word 0x00 "CAP12_L,SCT capture register of capture channel 12 low counter 16-bit"
|
|
line.word 0x02 "CAP12_H,SCT capture register of capture channel 12 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MATCH13,SCT match value register of match channel 13"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CAP13,SCT capture register of capture channel 13"
|
|
else
|
|
group.word 0x134++0x03
|
|
line.word 0x00 "MATCH13_L,SCT match value register of match channel 13 low counter 16-bit"
|
|
line.word 0x02 "MATCH13_H,SCT match value register of match channel 13 high counter 16-bit"
|
|
rgroup.word 0x134++0x03
|
|
line.word 0x00 "CAP13_L,SCT capture register of capture channel 13 low counter 16-bit"
|
|
line.word 0x02 "CAP13_H,SCT capture register of capture channel 13 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MATCH14,SCT match value register of match channel 14"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "CAP14,SCT capture register of capture channel 14"
|
|
else
|
|
group.word 0x138++0x03
|
|
line.word 0x00 "MATCH14_L,SCT match value register of match channel 14 low counter 16-bit"
|
|
line.word 0x02 "MATCH14_H,SCT match value register of match channel 14 high counter 16-bit"
|
|
rgroup.word 0x138++0x03
|
|
line.word 0x00 "CAP14_L,SCT capture register of capture channel 14 low counter 16-bit"
|
|
line.word 0x02 "CAP14_H,SCT capture register of capture channel 14 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MATCH15,SCT match value register of match channel 15"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "CAP15,SCT capture register of capture channel 15"
|
|
else
|
|
group.word 0x13C++0x03
|
|
line.word 0x00 "MATCH15_L,SCT match value register of match channel 15 low counter 16-bit"
|
|
line.word 0x02 "MATCH15_H,SCT match value register of match channel 15 high counter 16-bit"
|
|
rgroup.word 0x13C++0x03
|
|
line.word 0x00 "CAP15_L,SCT capture register of capture channel 15 low counter 16-bit"
|
|
line.word 0x02 "CAP15_H,SCT capture register of capture channel 15 high counter 16-bit"
|
|
endif
|
|
tree.end
|
|
tree "Fractional match registers"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x140+0x40)++0x03
|
|
line.long 0x00 "FRACMAT0,Fractional match register 0 SCT match value register 0"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH0 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x140++0x03
|
|
line.word 0x00 "FRACMAT0_L,Fractional match register 0 SCT match value register 0 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH0_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT0_H,Fractional match register 0 SCT match value register 0 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH0_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x144+0x40)++0x03
|
|
line.long 0x00 "FRACMAT1,Fractional match register 1 SCT match value register 1"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH1 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x144++0x03
|
|
line.word 0x00 "FRACMAT1_L,Fractional match register 1 SCT match value register 1 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH1_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT1_H,Fractional match register 1 SCT match value register 1 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH1_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x148+0x40)++0x03
|
|
line.long 0x00 "FRACMAT2,Fractional match register 2 SCT match value register 2"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH2 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x148++0x03
|
|
line.word 0x00 "FRACMAT2_L,Fractional match register 2 SCT match value register 2 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH2_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT2_H,Fractional match register 2 SCT match value register 2 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH2_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x14C+0x40)++0x03
|
|
line.long 0x00 "FRACMAT3,Fractional match register 3 SCT match value register 3"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH3 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x14C++0x03
|
|
line.word 0x00 "FRACMAT3_L,Fractional match register 3 SCT match value register 3 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH3_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT3_H,Fractional match register 3 SCT match value register 3 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH3_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x150+0x40)++0x03
|
|
line.long 0x00 "FRACMAT4,Fractional match register 4 SCT match value register 4"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH4 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x150++0x03
|
|
line.word 0x00 "FRACMAT4_L,Fractional match register 4 SCT match value register 4 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH4_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT4_H,Fractional match register 4 SCT match value register 4 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH4_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x154+0x40)++0x03
|
|
line.long 0x00 "FRACMAT5,Fractional match register 5 SCT match value register 5"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH5 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x154++0x03
|
|
line.word 0x00 "FRACMAT5_L,Fractional match register 5 SCT match value register 5 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH5_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT5_H,Fractional match register 5 SCT match value register 5 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH5_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Match reload and capture control registers"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MATCHREL0,SCT match reload value register 0"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CAPCTRL0,SCT capture control register 0"
|
|
bitfld.long 0x00 15. " CAPCON0[15] ,Event 15 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON0[14] ,Event 14 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON0[13] ,Event 13 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON0[12] ,Event 12 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON0[11] ,Event 11 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON0[10] ,Event 10 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON0[9] ,Event 9 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON0[8] ,Event 8 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON0[7] ,Event 7 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON0[6] ,Event 6 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON0[5] ,Event 5 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON0[4] ,Event 4 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON0[3] ,Event 3 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON0[2] ,Event 2 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON0[1] ,Event 1 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON0[0] ,Event 0 causes load of CAP0 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "MATCHREL0_L,SCT match reload value register 0 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL0_H,SCT match reload value register 0 high counter 16-bit"
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "CAPCTRL0_L,SCT capture control register 0 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON0_L[15] ,Event 15 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON0_L[14] ,Event 14 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON0_L[13] ,Event 13 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON0_L[12] ,Event 12 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON0_L[11] ,Event 11 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON0_L[10] ,Event 10 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON0_L[9] ,Event 9 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON0_L[8] ,Event 8 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON0_L[7] ,Event 7 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON0_L[6] ,Event 6 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON0_L[5] ,Event 5 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON0_L[4] ,Event 4 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON0_L[3] ,Event 3 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON0_L[2] ,Event 2 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON0_L[1] ,Event 1 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON0_L[0] ,Event 0 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL0_H,SCT capture control register 0 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON0_H[15] ,Event 15 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON0_H[14] ,Event 14 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON0_H[13] ,Event 13 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON0_H[12] ,Event 12 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON0_H[11] ,Event 11 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON0_H[10] ,Event 10 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON0_H[9] ,Event 9 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON0_H[8] ,Event 8 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON0_H[7] ,Event 7 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON0_H[6] ,Event 6 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON0_H[5] ,Event 5 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON0_H[4] ,Event 4 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON0_H[3] ,Event 3 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON0_H[2] ,Event 2 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON0_H[1] ,Event 1 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON0_H[0] ,Event 0 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "MATCHREL1,SCT match reload value register 1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CAPCTRL1,SCT capture control register 1"
|
|
bitfld.long 0x00 15. " CAPCON1[15] ,Event 15 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON1[14] ,Event 14 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON1[13] ,Event 13 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON1[12] ,Event 12 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON1[11] ,Event 11 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON1[10] ,Event 10 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON1[9] ,Event 9 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON1[8] ,Event 8 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON1[7] ,Event 7 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON1[6] ,Event 6 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON1[5] ,Event 5 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON1[4] ,Event 4 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON1[3] ,Event 3 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON1[2] ,Event 2 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON1[1] ,Event 1 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON1[0] ,Event 0 causes load of CAP1 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "MATCHREL1_L,SCT match reload value register 1 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL1_H,SCT match reload value register 1 high counter 16-bit"
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "CAPCTRL1_L,SCT capture control register 1 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON1_L[15] ,Event 15 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON1_L[14] ,Event 14 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON1_L[13] ,Event 13 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON1_L[12] ,Event 12 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON1_L[11] ,Event 11 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON1_L[10] ,Event 10 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON1_L[9] ,Event 9 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON1_L[8] ,Event 8 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON1_L[7] ,Event 7 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON1_L[6] ,Event 6 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON1_L[5] ,Event 5 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON1_L[4] ,Event 4 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON1_L[3] ,Event 3 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON1_L[2] ,Event 2 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON1_L[1] ,Event 1 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON1_L[0] ,Event 0 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL1_H,SCT capture control register 1 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON1_H[15] ,Event 15 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON1_H[14] ,Event 14 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON1_H[13] ,Event 13 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON1_H[12] ,Event 12 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON1_H[11] ,Event 11 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON1_H[10] ,Event 10 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON1_H[9] ,Event 9 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON1_H[8] ,Event 8 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON1_H[7] ,Event 7 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON1_H[6] ,Event 6 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON1_H[5] ,Event 5 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON1_H[4] ,Event 4 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON1_H[3] ,Event 3 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON1_H[2] ,Event 2 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON1_H[1] ,Event 1 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON1_H[0] ,Event 0 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "MATCHREL2,SCT match reload value register 2"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CAPCTRL2,SCT capture control register 2"
|
|
bitfld.long 0x00 15. " CAPCON2[15] ,Event 15 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON2[14] ,Event 14 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON2[13] ,Event 13 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON2[12] ,Event 12 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON2[11] ,Event 11 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON2[10] ,Event 10 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON2[9] ,Event 9 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON2[8] ,Event 8 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON2[7] ,Event 7 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON2[6] ,Event 6 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON2[5] ,Event 5 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON2[4] ,Event 4 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON2[3] ,Event 3 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON2[2] ,Event 2 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON2[1] ,Event 1 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON2[0] ,Event 0 causes load of CAP2 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "MATCHREL2_L,SCT match reload value register 2 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL2_H,SCT match reload value register 2 high counter 16-bit"
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "CAPCTRL2_L,SCT capture control register 2 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON2_L[15] ,Event 15 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON2_L[14] ,Event 14 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON2_L[13] ,Event 13 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON2_L[12] ,Event 12 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON2_L[11] ,Event 11 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON2_L[10] ,Event 10 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON2_L[9] ,Event 9 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON2_L[8] ,Event 8 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON2_L[7] ,Event 7 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON2_L[6] ,Event 6 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON2_L[5] ,Event 5 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON2_L[4] ,Event 4 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON2_L[3] ,Event 3 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON2_L[2] ,Event 2 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON2_L[1] ,Event 1 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON2_L[0] ,Event 0 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL2_H,SCT capture control register 2 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON2_H[15] ,Event 15 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON2_H[14] ,Event 14 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON2_H[13] ,Event 13 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON2_H[12] ,Event 12 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON2_H[11] ,Event 11 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON2_H[10] ,Event 10 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON2_H[9] ,Event 9 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON2_H[8] ,Event 8 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON2_H[7] ,Event 7 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON2_H[6] ,Event 6 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON2_H[5] ,Event 5 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON2_H[4] ,Event 4 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON2_H[3] ,Event 3 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON2_H[2] ,Event 2 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON2_H[1] ,Event 1 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON2_H[0] ,Event 0 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "MATCHREL3,SCT match reload value register 3"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CAPCTRL3,SCT capture control register 3"
|
|
bitfld.long 0x00 15. " CAPCON3[15] ,Event 15 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON3[14] ,Event 14 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON3[13] ,Event 13 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON3[12] ,Event 12 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON3[11] ,Event 11 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON3[10] ,Event 10 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON3[9] ,Event 9 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON3[8] ,Event 8 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON3[7] ,Event 7 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON3[6] ,Event 6 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON3[5] ,Event 5 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON3[4] ,Event 4 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON3[3] ,Event 3 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON3[2] ,Event 2 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON3[1] ,Event 1 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON3[0] ,Event 0 causes load of CAP3 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "MATCHREL3_L,SCT match reload value register 3 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL3_H,SCT match reload value register 3 high counter 16-bit"
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "CAPCTRL3_L,SCT capture control register 3 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON3_L[15] ,Event 15 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON3_L[14] ,Event 14 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON3_L[13] ,Event 13 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON3_L[12] ,Event 12 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON3_L[11] ,Event 11 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON3_L[10] ,Event 10 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON3_L[9] ,Event 9 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON3_L[8] ,Event 8 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON3_L[7] ,Event 7 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON3_L[6] ,Event 6 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON3_L[5] ,Event 5 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON3_L[4] ,Event 4 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON3_L[3] ,Event 3 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON3_L[2] ,Event 2 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON3_L[1] ,Event 1 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON3_L[0] ,Event 0 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL3_H,SCT capture control register 3 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON3_H[15] ,Event 15 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON3_H[14] ,Event 14 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON3_H[13] ,Event 13 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON3_H[12] ,Event 12 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON3_H[11] ,Event 11 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON3_H[10] ,Event 10 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON3_H[9] ,Event 9 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON3_H[8] ,Event 8 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON3_H[7] ,Event 7 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON3_H[6] ,Event 6 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON3_H[5] ,Event 5 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON3_H[4] ,Event 4 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON3_H[3] ,Event 3 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON3_H[2] ,Event 2 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON3_H[1] ,Event 1 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON3_H[0] ,Event 0 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "MATCHREL4,SCT match reload value register 4"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CAPCTRL4,SCT capture control register 4"
|
|
bitfld.long 0x00 15. " CAPCON4[15] ,Event 15 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON4[14] ,Event 14 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON4[13] ,Event 13 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON4[12] ,Event 12 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON4[11] ,Event 11 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON4[10] ,Event 10 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON4[9] ,Event 9 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON4[8] ,Event 8 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON4[7] ,Event 7 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON4[6] ,Event 6 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON4[5] ,Event 5 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON4[4] ,Event 4 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON4[3] ,Event 3 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON4[2] ,Event 2 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON4[1] ,Event 1 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON4[0] ,Event 0 causes load of CAP4 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "MATCHREL4_L,SCT match reload value register 4 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL4_H,SCT match reload value register 4 high counter 16-bit"
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "CAPCTRL4_L,SCT capture control register 4 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON4_L[15] ,Event 15 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON4_L[14] ,Event 14 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON4_L[13] ,Event 13 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON4_L[12] ,Event 12 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON4_L[11] ,Event 11 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON4_L[10] ,Event 10 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON4_L[9] ,Event 9 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON4_L[8] ,Event 8 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON4_L[7] ,Event 7 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON4_L[6] ,Event 6 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON4_L[5] ,Event 5 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON4_L[4] ,Event 4 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON4_L[3] ,Event 3 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON4_L[2] ,Event 2 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON4_L[1] ,Event 1 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON4_L[0] ,Event 0 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL4_H,SCT capture control register 4 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON4_H[15] ,Event 15 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON4_H[14] ,Event 14 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON4_H[13] ,Event 13 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON4_H[12] ,Event 12 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON4_H[11] ,Event 11 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON4_H[10] ,Event 10 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON4_H[9] ,Event 9 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON4_H[8] ,Event 8 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON4_H[7] ,Event 7 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON4_H[6] ,Event 6 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON4_H[5] ,Event 5 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON4_H[4] ,Event 4 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON4_H[3] ,Event 3 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON4_H[2] ,Event 2 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON4_H[1] ,Event 1 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON4_H[0] ,Event 0 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "MATCHREL5,SCT match reload value register 5"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CAPCTRL5,SCT capture control register 5"
|
|
bitfld.long 0x00 15. " CAPCON5[15] ,Event 15 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON5[14] ,Event 14 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON5[13] ,Event 13 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON5[12] ,Event 12 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON5[11] ,Event 11 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON5[10] ,Event 10 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON5[9] ,Event 9 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON5[8] ,Event 8 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON5[7] ,Event 7 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON5[6] ,Event 6 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON5[5] ,Event 5 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON5[4] ,Event 4 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON5[3] ,Event 3 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON5[2] ,Event 2 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON5[1] ,Event 1 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON5[0] ,Event 0 causes load of CAP5 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "MATCHREL5_L,SCT match reload value register 5 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL5_H,SCT match reload value register 5 high counter 16-bit"
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "CAPCTRL5_L,SCT capture control register 5 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON5_L[15] ,Event 15 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON5_L[14] ,Event 14 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON5_L[13] ,Event 13 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON5_L[12] ,Event 12 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON5_L[11] ,Event 11 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON5_L[10] ,Event 10 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON5_L[9] ,Event 9 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON5_L[8] ,Event 8 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON5_L[7] ,Event 7 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON5_L[6] ,Event 6 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON5_L[5] ,Event 5 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON5_L[4] ,Event 4 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON5_L[3] ,Event 3 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON5_L[2] ,Event 2 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON5_L[1] ,Event 1 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON5_L[0] ,Event 0 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL5_H,SCT capture control register 5 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON5_H[15] ,Event 15 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON5_H[14] ,Event 14 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON5_H[13] ,Event 13 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON5_H[12] ,Event 12 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON5_H[11] ,Event 11 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON5_H[10] ,Event 10 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON5_H[9] ,Event 9 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON5_H[8] ,Event 8 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON5_H[7] ,Event 7 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON5_H[6] ,Event 6 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON5_H[5] ,Event 5 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON5_H[4] ,Event 4 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON5_H[3] ,Event 3 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON5_H[2] ,Event 2 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON5_H[1] ,Event 1 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON5_H[0] ,Event 0 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "MATCHREL6,SCT match reload value register 6"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "CAPCTRL6,SCT capture control register 6"
|
|
bitfld.long 0x00 15. " CAPCON6[15] ,Event 15 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON6[14] ,Event 14 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON6[13] ,Event 13 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON6[12] ,Event 12 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON6[11] ,Event 11 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON6[10] ,Event 10 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON6[9] ,Event 9 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON6[8] ,Event 8 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON6[7] ,Event 7 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON6[6] ,Event 6 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON6[5] ,Event 5 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON6[4] ,Event 4 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON6[3] ,Event 3 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON6[2] ,Event 2 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON6[1] ,Event 1 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON6[0] ,Event 0 causes load of CAP6 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "MATCHREL6_L,SCT match reload value register 6 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL6_H,SCT match reload value register 6 high counter 16-bit"
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "CAPCTRL6_L,SCT capture control register 6 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON6_L[15] ,Event 15 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON6_L[14] ,Event 14 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON6_L[13] ,Event 13 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON6_L[12] ,Event 12 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON6_L[11] ,Event 11 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON6_L[10] ,Event 10 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON6_L[9] ,Event 9 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON6_L[8] ,Event 8 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON6_L[7] ,Event 7 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON6_L[6] ,Event 6 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON6_L[5] ,Event 5 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON6_L[4] ,Event 4 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON6_L[3] ,Event 3 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON6_L[2] ,Event 2 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON6_L[1] ,Event 1 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON6_L[0] ,Event 0 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL6_H,SCT capture control register 6 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON6_H[15] ,Event 15 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON6_H[14] ,Event 14 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON6_H[13] ,Event 13 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON6_H[12] ,Event 12 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON6_H[11] ,Event 11 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON6_H[10] ,Event 10 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON6_H[9] ,Event 9 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON6_H[8] ,Event 8 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON6_H[7] ,Event 7 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON6_H[6] ,Event 6 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON6_H[5] ,Event 5 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON6_H[4] ,Event 4 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON6_H[3] ,Event 3 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON6_H[2] ,Event 2 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON6_H[1] ,Event 1 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON6_H[0] ,Event 0 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MATCHREL7,SCT match reload value register 7"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CAPCTRL7,SCT capture control register 7"
|
|
bitfld.long 0x00 15. " CAPCON7[15] ,Event 15 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON7[14] ,Event 14 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON7[13] ,Event 13 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON7[12] ,Event 12 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON7[11] ,Event 11 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON7[10] ,Event 10 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON7[9] ,Event 9 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON7[8] ,Event 8 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON7[7] ,Event 7 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON7[6] ,Event 6 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON7[5] ,Event 5 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON7[4] ,Event 4 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON7[3] ,Event 3 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON7[2] ,Event 2 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON7[1] ,Event 1 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON7[0] ,Event 0 causes load of CAP7 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "MATCHREL7_L,SCT match reload value register 7 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL7_H,SCT match reload value register 7 high counter 16-bit"
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "CAPCTRL7_L,SCT capture control register 7 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON7_L[15] ,Event 15 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON7_L[14] ,Event 14 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON7_L[13] ,Event 13 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON7_L[12] ,Event 12 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON7_L[11] ,Event 11 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON7_L[10] ,Event 10 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON7_L[9] ,Event 9 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON7_L[8] ,Event 8 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON7_L[7] ,Event 7 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON7_L[6] ,Event 6 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON7_L[5] ,Event 5 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON7_L[4] ,Event 4 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON7_L[3] ,Event 3 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON7_L[2] ,Event 2 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON7_L[1] ,Event 1 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON7_L[0] ,Event 0 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL7_H,SCT capture control register 7 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON7_H[15] ,Event 15 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON7_H[14] ,Event 14 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON7_H[13] ,Event 13 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON7_H[12] ,Event 12 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON7_H[11] ,Event 11 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON7_H[10] ,Event 10 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON7_H[9] ,Event 9 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON7_H[8] ,Event 8 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON7_H[7] ,Event 7 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON7_H[6] ,Event 6 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON7_H[5] ,Event 5 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON7_H[4] ,Event 4 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON7_H[3] ,Event 3 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON7_H[2] ,Event 2 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON7_H[1] ,Event 1 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON7_H[0] ,Event 0 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "MATCHREL8,SCT match reload value register 8"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CAPCTRL8,SCT capture control register 8"
|
|
bitfld.long 0x00 15. " CAPCON8[15] ,Event 15 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON8[14] ,Event 14 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON8[13] ,Event 13 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON8[12] ,Event 12 causes load of CAP8 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON8[11] ,Event 11 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON8[10] ,Event 10 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON8[9] ,Event 9 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON8[8] ,Event 8 causes load of CAP8 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON8[7] ,Event 7 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON8[6] ,Event 6 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON8[5] ,Event 5 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON8[4] ,Event 4 causes load of CAP8 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON8[3] ,Event 3 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON8[2] ,Event 2 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON8[1] ,Event 1 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON8[0] ,Event 0 causes load of CAP8 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x220++0x03
|
|
line.word 0x00 "MATCHREL8_L,SCT match reload value register 8 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL8_H,SCT match reload value register 8 high counter 16-bit"
|
|
group.word 0x220++0x03
|
|
line.word 0x00 "CAPCTRL8_L,SCT capture control register 8 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON8_L[15] ,Event 15 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON8_L[14] ,Event 14 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON8_L[13] ,Event 13 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON8_L[12] ,Event 12 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON8_L[11] ,Event 11 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON8_L[10] ,Event 10 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON8_L[9] ,Event 9 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON8_L[8] ,Event 8 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON8_L[7] ,Event 7 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON8_L[6] ,Event 6 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON8_L[5] ,Event 5 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON8_L[4] ,Event 4 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON8_L[3] ,Event 3 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON8_L[2] ,Event 2 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON8_L[1] ,Event 1 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON8_L[0] ,Event 0 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL8_H,SCT capture control register 8 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON8_H[15] ,Event 15 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON8_H[14] ,Event 14 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON8_H[13] ,Event 13 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON8_H[12] ,Event 12 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON8_H[11] ,Event 11 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON8_H[10] ,Event 10 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON8_H[9] ,Event 9 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON8_H[8] ,Event 8 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON8_H[7] ,Event 7 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON8_H[6] ,Event 6 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON8_H[5] ,Event 5 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON8_H[4] ,Event 4 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON8_H[3] ,Event 3 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON8_H[2] ,Event 2 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON8_H[1] ,Event 1 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON8_H[0] ,Event 0 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "MATCHREL9,SCT match reload value register 9"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "CAPCTRL9,SCT capture control register 9"
|
|
bitfld.long 0x00 15. " CAPCON9[15] ,Event 15 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON9[14] ,Event 14 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON9[13] ,Event 13 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON9[12] ,Event 12 causes load of CAP9 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON9[11] ,Event 11 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON9[10] ,Event 10 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON9[9] ,Event 9 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON9[8] ,Event 8 causes load of CAP9 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON9[7] ,Event 7 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON9[6] ,Event 6 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON9[5] ,Event 5 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON9[4] ,Event 4 causes load of CAP9 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON9[3] ,Event 3 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON9[2] ,Event 2 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON9[1] ,Event 1 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON9[0] ,Event 0 causes load of CAP9 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x224++0x03
|
|
line.word 0x00 "MATCHREL9_L,SCT match reload value register 9 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL9_H,SCT match reload value register 9 high counter 16-bit"
|
|
group.word 0x224++0x03
|
|
line.word 0x00 "CAPCTRL9_L,SCT capture control register 9 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON9_L[15] ,Event 15 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON9_L[14] ,Event 14 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON9_L[13] ,Event 13 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON9_L[12] ,Event 12 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON9_L[11] ,Event 11 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON9_L[10] ,Event 10 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON9_L[9] ,Event 9 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON9_L[8] ,Event 8 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON9_L[7] ,Event 7 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON9_L[6] ,Event 6 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON9_L[5] ,Event 5 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON9_L[4] ,Event 4 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON9_L[3] ,Event 3 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON9_L[2] ,Event 2 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON9_L[1] ,Event 1 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON9_L[0] ,Event 0 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL9_H,SCT capture control register 9 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON9_H[15] ,Event 15 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON9_H[14] ,Event 14 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON9_H[13] ,Event 13 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON9_H[12] ,Event 12 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON9_H[11] ,Event 11 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON9_H[10] ,Event 10 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON9_H[9] ,Event 9 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON9_H[8] ,Event 8 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON9_H[7] ,Event 7 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON9_H[6] ,Event 6 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON9_H[5] ,Event 5 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON9_H[4] ,Event 4 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON9_H[3] ,Event 3 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON9_H[2] ,Event 2 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON9_H[1] ,Event 1 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON9_H[0] ,Event 0 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "MATCHREL10,SCT match reload value register 10"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "CAPCTRL10,SCT capture control register 10"
|
|
bitfld.long 0x00 15. " CAPCON10[15] ,Event 15 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON10[14] ,Event 14 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON10[13] ,Event 13 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON10[12] ,Event 12 causes load of CAP10 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON10[11] ,Event 11 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON10[10] ,Event 10 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON10[9] ,Event 9 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON10[8] ,Event 8 causes load of CAP10 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON10[7] ,Event 7 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON10[6] ,Event 6 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON10[5] ,Event 5 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON10[4] ,Event 4 causes load of CAP10 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON10[3] ,Event 3 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON10[2] ,Event 2 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON10[1] ,Event 1 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON10[0] ,Event 0 causes load of CAP10 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x228++0x03
|
|
line.word 0x00 "MATCHREL10_L,SCT match reload value register 10 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL10_H,SCT match reload value register 10 high counter 16-bit"
|
|
group.word 0x228++0x03
|
|
line.word 0x00 "CAPCTRL10_L,SCT capture control register 10 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON10_L[15] ,Event 15 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON10_L[14] ,Event 14 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON10_L[13] ,Event 13 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON10_L[12] ,Event 12 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON10_L[11] ,Event 11 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON10_L[10] ,Event 10 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON10_L[9] ,Event 9 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON10_L[8] ,Event 8 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON10_L[7] ,Event 7 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON10_L[6] ,Event 6 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON10_L[5] ,Event 5 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON10_L[4] ,Event 4 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON10_L[3] ,Event 3 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON10_L[2] ,Event 2 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON10_L[1] ,Event 1 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON10_L[0] ,Event 0 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL10_H,SCT capture control register 10 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON10_H[15] ,Event 15 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON10_H[14] ,Event 14 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON10_H[13] ,Event 13 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON10_H[12] ,Event 12 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON10_H[11] ,Event 11 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON10_H[10] ,Event 10 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON10_H[9] ,Event 9 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON10_H[8] ,Event 8 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON10_H[7] ,Event 7 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON10_H[6] ,Event 6 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON10_H[5] ,Event 5 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON10_H[4] ,Event 4 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON10_H[3] ,Event 3 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON10_H[2] ,Event 2 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON10_H[1] ,Event 1 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON10_H[0] ,Event 0 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "MATCHREL11,SCT match reload value register 11"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "CAPCTRL11,SCT capture control register 11"
|
|
bitfld.long 0x00 15. " CAPCON11[15] ,Event 15 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON11[14] ,Event 14 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON11[13] ,Event 13 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON11[12] ,Event 12 causes load of CAP11 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON11[11] ,Event 11 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON11[10] ,Event 10 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON11[9] ,Event 9 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON11[8] ,Event 8 causes load of CAP11 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON11[7] ,Event 7 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON11[6] ,Event 6 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON11[5] ,Event 5 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON11[4] ,Event 4 causes load of CAP11 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON11[3] ,Event 3 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON11[2] ,Event 2 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON11[1] ,Event 1 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON11[0] ,Event 0 causes load of CAP11 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x22C++0x03
|
|
line.word 0x00 "MATCHREL11_L,SCT match reload value register 11 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL11_H,SCT match reload value register 11 high counter 16-bit"
|
|
group.word 0x22C++0x03
|
|
line.word 0x00 "CAPCTRL11_L,SCT capture control register 11 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON11_L[15] ,Event 15 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON11_L[14] ,Event 14 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON11_L[13] ,Event 13 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON11_L[12] ,Event 12 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON11_L[11] ,Event 11 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON11_L[10] ,Event 10 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON11_L[9] ,Event 9 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON11_L[8] ,Event 8 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON11_L[7] ,Event 7 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON11_L[6] ,Event 6 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON11_L[5] ,Event 5 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON11_L[4] ,Event 4 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON11_L[3] ,Event 3 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON11_L[2] ,Event 2 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON11_L[1] ,Event 1 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON11_L[0] ,Event 0 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL11_H,SCT capture control register 11 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON11_H[15] ,Event 15 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON11_H[14] ,Event 14 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON11_H[13] ,Event 13 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON11_H[12] ,Event 12 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON11_H[11] ,Event 11 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON11_H[10] ,Event 10 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON11_H[9] ,Event 9 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON11_H[8] ,Event 8 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON11_H[7] ,Event 7 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON11_H[6] ,Event 6 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON11_H[5] ,Event 5 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON11_H[4] ,Event 4 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON11_H[3] ,Event 3 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON11_H[2] ,Event 2 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON11_H[1] ,Event 1 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON11_H[0] ,Event 0 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "MATCHREL12,SCT match reload value register 12"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "CAPCTRL12,SCT capture control register 12"
|
|
bitfld.long 0x00 15. " CAPCON12[15] ,Event 15 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON12[14] ,Event 14 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON12[13] ,Event 13 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON12[12] ,Event 12 causes load of CAP12 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON12[11] ,Event 11 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON12[10] ,Event 10 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON12[9] ,Event 9 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON12[8] ,Event 8 causes load of CAP12 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON12[7] ,Event 7 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON12[6] ,Event 6 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON12[5] ,Event 5 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON12[4] ,Event 4 causes load of CAP12 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON12[3] ,Event 3 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON12[2] ,Event 2 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON12[1] ,Event 1 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON12[0] ,Event 0 causes load of CAP12 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x230++0x03
|
|
line.word 0x00 "MATCHREL12_L,SCT match reload value register 12 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL12_H,SCT match reload value register 12 high counter 16-bit"
|
|
group.word 0x230++0x03
|
|
line.word 0x00 "CAPCTRL12_L,SCT capture control register 12 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON12_L[15] ,Event 15 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON12_L[14] ,Event 14 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON12_L[13] ,Event 13 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON12_L[12] ,Event 12 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON12_L[11] ,Event 11 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON12_L[10] ,Event 10 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON12_L[9] ,Event 9 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON12_L[8] ,Event 8 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON12_L[7] ,Event 7 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON12_L[6] ,Event 6 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON12_L[5] ,Event 5 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON12_L[4] ,Event 4 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON12_L[3] ,Event 3 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON12_L[2] ,Event 2 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON12_L[1] ,Event 1 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON12_L[0] ,Event 0 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL12_H,SCT capture control register 12 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON12_H[15] ,Event 15 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON12_H[14] ,Event 14 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON12_H[13] ,Event 13 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON12_H[12] ,Event 12 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON12_H[11] ,Event 11 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON12_H[10] ,Event 10 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON12_H[9] ,Event 9 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON12_H[8] ,Event 8 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON12_H[7] ,Event 7 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON12_H[6] ,Event 6 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON12_H[5] ,Event 5 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON12_H[4] ,Event 4 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON12_H[3] ,Event 3 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON12_H[2] ,Event 2 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON12_H[1] ,Event 1 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON12_H[0] ,Event 0 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "MATCHREL13,SCT match reload value register 13"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "CAPCTRL13,SCT capture control register 13"
|
|
bitfld.long 0x00 15. " CAPCON13[15] ,Event 15 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON13[14] ,Event 14 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON13[13] ,Event 13 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON13[12] ,Event 12 causes load of CAP13 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON13[11] ,Event 11 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON13[10] ,Event 10 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON13[9] ,Event 9 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON13[8] ,Event 8 causes load of CAP13 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON13[7] ,Event 7 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON13[6] ,Event 6 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON13[5] ,Event 5 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON13[4] ,Event 4 causes load of CAP13 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON13[3] ,Event 3 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON13[2] ,Event 2 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON13[1] ,Event 1 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON13[0] ,Event 0 causes load of CAP13 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x234++0x03
|
|
line.word 0x00 "MATCHREL13_L,SCT match reload value register 13 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL13_H,SCT match reload value register 13 high counter 16-bit"
|
|
group.word 0x234++0x03
|
|
line.word 0x00 "CAPCTRL13_L,SCT capture control register 13 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON13_L[15] ,Event 15 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON13_L[14] ,Event 14 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON13_L[13] ,Event 13 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON13_L[12] ,Event 12 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON13_L[11] ,Event 11 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON13_L[10] ,Event 10 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON13_L[9] ,Event 9 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON13_L[8] ,Event 8 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON13_L[7] ,Event 7 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON13_L[6] ,Event 6 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON13_L[5] ,Event 5 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON13_L[4] ,Event 4 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON13_L[3] ,Event 3 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON13_L[2] ,Event 2 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON13_L[1] ,Event 1 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON13_L[0] ,Event 0 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL13_H,SCT capture control register 13 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON13_H[15] ,Event 15 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON13_H[14] ,Event 14 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON13_H[13] ,Event 13 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON13_H[12] ,Event 12 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON13_H[11] ,Event 11 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON13_H[10] ,Event 10 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON13_H[9] ,Event 9 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON13_H[8] ,Event 8 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON13_H[7] ,Event 7 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON13_H[6] ,Event 6 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON13_H[5] ,Event 5 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON13_H[4] ,Event 4 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON13_H[3] ,Event 3 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON13_H[2] ,Event 2 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON13_H[1] ,Event 1 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON13_H[0] ,Event 0 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "MATCHREL14,SCT match reload value register 14"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "CAPCTRL14,SCT capture control register 14"
|
|
bitfld.long 0x00 15. " CAPCON14[15] ,Event 15 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON14[14] ,Event 14 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON14[13] ,Event 13 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON14[12] ,Event 12 causes load of CAP14 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON14[11] ,Event 11 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON14[10] ,Event 10 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON14[9] ,Event 9 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON14[8] ,Event 8 causes load of CAP14 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON14[7] ,Event 7 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON14[6] ,Event 6 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON14[5] ,Event 5 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON14[4] ,Event 4 causes load of CAP14 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON14[3] ,Event 3 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON14[2] ,Event 2 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON14[1] ,Event 1 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON14[0] ,Event 0 causes load of CAP14 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x238++0x03
|
|
line.word 0x00 "MATCHREL14_L,SCT match reload value register 14 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL14_H,SCT match reload value register 14 high counter 16-bit"
|
|
group.word 0x238++0x03
|
|
line.word 0x00 "CAPCTRL14_L,SCT capture control register 14 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON14_L[15] ,Event 15 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON14_L[14] ,Event 14 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON14_L[13] ,Event 13 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON14_L[12] ,Event 12 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON14_L[11] ,Event 11 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON14_L[10] ,Event 10 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON14_L[9] ,Event 9 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON14_L[8] ,Event 8 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON14_L[7] ,Event 7 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON14_L[6] ,Event 6 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON14_L[5] ,Event 5 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON14_L[4] ,Event 4 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON14_L[3] ,Event 3 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON14_L[2] ,Event 2 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON14_L[1] ,Event 1 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON14_L[0] ,Event 0 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL14_H,SCT capture control register 14 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON14_H[15] ,Event 15 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON14_H[14] ,Event 14 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON14_H[13] ,Event 13 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON14_H[12] ,Event 12 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON14_H[11] ,Event 11 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON14_H[10] ,Event 10 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON14_H[9] ,Event 9 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON14_H[8] ,Event 8 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON14_H[7] ,Event 7 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON14_H[6] ,Event 6 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON14_H[5] ,Event 5 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON14_H[4] ,Event 4 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON14_H[3] ,Event 3 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON14_H[2] ,Event 2 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON14_H[1] ,Event 1 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON14_H[0] ,Event 0 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "MATCHREL15,SCT match reload value register 15"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "CAPCTRL15,SCT capture control register 15"
|
|
bitfld.long 0x00 15. " CAPCON15[15] ,Event 15 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON15[14] ,Event 14 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON15[13] ,Event 13 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON15[12] ,Event 12 causes load of CAP15 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON15[11] ,Event 11 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON15[10] ,Event 10 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON15[9] ,Event 9 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON15[8] ,Event 8 causes load of CAP15 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON15[7] ,Event 7 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON15[6] ,Event 6 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON15[5] ,Event 5 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON15[4] ,Event 4 causes load of CAP15 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON15[3] ,Event 3 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON15[2] ,Event 2 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON15[1] ,Event 1 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON15[0] ,Event 0 causes load of CAP15 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x23C++0x03
|
|
line.word 0x00 "MATCHREL15_L,SCT match reload value register 15 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL15_H,SCT match reload value register 15 high counter 16-bit"
|
|
group.word 0x23C++0x03
|
|
line.word 0x00 "CAPCTRL15_L,SCT capture control register 15 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON15_L[15] ,Event 15 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON15_L[14] ,Event 14 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON15_L[13] ,Event 13 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON15_L[12] ,Event 12 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON15_L[11] ,Event 11 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON15_L[10] ,Event 10 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON15_L[9] ,Event 9 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON15_L[8] ,Event 8 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON15_L[7] ,Event 7 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON15_L[6] ,Event 6 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON15_L[5] ,Event 5 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON15_L[4] ,Event 4 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON15_L[3] ,Event 3 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON15_L[2] ,Event 2 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON15_L[1] ,Event 1 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON15_L[0] ,Event 0 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL15_H,SCT capture control register 15 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON15_H[15] ,Event 15 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON15_H[14] ,Event 14 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON15_H[13] ,Event 13 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON15_H[12] ,Event 12 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON15_H[11] ,Event 11 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON15_H[10] ,Event 10 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON15_H[9] ,Event 9 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON15_H[8] ,Event 8 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON15_H[7] ,Event 7 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON15_H[6] ,Event 6 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON15_H[5] ,Event 5 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON15_H[4] ,Event 4 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON15_H[3] ,Event 3 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON15_H[2] ,Event 2 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON15_H[1] ,Event 1 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON15_H[0] ,Event 0 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
endif
|
|
tree.end
|
|
tree "Fractional match reload registers"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "FRACMATREL0,Fractional match reload register 0 for SCT match value register 0"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x240++0x03
|
|
line.word 0x00 "FRACMATREL0_L,Fractional match reload register 0 for SCT match value register 0 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL0_H,Fractional match reload register 0 for SCT match value register 0 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "FRACMATREL1,Fractional match reload register 1 for SCT match value register 1"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x244++0x03
|
|
line.word 0x00 "FRACMATREL1_L,Fractional match reload register 1 for SCT match value register 1 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL1_H,Fractional match reload register 1 for SCT match value register 1 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "FRACMATREL2,Fractional match reload register 2 for SCT match value register 2"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x248++0x03
|
|
line.word 0x00 "FRACMATREL2_L,Fractional match reload register 2 for SCT match value register 2 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL2_H,Fractional match reload register 2 for SCT match value register 2 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "FRACMATREL3,Fractional match reload register 3 for SCT match value register 3"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x24C++0x03
|
|
line.word 0x00 "FRACMATREL3_L,Fractional match reload register 3 for SCT match value register 3 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL3_H,Fractional match reload register 3 for SCT match value register 3 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "FRACMATREL4,Fractional match reload register 4 for SCT match value register 4"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x250++0x03
|
|
line.word 0x00 "FRACMATREL4_L,Fractional match reload register 4 for SCT match value register 4 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT4_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL4_H,Fractional match reload register 4 for SCT match value register 4 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT4_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "FRACMATREL5,Fractional match reload register 5 for SCT match value register 5"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x254++0x03
|
|
line.word 0x00 "FRACMATREL5_L,Fractional match reload register 5 for SCT match value register 5 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT5_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL5_H,Fractional match reload register 5 for SCT match value register 5 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT5_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Event state and control registers"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "EV0_STATE,SCT event state register 0"
|
|
bitfld.long 0x00 31. " STATEMSK0[31] ,State 31 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK0[30] ,State 30 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK0[29] ,State 29 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK0[28] ,State 28 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK0[27] ,State 27 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK0[26] ,State 26 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK0[25] ,State 25 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK0[24] ,State 24 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK0[23] ,State 23 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK0[22] ,State 22 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK0[21] ,State 21 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK0[20] ,State 20 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK0[19] ,State 19 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK0[18] ,State 18 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK0[17] ,State 17 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK0[16] ,State 16 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK0[15] ,State 15 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK0[14] ,State 14 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK0[13] ,State 13 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK0[12] ,State 12 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK0[11] ,State 11 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK0[10] ,State 10 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK0[9] ,State 9 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK0[8] ,State 8 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK0[7] ,State 7 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK0[6] ,State 6 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK0[5] ,State 5 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK0[4] ,State 4 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK0[3] ,State 3 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK0[2] ,State 2 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK0[1] ,State 1 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK0[0] ,State 0 of event 0 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0_CTRL,SCT event control register 0"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0_CTRL,SCT event control register 0"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EV1_STATE,SCT event state register 1"
|
|
bitfld.long 0x00 31. " STATEMSK1[31] ,State 31 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK1[30] ,State 30 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK1[29] ,State 29 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK1[28] ,State 28 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK1[27] ,State 27 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK1[26] ,State 26 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK1[25] ,State 25 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK1[24] ,State 24 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK1[23] ,State 23 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK1[22] ,State 22 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK1[21] ,State 21 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK1[20] ,State 20 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK1[19] ,State 19 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK1[18] ,State 18 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK1[17] ,State 17 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK1[16] ,State 16 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK1[15] ,State 15 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK1[14] ,State 14 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK1[13] ,State 13 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK1[12] ,State 12 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK1[11] ,State 11 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK1[10] ,State 10 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK1[9] ,State 9 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK1[8] ,State 8 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK1[7] ,State 7 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK1[6] ,State 6 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK1[5] ,State 5 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK1[4] ,State 4 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK1[3] ,State 3 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK1[2] ,State 2 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK1[1] ,State 1 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK1[0] ,State 0 of event 1 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1_CTRL,SCT event control register 1"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1_CTRL,SCT event control register 1"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EV2_STATE,SCT event state register 2"
|
|
bitfld.long 0x00 31. " STATEMSK2[31] ,State 31 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK2[30] ,State 30 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK2[29] ,State 29 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK2[28] ,State 28 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK2[27] ,State 27 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK2[26] ,State 26 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK2[25] ,State 25 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK2[24] ,State 24 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK2[23] ,State 23 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK2[22] ,State 22 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK2[21] ,State 21 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK2[20] ,State 20 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK2[19] ,State 19 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK2[18] ,State 18 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK2[17] ,State 17 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK2[16] ,State 16 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK2[15] ,State 15 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK2[14] ,State 14 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK2[13] ,State 13 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK2[12] ,State 12 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK2[11] ,State 11 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK2[10] ,State 10 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK2[9] ,State 9 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK2[8] ,State 8 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK2[7] ,State 7 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK2[6] ,State 6 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK2[5] ,State 5 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK2[4] ,State 4 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK2[3] ,State 3 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK2[2] ,State 2 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK2[1] ,State 1 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK2[0] ,State 0 of event 2 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2_CTRL,SCT event control register 2"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2_CTRL,SCT event control register 2"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EV3_STATE,SCT event state register 3"
|
|
bitfld.long 0x00 31. " STATEMSK3[31] ,State 31 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK3[30] ,State 30 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK3[29] ,State 29 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK3[28] ,State 28 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK3[27] ,State 27 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK3[26] ,State 26 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK3[25] ,State 25 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK3[24] ,State 24 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK3[23] ,State 23 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK3[22] ,State 22 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK3[21] ,State 21 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK3[20] ,State 20 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK3[19] ,State 19 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK3[18] ,State 18 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK3[17] ,State 17 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK3[16] ,State 16 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK3[15] ,State 15 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK3[14] ,State 14 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK3[13] ,State 13 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK3[12] ,State 12 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK3[11] ,State 11 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK3[10] ,State 10 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK3[9] ,State 9 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK3[8] ,State 8 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK3[7] ,State 7 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK3[6] ,State 6 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK3[5] ,State 5 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK3[4] ,State 4 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK3[3] ,State 3 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK3[2] ,State 2 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK3[1] ,State 1 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK3[0] ,State 0 of event 3 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3_CTRL,SCT event control register 3"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3_CTRL,SCT event control register 3"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EV4_STATE,SCT event state register 4"
|
|
bitfld.long 0x00 31. " STATEMSK4[31] ,State 31 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK4[30] ,State 30 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK4[29] ,State 29 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK4[28] ,State 28 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK4[27] ,State 27 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK4[26] ,State 26 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK4[25] ,State 25 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK4[24] ,State 24 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK4[23] ,State 23 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK4[22] ,State 22 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK4[21] ,State 21 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK4[20] ,State 20 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK4[19] ,State 19 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK4[18] ,State 18 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK4[17] ,State 17 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK4[16] ,State 16 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK4[15] ,State 15 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK4[14] ,State 14 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK4[13] ,State 13 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK4[12] ,State 12 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK4[11] ,State 11 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK4[10] ,State 10 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK4[9] ,State 9 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK4[8] ,State 8 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK4[7] ,State 7 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK4[6] ,State 6 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK4[5] ,State 5 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK4[4] ,State 4 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK4[3] ,State 3 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK4[2] ,State 2 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK4[1] ,State 1 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK4[0] ,State 0 of event 4 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4_CTRL,SCT event control register 4"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4_CTRL,SCT event control register 4"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EV5_STATE,SCT event state register 5"
|
|
bitfld.long 0x00 31. " STATEMSK5[31] ,State 31 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK5[30] ,State 30 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK5[29] ,State 29 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK5[28] ,State 28 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK5[27] ,State 27 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK5[26] ,State 26 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK5[25] ,State 25 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK5[24] ,State 24 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK5[23] ,State 23 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK5[22] ,State 22 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK5[21] ,State 21 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK5[20] ,State 20 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK5[19] ,State 19 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK5[18] ,State 18 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK5[17] ,State 17 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK5[16] ,State 16 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK5[15] ,State 15 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK5[14] ,State 14 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK5[13] ,State 13 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK5[12] ,State 12 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK5[11] ,State 11 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK5[10] ,State 10 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK5[9] ,State 9 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK5[8] ,State 8 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK5[7] ,State 7 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK5[6] ,State 6 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK5[5] ,State 5 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK5[4] ,State 4 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK5[3] ,State 3 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK5[2] ,State 2 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK5[1] ,State 1 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK5[0] ,State 0 of event 5 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5_CTRL,SCT event control register 5"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5_CTRL,SCT event control register 5"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EV6_STATE,SCT event state register 6"
|
|
bitfld.long 0x00 31. " STATEMSK6[31] ,State 31 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK6[30] ,State 30 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK6[29] ,State 29 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK6[28] ,State 28 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK6[27] ,State 27 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK6[26] ,State 26 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK6[25] ,State 25 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK6[24] ,State 24 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK6[23] ,State 23 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK6[22] ,State 22 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK6[21] ,State 21 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK6[20] ,State 20 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK6[19] ,State 19 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK6[18] ,State 18 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK6[17] ,State 17 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK6[16] ,State 16 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK6[15] ,State 15 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK6[14] ,State 14 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK6[13] ,State 13 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK6[12] ,State 12 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK6[11] ,State 11 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK6[10] ,State 10 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK6[9] ,State 9 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK6[8] ,State 8 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK6[7] ,State 7 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK6[6] ,State 6 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK6[5] ,State 5 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK6[4] ,State 4 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK6[3] ,State 3 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK6[2] ,State 2 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK6[1] ,State 1 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK6[0] ,State 0 of event 6 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6_CTRL,SCT event control register 6"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6_CTRL,SCT event control register 6"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EV7_STATE,SCT event state register 7"
|
|
bitfld.long 0x00 31. " STATEMSK7[31] ,State 31 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK7[30] ,State 30 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK7[29] ,State 29 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK7[28] ,State 28 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK7[27] ,State 27 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK7[26] ,State 26 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK7[25] ,State 25 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK7[24] ,State 24 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK7[23] ,State 23 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK7[22] ,State 22 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK7[21] ,State 21 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK7[20] ,State 20 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK7[19] ,State 19 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK7[18] ,State 18 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK7[17] ,State 17 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK7[16] ,State 16 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK7[15] ,State 15 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK7[14] ,State 14 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK7[13] ,State 13 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK7[12] ,State 12 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK7[11] ,State 11 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK7[10] ,State 10 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK7[9] ,State 9 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK7[8] ,State 8 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK7[7] ,State 7 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK7[6] ,State 6 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK7[5] ,State 5 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK7[4] ,State 4 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK7[3] ,State 3 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK7[2] ,State 2 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK7[1] ,State 1 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK7[0] ,State 0 of event 7 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7_CTRL,SCT event control register 7"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7_CTRL,SCT event control register 7"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "EV8_STATE,SCT event state register 8"
|
|
bitfld.long 0x00 31. " STATEMSK8[31] ,State 31 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK8[30] ,State 30 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK8[29] ,State 29 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK8[28] ,State 28 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK8[27] ,State 27 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK8[26] ,State 26 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK8[25] ,State 25 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK8[24] ,State 24 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK8[23] ,State 23 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK8[22] ,State 22 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK8[21] ,State 21 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK8[20] ,State 20 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK8[19] ,State 19 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK8[18] ,State 18 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK8[17] ,State 17 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK8[16] ,State 16 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK8[15] ,State 15 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK8[14] ,State 14 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK8[13] ,State 13 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK8[12] ,State 12 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK8[11] ,State 11 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK8[10] ,State 10 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK8[9] ,State 9 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK8[8] ,State 8 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK8[7] ,State 7 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK8[6] ,State 6 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK8[5] ,State 5 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK8[4] ,State 4 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK8[3] ,State 3 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK8[2] ,State 2 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK8[1] ,State 1 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK8[0] ,State 0 of event 8 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8_CTRL,SCT event control register 8"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8_CTRL,SCT event control register 8"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EV9_STATE,SCT event state register 9"
|
|
bitfld.long 0x00 31. " STATEMSK9[31] ,State 31 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK9[30] ,State 30 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK9[29] ,State 29 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK9[28] ,State 28 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK9[27] ,State 27 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK9[26] ,State 26 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK9[25] ,State 25 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK9[24] ,State 24 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK9[23] ,State 23 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK9[22] ,State 22 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK9[21] ,State 21 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK9[20] ,State 20 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK9[19] ,State 19 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK9[18] ,State 18 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK9[17] ,State 17 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK9[16] ,State 16 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK9[15] ,State 15 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK9[14] ,State 14 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK9[13] ,State 13 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK9[12] ,State 12 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK9[11] ,State 11 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK9[10] ,State 10 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK9[9] ,State 9 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK9[8] ,State 8 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK9[7] ,State 7 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK9[6] ,State 6 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK9[5] ,State 5 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK9[4] ,State 4 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK9[3] ,State 3 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK9[2] ,State 2 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK9[1] ,State 1 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK9[0] ,State 0 of event 9 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9_CTRL,SCT event control register 9"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9_CTRL,SCT event control register 9"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline ""
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "EV10_STATE,SCT event state register 10"
|
|
bitfld.long 0x00 31. " STATEMSK10[31] ,State 31 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK10[30] ,State 30 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK10[29] ,State 29 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK10[28] ,State 28 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK10[27] ,State 27 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK10[26] ,State 26 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK10[25] ,State 25 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK10[24] ,State 24 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK10[23] ,State 23 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK10[22] ,State 22 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK10[21] ,State 21 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK10[20] ,State 20 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK10[19] ,State 19 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK10[18] ,State 18 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK10[17] ,State 17 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK10[16] ,State 16 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK10[15] ,State 15 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK10[14] ,State 14 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK10[13] ,State 13 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK10[12] ,State 12 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK10[11] ,State 11 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK10[10] ,State 10 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK10[9] ,State 9 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK10[8] ,State 8 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK10[7] ,State 7 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK10[6] ,State 6 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK10[5] ,State 5 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK10[4] ,State 4 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK10[3] ,State 3 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK10[2] ,State 2 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK10[1] ,State 1 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK10[0] ,State 0 of event 10 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x350+0x4)++0x03
|
|
line.long 0x00 "EV10_CTRL,SCT event control register 10"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 10" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x350+0x4)++0x03
|
|
line.long 0x00 "EV10_CTRL,SCT event control register 10"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 10" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "EV11_STATE,SCT event state register 11"
|
|
bitfld.long 0x00 31. " STATEMSK11[31] ,State 31 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK11[30] ,State 30 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK11[29] ,State 29 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK11[28] ,State 28 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK11[27] ,State 27 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK11[26] ,State 26 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK11[25] ,State 25 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK11[24] ,State 24 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK11[23] ,State 23 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK11[22] ,State 22 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK11[21] ,State 21 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK11[20] ,State 20 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK11[19] ,State 19 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK11[18] ,State 18 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK11[17] ,State 17 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK11[16] ,State 16 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK11[15] ,State 15 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK11[14] ,State 14 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK11[13] ,State 13 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK11[12] ,State 12 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK11[11] ,State 11 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK11[10] ,State 10 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK11[9] ,State 9 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK11[8] ,State 8 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK11[7] ,State 7 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK11[6] ,State 6 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK11[5] ,State 5 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK11[4] ,State 4 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK11[3] ,State 3 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK11[2] ,State 2 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK11[1] ,State 1 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK11[0] ,State 0 of event 11 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x358+0x4)++0x03
|
|
line.long 0x00 "EV11_CTRL,SCT event control register 11"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 11" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x358+0x4)++0x03
|
|
line.long 0x00 "EV11_CTRL,SCT event control register 11"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 11" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "EV12_STATE,SCT event state register 12"
|
|
bitfld.long 0x00 31. " STATEMSK12[31] ,State 31 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK12[30] ,State 30 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK12[29] ,State 29 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK12[28] ,State 28 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK12[27] ,State 27 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK12[26] ,State 26 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK12[25] ,State 25 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK12[24] ,State 24 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK12[23] ,State 23 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK12[22] ,State 22 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK12[21] ,State 21 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK12[20] ,State 20 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK12[19] ,State 19 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK12[18] ,State 18 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK12[17] ,State 17 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK12[16] ,State 16 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK12[15] ,State 15 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK12[14] ,State 14 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK12[13] ,State 13 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK12[12] ,State 12 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK12[11] ,State 11 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK12[10] ,State 10 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK12[9] ,State 9 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK12[8] ,State 8 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK12[7] ,State 7 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK12[6] ,State 6 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK12[5] ,State 5 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK12[4] ,State 4 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK12[3] ,State 3 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK12[2] ,State 2 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK12[1] ,State 1 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK12[0] ,State 0 of event 12 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x360+0x4)++0x03
|
|
line.long 0x00 "EV12_CTRL,SCT event control register 12"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 12" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x360+0x4)++0x03
|
|
line.long 0x00 "EV12_CTRL,SCT event control register 12"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 12" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "EV13_STATE,SCT event state register 13"
|
|
bitfld.long 0x00 31. " STATEMSK13[31] ,State 31 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK13[30] ,State 30 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK13[29] ,State 29 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK13[28] ,State 28 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK13[27] ,State 27 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK13[26] ,State 26 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK13[25] ,State 25 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK13[24] ,State 24 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK13[23] ,State 23 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK13[22] ,State 22 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK13[21] ,State 21 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK13[20] ,State 20 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK13[19] ,State 19 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK13[18] ,State 18 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK13[17] ,State 17 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK13[16] ,State 16 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK13[15] ,State 15 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK13[14] ,State 14 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK13[13] ,State 13 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK13[12] ,State 12 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK13[11] ,State 11 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK13[10] ,State 10 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK13[9] ,State 9 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK13[8] ,State 8 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK13[7] ,State 7 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK13[6] ,State 6 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK13[5] ,State 5 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK13[4] ,State 4 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK13[3] ,State 3 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK13[2] ,State 2 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK13[1] ,State 1 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK13[0] ,State 0 of event 13 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x368+0x4)++0x03
|
|
line.long 0x00 "EV13_CTRL,SCT event control register 13"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 13" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x368+0x4)++0x03
|
|
line.long 0x00 "EV13_CTRL,SCT event control register 13"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 13" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "EV14_STATE,SCT event state register 14"
|
|
bitfld.long 0x00 31. " STATEMSK14[31] ,State 31 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK14[30] ,State 30 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK14[29] ,State 29 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK14[28] ,State 28 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK14[27] ,State 27 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK14[26] ,State 26 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK14[25] ,State 25 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK14[24] ,State 24 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK14[23] ,State 23 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK14[22] ,State 22 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK14[21] ,State 21 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK14[20] ,State 20 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK14[19] ,State 19 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK14[18] ,State 18 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK14[17] ,State 17 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK14[16] ,State 16 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK14[15] ,State 15 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK14[14] ,State 14 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK14[13] ,State 13 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK14[12] ,State 12 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK14[11] ,State 11 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK14[10] ,State 10 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK14[9] ,State 9 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK14[8] ,State 8 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK14[7] ,State 7 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK14[6] ,State 6 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK14[5] ,State 5 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK14[4] ,State 4 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK14[3] ,State 3 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK14[2] ,State 2 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK14[1] ,State 1 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK14[0] ,State 0 of event 14 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x370+0x4)++0x03
|
|
line.long 0x00 "EV14_CTRL,SCT event control register 14"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 14" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x370+0x4)++0x03
|
|
line.long 0x00 "EV14_CTRL,SCT event control register 14"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 14" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "EV15_STATE,SCT event state register 15"
|
|
bitfld.long 0x00 31. " STATEMSK15[31] ,State 31 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK15[30] ,State 30 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK15[29] ,State 29 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK15[28] ,State 28 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK15[27] ,State 27 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK15[26] ,State 26 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK15[25] ,State 25 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK15[24] ,State 24 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK15[23] ,State 23 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK15[22] ,State 22 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK15[21] ,State 21 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK15[20] ,State 20 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK15[19] ,State 19 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK15[18] ,State 18 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK15[17] ,State 17 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK15[16] ,State 16 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK15[15] ,State 15 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK15[14] ,State 14 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK15[13] ,State 13 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK15[12] ,State 12 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK15[11] ,State 11 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK15[10] ,State 10 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK15[9] ,State 9 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK15[8] ,State 8 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK15[7] ,State 7 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK15[6] ,State 6 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK15[5] ,State 5 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK15[4] ,State 4 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK15[3] ,State 3 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK15[2] ,State 2 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK15[1] ,State 1 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK15[0] ,State 0 of event 15 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C018000)))&0x1)==0x1)
|
|
group.long (0x378+0x4)++0x03
|
|
line.long 0x00 "EV15_CTRL,SCT event control register 15"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 15" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x378+0x4)++0x03
|
|
line.long 0x00 "EV15_CTRL,SCT event control register 15"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 15" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Output set/clear registers"
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OUT0_SET,SCT output 0 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 0" "Not set,Set"
|
|
line.long 0x04 "OUT0_CLR,SCT output 0 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 0" "Not set,Set"
|
|
group.long 0x508++0x07
|
|
line.long 0x00 "OUT1_SET,SCT output 1 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 1" "Not set,Set"
|
|
line.long 0x04 "OUT1_CLR,SCT output 1 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 1" "Not set,Set"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OUT2_SET,SCT output 2 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 2" "Not set,Set"
|
|
line.long 0x04 "OUT2_CLR,SCT output 2 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 2" "Not set,Set"
|
|
group.long 0x518++0x07
|
|
line.long 0x00 "OUT3_SET,SCT output 3 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 3" "Not set,Set"
|
|
line.long 0x04 "OUT3_CLR,SCT output 3 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 3" "Not set,Set"
|
|
group.long 0x520++0x07
|
|
line.long 0x00 "OUT4_SET,SCT output 4 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 4" "Not set,Set"
|
|
line.long 0x04 "OUT4_CLR,SCT output 4 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 4" "Not set,Set"
|
|
group.long 0x528++0x07
|
|
line.long 0x00 "OUT5_SET,SCT output 5 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 5" "Not set,Set"
|
|
line.long 0x04 "OUT5_CLR,SCT output 5 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 5" "Not set,Set"
|
|
group.long 0x530++0x07
|
|
line.long 0x00 "OUT6_SET,SCT output 6 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 6" "Not set,Set"
|
|
line.long 0x04 "OUT6_CLR,SCT output 6 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 6" "Not set,Set"
|
|
group.long 0x538++0x07
|
|
line.long 0x00 "OUT7_SET,SCT output 7 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 7" "Not set,Set"
|
|
line.long 0x04 "OUT7_CLR,SCT output 7 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 7" "Not set,Set"
|
|
group.long 0x540++0x07
|
|
line.long 0x00 "OUT8_SET,SCT output 8 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 8" "Not set,Set"
|
|
line.long 0x04 "OUT8_CLR,SCT output 8 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 8" "Not set,Set"
|
|
group.long 0x548++0x07
|
|
line.long 0x00 "OUT9_SET,SCT output 9 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 9" "Not set,Set"
|
|
line.long 0x04 "OUT9_CLR,SCT output 9 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 9" "Not set,Set"
|
|
tree.end
|
|
width 0x0b
|
|
tree.end
|
|
tree "SCTimer 1"
|
|
base ad:0x1C01C000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,SCT configuration register"
|
|
bitfld.long 0x00 18. " AUTOLIMIT_H ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " NORELOAD_H ,Prevent the higher match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
bitfld.long 0x00 7. " NORELOAD_L ,Prevent the lower match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input (0:7)" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,Rising 4,Falling 4,Rising 5,Falling 5,Rising 6,Falling 6,Rising 7,Falling 7"
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System,Prescaled system,SCT input,Prescaled SCT input"
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operate as unified 32-bit counter" "Not unified,Unified"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "CTRL,SCT control register"
|
|
hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock"
|
|
bitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down"
|
|
line.long 0x04 "LIMIT,SCT limit register"
|
|
bitfld.long 0x04 15. " LIMMSK[15] ,Event 15 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 14. " LIMMSK[14] ,Event 14 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 13. " LIMMSK[13] ,Event 13 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 12. " LIMMSK[12] ,Event 12 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LIMMSK[11] ,Event 11 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 10. " LIMMSK[10] ,Event 10 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 9. " LIMMSK[9] ,Event 9 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 8. " LIMMSK[8] ,Event 8 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LIMMSK[7] ,Event 7 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 6. " LIMMSK[6] ,Event 6 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 5. " LIMMSK[5] ,Event 5 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 4. " LIMMSK[4] ,Event 4 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LIMMSK[3] ,Event 3 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 2. " LIMMSK[2] ,Event 2 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 1. " LIMMSK[1] ,Event 1 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 0. " LIMMSK[0] ,Event 0 use as counter limit for unified counter" "Not used,Used"
|
|
line.long 0x08 "HALT,SCT halt condition register"
|
|
bitfld.long 0x08 15. " HALTMSK[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 14. " HALTMSK[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 13. " HALTMSK[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 12. " HALTMSK[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HALTMSK[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 10. " HALTMSK[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 9. " HALTMSK[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 8. " HALTMSK[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HALTMSK[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 6. " HALTMSK[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 5. " HALTMSK[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 4. " HALTMSK[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HALTMSK[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 2. " HALTMSK[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 1. " HALTMSK[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 0. " HALTMSK[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x0C "STOP,SCT stop condition register"
|
|
bitfld.long 0x0C 15. " STOPMSK[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 14. " STOPMSK[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 13. " STOPMSK[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 12. " STOPMSK[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " STOPMSK[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 10. " STOPMSK[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 9. " STOPMSK[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 8. " STOPMSK[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " STOPMSK[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 6. " STOPMSK[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 5. " STOPMSK[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 4. " STOPMSK[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " STOPMSK[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 2. " STOPMSK[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 1. " STOPMSK[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 0. " STOPMSK[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x10 "START,SCT start condition register"
|
|
bitfld.long 0x10 15. " STARTMSK[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 14. " STARTMSK[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 13. " STARTMSK[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 12. " STARTMSK[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 11. " STARTMSK[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 10. " STARTMSK[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 9. " STARTMSK[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 8. " STARTMSK[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 7. " STARTMSK[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 6. " STARTMSK[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 5. " STARTMSK[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 4. " STARTMSK[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 3. " STARTMSK[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 2. " STARTMSK[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 1. " STARTMSK[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 0. " STARTMSK[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
line.long 0x14 "DITHER,SCT dither condition register"
|
|
bitfld.long 0x14 15. " DITHMSK[15] ,Event 15 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 14. " DITHMSK[14] ,Event 14 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 13. " DITHMSK[13] ,Event 13 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 12. " DITHMSK[12] ,Event 12 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DITHMSK[11] ,Event 11 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 10. " DITHMSK[10] ,Event 10 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 9. " DITHMSK[9] ,Event 9 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 8. " DITHMSK[8] ,Event 8 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DITHMSK[7] ,Event 7 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 6. " DITHMSK[6] ,Event 6 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 5. " DITHMSK[5] ,Event 5 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 4. " DITHMSK[4] ,Event 4 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DITHMSK[3] ,Event 3 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 2. " DITHMSK[2] ,Event 2 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 1. " DITHMSK[1] ,Event 1 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.long 0x14 0. " DITHMSK[0] ,Event 0 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "COUNT,SCT counter register"
|
|
line.long 0x04 "STATE,SCT state register"
|
|
bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 23. " SIN7 ,Input 7 state" "Low,High"
|
|
bitfld.long 0x00 22. " SIN6 ,Input 6 state" "Low,High"
|
|
bitfld.long 0x00 21. " SIN5 ,Input 5 state" "Low,High"
|
|
bitfld.long 0x00 20. " SIN4 ,Input 4 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AIN7 ,Input 7 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 6. " AIN6 ,Input 6 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 5. " AIN5 ,Input 5 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 4. " AIN4 ,Input 4 state(Direct read)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT match/capture registers mode register"
|
|
bitfld.long 0x00 15. " REGMOD[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 14. " REGMOD[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 13. " REGMOD[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 12. " REGMOD[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REGMOD[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 10. " REGMOD[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 9. " REGMOD[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 8. " REGMOD[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REGMOD[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 6. " REGMOD[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 5. " REGMOD[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 4. " REGMOD[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REGMOD[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 2. " REGMOD[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 1. " REGMOD[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 0. " REGMOD[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
else
|
|
group.word 0x04++0x17
|
|
line.word 0x00 "CTRL_L,SCT control lower 16-bit register"
|
|
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock"
|
|
bitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down"
|
|
line.word 0x02 "CTRL_H,SCT control higher 16-bit register"
|
|
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock"
|
|
bitfld.word 0x02 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x02 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x02 2. " HALT_H ,H counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x02 1. " STOP_H ,H counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x02 0. " DOWN_H ,H counter counting down" "Counting up,Counting down"
|
|
line.word 0x04 "LIMIT_L,SCT limit higher 16-bit register"
|
|
bitfld.word 0x04 15. " LIMMSK_L[15] ,Event 15 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 14. " LIMMSK_L[14] ,Event 14 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 13. " LIMMSK_L[13] ,Event 13 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 12. " LIMMSK_L[12] ,Event 12 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 11. " LIMMSK_L[11] ,Event 11 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 10. " LIMMSK_L[10] ,Event 10 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 9. " LIMMSK_L[9] ,Event 9 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 8. " LIMMSK_L[8] ,Event 8 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 7. " LIMMSK_L[7] ,Event 7 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 6. " LIMMSK_L[6] ,Event 6 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 5. " LIMMSK_L[5] ,Event 5 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 4. " LIMMSK_L[4] ,Event 4 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 3. " LIMMSK_L[3] ,Event 3 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 2. " LIMMSK_L[2] ,Event 2 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 1. " LIMMSK_L[1] ,Event 1 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 0. " LIMMSK_L[0] ,Event 0 use as counter limit for L counter" "Not used,Used"
|
|
line.word 0x06 "LIMIT_H,SCT limit lower 16-bit register"
|
|
bitfld.word 0x06 15. " LIMMSK_H[15] ,Event 15 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 14. " LIMMSK_H[14] ,Event 14 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 13. " LIMMSK_H[13] ,Event 13 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 12. " LIMMSK_H[12] ,Event 12 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 11. " LIMMSK_H[11] ,Event 11 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 10. " LIMMSK_H[10] ,Event 10 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 9. " LIMMSK_H[9] ,Event 9 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 8. " LIMMSK_H[8] ,Event 8 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 7. " LIMMSK_H[7] ,Event 7 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 6. " LIMMSK_H[6] ,Event 6 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 5. " LIMMSK_H[5] ,Event 5 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 4. " LIMMSK_H[4] ,Event 4 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 3. " LIMMSK_H[3] ,Event 3 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 2. " LIMMSK_H[2] ,Event 2 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 1. " LIMMSK_H[1] ,Event 1 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 0. " LIMMSK_H[0] ,Event 0 use as counter limit for H counter" "Not used,Used"
|
|
line.word 0x08 "HALT_L,SCT halt condition lower 16-bit register"
|
|
bitfld.word 0x08 15. " HALTMSK_L[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 14. " HALTMSK_L[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 13. " HALTMSK_L[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 12. " HALTMSK_L[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 11. " HALTMSK_L[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 10. " HALTMSK_L[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 9. " HALTMSK_L[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 8. " HALTMSK_L[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 7. " HALTMSK_L[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 6. " HALTMSK_L[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 5. " HALTMSK_L[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 4. " HALTMSK_L[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 3. " HALTMSK_L[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 2. " HALTMSK_L[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 1. " HALTMSK_L[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 0. " HALTMSK_L[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0A "HALT_H,SCT halt condition higher 16-bit register"
|
|
bitfld.word 0x0A 15. " HALTMSK_H[15] ,Event 15 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 14. " HALTMSK_H[14] ,Event 14 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 13. " HALTMSK_H[13] ,Event 13 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 12. " HALTMSK_H[12] ,Event 12 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 11. " HALTMSK_H[11] ,Event 11 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 10. " HALTMSK_H[10] ,Event 10 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 9. " HALTMSK_H[9] ,Event 9 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 8. " HALTMSK_H[8] ,Event 8 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 7. " HALTMSK_H[7] ,Event 7 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 6. " HALTMSK_H[6] ,Event 6 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 5. " HALTMSK_H[5] ,Event 5 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 4. " HALTMSK_H[4] ,Event 4 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 3. " HALTMSK_H[3] ,Event 3 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 2. " HALTMSK_H[2] ,Event 2 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 1. " HALTMSK_H[1] ,Event 1 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 0. " HALTMSK_H[0] ,Event 0 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x0C "STOP_L,SCT stop condition lower 16-bit register"
|
|
bitfld.word 0x0C 15. " STOPMSK_L[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 14. " STOPMSK_L[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 13. " STOPMSK_L[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 12. " STOPMSK_L[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 11. " STOPMSK_L[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 10. " STOPMSK_L[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 9. " STOPMSK_L[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 8. " STOPMSK_L[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 7. " STOPMSK_L[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 6. " STOPMSK_L[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 5. " STOPMSK_L[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 4. " STOPMSK_L[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 3. " STOPMSK_L[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 2. " STOPMSK_L[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 1. " STOPMSK_L[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 0. " STOPMSK_L[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0E "STOP_H,SCT stop condition higher 16-bit register"
|
|
bitfld.word 0x0E 15. " STOPMSK_H[15] ,Event 15 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 14. " STOPMSK_H[14] ,Event 14 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 13. " STOPMSK_H[13] ,Event 13 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 12. " STOPMSK_H[12] ,Event 12 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 11. " STOPMSK_H[11] ,Event 11 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 10. " STOPMSK_H[10] ,Event 10 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 9. " STOPMSK_H[9] ,Event 9 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 8. " STOPMSK_H[8] ,Event 8 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 7. " STOPMSK_H[7] ,Event 7 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 6. " STOPMSK_H[6] ,Event 6 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 5. " STOPMSK_H[5] ,Event 5 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 4. " STOPMSK_H[4] ,Event 4 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 3. " STOPMSK_H[3] ,Event 3 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 2. " STOPMSK_H[2] ,Event 2 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 1. " STOPMSK_H[1] ,Event 1 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 0. " STOPMSK_H[0] ,Event 0 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x10 "START_L,SCT start condition lower 16-bit register"
|
|
bitfld.word 0x10 15. " STARTMSK_L[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 14. " STARTMSK_L[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 13. " STARTMSK_L[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 12. " STARTMSK_L[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 11. " STARTMSK_L[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 10. " STARTMSK_L[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 9. " STARTMSK_L[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 8. " STARTMSK_L[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 7. " STARTMSK_L[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 6. " STARTMSK_L[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 5. " STARTMSK_L[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 4. " STARTMSK_L[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 3. " STARTMSK_L[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 2. " STARTMSK_L[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 1. " STARTMSK_L[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 0. " STARTMSK_L[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
line.word 0x12 "START_H,SCT start condition higher 16-bit register"
|
|
bitfld.word 0x12 15. " STARTMSK_H[15] ,Event 15 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 14. " STARTMSK_H[14] ,Event 14 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 13. " STARTMSK_H[13] ,Event 13 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 12. " STARTMSK_H[12] ,Event 12 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 11. " STARTMSK_H[11] ,Event 11 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 10. " STARTMSK_H[10] ,Event 10 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 9. " STARTMSK_H[9] ,Event 9 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 8. " STARTMSK_H[8] ,Event 8 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 7. " STARTMSK_H[7] ,Event 7 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 6. " STARTMSK_H[6] ,Event 6 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 5. " STARTMSK_H[5] ,Event 5 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 4. " STARTMSK_H[4] ,Event 4 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 3. " STARTMSK_H[3] ,Event 3 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 2. " STARTMSK_H[2] ,Event 2 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 1. " STARTMSK_H[1] ,Event 1 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 0. " STARTMSK_H[0] ,Event 0 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
line.word 0x14 "DITHER_L,SCT dither condition lower 16-bit register"
|
|
bitfld.word 0x14 15. " DITHMSK_L[15] ,Event 15 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 14. " DITHMSK_L[14] ,Event 14 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 13. " DITHMSK_L[13] ,Event 13 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 12. " DITHMSK_L[12] ,Event 12 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x14 11. " DITHMSK_L[11] ,Event 11 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 10. " DITHMSK_L[10] ,Event 10 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 9. " DITHMSK_L[9] ,Event 9 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 8. " DITHMSK_L[8] ,Event 8 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x14 7. " DITHMSK_L[7] ,Event 7 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 6. " DITHMSK_L[6] ,Event 6 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 5. " DITHMSK_L[5] ,Event 5 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 4. " DITHMSK_L[4] ,Event 4 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x14 3. " DITHMSK_L[3] ,Event 3 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 2. " DITHMSK_L[2] ,Event 2 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 1. " DITHMSK_L[1] ,Event 1 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x14 0. " DITHMSK_L[0] ,Event 0 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
line.word 0x16 "DITHER_H,SCT dither condition higher 16-bit register"
|
|
bitfld.word 0x16 15. " DITHMSK_H[15] ,Event 15 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 14. " DITHMSK_H[14] ,Event 14 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 13. " DITHMSK_H[13] ,Event 13 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 12. " DITHMSK_H[12] ,Event 12 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x16 11. " DITHMSK_H[11] ,Event 11 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 10. " DITHMSK_H[10] ,Event 10 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 9. " DITHMSK_H[9] ,Event 9 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 8. " DITHMSK_H[8] ,Event 8 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x16 7. " DITHMSK_H[7] ,Event 7 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 6. " DITHMSK_H[6] ,Event 6 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 5. " DITHMSK_H[5] ,Event 5 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 4. " DITHMSK_H[4] ,Event 4 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x16 3. " DITHMSK_H[3] ,Event 3 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 2. " DITHMSK_H[2] ,Event 2 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 1. " DITHMSK_H[1] ,Event 1 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
bitfld.word 0x16 0. " DITHMSK_H[0] ,Event 0 causes the dither engine to advance to the next element" "Not occurred,Occurred"
|
|
group.word 0x40++0x7
|
|
line.word 0x00 "COUNT_L,SCT counter register low counter 16-bit"
|
|
line.word 0x02 "COUNT_H,SCT counter register high counter 16-bit"
|
|
line.word 0x04 "STATE_L,SCT state register low counter 16-bit"
|
|
bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x06 "STATE_L,SCT state register high counter 16-bit"
|
|
bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 23. " SIN7 ,Input 7 state" "Low,High"
|
|
bitfld.long 0x00 22. " SIN6 ,Input 6 state" "Low,High"
|
|
bitfld.long 0x00 21. " SIN5 ,Input 5 state" "Low,High"
|
|
bitfld.long 0x00 20. " SIN4 ,Input 4 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AIN7 ,Input 7 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 6. " AIN6 ,Input 6 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 5. " AIN5 ,Input 5 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 4. " AIN4 ,Input 4 state(Direct read)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.word 0x4C++0x03
|
|
line.word 0x00 "REGMODE_L,SCT match/capture registers mode register low counter 16-bit"
|
|
bitfld.word 0x00 15. " REGMOD_L[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 14. " REGMOD_L[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 13. " REGMOD_L[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 12. " REGMOD_L[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 11. " REGMOD_L[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 10. " REGMOD_L[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 9. " REGMOD_L[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 8. " REGMOD_L[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 7. " REGMOD_L[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 6. " REGMOD_L[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 5. " REGMOD_L[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 4. " REGMOD_L[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 3. " REGMOD_L[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 2. " REGMOD_L[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 1. " REGMOD_L[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 0. " REGMOD_L[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
line.word 0x02 "REGMODE_H,SCT match/capture registers mode register high counter 16-bit"
|
|
bitfld.word 0x02 15. " REGMOD_H[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 14. " REGMOD_H[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 13. " REGMOD_H[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 12. " REGMOD_H[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 11. " REGMOD_H[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 10. " REGMOD_H[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 9. " REGMOD_H[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 8. " REGMOD_H[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 7. " REGMOD_H[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 6. " REGMOD_H[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 5. " REGMOD_H[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 4. " REGMOD_H[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 3. " REGMOD_H[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 2. " REGMOD_H[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 1. " REGMOD_H[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 0. " REGMOD_H[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT output register"
|
|
bitfld.long 0x00 9. " OUT[9] ,Set high on output 9" "Low,High"
|
|
bitfld.long 0x00 8. " OUT[8] ,Set high on output 8" "Low,High"
|
|
bitfld.long 0x00 7. " OUT[7] ,Set high on output 7" "Low,High"
|
|
bitfld.long 0x00 6. " OUT[6] ,Set high on output 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OUT[5] ,Set high on output 5" "Low,High"
|
|
bitfld.long 0x00 4. " OUT[4] ,Set high on output 4" "Low,High"
|
|
bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT[2] ,Set high on output 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT[1] ,Set high on output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT[0] ,Set high on output 0" "Low,High"
|
|
line.long 0x04 "OUTPUTDIRCTRL,SCT output counter direction control register"
|
|
bitfld.long 0x04 18.--19. " SETCLR9 ,Set/clear operation on output 9 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 16.--17. " SETCLR8 ,Set/clear operation on output 8 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 14.--15. " SETCLR7 ,Set/clear operation on output 7 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 12.--13. " SETCLR6 ,Set/clear operation on output 6 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " SETCLR5 ,Set/clear operation on output 5 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 8.--9. " SETCLR4 ,Set/clear operation on output 4 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 6.--7. " SETCLR3 ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 4.--5. " SETCLR2 ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SETCLR1 ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 0.--1. " SETCLR0 ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
line.long 0x08 "RES,SCT conflict resolution register"
|
|
bitfld.long 0x08 18.--19. " O9RES ,Effect of simultaneous set and clear on output 9" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 16.--17. " O8RES ,Effect of simultaneous set and clear on output 8" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 14.--15. " O7RES ,Effect of simultaneous set and clear on output 7" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 12.--13. " O6RES ,Effect of simultaneous set and clear on output 6" "No change,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle"
|
|
line.long 0x0c "DMAREQ0,SCT DMA request 0 register"
|
|
rbitfld.long 0x0c 31. " DRQ0 ,Indicates the state of DMA Request 0" "Low,High"
|
|
bitfld.long 0x0c 30. " DRL0 ,SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x0c 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 14. " DEV_0[14] ,Event 14 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " DEV_0[13] ,Event 13 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 12. " DEV_0[12] ,Event 12 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 11. " DEV_0[11] ,Event 11 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 10. " DEV_0[10] ,Event 10 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " DEV_0[9] ,Event 9 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 8. " DEV_0[8] ,Event 8 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 7. " DEV_0[7] ,Event 7 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 6. " DEV_0[6] ,Event 6 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 4. " DEV_0[4] ,Event 4 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 3. " DEV_0[3] ,Event 3 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 2. " DEV_0[2] ,Event 2 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " DEV_0[1] ,Event 1 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 0. " DEV_0[0] ,Event 0 sets DMA request 0" "Not set,Set"
|
|
line.long 0x10 "DMAREQ1,SCT DMA request 1 register"
|
|
rbitfld.long 0x10 31. " DRQ1 ,Indicates the state of DMA Request 1" "Low,High"
|
|
bitfld.long 0x10 30. " DRL1 ,SCT set DMA request 1 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x10 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 14. " DEV_1[14] ,Event 14 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DEV_1[13] ,Event 13 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 12. " DEV_1[12] ,Event 12 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 11. " DEV_1[11] ,Event 11 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 10. " DEV_1[10] ,Event 10 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DEV_1[9] ,Event 9 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 8. " DEV_1[8] ,Event 8 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 7. " DEV_1[7] ,Event 7 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 6. " DEV_1[6] ,Event 6 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 4. " DEV_1[4] ,Event 4 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 3. " DEV_1[3] ,Event 3 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 2. " DEV_1[2] ,Event 2 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DEV_1[1] ,Event 1 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 0. " DEV_1[0] ,Event 0 sets DMA request 1" "Not set,Set"
|
|
group.long 0xF0++0xf
|
|
line.long 0x00 "EVEN,SCT event enable register"
|
|
bitfld.long 0x00 15. " IEN[15] ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IEN[14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IEN[13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IEN[12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IEN[11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IEN[10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVFLAG,SCT event flag register"
|
|
bitfld.long 0x04 15. " FLAG[15] ,Event 15 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " FLAG[14] ,Event 14 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " FLAG[13] ,Event 13 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " FLAG[12] ,Event 12 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FLAG[11] ,Event 11 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " FLAG[10] ,Event 10 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " FLAG[9] ,Event 9 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " FLAG[8] ,Event 8 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FLAG[7] ,Event 7 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " FLAG[6] ,Event 6 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " FLAG[4] ,Event 4 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLAG[3] ,Event 3 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " FLAG[2] ,Event 2 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " FLAG[1] ,Event 1 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " FLAG[0] ,Event 0 occurred flag" "Not occurred,Occurred"
|
|
line.long 0x08 "CONEN,SCT conflict enable register"
|
|
bitfld.long 0x08 9. " NCEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NCEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " NCEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NCEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " NCEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NCEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " NCEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NCEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NCEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NCEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CONFLAG,SCT conflict flag register"
|
|
bitfld.long 0x0c 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the Output register when the H counter was not halted" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 30. " BUSERRL ,Error writing CTR L/Unified STATE L/Unified MATCH L/Unified or the Output register when the L/U counter was not halted" "No error,Error"
|
|
bitfld.long 0x0c 9. " NCFLAG[9] ,No-change event occurred on output 9 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 8. " NCFLAG[8] ,No-change event occurred on output 8 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " NCFLAG[7] ,No-change event occurred on output 7 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 6. " NCFLAG[6] ,No-change event occurred on output 6 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 5. " NCFLAG[5] ,No-change event occurred on output 5 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 4. " NCFLAG[4] ,No-change event occurred on output 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 2. " NCFLAG[2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 1. " NCFLAG[1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 0. " NCFLAG[0] ,No-change event occurred on output 0 flag" "Not occurred,Occurred"
|
|
tree "Match value and capture registers"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT match value register of match channel 0"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT capture register of capture channel 0"
|
|
else
|
|
group.word 0x100++0x03
|
|
line.word 0x00 "MATCH0_L,SCT match value register of match channel 0 low counter 16-bit"
|
|
line.word 0x02 "MATCH0_H,SCT match value register of match channel 0 high counter 16-bit"
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "CAP0_L,SCT capture register of capture channel 0 low counter 16-bit"
|
|
line.word 0x02 "CAP0_H,SCT capture register of capture channel 0 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT match value register of match channel 1"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT capture register of capture channel 1"
|
|
else
|
|
group.word 0x104++0x03
|
|
line.word 0x00 "MATCH1_L,SCT match value register of match channel 1 low counter 16-bit"
|
|
line.word 0x02 "MATCH1_H,SCT match value register of match channel 1 high counter 16-bit"
|
|
rgroup.word 0x104++0x03
|
|
line.word 0x00 "CAP1_L,SCT capture register of capture channel 1 low counter 16-bit"
|
|
line.word 0x02 "CAP1_H,SCT capture register of capture channel 1 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT match value register of match channel 2"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT capture register of capture channel 2"
|
|
else
|
|
group.word 0x108++0x03
|
|
line.word 0x00 "MATCH2_L,SCT match value register of match channel 2 low counter 16-bit"
|
|
line.word 0x02 "MATCH2_H,SCT match value register of match channel 2 high counter 16-bit"
|
|
rgroup.word 0x108++0x03
|
|
line.word 0x00 "CAP2_L,SCT capture register of capture channel 2 low counter 16-bit"
|
|
line.word 0x02 "CAP2_H,SCT capture register of capture channel 2 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT match value register of match channel 3"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT capture register of capture channel 3"
|
|
else
|
|
group.word 0x10C++0x03
|
|
line.word 0x00 "MATCH3_L,SCT match value register of match channel 3 low counter 16-bit"
|
|
line.word 0x02 "MATCH3_H,SCT match value register of match channel 3 high counter 16-bit"
|
|
rgroup.word 0x10C++0x03
|
|
line.word 0x00 "CAP3_L,SCT capture register of capture channel 3 low counter 16-bit"
|
|
line.word 0x02 "CAP3_H,SCT capture register of capture channel 3 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT match value register of match channel 4"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT capture register of capture channel 4"
|
|
else
|
|
group.word 0x110++0x03
|
|
line.word 0x00 "MATCH4_L,SCT match value register of match channel 4 low counter 16-bit"
|
|
line.word 0x02 "MATCH4_H,SCT match value register of match channel 4 high counter 16-bit"
|
|
rgroup.word 0x110++0x03
|
|
line.word 0x00 "CAP4_L,SCT capture register of capture channel 4 low counter 16-bit"
|
|
line.word 0x02 "CAP4_H,SCT capture register of capture channel 4 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT match value register of match channel 5"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT capture register of capture channel 5"
|
|
else
|
|
group.word 0x114++0x03
|
|
line.word 0x00 "MATCH5_L,SCT match value register of match channel 5 low counter 16-bit"
|
|
line.word 0x02 "MATCH5_H,SCT match value register of match channel 5 high counter 16-bit"
|
|
rgroup.word 0x114++0x03
|
|
line.word 0x00 "CAP5_L,SCT capture register of capture channel 5 low counter 16-bit"
|
|
line.word 0x02 "CAP5_H,SCT capture register of capture channel 5 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT match value register of match channel 6"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT capture register of capture channel 6"
|
|
else
|
|
group.word 0x118++0x03
|
|
line.word 0x00 "MATCH6_L,SCT match value register of match channel 6 low counter 16-bit"
|
|
line.word 0x02 "MATCH6_H,SCT match value register of match channel 6 high counter 16-bit"
|
|
rgroup.word 0x118++0x03
|
|
line.word 0x00 "CAP6_L,SCT capture register of capture channel 6 low counter 16-bit"
|
|
line.word 0x02 "CAP6_H,SCT capture register of capture channel 6 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT match value register of match channel 7"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT capture register of capture channel 7"
|
|
else
|
|
group.word 0x11C++0x03
|
|
line.word 0x00 "MATCH7_L,SCT match value register of match channel 7 low counter 16-bit"
|
|
line.word 0x02 "MATCH7_H,SCT match value register of match channel 7 high counter 16-bit"
|
|
rgroup.word 0x11C++0x03
|
|
line.word 0x00 "CAP7_L,SCT capture register of capture channel 7 low counter 16-bit"
|
|
line.word 0x02 "CAP7_H,SCT capture register of capture channel 7 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MATCH8,SCT match value register of match channel 8"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CAP8,SCT capture register of capture channel 8"
|
|
else
|
|
group.word 0x120++0x03
|
|
line.word 0x00 "MATCH8_L,SCT match value register of match channel 8 low counter 16-bit"
|
|
line.word 0x02 "MATCH8_H,SCT match value register of match channel 8 high counter 16-bit"
|
|
rgroup.word 0x120++0x03
|
|
line.word 0x00 "CAP8_L,SCT capture register of capture channel 8 low counter 16-bit"
|
|
line.word 0x02 "CAP8_H,SCT capture register of capture channel 8 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MATCH9,SCT match value register of match channel 9"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CAP9,SCT capture register of capture channel 9"
|
|
else
|
|
group.word 0x124++0x03
|
|
line.word 0x00 "MATCH9_L,SCT match value register of match channel 9 low counter 16-bit"
|
|
line.word 0x02 "MATCH9_H,SCT match value register of match channel 9 high counter 16-bit"
|
|
rgroup.word 0x124++0x03
|
|
line.word 0x00 "CAP9_L,SCT capture register of capture channel 9 low counter 16-bit"
|
|
line.word 0x02 "CAP9_H,SCT capture register of capture channel 9 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MATCH10,SCT match value register of match channel 10"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CAP10,SCT capture register of capture channel 10"
|
|
else
|
|
group.word 0x128++0x03
|
|
line.word 0x00 "MATCH10_L,SCT match value register of match channel 10 low counter 16-bit"
|
|
line.word 0x02 "MATCH10_H,SCT match value register of match channel 10 high counter 16-bit"
|
|
rgroup.word 0x128++0x03
|
|
line.word 0x00 "CAP10_L,SCT capture register of capture channel 10 low counter 16-bit"
|
|
line.word 0x02 "CAP10_H,SCT capture register of capture channel 10 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MATCH11,SCT match value register of match channel 11"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "CAP11,SCT capture register of capture channel 11"
|
|
else
|
|
group.word 0x12C++0x03
|
|
line.word 0x00 "MATCH11_L,SCT match value register of match channel 11 low counter 16-bit"
|
|
line.word 0x02 "MATCH11_H,SCT match value register of match channel 11 high counter 16-bit"
|
|
rgroup.word 0x12C++0x03
|
|
line.word 0x00 "CAP11_L,SCT capture register of capture channel 11 low counter 16-bit"
|
|
line.word 0x02 "CAP11_H,SCT capture register of capture channel 11 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MATCH12,SCT match value register of match channel 12"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CAP12,SCT capture register of capture channel 12"
|
|
else
|
|
group.word 0x130++0x03
|
|
line.word 0x00 "MATCH12_L,SCT match value register of match channel 12 low counter 16-bit"
|
|
line.word 0x02 "MATCH12_H,SCT match value register of match channel 12 high counter 16-bit"
|
|
rgroup.word 0x130++0x03
|
|
line.word 0x00 "CAP12_L,SCT capture register of capture channel 12 low counter 16-bit"
|
|
line.word 0x02 "CAP12_H,SCT capture register of capture channel 12 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MATCH13,SCT match value register of match channel 13"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CAP13,SCT capture register of capture channel 13"
|
|
else
|
|
group.word 0x134++0x03
|
|
line.word 0x00 "MATCH13_L,SCT match value register of match channel 13 low counter 16-bit"
|
|
line.word 0x02 "MATCH13_H,SCT match value register of match channel 13 high counter 16-bit"
|
|
rgroup.word 0x134++0x03
|
|
line.word 0x00 "CAP13_L,SCT capture register of capture channel 13 low counter 16-bit"
|
|
line.word 0x02 "CAP13_H,SCT capture register of capture channel 13 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MATCH14,SCT match value register of match channel 14"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "CAP14,SCT capture register of capture channel 14"
|
|
else
|
|
group.word 0x138++0x03
|
|
line.word 0x00 "MATCH14_L,SCT match value register of match channel 14 low counter 16-bit"
|
|
line.word 0x02 "MATCH14_H,SCT match value register of match channel 14 high counter 16-bit"
|
|
rgroup.word 0x138++0x03
|
|
line.word 0x00 "CAP14_L,SCT capture register of capture channel 14 low counter 16-bit"
|
|
line.word 0x02 "CAP14_H,SCT capture register of capture channel 14 high counter 16-bit"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MATCH15,SCT match value register of match channel 15"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "CAP15,SCT capture register of capture channel 15"
|
|
else
|
|
group.word 0x13C++0x03
|
|
line.word 0x00 "MATCH15_L,SCT match value register of match channel 15 low counter 16-bit"
|
|
line.word 0x02 "MATCH15_H,SCT match value register of match channel 15 high counter 16-bit"
|
|
rgroup.word 0x13C++0x03
|
|
line.word 0x00 "CAP15_L,SCT capture register of capture channel 15 low counter 16-bit"
|
|
line.word 0x02 "CAP15_H,SCT capture register of capture channel 15 high counter 16-bit"
|
|
endif
|
|
tree.end
|
|
tree "Fractional match registers"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x140+0x40)++0x03
|
|
line.long 0x00 "FRACMAT0,Fractional match register 0 SCT match value register 0"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH0 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x140++0x03
|
|
line.word 0x00 "FRACMAT0_L,Fractional match register 0 SCT match value register 0 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH0_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT0_H,Fractional match register 0 SCT match value register 0 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH0_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x144+0x40)++0x03
|
|
line.long 0x00 "FRACMAT1,Fractional match register 1 SCT match value register 1"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH1 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x144++0x03
|
|
line.word 0x00 "FRACMAT1_L,Fractional match register 1 SCT match value register 1 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH1_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT1_H,Fractional match register 1 SCT match value register 1 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH1_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x148+0x40)++0x03
|
|
line.long 0x00 "FRACMAT2,Fractional match register 2 SCT match value register 2"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH2 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x148++0x03
|
|
line.word 0x00 "FRACMAT2_L,Fractional match register 2 SCT match value register 2 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH2_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT2_H,Fractional match register 2 SCT match value register 2 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH2_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x14C+0x40)++0x03
|
|
line.long 0x00 "FRACMAT3,Fractional match register 3 SCT match value register 3"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH3 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x14C++0x03
|
|
line.word 0x00 "FRACMAT3_L,Fractional match register 3 SCT match value register 3 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH3_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT3_H,Fractional match register 3 SCT match value register 3 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH3_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x150+0x40)++0x03
|
|
line.long 0x00 "FRACMAT4,Fractional match register 4 SCT match value register 4"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH4 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x150++0x03
|
|
line.word 0x00 "FRACMAT4_L,Fractional match register 4 SCT match value register 4 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH4_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT4_H,Fractional match register 4 SCT match value register 4 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH4_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x154+0x40)++0x03
|
|
line.long 0x00 "FRACMAT5,Fractional match register 5 SCT match value register 5"
|
|
bitfld.long 0x00 0.--3. " FRACMAT ,Specifies the dither pattern to be applied to MATCH5 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x154++0x03
|
|
line.word 0x00 "FRACMAT5_L,Fractional match register 5 SCT match value register 5 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " FRACMAT_L ,Specifies the dither pattern to be applied to MATCH5_L register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMAT5_H,Fractional match register 5 SCT match value register 5 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " FRACMAT_H ,Specifies the dither pattern to be applied to MATCH5_H register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Match reload and capture control registers"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MATCHREL0,SCT match reload value register 0"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CAPCTRL0,SCT capture control register 0"
|
|
bitfld.long 0x00 15. " CAPCON0[15] ,Event 15 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON0[14] ,Event 14 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON0[13] ,Event 13 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON0[12] ,Event 12 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON0[11] ,Event 11 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON0[10] ,Event 10 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON0[9] ,Event 9 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON0[8] ,Event 8 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON0[7] ,Event 7 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON0[6] ,Event 6 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON0[5] ,Event 5 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON0[4] ,Event 4 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON0[3] ,Event 3 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON0[2] ,Event 2 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON0[1] ,Event 1 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON0[0] ,Event 0 causes load of CAP0 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "MATCHREL0_L,SCT match reload value register 0 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL0_H,SCT match reload value register 0 high counter 16-bit"
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "CAPCTRL0_L,SCT capture control register 0 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON0_L[15] ,Event 15 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON0_L[14] ,Event 14 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON0_L[13] ,Event 13 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON0_L[12] ,Event 12 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON0_L[11] ,Event 11 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON0_L[10] ,Event 10 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON0_L[9] ,Event 9 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON0_L[8] ,Event 8 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON0_L[7] ,Event 7 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON0_L[6] ,Event 6 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON0_L[5] ,Event 5 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON0_L[4] ,Event 4 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON0_L[3] ,Event 3 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON0_L[2] ,Event 2 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON0_L[1] ,Event 1 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON0_L[0] ,Event 0 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL0_H,SCT capture control register 0 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON0_H[15] ,Event 15 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON0_H[14] ,Event 14 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON0_H[13] ,Event 13 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON0_H[12] ,Event 12 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON0_H[11] ,Event 11 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON0_H[10] ,Event 10 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON0_H[9] ,Event 9 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON0_H[8] ,Event 8 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON0_H[7] ,Event 7 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON0_H[6] ,Event 6 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON0_H[5] ,Event 5 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON0_H[4] ,Event 4 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON0_H[3] ,Event 3 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON0_H[2] ,Event 2 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON0_H[1] ,Event 1 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON0_H[0] ,Event 0 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "MATCHREL1,SCT match reload value register 1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CAPCTRL1,SCT capture control register 1"
|
|
bitfld.long 0x00 15. " CAPCON1[15] ,Event 15 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON1[14] ,Event 14 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON1[13] ,Event 13 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON1[12] ,Event 12 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON1[11] ,Event 11 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON1[10] ,Event 10 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON1[9] ,Event 9 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON1[8] ,Event 8 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON1[7] ,Event 7 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON1[6] ,Event 6 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON1[5] ,Event 5 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON1[4] ,Event 4 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON1[3] ,Event 3 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON1[2] ,Event 2 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON1[1] ,Event 1 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON1[0] ,Event 0 causes load of CAP1 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "MATCHREL1_L,SCT match reload value register 1 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL1_H,SCT match reload value register 1 high counter 16-bit"
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "CAPCTRL1_L,SCT capture control register 1 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON1_L[15] ,Event 15 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON1_L[14] ,Event 14 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON1_L[13] ,Event 13 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON1_L[12] ,Event 12 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON1_L[11] ,Event 11 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON1_L[10] ,Event 10 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON1_L[9] ,Event 9 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON1_L[8] ,Event 8 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON1_L[7] ,Event 7 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON1_L[6] ,Event 6 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON1_L[5] ,Event 5 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON1_L[4] ,Event 4 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON1_L[3] ,Event 3 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON1_L[2] ,Event 2 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON1_L[1] ,Event 1 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON1_L[0] ,Event 0 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL1_H,SCT capture control register 1 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON1_H[15] ,Event 15 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON1_H[14] ,Event 14 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON1_H[13] ,Event 13 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON1_H[12] ,Event 12 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON1_H[11] ,Event 11 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON1_H[10] ,Event 10 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON1_H[9] ,Event 9 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON1_H[8] ,Event 8 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON1_H[7] ,Event 7 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON1_H[6] ,Event 6 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON1_H[5] ,Event 5 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON1_H[4] ,Event 4 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON1_H[3] ,Event 3 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON1_H[2] ,Event 2 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON1_H[1] ,Event 1 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON1_H[0] ,Event 0 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "MATCHREL2,SCT match reload value register 2"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CAPCTRL2,SCT capture control register 2"
|
|
bitfld.long 0x00 15. " CAPCON2[15] ,Event 15 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON2[14] ,Event 14 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON2[13] ,Event 13 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON2[12] ,Event 12 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON2[11] ,Event 11 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON2[10] ,Event 10 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON2[9] ,Event 9 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON2[8] ,Event 8 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON2[7] ,Event 7 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON2[6] ,Event 6 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON2[5] ,Event 5 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON2[4] ,Event 4 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON2[3] ,Event 3 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON2[2] ,Event 2 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON2[1] ,Event 1 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON2[0] ,Event 0 causes load of CAP2 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "MATCHREL2_L,SCT match reload value register 2 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL2_H,SCT match reload value register 2 high counter 16-bit"
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "CAPCTRL2_L,SCT capture control register 2 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON2_L[15] ,Event 15 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON2_L[14] ,Event 14 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON2_L[13] ,Event 13 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON2_L[12] ,Event 12 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON2_L[11] ,Event 11 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON2_L[10] ,Event 10 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON2_L[9] ,Event 9 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON2_L[8] ,Event 8 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON2_L[7] ,Event 7 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON2_L[6] ,Event 6 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON2_L[5] ,Event 5 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON2_L[4] ,Event 4 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON2_L[3] ,Event 3 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON2_L[2] ,Event 2 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON2_L[1] ,Event 1 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON2_L[0] ,Event 0 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL2_H,SCT capture control register 2 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON2_H[15] ,Event 15 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON2_H[14] ,Event 14 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON2_H[13] ,Event 13 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON2_H[12] ,Event 12 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON2_H[11] ,Event 11 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON2_H[10] ,Event 10 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON2_H[9] ,Event 9 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON2_H[8] ,Event 8 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON2_H[7] ,Event 7 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON2_H[6] ,Event 6 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON2_H[5] ,Event 5 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON2_H[4] ,Event 4 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON2_H[3] ,Event 3 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON2_H[2] ,Event 2 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON2_H[1] ,Event 1 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON2_H[0] ,Event 0 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "MATCHREL3,SCT match reload value register 3"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CAPCTRL3,SCT capture control register 3"
|
|
bitfld.long 0x00 15. " CAPCON3[15] ,Event 15 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON3[14] ,Event 14 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON3[13] ,Event 13 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON3[12] ,Event 12 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON3[11] ,Event 11 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON3[10] ,Event 10 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON3[9] ,Event 9 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON3[8] ,Event 8 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON3[7] ,Event 7 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON3[6] ,Event 6 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON3[5] ,Event 5 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON3[4] ,Event 4 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON3[3] ,Event 3 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON3[2] ,Event 2 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON3[1] ,Event 1 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON3[0] ,Event 0 causes load of CAP3 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "MATCHREL3_L,SCT match reload value register 3 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL3_H,SCT match reload value register 3 high counter 16-bit"
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "CAPCTRL3_L,SCT capture control register 3 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON3_L[15] ,Event 15 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON3_L[14] ,Event 14 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON3_L[13] ,Event 13 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON3_L[12] ,Event 12 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON3_L[11] ,Event 11 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON3_L[10] ,Event 10 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON3_L[9] ,Event 9 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON3_L[8] ,Event 8 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON3_L[7] ,Event 7 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON3_L[6] ,Event 6 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON3_L[5] ,Event 5 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON3_L[4] ,Event 4 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON3_L[3] ,Event 3 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON3_L[2] ,Event 2 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON3_L[1] ,Event 1 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON3_L[0] ,Event 0 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL3_H,SCT capture control register 3 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON3_H[15] ,Event 15 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON3_H[14] ,Event 14 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON3_H[13] ,Event 13 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON3_H[12] ,Event 12 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON3_H[11] ,Event 11 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON3_H[10] ,Event 10 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON3_H[9] ,Event 9 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON3_H[8] ,Event 8 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON3_H[7] ,Event 7 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON3_H[6] ,Event 6 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON3_H[5] ,Event 5 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON3_H[4] ,Event 4 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON3_H[3] ,Event 3 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON3_H[2] ,Event 2 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON3_H[1] ,Event 1 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON3_H[0] ,Event 0 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "MATCHREL4,SCT match reload value register 4"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CAPCTRL4,SCT capture control register 4"
|
|
bitfld.long 0x00 15. " CAPCON4[15] ,Event 15 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON4[14] ,Event 14 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON4[13] ,Event 13 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON4[12] ,Event 12 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON4[11] ,Event 11 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON4[10] ,Event 10 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON4[9] ,Event 9 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON4[8] ,Event 8 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON4[7] ,Event 7 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON4[6] ,Event 6 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON4[5] ,Event 5 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON4[4] ,Event 4 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON4[3] ,Event 3 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON4[2] ,Event 2 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON4[1] ,Event 1 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON4[0] ,Event 0 causes load of CAP4 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "MATCHREL4_L,SCT match reload value register 4 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL4_H,SCT match reload value register 4 high counter 16-bit"
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "CAPCTRL4_L,SCT capture control register 4 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON4_L[15] ,Event 15 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON4_L[14] ,Event 14 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON4_L[13] ,Event 13 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON4_L[12] ,Event 12 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON4_L[11] ,Event 11 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON4_L[10] ,Event 10 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON4_L[9] ,Event 9 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON4_L[8] ,Event 8 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON4_L[7] ,Event 7 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON4_L[6] ,Event 6 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON4_L[5] ,Event 5 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON4_L[4] ,Event 4 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON4_L[3] ,Event 3 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON4_L[2] ,Event 2 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON4_L[1] ,Event 1 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON4_L[0] ,Event 0 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL4_H,SCT capture control register 4 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON4_H[15] ,Event 15 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON4_H[14] ,Event 14 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON4_H[13] ,Event 13 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON4_H[12] ,Event 12 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON4_H[11] ,Event 11 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON4_H[10] ,Event 10 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON4_H[9] ,Event 9 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON4_H[8] ,Event 8 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON4_H[7] ,Event 7 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON4_H[6] ,Event 6 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON4_H[5] ,Event 5 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON4_H[4] ,Event 4 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON4_H[3] ,Event 3 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON4_H[2] ,Event 2 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON4_H[1] ,Event 1 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON4_H[0] ,Event 0 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "MATCHREL5,SCT match reload value register 5"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CAPCTRL5,SCT capture control register 5"
|
|
bitfld.long 0x00 15. " CAPCON5[15] ,Event 15 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON5[14] ,Event 14 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON5[13] ,Event 13 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON5[12] ,Event 12 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON5[11] ,Event 11 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON5[10] ,Event 10 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON5[9] ,Event 9 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON5[8] ,Event 8 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON5[7] ,Event 7 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON5[6] ,Event 6 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON5[5] ,Event 5 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON5[4] ,Event 4 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON5[3] ,Event 3 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON5[2] ,Event 2 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON5[1] ,Event 1 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON5[0] ,Event 0 causes load of CAP5 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "MATCHREL5_L,SCT match reload value register 5 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL5_H,SCT match reload value register 5 high counter 16-bit"
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "CAPCTRL5_L,SCT capture control register 5 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON5_L[15] ,Event 15 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON5_L[14] ,Event 14 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON5_L[13] ,Event 13 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON5_L[12] ,Event 12 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON5_L[11] ,Event 11 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON5_L[10] ,Event 10 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON5_L[9] ,Event 9 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON5_L[8] ,Event 8 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON5_L[7] ,Event 7 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON5_L[6] ,Event 6 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON5_L[5] ,Event 5 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON5_L[4] ,Event 4 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON5_L[3] ,Event 3 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON5_L[2] ,Event 2 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON5_L[1] ,Event 1 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON5_L[0] ,Event 0 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL5_H,SCT capture control register 5 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON5_H[15] ,Event 15 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON5_H[14] ,Event 14 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON5_H[13] ,Event 13 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON5_H[12] ,Event 12 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON5_H[11] ,Event 11 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON5_H[10] ,Event 10 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON5_H[9] ,Event 9 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON5_H[8] ,Event 8 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON5_H[7] ,Event 7 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON5_H[6] ,Event 6 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON5_H[5] ,Event 5 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON5_H[4] ,Event 4 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON5_H[3] ,Event 3 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON5_H[2] ,Event 2 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON5_H[1] ,Event 1 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON5_H[0] ,Event 0 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "MATCHREL6,SCT match reload value register 6"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "CAPCTRL6,SCT capture control register 6"
|
|
bitfld.long 0x00 15. " CAPCON6[15] ,Event 15 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON6[14] ,Event 14 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON6[13] ,Event 13 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON6[12] ,Event 12 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON6[11] ,Event 11 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON6[10] ,Event 10 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON6[9] ,Event 9 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON6[8] ,Event 8 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON6[7] ,Event 7 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON6[6] ,Event 6 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON6[5] ,Event 5 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON6[4] ,Event 4 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON6[3] ,Event 3 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON6[2] ,Event 2 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON6[1] ,Event 1 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON6[0] ,Event 0 causes load of CAP6 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "MATCHREL6_L,SCT match reload value register 6 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL6_H,SCT match reload value register 6 high counter 16-bit"
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "CAPCTRL6_L,SCT capture control register 6 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON6_L[15] ,Event 15 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON6_L[14] ,Event 14 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON6_L[13] ,Event 13 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON6_L[12] ,Event 12 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON6_L[11] ,Event 11 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON6_L[10] ,Event 10 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON6_L[9] ,Event 9 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON6_L[8] ,Event 8 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON6_L[7] ,Event 7 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON6_L[6] ,Event 6 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON6_L[5] ,Event 5 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON6_L[4] ,Event 4 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON6_L[3] ,Event 3 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON6_L[2] ,Event 2 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON6_L[1] ,Event 1 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON6_L[0] ,Event 0 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL6_H,SCT capture control register 6 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON6_H[15] ,Event 15 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON6_H[14] ,Event 14 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON6_H[13] ,Event 13 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON6_H[12] ,Event 12 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON6_H[11] ,Event 11 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON6_H[10] ,Event 10 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON6_H[9] ,Event 9 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON6_H[8] ,Event 8 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON6_H[7] ,Event 7 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON6_H[6] ,Event 6 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON6_H[5] ,Event 5 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON6_H[4] ,Event 4 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON6_H[3] ,Event 3 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON6_H[2] ,Event 2 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON6_H[1] ,Event 1 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON6_H[0] ,Event 0 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MATCHREL7,SCT match reload value register 7"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CAPCTRL7,SCT capture control register 7"
|
|
bitfld.long 0x00 15. " CAPCON7[15] ,Event 15 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON7[14] ,Event 14 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON7[13] ,Event 13 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON7[12] ,Event 12 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON7[11] ,Event 11 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON7[10] ,Event 10 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON7[9] ,Event 9 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON7[8] ,Event 8 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON7[7] ,Event 7 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON7[6] ,Event 6 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON7[5] ,Event 5 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON7[4] ,Event 4 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON7[3] ,Event 3 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON7[2] ,Event 2 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON7[1] ,Event 1 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON7[0] ,Event 0 causes load of CAP7 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "MATCHREL7_L,SCT match reload value register 7 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL7_H,SCT match reload value register 7 high counter 16-bit"
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "CAPCTRL7_L,SCT capture control register 7 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON7_L[15] ,Event 15 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON7_L[14] ,Event 14 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON7_L[13] ,Event 13 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON7_L[12] ,Event 12 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON7_L[11] ,Event 11 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON7_L[10] ,Event 10 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON7_L[9] ,Event 9 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON7_L[8] ,Event 8 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON7_L[7] ,Event 7 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON7_L[6] ,Event 6 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON7_L[5] ,Event 5 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON7_L[4] ,Event 4 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON7_L[3] ,Event 3 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON7_L[2] ,Event 2 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON7_L[1] ,Event 1 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON7_L[0] ,Event 0 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL7_H,SCT capture control register 7 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON7_H[15] ,Event 15 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON7_H[14] ,Event 14 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON7_H[13] ,Event 13 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON7_H[12] ,Event 12 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON7_H[11] ,Event 11 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON7_H[10] ,Event 10 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON7_H[9] ,Event 9 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON7_H[8] ,Event 8 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON7_H[7] ,Event 7 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON7_H[6] ,Event 6 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON7_H[5] ,Event 5 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON7_H[4] ,Event 4 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON7_H[3] ,Event 3 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON7_H[2] ,Event 2 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON7_H[1] ,Event 1 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON7_H[0] ,Event 0 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "MATCHREL8,SCT match reload value register 8"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CAPCTRL8,SCT capture control register 8"
|
|
bitfld.long 0x00 15. " CAPCON8[15] ,Event 15 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON8[14] ,Event 14 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON8[13] ,Event 13 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON8[12] ,Event 12 causes load of CAP8 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON8[11] ,Event 11 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON8[10] ,Event 10 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON8[9] ,Event 9 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON8[8] ,Event 8 causes load of CAP8 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON8[7] ,Event 7 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON8[6] ,Event 6 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON8[5] ,Event 5 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON8[4] ,Event 4 causes load of CAP8 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON8[3] ,Event 3 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON8[2] ,Event 2 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON8[1] ,Event 1 causes load of CAP8 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON8[0] ,Event 0 causes load of CAP8 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x220++0x03
|
|
line.word 0x00 "MATCHREL8_L,SCT match reload value register 8 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL8_H,SCT match reload value register 8 high counter 16-bit"
|
|
group.word 0x220++0x03
|
|
line.word 0x00 "CAPCTRL8_L,SCT capture control register 8 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON8_L[15] ,Event 15 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON8_L[14] ,Event 14 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON8_L[13] ,Event 13 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON8_L[12] ,Event 12 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON8_L[11] ,Event 11 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON8_L[10] ,Event 10 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON8_L[9] ,Event 9 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON8_L[8] ,Event 8 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON8_L[7] ,Event 7 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON8_L[6] ,Event 6 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON8_L[5] ,Event 5 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON8_L[4] ,Event 4 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON8_L[3] ,Event 3 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON8_L[2] ,Event 2 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON8_L[1] ,Event 1 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON8_L[0] ,Event 0 causes load of CAP8_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL8_H,SCT capture control register 8 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON8_H[15] ,Event 15 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON8_H[14] ,Event 14 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON8_H[13] ,Event 13 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON8_H[12] ,Event 12 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON8_H[11] ,Event 11 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON8_H[10] ,Event 10 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON8_H[9] ,Event 9 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON8_H[8] ,Event 8 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON8_H[7] ,Event 7 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON8_H[6] ,Event 6 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON8_H[5] ,Event 5 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON8_H[4] ,Event 4 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON8_H[3] ,Event 3 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON8_H[2] ,Event 2 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON8_H[1] ,Event 1 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON8_H[0] ,Event 0 causes load of CAP8_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "MATCHREL9,SCT match reload value register 9"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "CAPCTRL9,SCT capture control register 9"
|
|
bitfld.long 0x00 15. " CAPCON9[15] ,Event 15 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON9[14] ,Event 14 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON9[13] ,Event 13 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON9[12] ,Event 12 causes load of CAP9 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON9[11] ,Event 11 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON9[10] ,Event 10 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON9[9] ,Event 9 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON9[8] ,Event 8 causes load of CAP9 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON9[7] ,Event 7 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON9[6] ,Event 6 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON9[5] ,Event 5 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON9[4] ,Event 4 causes load of CAP9 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON9[3] ,Event 3 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON9[2] ,Event 2 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON9[1] ,Event 1 causes load of CAP9 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON9[0] ,Event 0 causes load of CAP9 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x224++0x03
|
|
line.word 0x00 "MATCHREL9_L,SCT match reload value register 9 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL9_H,SCT match reload value register 9 high counter 16-bit"
|
|
group.word 0x224++0x03
|
|
line.word 0x00 "CAPCTRL9_L,SCT capture control register 9 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON9_L[15] ,Event 15 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON9_L[14] ,Event 14 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON9_L[13] ,Event 13 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON9_L[12] ,Event 12 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON9_L[11] ,Event 11 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON9_L[10] ,Event 10 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON9_L[9] ,Event 9 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON9_L[8] ,Event 8 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON9_L[7] ,Event 7 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON9_L[6] ,Event 6 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON9_L[5] ,Event 5 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON9_L[4] ,Event 4 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON9_L[3] ,Event 3 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON9_L[2] ,Event 2 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON9_L[1] ,Event 1 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON9_L[0] ,Event 0 causes load of CAP9_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL9_H,SCT capture control register 9 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON9_H[15] ,Event 15 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON9_H[14] ,Event 14 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON9_H[13] ,Event 13 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON9_H[12] ,Event 12 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON9_H[11] ,Event 11 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON9_H[10] ,Event 10 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON9_H[9] ,Event 9 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON9_H[8] ,Event 8 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON9_H[7] ,Event 7 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON9_H[6] ,Event 6 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON9_H[5] ,Event 5 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON9_H[4] ,Event 4 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON9_H[3] ,Event 3 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON9_H[2] ,Event 2 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON9_H[1] ,Event 1 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON9_H[0] ,Event 0 causes load of CAP9_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "MATCHREL10,SCT match reload value register 10"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "CAPCTRL10,SCT capture control register 10"
|
|
bitfld.long 0x00 15. " CAPCON10[15] ,Event 15 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON10[14] ,Event 14 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON10[13] ,Event 13 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON10[12] ,Event 12 causes load of CAP10 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON10[11] ,Event 11 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON10[10] ,Event 10 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON10[9] ,Event 9 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON10[8] ,Event 8 causes load of CAP10 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON10[7] ,Event 7 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON10[6] ,Event 6 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON10[5] ,Event 5 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON10[4] ,Event 4 causes load of CAP10 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON10[3] ,Event 3 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON10[2] ,Event 2 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON10[1] ,Event 1 causes load of CAP10 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON10[0] ,Event 0 causes load of CAP10 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x228++0x03
|
|
line.word 0x00 "MATCHREL10_L,SCT match reload value register 10 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL10_H,SCT match reload value register 10 high counter 16-bit"
|
|
group.word 0x228++0x03
|
|
line.word 0x00 "CAPCTRL10_L,SCT capture control register 10 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON10_L[15] ,Event 15 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON10_L[14] ,Event 14 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON10_L[13] ,Event 13 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON10_L[12] ,Event 12 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON10_L[11] ,Event 11 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON10_L[10] ,Event 10 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON10_L[9] ,Event 9 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON10_L[8] ,Event 8 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON10_L[7] ,Event 7 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON10_L[6] ,Event 6 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON10_L[5] ,Event 5 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON10_L[4] ,Event 4 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON10_L[3] ,Event 3 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON10_L[2] ,Event 2 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON10_L[1] ,Event 1 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON10_L[0] ,Event 0 causes load of CAP10_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL10_H,SCT capture control register 10 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON10_H[15] ,Event 15 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON10_H[14] ,Event 14 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON10_H[13] ,Event 13 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON10_H[12] ,Event 12 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON10_H[11] ,Event 11 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON10_H[10] ,Event 10 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON10_H[9] ,Event 9 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON10_H[8] ,Event 8 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON10_H[7] ,Event 7 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON10_H[6] ,Event 6 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON10_H[5] ,Event 5 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON10_H[4] ,Event 4 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON10_H[3] ,Event 3 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON10_H[2] ,Event 2 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON10_H[1] ,Event 1 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON10_H[0] ,Event 0 causes load of CAP10_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "MATCHREL11,SCT match reload value register 11"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "CAPCTRL11,SCT capture control register 11"
|
|
bitfld.long 0x00 15. " CAPCON11[15] ,Event 15 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON11[14] ,Event 14 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON11[13] ,Event 13 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON11[12] ,Event 12 causes load of CAP11 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON11[11] ,Event 11 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON11[10] ,Event 10 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON11[9] ,Event 9 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON11[8] ,Event 8 causes load of CAP11 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON11[7] ,Event 7 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON11[6] ,Event 6 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON11[5] ,Event 5 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON11[4] ,Event 4 causes load of CAP11 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON11[3] ,Event 3 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON11[2] ,Event 2 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON11[1] ,Event 1 causes load of CAP11 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON11[0] ,Event 0 causes load of CAP11 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x22C++0x03
|
|
line.word 0x00 "MATCHREL11_L,SCT match reload value register 11 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL11_H,SCT match reload value register 11 high counter 16-bit"
|
|
group.word 0x22C++0x03
|
|
line.word 0x00 "CAPCTRL11_L,SCT capture control register 11 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON11_L[15] ,Event 15 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON11_L[14] ,Event 14 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON11_L[13] ,Event 13 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON11_L[12] ,Event 12 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON11_L[11] ,Event 11 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON11_L[10] ,Event 10 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON11_L[9] ,Event 9 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON11_L[8] ,Event 8 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON11_L[7] ,Event 7 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON11_L[6] ,Event 6 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON11_L[5] ,Event 5 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON11_L[4] ,Event 4 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON11_L[3] ,Event 3 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON11_L[2] ,Event 2 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON11_L[1] ,Event 1 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON11_L[0] ,Event 0 causes load of CAP11_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL11_H,SCT capture control register 11 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON11_H[15] ,Event 15 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON11_H[14] ,Event 14 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON11_H[13] ,Event 13 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON11_H[12] ,Event 12 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON11_H[11] ,Event 11 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON11_H[10] ,Event 10 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON11_H[9] ,Event 9 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON11_H[8] ,Event 8 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON11_H[7] ,Event 7 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON11_H[6] ,Event 6 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON11_H[5] ,Event 5 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON11_H[4] ,Event 4 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON11_H[3] ,Event 3 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON11_H[2] ,Event 2 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON11_H[1] ,Event 1 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON11_H[0] ,Event 0 causes load of CAP11_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "MATCHREL12,SCT match reload value register 12"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "CAPCTRL12,SCT capture control register 12"
|
|
bitfld.long 0x00 15. " CAPCON12[15] ,Event 15 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON12[14] ,Event 14 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON12[13] ,Event 13 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON12[12] ,Event 12 causes load of CAP12 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON12[11] ,Event 11 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON12[10] ,Event 10 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON12[9] ,Event 9 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON12[8] ,Event 8 causes load of CAP12 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON12[7] ,Event 7 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON12[6] ,Event 6 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON12[5] ,Event 5 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON12[4] ,Event 4 causes load of CAP12 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON12[3] ,Event 3 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON12[2] ,Event 2 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON12[1] ,Event 1 causes load of CAP12 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON12[0] ,Event 0 causes load of CAP12 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x230++0x03
|
|
line.word 0x00 "MATCHREL12_L,SCT match reload value register 12 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL12_H,SCT match reload value register 12 high counter 16-bit"
|
|
group.word 0x230++0x03
|
|
line.word 0x00 "CAPCTRL12_L,SCT capture control register 12 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON12_L[15] ,Event 15 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON12_L[14] ,Event 14 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON12_L[13] ,Event 13 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON12_L[12] ,Event 12 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON12_L[11] ,Event 11 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON12_L[10] ,Event 10 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON12_L[9] ,Event 9 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON12_L[8] ,Event 8 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON12_L[7] ,Event 7 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON12_L[6] ,Event 6 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON12_L[5] ,Event 5 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON12_L[4] ,Event 4 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON12_L[3] ,Event 3 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON12_L[2] ,Event 2 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON12_L[1] ,Event 1 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON12_L[0] ,Event 0 causes load of CAP12_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL12_H,SCT capture control register 12 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON12_H[15] ,Event 15 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON12_H[14] ,Event 14 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON12_H[13] ,Event 13 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON12_H[12] ,Event 12 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON12_H[11] ,Event 11 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON12_H[10] ,Event 10 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON12_H[9] ,Event 9 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON12_H[8] ,Event 8 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON12_H[7] ,Event 7 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON12_H[6] ,Event 6 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON12_H[5] ,Event 5 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON12_H[4] ,Event 4 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON12_H[3] ,Event 3 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON12_H[2] ,Event 2 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON12_H[1] ,Event 1 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON12_H[0] ,Event 0 causes load of CAP12_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "MATCHREL13,SCT match reload value register 13"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "CAPCTRL13,SCT capture control register 13"
|
|
bitfld.long 0x00 15. " CAPCON13[15] ,Event 15 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON13[14] ,Event 14 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON13[13] ,Event 13 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON13[12] ,Event 12 causes load of CAP13 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON13[11] ,Event 11 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON13[10] ,Event 10 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON13[9] ,Event 9 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON13[8] ,Event 8 causes load of CAP13 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON13[7] ,Event 7 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON13[6] ,Event 6 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON13[5] ,Event 5 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON13[4] ,Event 4 causes load of CAP13 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON13[3] ,Event 3 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON13[2] ,Event 2 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON13[1] ,Event 1 causes load of CAP13 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON13[0] ,Event 0 causes load of CAP13 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x234++0x03
|
|
line.word 0x00 "MATCHREL13_L,SCT match reload value register 13 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL13_H,SCT match reload value register 13 high counter 16-bit"
|
|
group.word 0x234++0x03
|
|
line.word 0x00 "CAPCTRL13_L,SCT capture control register 13 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON13_L[15] ,Event 15 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON13_L[14] ,Event 14 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON13_L[13] ,Event 13 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON13_L[12] ,Event 12 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON13_L[11] ,Event 11 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON13_L[10] ,Event 10 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON13_L[9] ,Event 9 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON13_L[8] ,Event 8 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON13_L[7] ,Event 7 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON13_L[6] ,Event 6 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON13_L[5] ,Event 5 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON13_L[4] ,Event 4 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON13_L[3] ,Event 3 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON13_L[2] ,Event 2 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON13_L[1] ,Event 1 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON13_L[0] ,Event 0 causes load of CAP13_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL13_H,SCT capture control register 13 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON13_H[15] ,Event 15 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON13_H[14] ,Event 14 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON13_H[13] ,Event 13 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON13_H[12] ,Event 12 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON13_H[11] ,Event 11 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON13_H[10] ,Event 10 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON13_H[9] ,Event 9 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON13_H[8] ,Event 8 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON13_H[7] ,Event 7 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON13_H[6] ,Event 6 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON13_H[5] ,Event 5 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON13_H[4] ,Event 4 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON13_H[3] ,Event 3 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON13_H[2] ,Event 2 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON13_H[1] ,Event 1 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON13_H[0] ,Event 0 causes load of CAP13_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "MATCHREL14,SCT match reload value register 14"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "CAPCTRL14,SCT capture control register 14"
|
|
bitfld.long 0x00 15. " CAPCON14[15] ,Event 15 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON14[14] ,Event 14 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON14[13] ,Event 13 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON14[12] ,Event 12 causes load of CAP14 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON14[11] ,Event 11 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON14[10] ,Event 10 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON14[9] ,Event 9 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON14[8] ,Event 8 causes load of CAP14 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON14[7] ,Event 7 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON14[6] ,Event 6 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON14[5] ,Event 5 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON14[4] ,Event 4 causes load of CAP14 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON14[3] ,Event 3 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON14[2] ,Event 2 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON14[1] ,Event 1 causes load of CAP14 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON14[0] ,Event 0 causes load of CAP14 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x238++0x03
|
|
line.word 0x00 "MATCHREL14_L,SCT match reload value register 14 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL14_H,SCT match reload value register 14 high counter 16-bit"
|
|
group.word 0x238++0x03
|
|
line.word 0x00 "CAPCTRL14_L,SCT capture control register 14 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON14_L[15] ,Event 15 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON14_L[14] ,Event 14 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON14_L[13] ,Event 13 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON14_L[12] ,Event 12 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON14_L[11] ,Event 11 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON14_L[10] ,Event 10 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON14_L[9] ,Event 9 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON14_L[8] ,Event 8 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON14_L[7] ,Event 7 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON14_L[6] ,Event 6 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON14_L[5] ,Event 5 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON14_L[4] ,Event 4 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON14_L[3] ,Event 3 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON14_L[2] ,Event 2 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON14_L[1] ,Event 1 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON14_L[0] ,Event 0 causes load of CAP14_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL14_H,SCT capture control register 14 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON14_H[15] ,Event 15 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON14_H[14] ,Event 14 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON14_H[13] ,Event 13 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON14_H[12] ,Event 12 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON14_H[11] ,Event 11 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON14_H[10] ,Event 10 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON14_H[9] ,Event 9 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON14_H[8] ,Event 8 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON14_H[7] ,Event 7 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON14_H[6] ,Event 6 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON14_H[5] ,Event 5 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON14_H[4] ,Event 4 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON14_H[3] ,Event 3 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON14_H[2] ,Event 2 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON14_H[1] ,Event 1 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON14_H[0] ,Event 0 causes load of CAP14_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "MATCHREL15,SCT match reload value register 15"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "CAPCTRL15,SCT capture control register 15"
|
|
bitfld.long 0x00 15. " CAPCON15[15] ,Event 15 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " CAPCON15[14] ,Event 14 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " CAPCON15[13] ,Event 13 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CAPCON15[12] ,Event 12 causes load of CAP15 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CAPCON15[11] ,Event 11 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CAPCON15[10] ,Event 10 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " CAPCON15[9] ,Event 9 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON15[8] ,Event 8 causes load of CAP15 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CAPCON15[7] ,Event 7 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON15[6] ,Event 6 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " CAPCON15[5] ,Event 5 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON15[4] ,Event 4 causes load of CAP15 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCON15[3] ,Event 3 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON15[2] ,Event 2 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " CAPCON15[1] ,Event 1 causes load of CAP15 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON15[0] ,Event 0 causes load of CAP15 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x23C++0x03
|
|
line.word 0x00 "MATCHREL15_L,SCT match reload value register 15 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL15_H,SCT match reload value register 15 high counter 16-bit"
|
|
group.word 0x23C++0x03
|
|
line.word 0x00 "CAPCTRL15_L,SCT capture control register 15 low counter 16-bit"
|
|
bitfld.word 0x00 15. " CAPCON15_L[15] ,Event 15 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " CAPCON15_L[14] ,Event 14 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " CAPCON15_L[13] ,Event 13 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " CAPCON15_L[12] ,Event 12 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CAPCON15_L[11] ,Event 11 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CAPCON15_L[10] ,Event 10 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CAPCON15_L[9] ,Event 9 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON15_L[8] ,Event 8 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CAPCON15_L[7] ,Event 7 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON15_L[6] ,Event 6 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " CAPCON15_L[5] ,Event 5 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON15_L[4] ,Event 4 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CAPCON15_L[3] ,Event 3 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON15_L[2] ,Event 2 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CAPCON15_L[1] ,Event 1 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON15_L[0] ,Event 0 causes load of CAP15_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL15_H,SCT capture control register 15 high counter 16-bit"
|
|
bitfld.word 0x02 15. " CAPCON15_H[15] ,Event 15 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " CAPCON15_H[14] ,Event 14 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 13. " CAPCON15_H[13] ,Event 13 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 12. " CAPCON15_H[12] ,Event 12 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 11. " CAPCON15_H[11] ,Event 11 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 10. " CAPCON15_H[10] ,Event 10 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 9. " CAPCON15_H[9] ,Event 9 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON15_H[8] ,Event 8 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 7. " CAPCON15_H[7] ,Event 7 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON15_H[6] ,Event 6 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 5. " CAPCON15_H[5] ,Event 5 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON15_H[4] ,Event 4 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 3. " CAPCON15_H[3] ,Event 3 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON15_H[2] ,Event 2 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 1. " CAPCON15_H[1] ,Event 1 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON15_H[0] ,Event 0 causes load of CAP15_H register" "Not occurred,Occurred"
|
|
endif
|
|
tree.end
|
|
tree "Fractional match reload registers"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "FRACMATREL0,Fractional match reload register 0 for SCT match value register 0"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x240++0x03
|
|
line.word 0x00 "FRACMATREL0_L,Fractional match reload register 0 for SCT match value register 0 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT0_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL0_H,Fractional match reload register 0 for SCT match value register 0 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT0_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "FRACMATREL1,Fractional match reload register 1 for SCT match value register 1"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x244++0x03
|
|
line.word 0x00 "FRACMATREL1_L,Fractional match reload register 1 for SCT match value register 1 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT1_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL1_H,Fractional match reload register 1 for SCT match value register 1 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT1_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "FRACMATREL2,Fractional match reload register 2 for SCT match value register 2"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x248++0x03
|
|
line.word 0x00 "FRACMATREL2_L,Fractional match reload register 2 for SCT match value register 2 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT2_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL2_H,Fractional match reload register 2 for SCT match value register 2 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT2_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "FRACMATREL3,Fractional match reload register 3 for SCT match value register 3"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x24C++0x03
|
|
line.word 0x00 "FRACMATREL3_L,Fractional match reload register 3 for SCT match value register 3 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT3_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL3_H,Fractional match reload register 3 for SCT match value register 3 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT3_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "FRACMATREL4,Fractional match reload register 4 for SCT match value register 4"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x250++0x03
|
|
line.word 0x00 "FRACMATREL4_L,Fractional match reload register 4 for SCT match value register 4 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT4_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL4_H,Fractional match reload register 4 for SCT match value register 4 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT4_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "FRACMATREL5,Fractional match reload register 5 for SCT match value register 5"
|
|
bitfld.long 0x00 16.--19. " RELFRAC_H ,Upper 4 bits value to be loaded into FRACMAT5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RELFRAC_L ,Lower 4 bits value to be loaded into FRACMAT5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x254++0x03
|
|
line.word 0x00 "FRACMATREL5_L,Fractional match reload register 5 for SCT match value register 5 low counter 16-bit"
|
|
bitfld.word 0x00 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT5_L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "FRACMATREL5_H,Fractional match reload register 5 for SCT match value register 5 high counter 16-bit"
|
|
bitfld.word 0x02 0.--3. " RELFRAC_L ,4 bits value to be loaded into FRACMAT5_H" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Event state and control registers"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "EV0_STATE,SCT event state register 0"
|
|
bitfld.long 0x00 31. " STATEMSK0[31] ,State 31 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK0[30] ,State 30 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK0[29] ,State 29 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK0[28] ,State 28 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK0[27] ,State 27 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK0[26] ,State 26 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK0[25] ,State 25 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK0[24] ,State 24 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK0[23] ,State 23 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK0[22] ,State 22 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK0[21] ,State 21 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK0[20] ,State 20 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK0[19] ,State 19 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK0[18] ,State 18 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK0[17] ,State 17 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK0[16] ,State 16 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK0[15] ,State 15 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK0[14] ,State 14 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK0[13] ,State 13 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK0[12] ,State 12 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK0[11] ,State 11 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK0[10] ,State 10 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK0[9] ,State 9 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK0[8] ,State 8 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK0[7] ,State 7 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK0[6] ,State 6 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK0[5] ,State 5 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK0[4] ,State 4 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK0[3] ,State 3 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK0[2] ,State 2 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK0[1] ,State 1 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK0[0] ,State 0 of event 0 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0_CTRL,SCT event control register 0"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0_CTRL,SCT event control register 0"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EV1_STATE,SCT event state register 1"
|
|
bitfld.long 0x00 31. " STATEMSK1[31] ,State 31 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK1[30] ,State 30 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK1[29] ,State 29 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK1[28] ,State 28 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK1[27] ,State 27 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK1[26] ,State 26 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK1[25] ,State 25 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK1[24] ,State 24 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK1[23] ,State 23 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK1[22] ,State 22 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK1[21] ,State 21 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK1[20] ,State 20 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK1[19] ,State 19 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK1[18] ,State 18 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK1[17] ,State 17 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK1[16] ,State 16 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK1[15] ,State 15 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK1[14] ,State 14 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK1[13] ,State 13 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK1[12] ,State 12 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK1[11] ,State 11 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK1[10] ,State 10 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK1[9] ,State 9 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK1[8] ,State 8 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK1[7] ,State 7 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK1[6] ,State 6 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK1[5] ,State 5 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK1[4] ,State 4 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK1[3] ,State 3 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK1[2] ,State 2 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK1[1] ,State 1 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK1[0] ,State 0 of event 1 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1_CTRL,SCT event control register 1"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1_CTRL,SCT event control register 1"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EV2_STATE,SCT event state register 2"
|
|
bitfld.long 0x00 31. " STATEMSK2[31] ,State 31 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK2[30] ,State 30 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK2[29] ,State 29 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK2[28] ,State 28 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK2[27] ,State 27 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK2[26] ,State 26 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK2[25] ,State 25 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK2[24] ,State 24 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK2[23] ,State 23 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK2[22] ,State 22 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK2[21] ,State 21 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK2[20] ,State 20 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK2[19] ,State 19 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK2[18] ,State 18 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK2[17] ,State 17 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK2[16] ,State 16 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK2[15] ,State 15 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK2[14] ,State 14 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK2[13] ,State 13 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK2[12] ,State 12 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK2[11] ,State 11 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK2[10] ,State 10 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK2[9] ,State 9 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK2[8] ,State 8 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK2[7] ,State 7 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK2[6] ,State 6 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK2[5] ,State 5 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK2[4] ,State 4 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK2[3] ,State 3 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK2[2] ,State 2 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK2[1] ,State 1 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK2[0] ,State 0 of event 2 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2_CTRL,SCT event control register 2"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2_CTRL,SCT event control register 2"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EV3_STATE,SCT event state register 3"
|
|
bitfld.long 0x00 31. " STATEMSK3[31] ,State 31 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK3[30] ,State 30 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK3[29] ,State 29 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK3[28] ,State 28 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK3[27] ,State 27 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK3[26] ,State 26 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK3[25] ,State 25 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK3[24] ,State 24 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK3[23] ,State 23 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK3[22] ,State 22 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK3[21] ,State 21 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK3[20] ,State 20 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK3[19] ,State 19 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK3[18] ,State 18 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK3[17] ,State 17 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK3[16] ,State 16 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK3[15] ,State 15 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK3[14] ,State 14 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK3[13] ,State 13 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK3[12] ,State 12 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK3[11] ,State 11 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK3[10] ,State 10 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK3[9] ,State 9 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK3[8] ,State 8 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK3[7] ,State 7 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK3[6] ,State 6 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK3[5] ,State 5 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK3[4] ,State 4 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK3[3] ,State 3 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK3[2] ,State 2 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK3[1] ,State 1 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK3[0] ,State 0 of event 3 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3_CTRL,SCT event control register 3"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3_CTRL,SCT event control register 3"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EV4_STATE,SCT event state register 4"
|
|
bitfld.long 0x00 31. " STATEMSK4[31] ,State 31 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK4[30] ,State 30 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK4[29] ,State 29 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK4[28] ,State 28 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK4[27] ,State 27 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK4[26] ,State 26 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK4[25] ,State 25 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK4[24] ,State 24 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK4[23] ,State 23 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK4[22] ,State 22 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK4[21] ,State 21 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK4[20] ,State 20 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK4[19] ,State 19 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK4[18] ,State 18 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK4[17] ,State 17 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK4[16] ,State 16 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK4[15] ,State 15 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK4[14] ,State 14 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK4[13] ,State 13 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK4[12] ,State 12 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK4[11] ,State 11 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK4[10] ,State 10 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK4[9] ,State 9 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK4[8] ,State 8 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK4[7] ,State 7 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK4[6] ,State 6 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK4[5] ,State 5 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK4[4] ,State 4 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK4[3] ,State 3 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK4[2] ,State 2 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK4[1] ,State 1 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK4[0] ,State 0 of event 4 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4_CTRL,SCT event control register 4"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4_CTRL,SCT event control register 4"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EV5_STATE,SCT event state register 5"
|
|
bitfld.long 0x00 31. " STATEMSK5[31] ,State 31 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK5[30] ,State 30 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK5[29] ,State 29 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK5[28] ,State 28 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK5[27] ,State 27 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK5[26] ,State 26 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK5[25] ,State 25 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK5[24] ,State 24 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK5[23] ,State 23 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK5[22] ,State 22 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK5[21] ,State 21 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK5[20] ,State 20 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK5[19] ,State 19 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK5[18] ,State 18 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK5[17] ,State 17 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK5[16] ,State 16 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK5[15] ,State 15 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK5[14] ,State 14 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK5[13] ,State 13 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK5[12] ,State 12 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK5[11] ,State 11 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK5[10] ,State 10 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK5[9] ,State 9 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK5[8] ,State 8 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK5[7] ,State 7 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK5[6] ,State 6 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK5[5] ,State 5 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK5[4] ,State 4 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK5[3] ,State 3 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK5[2] ,State 2 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK5[1] ,State 1 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK5[0] ,State 0 of event 5 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5_CTRL,SCT event control register 5"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5_CTRL,SCT event control register 5"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EV6_STATE,SCT event state register 6"
|
|
bitfld.long 0x00 31. " STATEMSK6[31] ,State 31 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK6[30] ,State 30 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK6[29] ,State 29 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK6[28] ,State 28 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK6[27] ,State 27 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK6[26] ,State 26 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK6[25] ,State 25 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK6[24] ,State 24 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK6[23] ,State 23 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK6[22] ,State 22 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK6[21] ,State 21 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK6[20] ,State 20 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK6[19] ,State 19 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK6[18] ,State 18 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK6[17] ,State 17 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK6[16] ,State 16 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK6[15] ,State 15 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK6[14] ,State 14 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK6[13] ,State 13 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK6[12] ,State 12 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK6[11] ,State 11 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK6[10] ,State 10 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK6[9] ,State 9 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK6[8] ,State 8 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK6[7] ,State 7 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK6[6] ,State 6 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK6[5] ,State 5 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK6[4] ,State 4 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK6[3] ,State 3 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK6[2] ,State 2 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK6[1] ,State 1 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK6[0] ,State 0 of event 6 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6_CTRL,SCT event control register 6"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6_CTRL,SCT event control register 6"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EV7_STATE,SCT event state register 7"
|
|
bitfld.long 0x00 31. " STATEMSK7[31] ,State 31 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK7[30] ,State 30 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK7[29] ,State 29 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK7[28] ,State 28 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK7[27] ,State 27 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK7[26] ,State 26 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK7[25] ,State 25 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK7[24] ,State 24 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK7[23] ,State 23 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK7[22] ,State 22 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK7[21] ,State 21 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK7[20] ,State 20 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK7[19] ,State 19 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK7[18] ,State 18 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK7[17] ,State 17 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK7[16] ,State 16 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK7[15] ,State 15 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK7[14] ,State 14 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK7[13] ,State 13 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK7[12] ,State 12 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK7[11] ,State 11 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK7[10] ,State 10 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK7[9] ,State 9 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK7[8] ,State 8 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK7[7] ,State 7 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK7[6] ,State 6 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK7[5] ,State 5 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK7[4] ,State 4 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK7[3] ,State 3 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK7[2] ,State 2 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK7[1] ,State 1 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK7[0] ,State 0 of event 7 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7_CTRL,SCT event control register 7"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7_CTRL,SCT event control register 7"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "EV8_STATE,SCT event state register 8"
|
|
bitfld.long 0x00 31. " STATEMSK8[31] ,State 31 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK8[30] ,State 30 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK8[29] ,State 29 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK8[28] ,State 28 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK8[27] ,State 27 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK8[26] ,State 26 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK8[25] ,State 25 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK8[24] ,State 24 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK8[23] ,State 23 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK8[22] ,State 22 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK8[21] ,State 21 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK8[20] ,State 20 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK8[19] ,State 19 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK8[18] ,State 18 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK8[17] ,State 17 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK8[16] ,State 16 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK8[15] ,State 15 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK8[14] ,State 14 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK8[13] ,State 13 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK8[12] ,State 12 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK8[11] ,State 11 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK8[10] ,State 10 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK8[9] ,State 9 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK8[8] ,State 8 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK8[7] ,State 7 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK8[6] ,State 6 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK8[5] ,State 5 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK8[4] ,State 4 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK8[3] ,State 3 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK8[2] ,State 2 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK8[1] ,State 1 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK8[0] ,State 0 of event 8 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8_CTRL,SCT event control register 8"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8_CTRL,SCT event control register 8"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EV9_STATE,SCT event state register 9"
|
|
bitfld.long 0x00 31. " STATEMSK9[31] ,State 31 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK9[30] ,State 30 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK9[29] ,State 29 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK9[28] ,State 28 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK9[27] ,State 27 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK9[26] ,State 26 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK9[25] ,State 25 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK9[24] ,State 24 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK9[23] ,State 23 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK9[22] ,State 22 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK9[21] ,State 21 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK9[20] ,State 20 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK9[19] ,State 19 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK9[18] ,State 18 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK9[17] ,State 17 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK9[16] ,State 16 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK9[15] ,State 15 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK9[14] ,State 14 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK9[13] ,State 13 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK9[12] ,State 12 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK9[11] ,State 11 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK9[10] ,State 10 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK9[9] ,State 9 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK9[8] ,State 8 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK9[7] ,State 7 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK9[6] ,State 6 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK9[5] ,State 5 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK9[4] ,State 4 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK9[3] ,State 3 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK9[2] ,State 2 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK9[1] ,State 1 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK9[0] ,State 0 of event 9 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9_CTRL,SCT event control register 9"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9_CTRL,SCT event control register 9"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline ""
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "EV10_STATE,SCT event state register 10"
|
|
bitfld.long 0x00 31. " STATEMSK10[31] ,State 31 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK10[30] ,State 30 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK10[29] ,State 29 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK10[28] ,State 28 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK10[27] ,State 27 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK10[26] ,State 26 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK10[25] ,State 25 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK10[24] ,State 24 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK10[23] ,State 23 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK10[22] ,State 22 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK10[21] ,State 21 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK10[20] ,State 20 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK10[19] ,State 19 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK10[18] ,State 18 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK10[17] ,State 17 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK10[16] ,State 16 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK10[15] ,State 15 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK10[14] ,State 14 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK10[13] ,State 13 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK10[12] ,State 12 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK10[11] ,State 11 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK10[10] ,State 10 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK10[9] ,State 9 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK10[8] ,State 8 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK10[7] ,State 7 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK10[6] ,State 6 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK10[5] ,State 5 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK10[4] ,State 4 of event 10 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK10[3] ,State 3 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK10[2] ,State 2 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK10[1] ,State 1 of event 10 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK10[0] ,State 0 of event 10 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x350+0x4)++0x03
|
|
line.long 0x00 "EV10_CTRL,SCT event control register 10"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 10" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x350+0x4)++0x03
|
|
line.long 0x00 "EV10_CTRL,SCT event control register 10"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 10" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "EV11_STATE,SCT event state register 11"
|
|
bitfld.long 0x00 31. " STATEMSK11[31] ,State 31 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK11[30] ,State 30 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK11[29] ,State 29 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK11[28] ,State 28 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK11[27] ,State 27 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK11[26] ,State 26 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK11[25] ,State 25 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK11[24] ,State 24 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK11[23] ,State 23 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK11[22] ,State 22 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK11[21] ,State 21 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK11[20] ,State 20 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK11[19] ,State 19 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK11[18] ,State 18 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK11[17] ,State 17 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK11[16] ,State 16 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK11[15] ,State 15 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK11[14] ,State 14 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK11[13] ,State 13 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK11[12] ,State 12 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK11[11] ,State 11 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK11[10] ,State 10 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK11[9] ,State 9 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK11[8] ,State 8 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK11[7] ,State 7 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK11[6] ,State 6 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK11[5] ,State 5 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK11[4] ,State 4 of event 11 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK11[3] ,State 3 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK11[2] ,State 2 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK11[1] ,State 1 of event 11 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK11[0] ,State 0 of event 11 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x358+0x4)++0x03
|
|
line.long 0x00 "EV11_CTRL,SCT event control register 11"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 11" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x358+0x4)++0x03
|
|
line.long 0x00 "EV11_CTRL,SCT event control register 11"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 11" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "EV12_STATE,SCT event state register 12"
|
|
bitfld.long 0x00 31. " STATEMSK12[31] ,State 31 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK12[30] ,State 30 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK12[29] ,State 29 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK12[28] ,State 28 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK12[27] ,State 27 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK12[26] ,State 26 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK12[25] ,State 25 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK12[24] ,State 24 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK12[23] ,State 23 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK12[22] ,State 22 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK12[21] ,State 21 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK12[20] ,State 20 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK12[19] ,State 19 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK12[18] ,State 18 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK12[17] ,State 17 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK12[16] ,State 16 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK12[15] ,State 15 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK12[14] ,State 14 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK12[13] ,State 13 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK12[12] ,State 12 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK12[11] ,State 11 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK12[10] ,State 10 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK12[9] ,State 9 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK12[8] ,State 8 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK12[7] ,State 7 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK12[6] ,State 6 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK12[5] ,State 5 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK12[4] ,State 4 of event 12 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK12[3] ,State 3 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK12[2] ,State 2 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK12[1] ,State 1 of event 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK12[0] ,State 0 of event 12 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x360+0x4)++0x03
|
|
line.long 0x00 "EV12_CTRL,SCT event control register 12"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 12" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x360+0x4)++0x03
|
|
line.long 0x00 "EV12_CTRL,SCT event control register 12"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 12" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "EV13_STATE,SCT event state register 13"
|
|
bitfld.long 0x00 31. " STATEMSK13[31] ,State 31 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK13[30] ,State 30 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK13[29] ,State 29 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK13[28] ,State 28 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK13[27] ,State 27 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK13[26] ,State 26 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK13[25] ,State 25 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK13[24] ,State 24 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK13[23] ,State 23 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK13[22] ,State 22 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK13[21] ,State 21 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK13[20] ,State 20 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK13[19] ,State 19 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK13[18] ,State 18 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK13[17] ,State 17 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK13[16] ,State 16 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK13[15] ,State 15 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK13[14] ,State 14 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK13[13] ,State 13 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK13[12] ,State 12 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK13[11] ,State 11 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK13[10] ,State 10 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK13[9] ,State 9 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK13[8] ,State 8 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK13[7] ,State 7 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK13[6] ,State 6 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK13[5] ,State 5 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK13[4] ,State 4 of event 13 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK13[3] ,State 3 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK13[2] ,State 2 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK13[1] ,State 1 of event 13 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK13[0] ,State 0 of event 13 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x368+0x4)++0x03
|
|
line.long 0x00 "EV13_CTRL,SCT event control register 13"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 13" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x368+0x4)++0x03
|
|
line.long 0x00 "EV13_CTRL,SCT event control register 13"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 13" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "EV14_STATE,SCT event state register 14"
|
|
bitfld.long 0x00 31. " STATEMSK14[31] ,State 31 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK14[30] ,State 30 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK14[29] ,State 29 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK14[28] ,State 28 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK14[27] ,State 27 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK14[26] ,State 26 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK14[25] ,State 25 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK14[24] ,State 24 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK14[23] ,State 23 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK14[22] ,State 22 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK14[21] ,State 21 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK14[20] ,State 20 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK14[19] ,State 19 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK14[18] ,State 18 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK14[17] ,State 17 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK14[16] ,State 16 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK14[15] ,State 15 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK14[14] ,State 14 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK14[13] ,State 13 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK14[12] ,State 12 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK14[11] ,State 11 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK14[10] ,State 10 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK14[9] ,State 9 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK14[8] ,State 8 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK14[7] ,State 7 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK14[6] ,State 6 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK14[5] ,State 5 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK14[4] ,State 4 of event 14 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK14[3] ,State 3 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK14[2] ,State 2 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK14[1] ,State 1 of event 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK14[0] ,State 0 of event 14 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x370+0x4)++0x03
|
|
line.long 0x00 "EV14_CTRL,SCT event control register 14"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 14" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x370+0x4)++0x03
|
|
line.long 0x00 "EV14_CTRL,SCT event control register 14"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 14" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "EV15_STATE,SCT event state register 15"
|
|
bitfld.long 0x00 31. " STATEMSK15[31] ,State 31 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " STATEMSK15[30] ,State 30 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 29. " STATEMSK15[29] ,State 29 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " STATEMSK15[28] ,State 28 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " STATEMSK15[27] ,State 27 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " STATEMSK15[26] ,State 26 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 25. " STATEMSK15[25] ,State 25 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " STATEMSK15[24] ,State 24 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STATEMSK15[23] ,State 23 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " STATEMSK15[22] ,State 22 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 21. " STATEMSK15[21] ,State 21 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " STATEMSK15[20] ,State 20 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " STATEMSK15[19] ,State 19 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " STATEMSK15[18] ,State 18 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " STATEMSK15[17] ,State 17 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " STATEMSK15[16] ,State 16 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STATEMSK15[15] ,State 15 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " STATEMSK15[14] ,State 14 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " STATEMSK15[13] ,State 13 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " STATEMSK15[12] ,State 12 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STATEMSK15[11] ,State 11 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " STATEMSK15[10] ,State 10 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " STATEMSK15[9] ,State 9 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK15[8] ,State 8 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STATEMSK15[7] ,State 7 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK15[6] ,State 6 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " STATEMSK15[5] ,State 5 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK15[4] ,State 4 of event 15 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATEMSK15[3] ,State 3 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK15[2] ,State 2 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STATEMSK15[1] ,State 1 of event 15 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK15[0] ,State 0 of event 15 select" "Not selected,Selected"
|
|
if (((per.l((ad:0x1C01C000)))&0x1)==0x1)
|
|
group.long (0x378+0x4)++0x03
|
|
line.long 0x00 "EV15_CTRL,SCT event control register 15"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 15" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x378+0x4)++0x03
|
|
line.long 0x00 "EV15_CTRL,SCT event control register 15"
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 15" "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Output set/clear registers"
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OUT0_SET,SCT output 0 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 0" "Not set,Set"
|
|
line.long 0x04 "OUT0_CLR,SCT output 0 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 0" "Not set,Set"
|
|
group.long 0x508++0x07
|
|
line.long 0x00 "OUT1_SET,SCT output 1 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 1" "Not set,Set"
|
|
line.long 0x04 "OUT1_CLR,SCT output 1 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 1" "Not set,Set"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OUT2_SET,SCT output 2 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 2" "Not set,Set"
|
|
line.long 0x04 "OUT2_CLR,SCT output 2 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 2" "Not set,Set"
|
|
group.long 0x518++0x07
|
|
line.long 0x00 "OUT3_SET,SCT output 3 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 3" "Not set,Set"
|
|
line.long 0x04 "OUT3_CLR,SCT output 3 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 3" "Not set,Set"
|
|
group.long 0x520++0x07
|
|
line.long 0x00 "OUT4_SET,SCT output 4 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 4" "Not set,Set"
|
|
line.long 0x04 "OUT4_CLR,SCT output 4 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 4" "Not set,Set"
|
|
group.long 0x528++0x07
|
|
line.long 0x00 "OUT5_SET,SCT output 5 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 5" "Not set,Set"
|
|
line.long 0x04 "OUT5_CLR,SCT output 5 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 5" "Not set,Set"
|
|
group.long 0x530++0x07
|
|
line.long 0x00 "OUT6_SET,SCT output 6 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 6" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 6" "Not set,Set"
|
|
line.long 0x04 "OUT6_CLR,SCT output 6 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 6" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 6" "Not set,Set"
|
|
group.long 0x538++0x07
|
|
line.long 0x00 "OUT7_SET,SCT output 7 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 7" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 7" "Not set,Set"
|
|
line.long 0x04 "OUT7_CLR,SCT output 7 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 7" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 7" "Not set,Set"
|
|
group.long 0x540++0x07
|
|
line.long 0x00 "OUT8_SET,SCT output 8 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 8" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 8" "Not set,Set"
|
|
line.long 0x04 "OUT8_CLR,SCT output 8 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 8" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 8" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 8" "Not set,Set"
|
|
group.long 0x548++0x07
|
|
line.long 0x00 "OUT9_SET,SCT output 9 set register"
|
|
bitfld.long 0x00 15. " SET[15] ,Event 15 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 14. " SET[14] ,Event 14 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 13. " SET[13] ,Event 13 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 12. " SET[12] ,Event 12 set output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET[11] ,Event 11 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 10. " SET[10] ,Event 10 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 9" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 9" "Not set,Set"
|
|
line.long 0x04 "OUT9_CLR,SCT output 9 clear register"
|
|
bitfld.long 0x04 15. " CLR[15] ,Event 15 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 14. " CLR[14] ,Event 14 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 13. " CLR[13] ,Event 13 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 12. " CLR[12] ,Event 12 clear output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLR[11] ,Event 11 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 10. " CLR[10] ,Event 10 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 9" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 9" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 9" "Not set,Set"
|
|
tree.end
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree.open "Small SCTimers"
|
|
tree "SCTimer 2"
|
|
base ad:0x1C020000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,SCT configuration register"
|
|
bitfld.long 0x00 18. " AUTOLIMIT_H ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " NORELOAD_H ,Prevent the higher match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
bitfld.long 0x00 7. " NORELOAD_L ,Prevent the lower match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input (0:7)" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operate as unified 32-bit counter" "Not unified,Unified"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "CTRL,SCT control register"
|
|
hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock"
|
|
bitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down"
|
|
line.long 0x04 "LIMIT,SCT limit register"
|
|
bitfld.long 0x04 15. " LIMMSK[15] ,Event 15 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 14. " LIMMSK[14] ,Event 14 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 13. " LIMMSK[13] ,Event 13 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 12. " LIMMSK[12] ,Event 12 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LIMMSK[11] ,Event 11 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 10. " LIMMSK[10] ,Event 10 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 9. " LIMMSK[9] ,Event 9 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 8. " LIMMSK[8] ,Event 8 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LIMMSK[7] ,Event 7 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 6. " LIMMSK[6] ,Event 6 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 5. " LIMMSK[5] ,Event 5 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 4. " LIMMSK[4] ,Event 4 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LIMMSK[3] ,Event 3 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 2. " LIMMSK[2] ,Event 2 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 1. " LIMMSK[1] ,Event 1 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 0. " LIMMSK[0] ,Event 0 use as counter limit for unified counter" "Not used,Used"
|
|
line.long 0x08 "HALT,SCT halt condition register"
|
|
bitfld.long 0x08 15. " HALTMSK[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 14. " HALTMSK[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 13. " HALTMSK[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 12. " HALTMSK[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HALTMSK[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 10. " HALTMSK[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 9. " HALTMSK[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 8. " HALTMSK[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HALTMSK[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 6. " HALTMSK[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 5. " HALTMSK[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 4. " HALTMSK[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HALTMSK[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 2. " HALTMSK[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 1. " HALTMSK[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 0. " HALTMSK[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x0C "STOP,SCT stop condition register"
|
|
bitfld.long 0x0C 15. " STOPMSK[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 14. " STOPMSK[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 13. " STOPMSK[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 12. " STOPMSK[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " STOPMSK[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 10. " STOPMSK[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 9. " STOPMSK[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 8. " STOPMSK[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " STOPMSK[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 6. " STOPMSK[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 5. " STOPMSK[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 4. " STOPMSK[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " STOPMSK[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 2. " STOPMSK[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 1. " STOPMSK[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 0. " STOPMSK[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x10 "START,SCT start condition register"
|
|
bitfld.long 0x10 15. " STARTMSK[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 14. " STARTMSK[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 13. " STARTMSK[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 12. " STARTMSK[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 11. " STARTMSK[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 10. " STARTMSK[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 9. " STARTMSK[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 8. " STARTMSK[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 7. " STARTMSK[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 6. " STARTMSK[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 5. " STARTMSK[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 4. " STARTMSK[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 3. " STARTMSK[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 2. " STARTMSK[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 1. " STARTMSK[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 0. " STARTMSK[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "COUNT,SCT counter register"
|
|
line.long 0x04 "STATE,SCT state register"
|
|
bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT match/capture registers mode register"
|
|
bitfld.long 0x00 15. " REGMOD[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 14. " REGMOD[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 13. " REGMOD[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 12. " REGMOD[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REGMOD[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 10. " REGMOD[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 9. " REGMOD[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 8. " REGMOD[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REGMOD[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 6. " REGMOD[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 5. " REGMOD[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 4. " REGMOD[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REGMOD[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 2. " REGMOD[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 1. " REGMOD[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 0. " REGMOD[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
else
|
|
group.word 0x04++0x13
|
|
line.word 0x00 "CTRL_L,SCT control lower 16-bit register"
|
|
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock"
|
|
bitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down"
|
|
line.word 0x02 "CTRL_H,SCT control higher 16-bit register"
|
|
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock"
|
|
bitfld.word 0x02 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x02 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x02 2. " HALT_H ,H counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x02 1. " STOP_H ,H counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x02 0. " DOWN_H ,H counter counting down" "Counting up,Counting down"
|
|
line.word 0x04 "LIMIT_L,SCT limit higher 16-bit register"
|
|
bitfld.word 0x04 15. " LIMMSK_L[15] ,Event 15 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 14. " LIMMSK_L[14] ,Event 14 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 13. " LIMMSK_L[13] ,Event 13 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 12. " LIMMSK_L[12] ,Event 12 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 11. " LIMMSK_L[11] ,Event 11 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 10. " LIMMSK_L[10] ,Event 10 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 9. " LIMMSK_L[9] ,Event 9 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 8. " LIMMSK_L[8] ,Event 8 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 7. " LIMMSK_L[7] ,Event 7 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 6. " LIMMSK_L[6] ,Event 6 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 5. " LIMMSK_L[5] ,Event 5 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 4. " LIMMSK_L[4] ,Event 4 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 3. " LIMMSK_L[3] ,Event 3 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 2. " LIMMSK_L[2] ,Event 2 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 1. " LIMMSK_L[1] ,Event 1 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 0. " LIMMSK_L[0] ,Event 0 use as counter limit for L counter" "Not used,Used"
|
|
line.word 0x06 "LIMIT_H,SCT limit lower 16-bit register"
|
|
bitfld.word 0x06 15. " LIMMSK_H[15] ,Event 15 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 14. " LIMMSK_H[14] ,Event 14 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 13. " LIMMSK_H[13] ,Event 13 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 12. " LIMMSK_H[12] ,Event 12 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 11. " LIMMSK_H[11] ,Event 11 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 10. " LIMMSK_H[10] ,Event 10 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 9. " LIMMSK_H[9] ,Event 9 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 8. " LIMMSK_H[8] ,Event 8 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 7. " LIMMSK_H[7] ,Event 7 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 6. " LIMMSK_H[6] ,Event 6 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 5. " LIMMSK_H[5] ,Event 5 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 4. " LIMMSK_H[4] ,Event 4 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 3. " LIMMSK_H[3] ,Event 3 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 2. " LIMMSK_H[2] ,Event 2 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 1. " LIMMSK_H[1] ,Event 1 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 0. " LIMMSK_H[0] ,Event 0 use as counter limit for H counter" "Not used,Used"
|
|
line.word 0x08 "HALT_L,SCT halt condition lower 16-bit register"
|
|
bitfld.word 0x08 15. " HALTMSK_L[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 14. " HALTMSK_L[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 13. " HALTMSK_L[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 12. " HALTMSK_L[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 11. " HALTMSK_L[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 10. " HALTMSK_L[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 9. " HALTMSK_L[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 8. " HALTMSK_L[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 7. " HALTMSK_L[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 6. " HALTMSK_L[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 5. " HALTMSK_L[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 4. " HALTMSK_L[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 3. " HALTMSK_L[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 2. " HALTMSK_L[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 1. " HALTMSK_L[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 0. " HALTMSK_L[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0A "HALT_H,SCT halt condition higher 16-bit register"
|
|
bitfld.word 0x0A 15. " HALTMSK_H[15] ,Event 15 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 14. " HALTMSK_H[14] ,Event 14 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 13. " HALTMSK_H[13] ,Event 13 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 12. " HALTMSK_H[12] ,Event 12 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 11. " HALTMSK_H[11] ,Event 11 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 10. " HALTMSK_H[10] ,Event 10 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 9. " HALTMSK_H[9] ,Event 9 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 8. " HALTMSK_H[8] ,Event 8 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 7. " HALTMSK_H[7] ,Event 7 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 6. " HALTMSK_H[6] ,Event 6 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 5. " HALTMSK_H[5] ,Event 5 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 4. " HALTMSK_H[4] ,Event 4 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 3. " HALTMSK_H[3] ,Event 3 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 2. " HALTMSK_H[2] ,Event 2 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 1. " HALTMSK_H[1] ,Event 1 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 0. " HALTMSK_H[0] ,Event 0 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x0C "STOP_L,SCT stop condition lower 16-bit register"
|
|
bitfld.word 0x0C 15. " STOPMSK_L[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 14. " STOPMSK_L[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 13. " STOPMSK_L[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 12. " STOPMSK_L[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 11. " STOPMSK_L[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 10. " STOPMSK_L[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 9. " STOPMSK_L[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 8. " STOPMSK_L[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 7. " STOPMSK_L[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 6. " STOPMSK_L[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 5. " STOPMSK_L[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 4. " STOPMSK_L[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 3. " STOPMSK_L[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 2. " STOPMSK_L[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 1. " STOPMSK_L[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 0. " STOPMSK_L[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0E "STOP_H,SCT stop condition higher 16-bit register"
|
|
bitfld.word 0x0E 15. " STOPMSK_H[15] ,Event 15 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 14. " STOPMSK_H[14] ,Event 14 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 13. " STOPMSK_H[13] ,Event 13 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 12. " STOPMSK_H[12] ,Event 12 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 11. " STOPMSK_H[11] ,Event 11 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 10. " STOPMSK_H[10] ,Event 10 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 9. " STOPMSK_H[9] ,Event 9 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 8. " STOPMSK_H[8] ,Event 8 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 7. " STOPMSK_H[7] ,Event 7 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 6. " STOPMSK_H[6] ,Event 6 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 5. " STOPMSK_H[5] ,Event 5 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 4. " STOPMSK_H[4] ,Event 4 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 3. " STOPMSK_H[3] ,Event 3 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 2. " STOPMSK_H[2] ,Event 2 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 1. " STOPMSK_H[1] ,Event 1 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 0. " STOPMSK_H[0] ,Event 0 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x10 "START_L,SCT start condition lower 16-bit register"
|
|
bitfld.word 0x10 15. " STARTMSK_L[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 14. " STARTMSK_L[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 13. " STARTMSK_L[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 12. " STARTMSK_L[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 11. " STARTMSK_L[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 10. " STARTMSK_L[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 9. " STARTMSK_L[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 8. " STARTMSK_L[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 7. " STARTMSK_L[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 6. " STARTMSK_L[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 5. " STARTMSK_L[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 4. " STARTMSK_L[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 3. " STARTMSK_L[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 2. " STARTMSK_L[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 1. " STARTMSK_L[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 0. " STARTMSK_L[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
line.word 0x12 "START_H,SCT start condition higher 16-bit register"
|
|
bitfld.word 0x12 15. " STARTMSK_H[15] ,Event 15 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 14. " STARTMSK_H[14] ,Event 14 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 13. " STARTMSK_H[13] ,Event 13 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 12. " STARTMSK_H[12] ,Event 12 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 11. " STARTMSK_H[11] ,Event 11 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 10. " STARTMSK_H[10] ,Event 10 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 9. " STARTMSK_H[9] ,Event 9 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 8. " STARTMSK_H[8] ,Event 8 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 7. " STARTMSK_H[7] ,Event 7 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 6. " STARTMSK_H[6] ,Event 6 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 5. " STARTMSK_H[5] ,Event 5 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 4. " STARTMSK_H[4] ,Event 4 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 3. " STARTMSK_H[3] ,Event 3 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 2. " STARTMSK_H[2] ,Event 2 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 1. " STARTMSK_H[1] ,Event 1 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 0. " STARTMSK_H[0] ,Event 0 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
group.word 0x40++0x7
|
|
line.word 0x00 "COUNT_L,SCT counter register low counter 16-bit"
|
|
line.word 0x02 "COUNT_H,SCT counter register high counter 16-bit"
|
|
line.word 0x04 "STATE_L,SCT state register low counter 16-bit"
|
|
bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x06 "STATE_L,SCT state register high counter 16-bit"
|
|
bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.word 0x4C++0x03
|
|
line.word 0x00 "REGMODE_L,SCT match/capture registers mode register low counter 16-bit"
|
|
bitfld.word 0x00 15. " REGMOD_L[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 14. " REGMOD_L[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 13. " REGMOD_L[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 12. " REGMOD_L[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 11. " REGMOD_L[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 10. " REGMOD_L[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 9. " REGMOD_L[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 8. " REGMOD_L[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 7. " REGMOD_L[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 6. " REGMOD_L[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 5. " REGMOD_L[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 4. " REGMOD_L[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 3. " REGMOD_L[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 2. " REGMOD_L[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 1. " REGMOD_L[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 0. " REGMOD_L[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
line.word 0x02 "REGMODE_H,SCT match/capture registers mode register high counter 16-bit"
|
|
bitfld.word 0x02 15. " REGMOD_H[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 14. " REGMOD_H[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 13. " REGMOD_H[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 12. " REGMOD_H[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 11. " REGMOD_H[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 10. " REGMOD_H[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 9. " REGMOD_H[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 8. " REGMOD_H[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 7. " REGMOD_H[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 6. " REGMOD_H[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 5. " REGMOD_H[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 4. " REGMOD_H[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 3. " REGMOD_H[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 2. " REGMOD_H[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 1. " REGMOD_H[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 0. " REGMOD_H[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT output register"
|
|
bitfld.long 0x00 5. " OUT[5] ,Set high on output 5" "Low,High"
|
|
bitfld.long 0x00 4. " OUT[4] ,Set high on output 4" "Low,High"
|
|
bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT[2] ,Set high on output 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT[1] ,Set high on output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT[0] ,Set high on output 0" "Low,High"
|
|
line.long 0x04 "OUTPUTDIRCTRL,SCT output counter direction control register"
|
|
bitfld.long 0x04 10.--11. " SETCLR5 ,Set/clear operation on output 5 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 8.--9. " SETCLR4 ,Set/clear operation on output 4 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 6.--7. " SETCLR3 ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 4.--5. " SETCLR2 ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SETCLR1 ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 0.--1. " SETCLR0 ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
line.long 0x08 "RES,SCT conflict resolution register"
|
|
bitfld.long 0x08 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle"
|
|
line.long 0x0c "DMAREQ0,SCT DMA request 0 register"
|
|
rbitfld.long 0x0c 31. " DRQ0 ,Indicates the state of DMA Request 0" "Low,High"
|
|
bitfld.long 0x0c 30. " DRL0 ,SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x0c 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 14. " DEV_0[14] ,Event 14 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " DEV_0[13] ,Event 13 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 12. " DEV_0[12] ,Event 12 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 11. " DEV_0[11] ,Event 11 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 10. " DEV_0[10] ,Event 10 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " DEV_0[9] ,Event 9 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 8. " DEV_0[8] ,Event 8 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 7. " DEV_0[7] ,Event 7 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 6. " DEV_0[6] ,Event 6 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 4. " DEV_0[4] ,Event 4 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 3. " DEV_0[3] ,Event 3 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 2. " DEV_0[2] ,Event 2 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " DEV_0[1] ,Event 1 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 0. " DEV_0[0] ,Event 0 sets DMA request 0" "Not set,Set"
|
|
line.long 0x10 "DMAREQ1,SCT DMA request 1 register"
|
|
rbitfld.long 0x10 31. " DRQ1 ,Indicates the state of DMA Request 1" "Low,High"
|
|
bitfld.long 0x10 30. " DRL1 ,SCT set DMA request 1 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x10 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 14. " DEV_1[14] ,Event 14 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DEV_1[13] ,Event 13 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 12. " DEV_1[12] ,Event 12 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 11. " DEV_1[11] ,Event 11 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 10. " DEV_1[10] ,Event 10 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DEV_1[9] ,Event 9 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 8. " DEV_1[8] ,Event 8 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 7. " DEV_1[7] ,Event 7 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 6. " DEV_1[6] ,Event 6 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 4. " DEV_1[4] ,Event 4 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 3. " DEV_1[3] ,Event 3 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 2. " DEV_1[2] ,Event 2 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DEV_1[1] ,Event 1 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 0. " DEV_1[0] ,Event 0 sets DMA request 1" "Not set,Set"
|
|
group.long 0xF0++0xf
|
|
line.long 0x00 "EVEN,SCT event enable register"
|
|
bitfld.long 0x00 15. " IEN[15] ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IEN[14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IEN[13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IEN[12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IEN[11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IEN[10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVFLAG,SCT event flag register"
|
|
bitfld.long 0x04 15. " FLAG[15] ,Event 15 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " FLAG[14] ,Event 14 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " FLAG[13] ,Event 13 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " FLAG[12] ,Event 12 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FLAG[11] ,Event 11 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " FLAG[10] ,Event 10 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " FLAG[9] ,Event 9 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " FLAG[8] ,Event 8 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FLAG[7] ,Event 7 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " FLAG[6] ,Event 6 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " FLAG[4] ,Event 4 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLAG[3] ,Event 3 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " FLAG[2] ,Event 2 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " FLAG[1] ,Event 1 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " FLAG[0] ,Event 0 occurred flag" "Not occurred,Occurred"
|
|
line.long 0x08 "CONEN,SCT conflict enable register"
|
|
bitfld.long 0x08 15. " NCEN[15] ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NCEN[14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " NCEN[13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NCEN[12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NCEN[11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NCEN[10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " NCEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NCEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NCEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NCEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " NCEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NCEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NCEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NCEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " NCEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NCEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CONFLAG,SCT conflict flag register"
|
|
bitfld.long 0x0c 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the Output register when the H counter was not halted" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 30. " BUSERRL ,Error writing CTR L/Unified STATE L/Unified MATCH L/Unified or the Output register when the L/U counter was not halted" "No error,Error"
|
|
bitfld.long 0x0c 5. " NCFLAG[5] ,No-change event occurred on output 5 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 4. " NCFLAG[4] ,No-change event occurred on output 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 2. " NCFLAG[2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 1. " NCFLAG[1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 0. " NCFLAG[0] ,No-change event occurred on output 0 flag" "Not occurred,Occurred"
|
|
tree "Match value and capture registers"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT match value register of match channel 0"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT capture register of capture channel 0"
|
|
else
|
|
group.word 0x100++0x03
|
|
line.word 0x00 "MATCH0_L,SCT match value register of match channel 0 low counter 16-bit"
|
|
line.word 0x02 "MATCH0_H,SCT match value register of match channel 0 high counter 16-bit"
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "CAP0_L,SCT capture register of capture channel 0 low counter 16-bit"
|
|
line.word 0x02 "CAP0_H,SCT capture register of capture channel 0 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT match value register of match channel 1"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT capture register of capture channel 1"
|
|
else
|
|
group.word 0x104++0x03
|
|
line.word 0x00 "MATCH1_L,SCT match value register of match channel 1 low counter 16-bit"
|
|
line.word 0x02 "MATCH1_H,SCT match value register of match channel 1 high counter 16-bit"
|
|
rgroup.word 0x104++0x03
|
|
line.word 0x00 "CAP1_L,SCT capture register of capture channel 1 low counter 16-bit"
|
|
line.word 0x02 "CAP1_H,SCT capture register of capture channel 1 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT match value register of match channel 2"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT capture register of capture channel 2"
|
|
else
|
|
group.word 0x108++0x03
|
|
line.word 0x00 "MATCH2_L,SCT match value register of match channel 2 low counter 16-bit"
|
|
line.word 0x02 "MATCH2_H,SCT match value register of match channel 2 high counter 16-bit"
|
|
rgroup.word 0x108++0x03
|
|
line.word 0x00 "CAP2_L,SCT capture register of capture channel 2 low counter 16-bit"
|
|
line.word 0x02 "CAP2_H,SCT capture register of capture channel 2 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT match value register of match channel 3"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT capture register of capture channel 3"
|
|
else
|
|
group.word 0x10C++0x03
|
|
line.word 0x00 "MATCH3_L,SCT match value register of match channel 3 low counter 16-bit"
|
|
line.word 0x02 "MATCH3_H,SCT match value register of match channel 3 high counter 16-bit"
|
|
rgroup.word 0x10C++0x03
|
|
line.word 0x00 "CAP3_L,SCT capture register of capture channel 3 low counter 16-bit"
|
|
line.word 0x02 "CAP3_H,SCT capture register of capture channel 3 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT match value register of match channel 4"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT capture register of capture channel 4"
|
|
else
|
|
group.word 0x110++0x03
|
|
line.word 0x00 "MATCH4_L,SCT match value register of match channel 4 low counter 16-bit"
|
|
line.word 0x02 "MATCH4_H,SCT match value register of match channel 4 high counter 16-bit"
|
|
rgroup.word 0x110++0x03
|
|
line.word 0x00 "CAP4_L,SCT capture register of capture channel 4 low counter 16-bit"
|
|
line.word 0x02 "CAP4_H,SCT capture register of capture channel 4 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT match value register of match channel 5"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT capture register of capture channel 5"
|
|
else
|
|
group.word 0x114++0x03
|
|
line.word 0x00 "MATCH5_L,SCT match value register of match channel 5 low counter 16-bit"
|
|
line.word 0x02 "MATCH5_H,SCT match value register of match channel 5 high counter 16-bit"
|
|
rgroup.word 0x114++0x03
|
|
line.word 0x00 "CAP5_L,SCT capture register of capture channel 5 low counter 16-bit"
|
|
line.word 0x02 "CAP5_H,SCT capture register of capture channel 5 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT match value register of match channel 6"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT capture register of capture channel 6"
|
|
else
|
|
group.word 0x118++0x03
|
|
line.word 0x00 "MATCH6_L,SCT match value register of match channel 6 low counter 16-bit"
|
|
line.word 0x02 "MATCH6_H,SCT match value register of match channel 6 high counter 16-bit"
|
|
rgroup.word 0x118++0x03
|
|
line.word 0x00 "CAP6_L,SCT capture register of capture channel 6 low counter 16-bit"
|
|
line.word 0x02 "CAP6_H,SCT capture register of capture channel 6 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT match value register of match channel 7"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT capture register of capture channel 7"
|
|
else
|
|
group.word 0x11C++0x03
|
|
line.word 0x00 "MATCH7_L,SCT match value register of match channel 7 low counter 16-bit"
|
|
line.word 0x02 "MATCH7_H,SCT match value register of match channel 7 high counter 16-bit"
|
|
rgroup.word 0x11C++0x03
|
|
line.word 0x00 "CAP7_L,SCT capture register of capture channel 7 low counter 16-bit"
|
|
line.word 0x02 "CAP7_H,SCT capture register of capture channel 7 high counter 16-bit"
|
|
endif
|
|
tree.end
|
|
tree "Match reload and capture control registers"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MATCHREL0,SCT match reload value register 0"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CAPCTRL0,SCT capture control register 0"
|
|
bitfld.long 0x00 9. " CAPCON0[9] ,Event 9 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON0[8] ,Event 8 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON0[7] ,Event 7 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON0[6] ,Event 6 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON0[5] ,Event 5 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON0[4] ,Event 4 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON0[3] ,Event 3 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON0[2] ,Event 2 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON0[1] ,Event 1 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON0[0] ,Event 0 causes load of CAP0 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "MATCHREL0_L,SCT match reload value register 0 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL0_H,SCT match reload value register 0 high counter 16-bit"
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "CAPCTRL0_L,SCT capture control register 0 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON0_L[9] ,Event 9 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON0_L[8] ,Event 8 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON0_L[7] ,Event 7 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON0_L[6] ,Event 6 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON0_L[5] ,Event 5 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON0_L[4] ,Event 4 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON0_L[3] ,Event 3 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON0_L[2] ,Event 2 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON0_L[1] ,Event 1 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON0_L[0] ,Event 0 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL0_H,SCT capture control register 0 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON0_H[9] ,Event 9 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON0_H[8] ,Event 8 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON0_H[7] ,Event 7 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON0_H[6] ,Event 6 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON0_H[5] ,Event 5 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON0_H[4] ,Event 4 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON0_H[3] ,Event 3 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON0_H[2] ,Event 2 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON0_H[1] ,Event 1 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON0_H[0] ,Event 0 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "MATCHREL1,SCT match reload value register 1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CAPCTRL1,SCT capture control register 1"
|
|
bitfld.long 0x00 9. " CAPCON1[9] ,Event 9 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON1[8] ,Event 8 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON1[7] ,Event 7 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON1[6] ,Event 6 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON1[5] ,Event 5 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON1[4] ,Event 4 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON1[3] ,Event 3 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON1[2] ,Event 2 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON1[1] ,Event 1 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON1[0] ,Event 0 causes load of CAP1 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "MATCHREL1_L,SCT match reload value register 1 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL1_H,SCT match reload value register 1 high counter 16-bit"
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "CAPCTRL1_L,SCT capture control register 1 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON1_L[9] ,Event 9 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON1_L[8] ,Event 8 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON1_L[7] ,Event 7 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON1_L[6] ,Event 6 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON1_L[5] ,Event 5 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON1_L[4] ,Event 4 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON1_L[3] ,Event 3 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON1_L[2] ,Event 2 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON1_L[1] ,Event 1 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON1_L[0] ,Event 0 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL1_H,SCT capture control register 1 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON1_H[9] ,Event 9 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON1_H[8] ,Event 8 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON1_H[7] ,Event 7 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON1_H[6] ,Event 6 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON1_H[5] ,Event 5 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON1_H[4] ,Event 4 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON1_H[3] ,Event 3 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON1_H[2] ,Event 2 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON1_H[1] ,Event 1 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON1_H[0] ,Event 0 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "MATCHREL2,SCT match reload value register 2"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CAPCTRL2,SCT capture control register 2"
|
|
bitfld.long 0x00 9. " CAPCON2[9] ,Event 9 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON2[8] ,Event 8 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON2[7] ,Event 7 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON2[6] ,Event 6 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON2[5] ,Event 5 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON2[4] ,Event 4 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON2[3] ,Event 3 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON2[2] ,Event 2 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON2[1] ,Event 1 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON2[0] ,Event 0 causes load of CAP2 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "MATCHREL2_L,SCT match reload value register 2 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL2_H,SCT match reload value register 2 high counter 16-bit"
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "CAPCTRL2_L,SCT capture control register 2 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON2_L[9] ,Event 9 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON2_L[8] ,Event 8 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON2_L[7] ,Event 7 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON2_L[6] ,Event 6 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON2_L[5] ,Event 5 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON2_L[4] ,Event 4 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON2_L[3] ,Event 3 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON2_L[2] ,Event 2 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON2_L[1] ,Event 1 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON2_L[0] ,Event 0 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL2_H,SCT capture control register 2 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON2_H[9] ,Event 9 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON2_H[8] ,Event 8 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON2_H[7] ,Event 7 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON2_H[6] ,Event 6 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON2_H[5] ,Event 5 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON2_H[4] ,Event 4 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON2_H[3] ,Event 3 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON2_H[2] ,Event 2 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON2_H[1] ,Event 1 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON2_H[0] ,Event 0 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "MATCHREL3,SCT match reload value register 3"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CAPCTRL3,SCT capture control register 3"
|
|
bitfld.long 0x00 9. " CAPCON3[9] ,Event 9 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON3[8] ,Event 8 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON3[7] ,Event 7 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON3[6] ,Event 6 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON3[5] ,Event 5 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON3[4] ,Event 4 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON3[3] ,Event 3 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON3[2] ,Event 2 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON3[1] ,Event 1 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON3[0] ,Event 0 causes load of CAP3 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "MATCHREL3_L,SCT match reload value register 3 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL3_H,SCT match reload value register 3 high counter 16-bit"
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "CAPCTRL3_L,SCT capture control register 3 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON3_L[9] ,Event 9 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON3_L[8] ,Event 8 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON3_L[7] ,Event 7 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON3_L[6] ,Event 6 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON3_L[5] ,Event 5 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON3_L[4] ,Event 4 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON3_L[3] ,Event 3 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON3_L[2] ,Event 2 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON3_L[1] ,Event 1 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON3_L[0] ,Event 0 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL3_H,SCT capture control register 3 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON3_H[9] ,Event 9 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON3_H[8] ,Event 8 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON3_H[7] ,Event 7 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON3_H[6] ,Event 6 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON3_H[5] ,Event 5 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON3_H[4] ,Event 4 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON3_H[3] ,Event 3 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON3_H[2] ,Event 2 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON3_H[1] ,Event 1 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON3_H[0] ,Event 0 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "MATCHREL4,SCT match reload value register 4"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CAPCTRL4,SCT capture control register 4"
|
|
bitfld.long 0x00 9. " CAPCON4[9] ,Event 9 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON4[8] ,Event 8 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON4[7] ,Event 7 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON4[6] ,Event 6 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON4[5] ,Event 5 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON4[4] ,Event 4 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON4[3] ,Event 3 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON4[2] ,Event 2 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON4[1] ,Event 1 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON4[0] ,Event 0 causes load of CAP4 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "MATCHREL4_L,SCT match reload value register 4 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL4_H,SCT match reload value register 4 high counter 16-bit"
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "CAPCTRL4_L,SCT capture control register 4 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON4_L[9] ,Event 9 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON4_L[8] ,Event 8 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON4_L[7] ,Event 7 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON4_L[6] ,Event 6 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON4_L[5] ,Event 5 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON4_L[4] ,Event 4 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON4_L[3] ,Event 3 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON4_L[2] ,Event 2 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON4_L[1] ,Event 1 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON4_L[0] ,Event 0 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL4_H,SCT capture control register 4 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON4_H[9] ,Event 9 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON4_H[8] ,Event 8 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON4_H[7] ,Event 7 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON4_H[6] ,Event 6 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON4_H[5] ,Event 5 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON4_H[4] ,Event 4 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON4_H[3] ,Event 3 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON4_H[2] ,Event 2 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON4_H[1] ,Event 1 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON4_H[0] ,Event 0 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "MATCHREL5,SCT match reload value register 5"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CAPCTRL5,SCT capture control register 5"
|
|
bitfld.long 0x00 9. " CAPCON5[9] ,Event 9 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON5[8] ,Event 8 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON5[7] ,Event 7 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON5[6] ,Event 6 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON5[5] ,Event 5 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON5[4] ,Event 4 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON5[3] ,Event 3 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON5[2] ,Event 2 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON5[1] ,Event 1 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON5[0] ,Event 0 causes load of CAP5 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "MATCHREL5_L,SCT match reload value register 5 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL5_H,SCT match reload value register 5 high counter 16-bit"
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "CAPCTRL5_L,SCT capture control register 5 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON5_L[9] ,Event 9 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON5_L[8] ,Event 8 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON5_L[7] ,Event 7 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON5_L[6] ,Event 6 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON5_L[5] ,Event 5 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON5_L[4] ,Event 4 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON5_L[3] ,Event 3 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON5_L[2] ,Event 2 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON5_L[1] ,Event 1 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON5_L[0] ,Event 0 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL5_H,SCT capture control register 5 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON5_H[9] ,Event 9 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON5_H[8] ,Event 8 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON5_H[7] ,Event 7 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON5_H[6] ,Event 6 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON5_H[5] ,Event 5 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON5_H[4] ,Event 4 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON5_H[3] ,Event 3 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON5_H[2] ,Event 2 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON5_H[1] ,Event 1 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON5_H[0] ,Event 0 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "MATCHREL6,SCT match reload value register 6"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "CAPCTRL6,SCT capture control register 6"
|
|
bitfld.long 0x00 9. " CAPCON6[9] ,Event 9 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON6[8] ,Event 8 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON6[7] ,Event 7 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON6[6] ,Event 6 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON6[5] ,Event 5 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON6[4] ,Event 4 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON6[3] ,Event 3 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON6[2] ,Event 2 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON6[1] ,Event 1 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON6[0] ,Event 0 causes load of CAP6 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "MATCHREL6_L,SCT match reload value register 6 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL6_H,SCT match reload value register 6 high counter 16-bit"
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "CAPCTRL6_L,SCT capture control register 6 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON6_L[9] ,Event 9 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON6_L[8] ,Event 8 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON6_L[7] ,Event 7 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON6_L[6] ,Event 6 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON6_L[5] ,Event 5 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON6_L[4] ,Event 4 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON6_L[3] ,Event 3 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON6_L[2] ,Event 2 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON6_L[1] ,Event 1 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON6_L[0] ,Event 0 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL6_H,SCT capture control register 6 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON6_H[9] ,Event 9 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON6_H[8] ,Event 8 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON6_H[7] ,Event 7 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON6_H[6] ,Event 6 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON6_H[5] ,Event 5 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON6_H[4] ,Event 4 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON6_H[3] ,Event 3 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON6_H[2] ,Event 2 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON6_H[1] ,Event 1 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON6_H[0] ,Event 0 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MATCHREL7,SCT match reload value register 7"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CAPCTRL7,SCT capture control register 7"
|
|
bitfld.long 0x00 9. " CAPCON7[9] ,Event 9 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON7[8] ,Event 8 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON7[7] ,Event 7 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON7[6] ,Event 6 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON7[5] ,Event 5 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON7[4] ,Event 4 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON7[3] ,Event 3 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON7[2] ,Event 2 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON7[1] ,Event 1 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON7[0] ,Event 0 causes load of CAP7 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "MATCHREL7_L,SCT match reload value register 7 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL7_H,SCT match reload value register 7 high counter 16-bit"
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "CAPCTRL7_L,SCT capture control register 7 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON7_L[9] ,Event 9 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON7_L[8] ,Event 8 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON7_L[7] ,Event 7 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON7_L[6] ,Event 6 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON7_L[5] ,Event 5 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON7_L[4] ,Event 4 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON7_L[3] ,Event 3 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON7_L[2] ,Event 2 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON7_L[1] ,Event 1 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON7_L[0] ,Event 0 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL7_H,SCT capture control register 7 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON7_H[9] ,Event 9 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON7_H[8] ,Event 8 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON7_H[7] ,Event 7 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON7_H[6] ,Event 6 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON7_H[5] ,Event 5 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON7_H[4] ,Event 4 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON7_H[3] ,Event 3 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON7_H[2] ,Event 2 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON7_H[1] ,Event 1 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON7_H[0] ,Event 0 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
endif
|
|
tree.end
|
|
tree "Event state and control registers"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "EV0 _STATE,SCT event state register 0 "
|
|
bitfld.long 0x00 9. " STATEMSK0 [9] ,State 9 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK0 [8] ,State 8 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK0 [7] ,State 7 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK0 [6] ,State 6 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK0 [5] ,State 5 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK0 [4] ,State 4 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK0 [3] ,State 3 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK0 [2] ,State 2 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK0 [1] ,State 1 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK0 [0] ,State 0 of event 0 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0 _CTRL,SCT event control register 0 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0 _CTRL,SCT event control register 0 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EV1 _STATE,SCT event state register 1 "
|
|
bitfld.long 0x00 9. " STATEMSK1 [9] ,State 9 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK1 [8] ,State 8 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK1 [7] ,State 7 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK1 [6] ,State 6 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK1 [5] ,State 5 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK1 [4] ,State 4 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK1 [3] ,State 3 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK1 [2] ,State 2 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK1 [1] ,State 1 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK1 [0] ,State 0 of event 1 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1 _CTRL,SCT event control register 1 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1 _CTRL,SCT event control register 1 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EV2 _STATE,SCT event state register 2 "
|
|
bitfld.long 0x00 9. " STATEMSK2 [9] ,State 9 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK2 [8] ,State 8 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK2 [7] ,State 7 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK2 [6] ,State 6 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK2 [5] ,State 5 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK2 [4] ,State 4 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK2 [3] ,State 3 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK2 [2] ,State 2 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK2 [1] ,State 1 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK2 [0] ,State 0 of event 2 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2 _CTRL,SCT event control register 2 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2 _CTRL,SCT event control register 2 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EV3 _STATE,SCT event state register 3 "
|
|
bitfld.long 0x00 9. " STATEMSK3 [9] ,State 9 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK3 [8] ,State 8 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK3 [7] ,State 7 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK3 [6] ,State 6 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK3 [5] ,State 5 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK3 [4] ,State 4 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK3 [3] ,State 3 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK3 [2] ,State 2 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK3 [1] ,State 1 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK3 [0] ,State 0 of event 3 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3 _CTRL,SCT event control register 3 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3 _CTRL,SCT event control register 3 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EV4 _STATE,SCT event state register 4 "
|
|
bitfld.long 0x00 9. " STATEMSK4 [9] ,State 9 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK4 [8] ,State 8 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK4 [7] ,State 7 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK4 [6] ,State 6 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK4 [5] ,State 5 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK4 [4] ,State 4 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK4 [3] ,State 3 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK4 [2] ,State 2 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK4 [1] ,State 1 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK4 [0] ,State 0 of event 4 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4 _CTRL,SCT event control register 4 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4 _CTRL,SCT event control register 4 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EV5 _STATE,SCT event state register 5 "
|
|
bitfld.long 0x00 9. " STATEMSK5 [9] ,State 9 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK5 [8] ,State 8 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK5 [7] ,State 7 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK5 [6] ,State 6 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK5 [5] ,State 5 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK5 [4] ,State 4 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK5 [3] ,State 3 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK5 [2] ,State 2 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK5 [1] ,State 1 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK5 [0] ,State 0 of event 5 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5 _CTRL,SCT event control register 5 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5 _CTRL,SCT event control register 5 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EV6 _STATE,SCT event state register 6 "
|
|
bitfld.long 0x00 9. " STATEMSK6 [9] ,State 9 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK6 [8] ,State 8 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK6 [7] ,State 7 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK6 [6] ,State 6 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK6 [5] ,State 5 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK6 [4] ,State 4 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK6 [3] ,State 3 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK6 [2] ,State 2 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK6 [1] ,State 1 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK6 [0] ,State 0 of event 6 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6 _CTRL,SCT event control register 6 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6 _CTRL,SCT event control register 6 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EV7 _STATE,SCT event state register 7 "
|
|
bitfld.long 0x00 9. " STATEMSK7 [9] ,State 9 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK7 [8] ,State 8 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK7 [7] ,State 7 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK7 [6] ,State 6 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK7 [5] ,State 5 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK7 [4] ,State 4 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK7 [3] ,State 3 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK7 [2] ,State 2 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK7 [1] ,State 1 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK7 [0] ,State 0 of event 7 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7 _CTRL,SCT event control register 7 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7 _CTRL,SCT event control register 7 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "EV8 _STATE,SCT event state register 8 "
|
|
bitfld.long 0x00 9. " STATEMSK8 [9] ,State 9 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK8 [8] ,State 8 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK8 [7] ,State 7 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK8 [6] ,State 6 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK8 [5] ,State 5 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK8 [4] ,State 4 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK8 [3] ,State 3 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK8 [2] ,State 2 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK8 [1] ,State 1 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK8 [0] ,State 0 of event 8 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8 _CTRL,SCT event control register 8 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8 _CTRL,SCT event control register 8 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EV9 _STATE,SCT event state register 9 "
|
|
bitfld.long 0x00 9. " STATEMSK9 [9] ,State 9 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK9 [8] ,State 8 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK9 [7] ,State 7 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK9 [6] ,State 6 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK9 [5] ,State 5 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK9 [4] ,State 4 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK9 [3] ,State 3 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK9 [2] ,State 2 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK9 [1] ,State 1 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK9 [0] ,State 0 of event 9 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C020000))&0x1)==0x1)
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9 _CTRL,SCT event control register 9 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9 _CTRL,SCT event control register 9 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Output set/clear registers"
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OUT0_SET,SCT output 0 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 0" "Not set,Set"
|
|
line.long 0x04 "OUT0_CLR,SCT output 0 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 0" "Not set,Set"
|
|
group.long 0x508++0x07
|
|
line.long 0x00 "OUT1_SET,SCT output 1 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 1" "Not set,Set"
|
|
line.long 0x04 "OUT1_CLR,SCT output 1 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 1" "Not set,Set"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OUT2_SET,SCT output 2 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 2" "Not set,Set"
|
|
line.long 0x04 "OUT2_CLR,SCT output 2 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 2" "Not set,Set"
|
|
group.long 0x518++0x07
|
|
line.long 0x00 "OUT3_SET,SCT output 3 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 3" "Not set,Set"
|
|
line.long 0x04 "OUT3_CLR,SCT output 3 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 3" "Not set,Set"
|
|
group.long 0x520++0x07
|
|
line.long 0x00 "OUT4_SET,SCT output 4 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 4" "Not set,Set"
|
|
line.long 0x04 "OUT4_CLR,SCT output 4 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 4" "Not set,Set"
|
|
group.long 0x528++0x07
|
|
line.long 0x00 "OUT5_SET,SCT output 5 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 5" "Not set,Set"
|
|
line.long 0x04 "OUT5_CLR,SCT output 5 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 5" "Not set,Set"
|
|
tree.end
|
|
width 0x0b
|
|
tree.end
|
|
tree "SCTimer 3"
|
|
base ad:0x1C024000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,SCT configuration register"
|
|
bitfld.long 0x00 18. " AUTOLIMIT_H ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto"
|
|
bitfld.long 0x00 16. " INSYNC7 ,Synchronization for input 7" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 15. " INSYNC6 ,Synchronization for input 6" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INSYNC5 ,Synchronization for input 5" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 13. " INSYNC4 ,Synchronization for input 4" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 12. " INSYNC3 ,Synchronization for input 3" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 11. " INSYNC2 ,Synchronization for input 2" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 10. " INSYNC1 ,Synchronization for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 9. " INSYNC0 ,Synchronization for input 0" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " NORELOAD_H ,Prevent the higher match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
bitfld.long 0x00 7. " NORELOAD_L ,Prevent the lower match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input (0:7)" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..."
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT"
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operate as unified 32-bit counter" "Not unified,Unified"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "CTRL,SCT control register"
|
|
hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock"
|
|
bitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down"
|
|
line.long 0x04 "LIMIT,SCT limit register"
|
|
bitfld.long 0x04 15. " LIMMSK[15] ,Event 15 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 14. " LIMMSK[14] ,Event 14 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 13. " LIMMSK[13] ,Event 13 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 12. " LIMMSK[12] ,Event 12 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LIMMSK[11] ,Event 11 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 10. " LIMMSK[10] ,Event 10 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 9. " LIMMSK[9] ,Event 9 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 8. " LIMMSK[8] ,Event 8 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LIMMSK[7] ,Event 7 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 6. " LIMMSK[6] ,Event 6 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 5. " LIMMSK[5] ,Event 5 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 4. " LIMMSK[4] ,Event 4 use as counter limit for unified counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LIMMSK[3] ,Event 3 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 2. " LIMMSK[2] ,Event 2 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 1. " LIMMSK[1] ,Event 1 use as counter limit for unified counter" "Not used,Used"
|
|
bitfld.long 0x04 0. " LIMMSK[0] ,Event 0 use as counter limit for unified counter" "Not used,Used"
|
|
line.long 0x08 "HALT,SCT halt condition register"
|
|
bitfld.long 0x08 15. " HALTMSK[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 14. " HALTMSK[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 13. " HALTMSK[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 12. " HALTMSK[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HALTMSK[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 10. " HALTMSK[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 9. " HALTMSK[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 8. " HALTMSK[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HALTMSK[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 6. " HALTMSK[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 5. " HALTMSK[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 4. " HALTMSK[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HALTMSK[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 2. " HALTMSK[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 1. " HALTMSK[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x08 0. " HALTMSK[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x0C "STOP,SCT stop condition register"
|
|
bitfld.long 0x0C 15. " STOPMSK[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 14. " STOPMSK[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 13. " STOPMSK[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 12. " STOPMSK[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " STOPMSK[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 10. " STOPMSK[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 9. " STOPMSK[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 8. " STOPMSK[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " STOPMSK[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 6. " STOPMSK[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 5. " STOPMSK[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 4. " STOPMSK[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " STOPMSK[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 2. " STOPMSK[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 1. " STOPMSK[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.long 0x0C 0. " STOPMSK[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.long 0x10 "START,SCT start condition register"
|
|
bitfld.long 0x10 15. " STARTMSK[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 14. " STARTMSK[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 13. " STARTMSK[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 12. " STARTMSK[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 11. " STARTMSK[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 10. " STARTMSK[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 9. " STARTMSK[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 8. " STARTMSK[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 7. " STARTMSK[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 6. " STARTMSK[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 5. " STARTMSK[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 4. " STARTMSK[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 3. " STARTMSK[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 2. " STARTMSK[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 1. " STARTMSK[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.long 0x10 0. " STARTMSK[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "COUNT,SCT counter register"
|
|
line.long 0x04 "STATE,SCT state register"
|
|
bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT match/capture registers mode register"
|
|
bitfld.long 0x00 15. " REGMOD[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 14. " REGMOD[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 13. " REGMOD[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 12. " REGMOD[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REGMOD[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 10. " REGMOD[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 9. " REGMOD[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 8. " REGMOD[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REGMOD[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 6. " REGMOD[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 5. " REGMOD[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 4. " REGMOD[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REGMOD[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 2. " REGMOD[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 1. " REGMOD[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.long 0x00 0. " REGMOD[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
else
|
|
group.word 0x04++0x13
|
|
line.word 0x00 "CTRL_L,SCT control lower 16-bit register"
|
|
hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock"
|
|
bitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down"
|
|
line.word 0x02 "CTRL_H,SCT control higher 16-bit register"
|
|
hexmask.word.byte 0x02 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock"
|
|
bitfld.word 0x02 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down"
|
|
bitfld.word 0x02 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared"
|
|
bitfld.word 0x02 2. " HALT_H ,H counter halt" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.word 0x02 1. " STOP_H ,H counter stop" "Not stopped,Stopped"
|
|
bitfld.word 0x02 0. " DOWN_H ,H counter counting down" "Counting up,Counting down"
|
|
line.word 0x04 "LIMIT_L,SCT limit higher 16-bit register"
|
|
bitfld.word 0x04 15. " LIMMSK_L[15] ,Event 15 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 14. " LIMMSK_L[14] ,Event 14 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 13. " LIMMSK_L[13] ,Event 13 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 12. " LIMMSK_L[12] ,Event 12 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 11. " LIMMSK_L[11] ,Event 11 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 10. " LIMMSK_L[10] ,Event 10 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 9. " LIMMSK_L[9] ,Event 9 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 8. " LIMMSK_L[8] ,Event 8 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 7. " LIMMSK_L[7] ,Event 7 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 6. " LIMMSK_L[6] ,Event 6 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 5. " LIMMSK_L[5] ,Event 5 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 4. " LIMMSK_L[4] ,Event 4 use as counter limit for L counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x04 3. " LIMMSK_L[3] ,Event 3 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 2. " LIMMSK_L[2] ,Event 2 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 1. " LIMMSK_L[1] ,Event 1 use as counter limit for L counter" "Not used,Used"
|
|
bitfld.word 0x04 0. " LIMMSK_L[0] ,Event 0 use as counter limit for L counter" "Not used,Used"
|
|
line.word 0x06 "LIMIT_H,SCT limit lower 16-bit register"
|
|
bitfld.word 0x06 15. " LIMMSK_H[15] ,Event 15 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 14. " LIMMSK_H[14] ,Event 14 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 13. " LIMMSK_H[13] ,Event 13 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 12. " LIMMSK_H[12] ,Event 12 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 11. " LIMMSK_H[11] ,Event 11 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 10. " LIMMSK_H[10] ,Event 10 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 9. " LIMMSK_H[9] ,Event 9 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 8. " LIMMSK_H[8] ,Event 8 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 7. " LIMMSK_H[7] ,Event 7 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 6. " LIMMSK_H[6] ,Event 6 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 5. " LIMMSK_H[5] ,Event 5 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 4. " LIMMSK_H[4] ,Event 4 use as counter limit for H counter" "Not used,Used"
|
|
textline " "
|
|
bitfld.word 0x06 3. " LIMMSK_H[3] ,Event 3 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 2. " LIMMSK_H[2] ,Event 2 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 1. " LIMMSK_H[1] ,Event 1 use as counter limit for H counter" "Not used,Used"
|
|
bitfld.word 0x06 0. " LIMMSK_H[0] ,Event 0 use as counter limit for H counter" "Not used,Used"
|
|
line.word 0x08 "HALT_L,SCT halt condition lower 16-bit register"
|
|
bitfld.word 0x08 15. " HALTMSK_L[15] ,Event 15 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 14. " HALTMSK_L[14] ,Event 14 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 13. " HALTMSK_L[13] ,Event 13 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 12. " HALTMSK_L[12] ,Event 12 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 11. " HALTMSK_L[11] ,Event 11 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 10. " HALTMSK_L[10] ,Event 10 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 9. " HALTMSK_L[9] ,Event 9 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 8. " HALTMSK_L[8] ,Event 8 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 7. " HALTMSK_L[7] ,Event 7 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 6. " HALTMSK_L[6] ,Event 6 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 5. " HALTMSK_L[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 4. " HALTMSK_L[4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x08 3. " HALTMSK_L[3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 2. " HALTMSK_L[2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 1. " HALTMSK_L[1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x08 0. " HALTMSK_L[0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0A "HALT_H,SCT halt condition higher 16-bit register"
|
|
bitfld.word 0x0A 15. " HALTMSK_H[15] ,Event 15 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 14. " HALTMSK_H[14] ,Event 14 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 13. " HALTMSK_H[13] ,Event 13 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 12. " HALTMSK_H[12] ,Event 12 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 11. " HALTMSK_H[11] ,Event 11 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 10. " HALTMSK_H[10] ,Event 10 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 9. " HALTMSK_H[9] ,Event 9 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 8. " HALTMSK_H[8] ,Event 8 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 7. " HALTMSK_H[7] ,Event 7 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 6. " HALTMSK_H[6] ,Event 6 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 5. " HALTMSK_H[5] ,Event 5 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 4. " HALTMSK_H[4] ,Event 4 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0A 3. " HALTMSK_H[3] ,Event 3 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 2. " HALTMSK_H[2] ,Event 2 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 1. " HALTMSK_H[1] ,Event 1 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0A 0. " HALTMSK_H[0] ,Event 0 sets HALT_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x0C "STOP_L,SCT stop condition lower 16-bit register"
|
|
bitfld.word 0x0C 15. " STOPMSK_L[15] ,Event 15 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 14. " STOPMSK_L[14] ,Event 14 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 13. " STOPMSK_L[13] ,Event 13 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 12. " STOPMSK_L[12] ,Event 12 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 11. " STOPMSK_L[11] ,Event 11 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 10. " STOPMSK_L[10] ,Event 10 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 9. " STOPMSK_L[9] ,Event 9 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 8. " STOPMSK_L[8] ,Event 8 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 7. " STOPMSK_L[7] ,Event 7 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 6. " STOPMSK_L[6] ,Event 6 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 5. " STOPMSK_L[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 4. " STOPMSK_L[4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0C 3. " STOPMSK_L[3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 2. " STOPMSK_L[2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 1. " STOPMSK_L[1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0C 0. " STOPMSK_L[0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set"
|
|
line.word 0x0E "STOP_H,SCT stop condition higher 16-bit register"
|
|
bitfld.word 0x0E 15. " STOPMSK_H[15] ,Event 15 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 14. " STOPMSK_H[14] ,Event 14 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 13. " STOPMSK_H[13] ,Event 13 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 12. " STOPMSK_H[12] ,Event 12 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 11. " STOPMSK_H[11] ,Event 11 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 10. " STOPMSK_H[10] ,Event 10 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 9. " STOPMSK_H[9] ,Event 9 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 8. " STOPMSK_H[8] ,Event 8 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 7. " STOPMSK_H[7] ,Event 7 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 6. " STOPMSK_H[6] ,Event 6 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 5. " STOPMSK_H[5] ,Event 5 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 4. " STOPMSK_H[4] ,Event 4 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
textline " "
|
|
bitfld.word 0x0E 3. " STOPMSK_H[3] ,Event 3 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 2. " STOPMSK_H[2] ,Event 2 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 1. " STOPMSK_H[1] ,Event 1 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
bitfld.word 0x0E 0. " STOPMSK_H[0] ,Event 0 sets STOP_H bit in CTRL register" "Not set,Set"
|
|
line.word 0x10 "START_L,SCT start condition lower 16-bit register"
|
|
bitfld.word 0x10 15. " STARTMSK_L[15] ,Event 15 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 14. " STARTMSK_L[14] ,Event 14 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 13. " STARTMSK_L[13] ,Event 13 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 12. " STARTMSK_L[12] ,Event 12 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 11. " STARTMSK_L[11] ,Event 11 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 10. " STARTMSK_L[10] ,Event 10 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 9. " STARTMSK_L[9] ,Event 9 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 8. " STARTMSK_L[8] ,Event 8 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 7. " STARTMSK_L[7] ,Event 7 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 6. " STARTMSK_L[6] ,Event 6 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 5. " STARTMSK_L[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 4. " STARTMSK_L[4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x10 3. " STARTMSK_L[3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 2. " STARTMSK_L[2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 1. " STARTMSK_L[1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x10 0. " STARTMSK_L[0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared"
|
|
line.word 0x12 "START_H,SCT start condition higher 16-bit register"
|
|
bitfld.word 0x12 15. " STARTMSK_H[15] ,Event 15 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 14. " STARTMSK_H[14] ,Event 14 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 13. " STARTMSK_H[13] ,Event 13 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 12. " STARTMSK_H[12] ,Event 12 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 11. " STARTMSK_H[11] ,Event 11 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 10. " STARTMSK_H[10] ,Event 10 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 9. " STARTMSK_H[9] ,Event 9 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 8. " STARTMSK_H[8] ,Event 8 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 7. " STARTMSK_H[7] ,Event 7 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 6. " STARTMSK_H[6] ,Event 6 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 5. " STARTMSK_H[5] ,Event 5 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 4. " STARTMSK_H[4] ,Event 4 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.word 0x12 3. " STARTMSK_H[3] ,Event 3 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 2. " STARTMSK_H[2] ,Event 2 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 1. " STARTMSK_H[1] ,Event 1 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
bitfld.word 0x12 0. " STARTMSK_H[0] ,Event 0 clears STOP_H bit in CTRL register" "Not cleared,Cleared"
|
|
group.word 0x40++0x7
|
|
line.word 0x00 "COUNT_L,SCT counter register low counter 16-bit"
|
|
line.word 0x02 "COUNT_H,SCT counter register high counter 16-bit"
|
|
line.word 0x04 "STATE_L,SCT state register low counter 16-bit"
|
|
bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x06 "STATE_L,SCT state register high counter 16-bit"
|
|
bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT input register"
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state" "Low,High"
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state(Direct read)" "Low,High"
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state(Direct read)" "Low,High"
|
|
group.word 0x4C++0x03
|
|
line.word 0x00 "REGMODE_L,SCT match/capture registers mode register low counter 16-bit"
|
|
bitfld.word 0x00 15. " REGMOD_L[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 14. " REGMOD_L[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 13. " REGMOD_L[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 12. " REGMOD_L[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 11. " REGMOD_L[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 10. " REGMOD_L[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 9. " REGMOD_L[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 8. " REGMOD_L[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 7. " REGMOD_L[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 6. " REGMOD_L[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 5. " REGMOD_L[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 4. " REGMOD_L[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 3. " REGMOD_L[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 2. " REGMOD_L[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 1. " REGMOD_L[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x00 0. " REGMOD_L[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
line.word 0x02 "REGMODE_H,SCT match/capture registers mode register high counter 16-bit"
|
|
bitfld.word 0x02 15. " REGMOD_H[15] ,Pair 15 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 14. " REGMOD_H[14] ,Pair 14 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 13. " REGMOD_H[13] ,Pair 13 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 12. " REGMOD_H[12] ,Pair 12 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 11. " REGMOD_H[11] ,Pair 11 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 10. " REGMOD_H[10] ,Pair 10 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 9. " REGMOD_H[9] ,Pair 9 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 8. " REGMOD_H[8] ,Pair 8 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 7. " REGMOD_H[7] ,Pair 7 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 6. " REGMOD_H[6] ,Pair 6 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 5. " REGMOD_H[5] ,Pair 5 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 4. " REGMOD_H[4] ,Pair 4 of match/capture register operation mode" "Match,Capture"
|
|
textline " "
|
|
bitfld.word 0x02 3. " REGMOD_H[3] ,Pair 3 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 2. " REGMOD_H[2] ,Pair 2 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 1. " REGMOD_H[1] ,Pair 1 of match/capture register operation mode" "Match,Capture"
|
|
bitfld.word 0x02 0. " REGMOD_H[0] ,Pair 0 of match/capture register operation mode" "Match,Capture"
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "OUTPUT,SCT output register"
|
|
bitfld.long 0x00 5. " OUT[5] ,Set high on output 5" "Low,High"
|
|
bitfld.long 0x00 4. " OUT[4] ,Set high on output 4" "Low,High"
|
|
bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High"
|
|
bitfld.long 0x00 2. " OUT[2] ,Set high on output 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUT[1] ,Set high on output 1" "Low,High"
|
|
bitfld.long 0x00 0. " OUT[0] ,Set high on output 0" "Low,High"
|
|
line.long 0x04 "OUTPUTDIRCTRL,SCT output counter direction control register"
|
|
bitfld.long 0x04 10.--11. " SETCLR5 ,Set/clear operation on output 5 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 8.--9. " SETCLR4 ,Set/clear operation on output 4 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 6.--7. " SETCLR3 ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 4.--5. " SETCLR2 ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SETCLR1 ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
bitfld.long 0x04 0.--1. " SETCLR0 ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..."
|
|
line.long 0x08 "RES,SCT conflict resolution register"
|
|
bitfld.long 0x08 10.--11. " O5RES ,Effect of simultaneous set and clear on output 5" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x08 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle"
|
|
line.long 0x0c "DMAREQ0,SCT DMA request 0 register"
|
|
rbitfld.long 0x0c 31. " DRQ0 ,Indicates the state of DMA Request 0" "Low,High"
|
|
bitfld.long 0x0c 30. " DRL0 ,SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x0c 15. " DEV_0[15] ,Event 15 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 14. " DEV_0[14] ,Event 14 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " DEV_0[13] ,Event 13 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 12. " DEV_0[12] ,Event 12 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 11. " DEV_0[11] ,Event 11 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 10. " DEV_0[10] ,Event 10 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " DEV_0[9] ,Event 9 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 8. " DEV_0[8] ,Event 8 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 7. " DEV_0[7] ,Event 7 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 6. " DEV_0[6] ,Event 6 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 4. " DEV_0[4] ,Event 4 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 3. " DEV_0[3] ,Event 3 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 2. " DEV_0[2] ,Event 2 sets DMA request 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " DEV_0[1] ,Event 1 sets DMA request 0" "Not set,Set"
|
|
bitfld.long 0x0c 0. " DEV_0[0] ,Event 0 sets DMA request 0" "Not set,Set"
|
|
line.long 0x10 "DMAREQ1,SCT DMA request 1 register"
|
|
rbitfld.long 0x10 31. " DRQ1 ,Indicates the state of DMA Request 1" "Low,High"
|
|
bitfld.long 0x10 30. " DRL1 ,SCT set DMA request 1 when it loads the Match_L/Unified registers from the Reload_L/Unified registers" "Low,High"
|
|
bitfld.long 0x10 15. " DEV_1[15] ,Event 15 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 14. " DEV_1[14] ,Event 14 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 13. " DEV_1[13] ,Event 13 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 12. " DEV_1[12] ,Event 12 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 11. " DEV_1[11] ,Event 11 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 10. " DEV_1[10] ,Event 10 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DEV_1[9] ,Event 9 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 8. " DEV_1[8] ,Event 8 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 7. " DEV_1[7] ,Event 7 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 6. " DEV_1[6] ,Event 6 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 4. " DEV_1[4] ,Event 4 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 3. " DEV_1[3] ,Event 3 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 2. " DEV_1[2] ,Event 2 sets DMA request 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DEV_1[1] ,Event 1 sets DMA request 1" "Not set,Set"
|
|
bitfld.long 0x10 0. " DEV_1[0] ,Event 0 sets DMA request 1" "Not set,Set"
|
|
group.long 0xF0++0xf
|
|
line.long 0x00 "EVEN,SCT event enable register"
|
|
bitfld.long 0x00 15. " IEN[15] ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IEN[14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IEN[13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IEN[12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IEN[11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IEN[10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVFLAG,SCT event flag register"
|
|
bitfld.long 0x04 15. " FLAG[15] ,Event 15 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " FLAG[14] ,Event 14 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " FLAG[13] ,Event 13 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " FLAG[12] ,Event 12 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FLAG[11] ,Event 11 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " FLAG[10] ,Event 10 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " FLAG[9] ,Event 9 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " FLAG[8] ,Event 8 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FLAG[7] ,Event 7 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " FLAG[6] ,Event 6 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " FLAG[4] ,Event 4 occurred flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLAG[3] ,Event 3 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " FLAG[2] ,Event 2 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " FLAG[1] ,Event 1 occurred flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " FLAG[0] ,Event 0 occurred flag" "Not occurred,Occurred"
|
|
line.long 0x08 "CONEN,SCT conflict enable register"
|
|
bitfld.long 0x08 15. " NCEN[15] ,Event 15 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " NCEN[14] ,Event 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " NCEN[13] ,Event 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " NCEN[12] ,Event 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " NCEN[11] ,Event 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " NCEN[10] ,Event 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " NCEN[9] ,Event 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " NCEN[8] ,Event 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " NCEN[7] ,Event 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " NCEN[6] ,Event 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " NCEN[5] ,Event 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NCEN[4] ,Event 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NCEN[3] ,Event 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NCEN[2] ,Event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " NCEN[1] ,Event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NCEN[0] ,Event 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "CONFLAG,SCT conflict flag register"
|
|
bitfld.long 0x0c 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the Output register when the H counter was not halted" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 30. " BUSERRL ,Error writing CTR L/Unified STATE L/Unified MATCH L/Unified or the Output register when the L/U counter was not halted" "No error,Error"
|
|
bitfld.long 0x0c 5. " NCFLAG[5] ,No-change event occurred on output 5 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 4. " NCFLAG[4] ,No-change event occurred on output 4 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 2. " NCFLAG[2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 1. " NCFLAG[1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred"
|
|
bitfld.long 0x0c 0. " NCFLAG[0] ,No-change event occurred on output 0 flag" "Not occurred,Occurred"
|
|
tree "Match value and capture registers"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT match value register of match channel 0"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT capture register of capture channel 0"
|
|
else
|
|
group.word 0x100++0x03
|
|
line.word 0x00 "MATCH0_L,SCT match value register of match channel 0 low counter 16-bit"
|
|
line.word 0x02 "MATCH0_H,SCT match value register of match channel 0 high counter 16-bit"
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "CAP0_L,SCT capture register of capture channel 0 low counter 16-bit"
|
|
line.word 0x02 "CAP0_H,SCT capture register of capture channel 0 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT match value register of match channel 1"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT capture register of capture channel 1"
|
|
else
|
|
group.word 0x104++0x03
|
|
line.word 0x00 "MATCH1_L,SCT match value register of match channel 1 low counter 16-bit"
|
|
line.word 0x02 "MATCH1_H,SCT match value register of match channel 1 high counter 16-bit"
|
|
rgroup.word 0x104++0x03
|
|
line.word 0x00 "CAP1_L,SCT capture register of capture channel 1 low counter 16-bit"
|
|
line.word 0x02 "CAP1_H,SCT capture register of capture channel 1 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT match value register of match channel 2"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT capture register of capture channel 2"
|
|
else
|
|
group.word 0x108++0x03
|
|
line.word 0x00 "MATCH2_L,SCT match value register of match channel 2 low counter 16-bit"
|
|
line.word 0x02 "MATCH2_H,SCT match value register of match channel 2 high counter 16-bit"
|
|
rgroup.word 0x108++0x03
|
|
line.word 0x00 "CAP2_L,SCT capture register of capture channel 2 low counter 16-bit"
|
|
line.word 0x02 "CAP2_H,SCT capture register of capture channel 2 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT match value register of match channel 3"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT capture register of capture channel 3"
|
|
else
|
|
group.word 0x10C++0x03
|
|
line.word 0x00 "MATCH3_L,SCT match value register of match channel 3 low counter 16-bit"
|
|
line.word 0x02 "MATCH3_H,SCT match value register of match channel 3 high counter 16-bit"
|
|
rgroup.word 0x10C++0x03
|
|
line.word 0x00 "CAP3_L,SCT capture register of capture channel 3 low counter 16-bit"
|
|
line.word 0x02 "CAP3_H,SCT capture register of capture channel 3 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT match value register of match channel 4"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT capture register of capture channel 4"
|
|
else
|
|
group.word 0x110++0x03
|
|
line.word 0x00 "MATCH4_L,SCT match value register of match channel 4 low counter 16-bit"
|
|
line.word 0x02 "MATCH4_H,SCT match value register of match channel 4 high counter 16-bit"
|
|
rgroup.word 0x110++0x03
|
|
line.word 0x00 "CAP4_L,SCT capture register of capture channel 4 low counter 16-bit"
|
|
line.word 0x02 "CAP4_H,SCT capture register of capture channel 4 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT match value register of match channel 5"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT capture register of capture channel 5"
|
|
else
|
|
group.word 0x114++0x03
|
|
line.word 0x00 "MATCH5_L,SCT match value register of match channel 5 low counter 16-bit"
|
|
line.word 0x02 "MATCH5_H,SCT match value register of match channel 5 high counter 16-bit"
|
|
rgroup.word 0x114++0x03
|
|
line.word 0x00 "CAP5_L,SCT capture register of capture channel 5 low counter 16-bit"
|
|
line.word 0x02 "CAP5_H,SCT capture register of capture channel 5 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT match value register of match channel 6"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT capture register of capture channel 6"
|
|
else
|
|
group.word 0x118++0x03
|
|
line.word 0x00 "MATCH6_L,SCT match value register of match channel 6 low counter 16-bit"
|
|
line.word 0x02 "MATCH6_H,SCT match value register of match channel 6 high counter 16-bit"
|
|
rgroup.word 0x118++0x03
|
|
line.word 0x00 "CAP6_L,SCT capture register of capture channel 6 low counter 16-bit"
|
|
line.word 0x02 "CAP6_H,SCT capture register of capture channel 6 high counter 16-bit"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT match value register of match channel 7"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT capture register of capture channel 7"
|
|
else
|
|
group.word 0x11C++0x03
|
|
line.word 0x00 "MATCH7_L,SCT match value register of match channel 7 low counter 16-bit"
|
|
line.word 0x02 "MATCH7_H,SCT match value register of match channel 7 high counter 16-bit"
|
|
rgroup.word 0x11C++0x03
|
|
line.word 0x00 "CAP7_L,SCT capture register of capture channel 7 low counter 16-bit"
|
|
line.word 0x02 "CAP7_H,SCT capture register of capture channel 7 high counter 16-bit"
|
|
endif
|
|
tree.end
|
|
tree "Match reload and capture control registers"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MATCHREL0,SCT match reload value register 0"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CAPCTRL0,SCT capture control register 0"
|
|
bitfld.long 0x00 9. " CAPCON0[9] ,Event 9 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON0[8] ,Event 8 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON0[7] ,Event 7 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON0[6] ,Event 6 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON0[5] ,Event 5 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON0[4] ,Event 4 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON0[3] ,Event 3 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON0[2] ,Event 2 causes load of CAP0 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON0[1] ,Event 1 causes load of CAP0 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON0[0] ,Event 0 causes load of CAP0 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "MATCHREL0_L,SCT match reload value register 0 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL0_H,SCT match reload value register 0 high counter 16-bit"
|
|
group.word 0x200++0x03
|
|
line.word 0x00 "CAPCTRL0_L,SCT capture control register 0 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON0_L[9] ,Event 9 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON0_L[8] ,Event 8 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON0_L[7] ,Event 7 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON0_L[6] ,Event 6 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON0_L[5] ,Event 5 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON0_L[4] ,Event 4 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON0_L[3] ,Event 3 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON0_L[2] ,Event 2 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON0_L[1] ,Event 1 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON0_L[0] ,Event 0 causes load of CAP0_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL0_H,SCT capture control register 0 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON0_H[9] ,Event 9 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON0_H[8] ,Event 8 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON0_H[7] ,Event 7 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON0_H[6] ,Event 6 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON0_H[5] ,Event 5 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON0_H[4] ,Event 4 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON0_H[3] ,Event 3 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON0_H[2] ,Event 2 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON0_H[1] ,Event 1 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON0_H[0] ,Event 0 causes load of CAP0_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "MATCHREL1,SCT match reload value register 1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CAPCTRL1,SCT capture control register 1"
|
|
bitfld.long 0x00 9. " CAPCON1[9] ,Event 9 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON1[8] ,Event 8 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON1[7] ,Event 7 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON1[6] ,Event 6 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON1[5] ,Event 5 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON1[4] ,Event 4 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON1[3] ,Event 3 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON1[2] ,Event 2 causes load of CAP1 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON1[1] ,Event 1 causes load of CAP1 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON1[0] ,Event 0 causes load of CAP1 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "MATCHREL1_L,SCT match reload value register 1 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL1_H,SCT match reload value register 1 high counter 16-bit"
|
|
group.word 0x204++0x03
|
|
line.word 0x00 "CAPCTRL1_L,SCT capture control register 1 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON1_L[9] ,Event 9 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON1_L[8] ,Event 8 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON1_L[7] ,Event 7 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON1_L[6] ,Event 6 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON1_L[5] ,Event 5 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON1_L[4] ,Event 4 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON1_L[3] ,Event 3 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON1_L[2] ,Event 2 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON1_L[1] ,Event 1 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON1_L[0] ,Event 0 causes load of CAP1_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL1_H,SCT capture control register 1 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON1_H[9] ,Event 9 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON1_H[8] ,Event 8 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON1_H[7] ,Event 7 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON1_H[6] ,Event 6 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON1_H[5] ,Event 5 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON1_H[4] ,Event 4 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON1_H[3] ,Event 3 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON1_H[2] ,Event 2 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON1_H[1] ,Event 1 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON1_H[0] ,Event 0 causes load of CAP1_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "MATCHREL2,SCT match reload value register 2"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CAPCTRL2,SCT capture control register 2"
|
|
bitfld.long 0x00 9. " CAPCON2[9] ,Event 9 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON2[8] ,Event 8 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON2[7] ,Event 7 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON2[6] ,Event 6 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON2[5] ,Event 5 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON2[4] ,Event 4 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON2[3] ,Event 3 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON2[2] ,Event 2 causes load of CAP2 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON2[1] ,Event 1 causes load of CAP2 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON2[0] ,Event 0 causes load of CAP2 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "MATCHREL2_L,SCT match reload value register 2 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL2_H,SCT match reload value register 2 high counter 16-bit"
|
|
group.word 0x208++0x03
|
|
line.word 0x00 "CAPCTRL2_L,SCT capture control register 2 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON2_L[9] ,Event 9 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON2_L[8] ,Event 8 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON2_L[7] ,Event 7 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON2_L[6] ,Event 6 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON2_L[5] ,Event 5 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON2_L[4] ,Event 4 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON2_L[3] ,Event 3 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON2_L[2] ,Event 2 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON2_L[1] ,Event 1 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON2_L[0] ,Event 0 causes load of CAP2_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL2_H,SCT capture control register 2 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON2_H[9] ,Event 9 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON2_H[8] ,Event 8 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON2_H[7] ,Event 7 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON2_H[6] ,Event 6 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON2_H[5] ,Event 5 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON2_H[4] ,Event 4 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON2_H[3] ,Event 3 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON2_H[2] ,Event 2 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON2_H[1] ,Event 1 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON2_H[0] ,Event 0 causes load of CAP2_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "MATCHREL3,SCT match reload value register 3"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CAPCTRL3,SCT capture control register 3"
|
|
bitfld.long 0x00 9. " CAPCON3[9] ,Event 9 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON3[8] ,Event 8 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON3[7] ,Event 7 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON3[6] ,Event 6 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON3[5] ,Event 5 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON3[4] ,Event 4 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON3[3] ,Event 3 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON3[2] ,Event 2 causes load of CAP3 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON3[1] ,Event 1 causes load of CAP3 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON3[0] ,Event 0 causes load of CAP3 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "MATCHREL3_L,SCT match reload value register 3 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL3_H,SCT match reload value register 3 high counter 16-bit"
|
|
group.word 0x20C++0x03
|
|
line.word 0x00 "CAPCTRL3_L,SCT capture control register 3 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON3_L[9] ,Event 9 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON3_L[8] ,Event 8 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON3_L[7] ,Event 7 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON3_L[6] ,Event 6 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON3_L[5] ,Event 5 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON3_L[4] ,Event 4 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON3_L[3] ,Event 3 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON3_L[2] ,Event 2 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON3_L[1] ,Event 1 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON3_L[0] ,Event 0 causes load of CAP3_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL3_H,SCT capture control register 3 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON3_H[9] ,Event 9 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON3_H[8] ,Event 8 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON3_H[7] ,Event 7 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON3_H[6] ,Event 6 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON3_H[5] ,Event 5 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON3_H[4] ,Event 4 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON3_H[3] ,Event 3 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON3_H[2] ,Event 2 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON3_H[1] ,Event 1 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON3_H[0] ,Event 0 causes load of CAP3_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "MATCHREL4,SCT match reload value register 4"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CAPCTRL4,SCT capture control register 4"
|
|
bitfld.long 0x00 9. " CAPCON4[9] ,Event 9 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON4[8] ,Event 8 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON4[7] ,Event 7 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON4[6] ,Event 6 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON4[5] ,Event 5 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON4[4] ,Event 4 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON4[3] ,Event 3 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON4[2] ,Event 2 causes load of CAP4 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON4[1] ,Event 1 causes load of CAP4 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON4[0] ,Event 0 causes load of CAP4 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "MATCHREL4_L,SCT match reload value register 4 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL4_H,SCT match reload value register 4 high counter 16-bit"
|
|
group.word 0x210++0x03
|
|
line.word 0x00 "CAPCTRL4_L,SCT capture control register 4 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON4_L[9] ,Event 9 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON4_L[8] ,Event 8 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON4_L[7] ,Event 7 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON4_L[6] ,Event 6 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON4_L[5] ,Event 5 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON4_L[4] ,Event 4 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON4_L[3] ,Event 3 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON4_L[2] ,Event 2 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON4_L[1] ,Event 1 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON4_L[0] ,Event 0 causes load of CAP4_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL4_H,SCT capture control register 4 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON4_H[9] ,Event 9 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON4_H[8] ,Event 8 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON4_H[7] ,Event 7 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON4_H[6] ,Event 6 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON4_H[5] ,Event 5 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON4_H[4] ,Event 4 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON4_H[3] ,Event 3 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON4_H[2] ,Event 2 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON4_H[1] ,Event 1 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON4_H[0] ,Event 0 causes load of CAP4_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "MATCHREL5,SCT match reload value register 5"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CAPCTRL5,SCT capture control register 5"
|
|
bitfld.long 0x00 9. " CAPCON5[9] ,Event 9 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON5[8] ,Event 8 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON5[7] ,Event 7 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON5[6] ,Event 6 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON5[5] ,Event 5 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON5[4] ,Event 4 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON5[3] ,Event 3 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON5[2] ,Event 2 causes load of CAP5 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON5[1] ,Event 1 causes load of CAP5 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON5[0] ,Event 0 causes load of CAP5 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "MATCHREL5_L,SCT match reload value register 5 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL5_H,SCT match reload value register 5 high counter 16-bit"
|
|
group.word 0x214++0x03
|
|
line.word 0x00 "CAPCTRL5_L,SCT capture control register 5 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON5_L[9] ,Event 9 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON5_L[8] ,Event 8 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON5_L[7] ,Event 7 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON5_L[6] ,Event 6 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON5_L[5] ,Event 5 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON5_L[4] ,Event 4 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON5_L[3] ,Event 3 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON5_L[2] ,Event 2 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON5_L[1] ,Event 1 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON5_L[0] ,Event 0 causes load of CAP5_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL5_H,SCT capture control register 5 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON5_H[9] ,Event 9 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON5_H[8] ,Event 8 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON5_H[7] ,Event 7 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON5_H[6] ,Event 6 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON5_H[5] ,Event 5 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON5_H[4] ,Event 4 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON5_H[3] ,Event 3 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON5_H[2] ,Event 2 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON5_H[1] ,Event 1 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON5_H[0] ,Event 0 causes load of CAP5_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "MATCHREL6,SCT match reload value register 6"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "CAPCTRL6,SCT capture control register 6"
|
|
bitfld.long 0x00 9. " CAPCON6[9] ,Event 9 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON6[8] ,Event 8 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON6[7] ,Event 7 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON6[6] ,Event 6 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON6[5] ,Event 5 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON6[4] ,Event 4 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON6[3] ,Event 3 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON6[2] ,Event 2 causes load of CAP6 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON6[1] ,Event 1 causes load of CAP6 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON6[0] ,Event 0 causes load of CAP6 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "MATCHREL6_L,SCT match reload value register 6 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL6_H,SCT match reload value register 6 high counter 16-bit"
|
|
group.word 0x218++0x03
|
|
line.word 0x00 "CAPCTRL6_L,SCT capture control register 6 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON6_L[9] ,Event 9 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON6_L[8] ,Event 8 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON6_L[7] ,Event 7 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON6_L[6] ,Event 6 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON6_L[5] ,Event 5 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON6_L[4] ,Event 4 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON6_L[3] ,Event 3 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON6_L[2] ,Event 2 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON6_L[1] ,Event 1 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON6_L[0] ,Event 0 causes load of CAP6_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL6_H,SCT capture control register 6 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON6_H[9] ,Event 9 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON6_H[8] ,Event 8 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON6_H[7] ,Event 7 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON6_H[6] ,Event 6 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON6_H[5] ,Event 5 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON6_H[4] ,Event 4 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON6_H[3] ,Event 3 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON6_H[2] ,Event 2 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON6_H[1] ,Event 1 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON6_H[0] ,Event 0 causes load of CAP6_H register" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MATCHREL7,SCT match reload value register 7"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CAPCTRL7,SCT capture control register 7"
|
|
bitfld.long 0x00 9. " CAPCON7[9] ,Event 9 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " CAPCON7[8] ,Event 8 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CAPCON7[7] ,Event 7 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CAPCON7[6] ,Event 6 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAPCON7[5] ,Event 5 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CAPCON7[4] ,Event 4 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CAPCON7[3] ,Event 3 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CAPCON7[2] ,Event 2 causes load of CAP7 register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPCON7[1] ,Event 1 causes load of CAP7 register" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CAPCON7[0] ,Event 0 causes load of CAP7 register" "Not occurred,Occurred"
|
|
else
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "MATCHREL7_L,SCT match reload value register 7 low counter 16-bit"
|
|
line.word 0x02 "MATCHREL7_H,SCT match reload value register 7 high counter 16-bit"
|
|
group.word 0x21C++0x03
|
|
line.word 0x00 "CAPCTRL7_L,SCT capture control register 7 low counter 16-bit"
|
|
bitfld.word 0x00 9. " CAPCON7_L[9] ,Event 9 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " CAPCON7_L[8] ,Event 8 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " CAPCON7_L[7] ,Event 7 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " CAPCON7_L[6] ,Event 6 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CAPCON7_L[5] ,Event 5 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CAPCON7_L[4] ,Event 4 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " CAPCON7_L[3] ,Event 3 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CAPCON7_L[2] ,Event 2 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CAPCON7_L[1] ,Event 1 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " CAPCON7_L[0] ,Event 0 causes load of CAP7_L register" "Not occurred,Occurred"
|
|
line.word 0x02 "CAPCTRL7_H,SCT capture control register 7 high counter 16-bit"
|
|
bitfld.word 0x02 9. " CAPCON7_H[9] ,Event 9 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 8. " CAPCON7_H[8] ,Event 8 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 7. " CAPCON7_H[7] ,Event 7 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 6. " CAPCON7_H[6] ,Event 6 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 5. " CAPCON7_H[5] ,Event 5 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 4. " CAPCON7_H[4] ,Event 4 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 3. " CAPCON7_H[3] ,Event 3 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 2. " CAPCON7_H[2] ,Event 2 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CAPCON7_H[1] ,Event 1 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
bitfld.word 0x02 0. " CAPCON7_H[0] ,Event 0 causes load of CAP7_H register" "Not occurred,Occurred"
|
|
endif
|
|
tree.end
|
|
tree "Event state and control registers"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "EV0 _STATE,SCT event state register 0 "
|
|
bitfld.long 0x00 9. " STATEMSK0 [9] ,State 9 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK0 [8] ,State 8 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK0 [7] ,State 7 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK0 [6] ,State 6 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK0 [5] ,State 5 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK0 [4] ,State 4 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK0 [3] ,State 3 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK0 [2] ,State 2 of event 0 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK0 [1] ,State 1 of event 0 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK0 [0] ,State 0 of event 0 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0 _CTRL,SCT event control register 0 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x300+0x4)++0x03
|
|
line.long 0x00 "EV0 _CTRL,SCT event control register 0 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EV1 _STATE,SCT event state register 1 "
|
|
bitfld.long 0x00 9. " STATEMSK1 [9] ,State 9 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK1 [8] ,State 8 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK1 [7] ,State 7 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK1 [6] ,State 6 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK1 [5] ,State 5 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK1 [4] ,State 4 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK1 [3] ,State 3 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK1 [2] ,State 2 of event 1 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK1 [1] ,State 1 of event 1 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK1 [0] ,State 0 of event 1 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1 _CTRL,SCT event control register 1 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x308+0x4)++0x03
|
|
line.long 0x00 "EV1 _CTRL,SCT event control register 1 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EV2 _STATE,SCT event state register 2 "
|
|
bitfld.long 0x00 9. " STATEMSK2 [9] ,State 9 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK2 [8] ,State 8 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK2 [7] ,State 7 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK2 [6] ,State 6 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK2 [5] ,State 5 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK2 [4] ,State 4 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK2 [3] ,State 3 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK2 [2] ,State 2 of event 2 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK2 [1] ,State 1 of event 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK2 [0] ,State 0 of event 2 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2 _CTRL,SCT event control register 2 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EV2 _CTRL,SCT event control register 2 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EV3 _STATE,SCT event state register 3 "
|
|
bitfld.long 0x00 9. " STATEMSK3 [9] ,State 9 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK3 [8] ,State 8 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK3 [7] ,State 7 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK3 [6] ,State 6 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK3 [5] ,State 5 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK3 [4] ,State 4 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK3 [3] ,State 3 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK3 [2] ,State 2 of event 3 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK3 [1] ,State 1 of event 3 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK3 [0] ,State 0 of event 3 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3 _CTRL,SCT event control register 3 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x318+0x4)++0x03
|
|
line.long 0x00 "EV3 _CTRL,SCT event control register 3 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EV4 _STATE,SCT event state register 4 "
|
|
bitfld.long 0x00 9. " STATEMSK4 [9] ,State 9 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK4 [8] ,State 8 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK4 [7] ,State 7 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK4 [6] ,State 6 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK4 [5] ,State 5 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK4 [4] ,State 4 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK4 [3] ,State 3 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK4 [2] ,State 2 of event 4 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK4 [1] ,State 1 of event 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK4 [0] ,State 0 of event 4 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4 _CTRL,SCT event control register 4 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x320+0x4)++0x03
|
|
line.long 0x00 "EV4 _CTRL,SCT event control register 4 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EV5 _STATE,SCT event state register 5 "
|
|
bitfld.long 0x00 9. " STATEMSK5 [9] ,State 9 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK5 [8] ,State 8 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK5 [7] ,State 7 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK5 [6] ,State 6 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK5 [5] ,State 5 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK5 [4] ,State 4 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK5 [3] ,State 3 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK5 [2] ,State 2 of event 5 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK5 [1] ,State 1 of event 5 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK5 [0] ,State 0 of event 5 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5 _CTRL,SCT event control register 5 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x328+0x4)++0x03
|
|
line.long 0x00 "EV5 _CTRL,SCT event control register 5 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EV6 _STATE,SCT event state register 6 "
|
|
bitfld.long 0x00 9. " STATEMSK6 [9] ,State 9 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK6 [8] ,State 8 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK6 [7] ,State 7 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK6 [6] ,State 6 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK6 [5] ,State 5 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK6 [4] ,State 4 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK6 [3] ,State 3 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK6 [2] ,State 2 of event 6 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK6 [1] ,State 1 of event 6 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK6 [0] ,State 0 of event 6 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6 _CTRL,SCT event control register 6 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x330+0x4)++0x03
|
|
line.long 0x00 "EV6 _CTRL,SCT event control register 6 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 6 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EV7 _STATE,SCT event state register 7 "
|
|
bitfld.long 0x00 9. " STATEMSK7 [9] ,State 9 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK7 [8] ,State 8 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK7 [7] ,State 7 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK7 [6] ,State 6 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK7 [5] ,State 5 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK7 [4] ,State 4 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK7 [3] ,State 3 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK7 [2] ,State 2 of event 7 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK7 [1] ,State 1 of event 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK7 [0] ,State 0 of event 7 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7 _CTRL,SCT event control register 7 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x338+0x4)++0x03
|
|
line.long 0x00 "EV7 _CTRL,SCT event control register 7 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 7 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "EV8 _STATE,SCT event state register 8 "
|
|
bitfld.long 0x00 9. " STATEMSK8 [9] ,State 9 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK8 [8] ,State 8 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK8 [7] ,State 7 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK8 [6] ,State 6 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK8 [5] ,State 5 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK8 [4] ,State 4 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK8 [3] ,State 3 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK8 [2] ,State 2 of event 8 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK8 [1] ,State 1 of event 8 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK8 [0] ,State 0 of event 8 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8 _CTRL,SCT event control register 8 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x340+0x4)++0x03
|
|
line.long 0x00 "EV8 _CTRL,SCT event control register 8 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 8 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EV9 _STATE,SCT event state register 9 "
|
|
bitfld.long 0x00 9. " STATEMSK9 [9] ,State 9 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " STATEMSK9 [8] ,State 8 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " STATEMSK9 [7] ,State 7 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " STATEMSK9 [6] ,State 6 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STATEMSK9 [5] ,State 5 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " STATEMSK9 [4] ,State 4 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STATEMSK9 [3] ,State 3 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " STATEMSK9 [2] ,State 2 of event 9 select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATEMSK9 [1] ,State 1 of event 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " STATEMSK9 [0] ,State 0 of event 9 select" "Not selected,Selected"
|
|
if (((per.l(ad:0x1C024000))&0x1)==0x1)
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9 _CTRL,SCT event control register 9 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x348+0x4)++0x03
|
|
line.long 0x00 "EV9 _CTRL,SCT event control register 9 "
|
|
bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggerring of this event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 9 " "LOW,Rise,Fall,HIGH"
|
|
bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "Output set/clear registers"
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OUT0_SET,SCT output 0 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 0" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 0" "Not set,Set"
|
|
line.long 0x04 "OUT0_CLR,SCT output 0 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 0" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 0" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 0" "Not set,Set"
|
|
group.long 0x508++0x07
|
|
line.long 0x00 "OUT1_SET,SCT output 1 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 1" "Not set,Set"
|
|
line.long 0x04 "OUT1_CLR,SCT output 1 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 1" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 1" "Not set,Set"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OUT2_SET,SCT output 2 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 2" "Not set,Set"
|
|
line.long 0x04 "OUT2_CLR,SCT output 2 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 2" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 2" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 2" "Not set,Set"
|
|
group.long 0x518++0x07
|
|
line.long 0x00 "OUT3_SET,SCT output 3 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 3" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 3" "Not set,Set"
|
|
line.long 0x04 "OUT3_CLR,SCT output 3 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 3" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 3" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 3" "Not set,Set"
|
|
group.long 0x520++0x07
|
|
line.long 0x00 "OUT4_SET,SCT output 4 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 4" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 4" "Not set,Set"
|
|
line.long 0x04 "OUT4_CLR,SCT output 4 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 4" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 4" "Not set,Set"
|
|
group.long 0x528++0x07
|
|
line.long 0x00 "OUT5_SET,SCT output 5 set register"
|
|
bitfld.long 0x00 9. " SET[9] ,Event 9 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 8. " SET[8] ,Event 8 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 7. " SET[7] ,Event 7 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 6. " SET[6] ,Event 6 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SET[5] ,Event 5 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " SET[4] ,Event 4 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 3. " SET[3] ,Event 3 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 2. " SET[2] ,Event 2 set output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET[1] ,Event 1 set output 5" "Not set,Set"
|
|
bitfld.long 0x00 0. " SET[0] ,Event 0 set output 5" "Not set,Set"
|
|
line.long 0x04 "OUT5_CLR,SCT output 5 clear register"
|
|
bitfld.long 0x04 9. " CLR[9] ,Event 9 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 8. " CLR[8] ,Event 8 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 7. " CLR[7] ,Event 7 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 6. " CLR[6] ,Event 6 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 4. " CLR[4] ,Event 4 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 3. " CLR[3] ,Event 3 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 2. " CLR[2] ,Event 2 clear output 5" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLR[1] ,Event 1 clear output 5" "Not set,Set"
|
|
bitfld.long 0x04 0. " CLR[0] ,Event 0 clear output 5" "Not set,Set"
|
|
tree.end
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree "WWDT (Windowed Watchdog Timer)"
|
|
base ad:0x4002C000
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "MOD,Watchdog mode register"
|
|
bitfld.long 0x00 5. " LOCK ,Prevents disabling or powering down the watchdog oscillator" "Not prevented,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Flexible,Threshold"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WDINT ,Warning interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WDTOF ,Watchdog time-out flag" "Not timed out,Timed out"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable bit" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "TC,Watchdog timer constant register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "FEED,Watchdog feed sequence register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value should be 0xAA followed by 0x55"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "TV,Watchdog timer value register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "WARNINT,Watchdog Warning Interrupt compare value"
|
|
hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value"
|
|
line.long 0x04 "WINDOW,Watchdog Window compare value"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value"
|
|
width 0x0b
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40028000
|
|
width 7.
|
|
sif cpuis("LPC11U6*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,RTC Control Register"
|
|
bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1.024 kHz clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1.024 kHz timer wake-up enable for deep power-down" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " WAKE1KHZ ,RTC 1.024 kHz timer wake-up flag status" "Run,Time-out"
|
|
bitfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm"
|
|
bitfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset"
|
|
elif cpuis("LPC11E6*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,RTC Control Register"
|
|
bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1 kHz clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1 kHz timer wake-up enable for deep power-down" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 3. " WAKE1KHZ ,RTC 1 kHz timer wake-up flag status" "Run,Time-out"
|
|
eventfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm"
|
|
eventfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,RTC Control Register"
|
|
bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1 kHz clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1 kHz timer wake-up enable for deep power-down" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " WAKE1KHZ ,RTC 1 kHz timer wake-up flag status" "Run,Time-out"
|
|
bitfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm"
|
|
bitfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MATCH,RTC Match Register"
|
|
if (((per.l((ad:0x40028000)))&0x80)==0x80)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNT,RTC Counter Register"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNT,RTC Counter Register"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WAKE,RTC High-Resolution/Wake-Up Timer Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,High-resolution/Wake-up timer current value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MRT (Multi-Rate Timer)"
|
|
base ad:0x400A0000
|
|
width 10.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "INTVAL0,MRT0 Time interval value register"
|
|
bitfld.long 0x00 31. " LOAD ,Way of loading IVALUE-1 to TIMER0" "At the end,Immediately"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE ,Time interval load value"
|
|
rgroup.long (0x0+0x4)++0x03
|
|
line.long 0x00 "TIMER0,MRT0 Timer register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Current timer value of the down-counter"
|
|
group.long (0x0+0x8)++0x7
|
|
line.long 0x00 "CTRL0,MRT0 Control register"
|
|
bitfld.long 0x00 1.--2. " MODE ,Timer interrupt mode" "Repeat,One-shot,?..."
|
|
bitfld.long 0x00 0. " INTEN ,Enable the TIMER0 interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "STAT0,MRT0 Status register"
|
|
rbitfld.long 0x04 1. " RUN ,Indicates the state of TIMER0" "Idle,Running"
|
|
bitfld.long 0x04 0. " INTFLAG ,Monitors the interrupt flag" "Not pending,Pending"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "INTVAL1,MRT1 Time interval value register"
|
|
bitfld.long 0x00 31. " LOAD ,Way of loading IVALUE-1 to TIMER1" "At the end,Immediately"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE ,Time interval load value"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "TIMER1,MRT1 Timer register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Current timer value of the down-counter"
|
|
group.long (0x10+0x8)++0x7
|
|
line.long 0x00 "CTRL1,MRT1 Control register"
|
|
bitfld.long 0x00 1.--2. " MODE ,Timer interrupt mode" "Repeat,One-shot,?..."
|
|
bitfld.long 0x00 0. " INTEN ,Enable the TIMER1 interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "STAT1,MRT1 Status register"
|
|
rbitfld.long 0x04 1. " RUN ,Indicates the state of TIMER1" "Idle,Running"
|
|
bitfld.long 0x04 0. " INTFLAG ,Monitors the interrupt flag" "Not pending,Pending"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "INTVAL2,MRT2 Time interval value register"
|
|
bitfld.long 0x00 31. " LOAD ,Way of loading IVALUE-1 to TIMER2" "At the end,Immediately"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE ,Time interval load value"
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "TIMER2,MRT2 Timer register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Current timer value of the down-counter"
|
|
group.long (0x20+0x8)++0x7
|
|
line.long 0x00 "CTRL2,MRT2 Control register"
|
|
bitfld.long 0x00 1.--2. " MODE ,Timer interrupt mode" "Repeat,One-shot,?..."
|
|
bitfld.long 0x00 0. " INTEN ,Enable the TIMER2 interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "STAT2,MRT2 Status register"
|
|
rbitfld.long 0x04 1. " RUN ,Indicates the state of TIMER2" "Idle,Running"
|
|
bitfld.long 0x04 0. " INTFLAG ,Monitors the interrupt flag" "Not pending,Pending"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "INTVAL3,MRT3 Time interval value register"
|
|
bitfld.long 0x00 31. " LOAD ,Way of loading IVALUE-1 to TIMER3" "At the end,Immediately"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IVALUE ,Time interval load value"
|
|
group.long (0x30+0x4)++0x03
|
|
line.long 0x00 "TIMER3,MRT3 Timer register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Current timer value of the down-counter"
|
|
group.long (0x30+0x8)++0x7
|
|
line.long 0x00 "CTRL3,MRT3 Control register"
|
|
bitfld.long 0x00 1.--2. " MODE ,Timer interrupt mode" "Repeat,One-shot,?..."
|
|
bitfld.long 0x00 0. " INTEN ,Enable the TIMER3 interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "STAT3,MRT3 Status register"
|
|
rbitfld.long 0x04 1. " RUN ,Indicates the state of TIMER3" "Idle,Running"
|
|
bitfld.long 0x04 0. " INTFLAG ,Monitors the interrupt flag" "Not pending,Pending"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "IDLE_CH,Idle channel register"
|
|
bitfld.long 0x00 4.--7. " CHAN ,Lowest idle timer channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "IRQ_FLAG,Global interrupt flag register"
|
|
bitfld.long 0x00 3. " GFLAG3 ,Monitors the interrupt flag of TIMER3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " GFLAG2 ,Monitors the interrupt flag of TIMER2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " GFLAG1 ,Monitors the interrupt flag of TIMER1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " GFLAG0 ,Monitors the interrupt flag of TIMER0" "No interrupt,Interrupt"
|
|
width 0x0b
|
|
tree.end
|
|
tree "RIT (Repetitive Interrupt Timer)"
|
|
base ad:0x400B4000
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "COMPVAL,Compare value LSB register"
|
|
bitfld.long 0x00 31. " RICOMP[31] ,31 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 30. " RICOMP[30] ,30 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 29. " RICOMP[29] ,29 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 28. " RICOMP[28] ,28 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RICOMP[27] ,27 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 26. " RICOMP[26] ,26 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 25. " RICOMP[25] ,25 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 24. " RICOMP[24] ,24 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RICOMP[23] ,23 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 22. " RICOMP[22] ,22 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 21. " RICOMP[21] ,21 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 20. " RICOMP[20] ,20 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RICOMP[19] ,19 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 18. " RICOMP[18] ,18 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 17. " RICOMP[17] ,17 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 16. " RICOMP[16] ,16 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RICOMP[15] ,15 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 14. " RICOMP[14] ,14 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 13. " RICOMP[13] ,13 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 12. " RICOMP[12] ,12 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RICOMP[11] ,11 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 10. " RICOMP[10] ,10 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 9. " RICOMP[9] ,9 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 8. " RICOMP[8] ,8 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RICOMP[7] ,7 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 6. " RICOMP[6] ,6 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 5. " RICOMP[5] ,5 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 4. " RICOMP[4] ,4 bit of LSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RICOMP[3] ,3 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 2. " RICOMP[2] ,2 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 1. " RICOMP[1] ,1 bit of LSB compare value" "0,1"
|
|
bitfld.long 0x00 0. " RICOMP[0] ,0 bit of LSB compare value" "0,1"
|
|
line.long 0x04 "MASK,Mask LSB register"
|
|
bitfld.long 0x04 31. " RIMASK[31] ,31 bit of mask value" "0,1"
|
|
bitfld.long 0x04 30. " RIMASK[30] ,30 bit of mask value" "0,1"
|
|
bitfld.long 0x04 29. " RIMASK[29] ,29 bit of mask value" "0,1"
|
|
bitfld.long 0x04 28. " RIMASK[28] ,28 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 27. " RIMASK[27] ,27 bit of mask value" "0,1"
|
|
bitfld.long 0x04 26. " RIMASK[26] ,26 bit of mask value" "0,1"
|
|
bitfld.long 0x04 25. " RIMASK[25] ,25 bit of mask value" "0,1"
|
|
bitfld.long 0x04 24. " RIMASK[24] ,24 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RIMASK[23] ,23 bit of mask value" "0,1"
|
|
bitfld.long 0x04 22. " RIMASK[22] ,22 bit of mask value" "0,1"
|
|
bitfld.long 0x04 21. " RIMASK[21] ,21 bit of mask value" "0,1"
|
|
bitfld.long 0x04 20. " RIMASK[20] ,20 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RIMASK[19] ,19 bit of mask value" "0,1"
|
|
bitfld.long 0x04 18. " RIMASK[18] ,18 bit of mask value" "0,1"
|
|
bitfld.long 0x04 17. " RIMASK[17] ,17 bit of mask value" "0,1"
|
|
bitfld.long 0x04 16. " RIMASK[16] ,16 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RIMASK[15] ,15 bit of mask value" "0,1"
|
|
bitfld.long 0x04 14. " RIMASK[14] ,14 bit of mask value" "0,1"
|
|
bitfld.long 0x04 13. " RIMASK[13] ,13 bit of mask value" "0,1"
|
|
bitfld.long 0x04 12. " RIMASK[12] ,12 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RIMASK[11] ,11 bit of mask value" "0,1"
|
|
bitfld.long 0x04 10. " RIMASK[10] ,10 bit of mask value" "0,1"
|
|
bitfld.long 0x04 9. " RIMASK[9] ,9 bit of mask value" "0,1"
|
|
bitfld.long 0x04 8. " RIMASK[8] ,8 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RIMASK[7] ,7 bit of mask value" "0,1"
|
|
bitfld.long 0x04 6. " RIMASK[6] ,6 bit of mask value" "0,1"
|
|
bitfld.long 0x04 5. " RIMASK[5] ,5 bit of mask value" "0,1"
|
|
bitfld.long 0x04 4. " RIMASK[4] ,4 bit of mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RIMASK[3] ,3 bit of mask value" "0,1"
|
|
bitfld.long 0x04 2. " RIMASK[2] ,2 bit of mask value" "0,1"
|
|
bitfld.long 0x04 1. " RIMASK[1] ,1 bit of mask value" "0,1"
|
|
bitfld.long 0x04 0. " RIMASK[0] ,0 bit of mask value" "0,1"
|
|
line.long 0x08 "CTRL,Control register"
|
|
bitfld.long 0x08 3. " RITEN ,Timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RITENBR ,Timer enable for debug" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RITENCLR ,Timer enable clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RITINT ,Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x0c "COUNTER,Counter LSB register"
|
|
line.long 0x10 "COMPVAL_H,Compare value MSB register"
|
|
bitfld.long 0x10 15. " RICOMP[15] ,15 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 14. " RICOMP[14] ,14 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 13. " RICOMP[13] ,13 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 12. " RICOMP[12] ,12 bit of MSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " RICOMP[11] ,11 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 10. " RICOMP[10] ,10 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 9. " RICOMP[9] ,9 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 8. " RICOMP[8] ,8 bit of MSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " RICOMP[7] ,7 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 6. " RICOMP[6] ,6 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 5. " RICOMP[5] ,5 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 4. " RICOMP[4] ,4 bit of MSB compare value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " RICOMP[3] ,3 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 2. " RICOMP[2] ,2 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 1. " RICOMP[1] ,1 bit of MSB compare value" "0,1"
|
|
bitfld.long 0x10 0. " RICOMP[0] ,0 bit of MSB compare value" "0,1"
|
|
line.long 0x14 "MASK_H,Mask MSB register"
|
|
bitfld.long 0x14 15. " RIMASK[15] ,15 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 14. " RIMASK[14] ,14 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 13. " RIMASK[13] ,13 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 12. " RIMASK[12] ,12 bit of MSB mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " RIMASK[11] ,11 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 10. " RIMASK[10] ,10 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 9. " RIMASK[9] ,9 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 8. " RIMASK[8] ,8 bit of MSB mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " RIMASK[7] ,7 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 6. " RIMASK[6] ,6 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 5. " RIMASK[5] ,5 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 4. " RIMASK[4] ,4 bit of MSB mask value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " RIMASK[3] ,3 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 2. " RIMASK[2] ,2 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 1. " RIMASK[1] ,1 bit of MSB mask value" "0,1"
|
|
bitfld.long 0x14 0. " RIMASK[0] ,0 bit of MSB mask value" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COUNTER_H,Counter MSB register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RICOUNTER ,16 LSBs of the up counter"
|
|
width 0x0b
|
|
tree.end
|
|
tree "QEI (Quadrature Encoder Interface)"
|
|
base ad:0x40058000
|
|
width 11.
|
|
wgroup.long 0x00++0x03 "Control registers"
|
|
line.long 0x00 "CON,Control register"
|
|
bitfld.long 0x00 3. " RESI ,Reset index counter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RESV ,Reset velocity" "No effect,Reset"
|
|
bitfld.long 0x00 1. " RESPI ,Reset position counter on index" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RESP ,Reset position counter" "No effect,Reset"
|
|
if (((per.l(ad:0x40058008))&0x1)==0x0)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,Encoder status register"
|
|
bitfld.long 0x00 0. " DIR ,Direction bit" "Forward,Reverse"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,Encoder status register"
|
|
bitfld.long 0x00 0. " DIR ,Direction bit" "Reverse,Forward"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONF,Configuration register"
|
|
bitfld.long 0x00 19. " INXGATE[3] ,Pass the index when Pha=0 Phb=0" "Not passed,Passed"
|
|
bitfld.long 0x00 18. " INXGATE[2] ,Pass the index when Pha=0 Phb=1" "Not passed,Passed"
|
|
bitfld.long 0x00 17. " INXGATE[1] ,Pass the index when Pha=1 Phb=1" "Not passed,Passed"
|
|
bitfld.long 0x00 16. " INXGATE[0] ,Pass the index when Pha=1 Phb=0" "Not passed,Passed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CRESPI ,Continuously reset position counter on index" "No reset,Reset"
|
|
bitfld.long 0x00 3. " INVINX ,Invert Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 2. " CAPMODE ,Capture Mode" "Only PhA,Both counted"
|
|
bitfld.long 0x00 1. " SIGMODE ,Signal Mode for PhA/PhB" "Quadrature encoder,Direction/clock signal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DIRINV ,Direction invert" "Not inverted,Inverted"
|
|
rgroup.long 0x0C++0x03 "Position, index, and timer registers"
|
|
line.long 0x00 "POS,Position register"
|
|
group.long 0x10++0x43
|
|
line.long 0x00 "MAXPOS,Maximum position register"
|
|
line.long 0x04 "CMPOS0,position compare register 0"
|
|
line.long 0x08 "CMPOS1,position compare register 1"
|
|
line.long 0x0c "CMPOS2,position compare register 2"
|
|
line.long 0x10 "INXCNT,Index count register"
|
|
line.long 0x14 "INXCMP0,Index compare register 0"
|
|
line.long 0x18 "LOAD,Velocity timer reload register"
|
|
line.long 0x1c "TIME,Velocity timer register"
|
|
line.long 0x20 "VEL,Velocity counter register"
|
|
line.long 0x24 "CAP,Velocity capture register"
|
|
line.long 0x28 "VELCOMP,Velocity compare register"
|
|
line.long 0x2c "FILTERPHA,Digital filter register on input phase A (QEI_A)"
|
|
line.long 0x30 "FILTERPHB,Digital filter register on input phase B (QEI_B)"
|
|
line.long 0x34 "FILTERINX,Digital filter register on input index (QEI_IDX)"
|
|
line.long 0x38 "WINDOW,Index acceptance window register"
|
|
line.long 0x3c "INXCMP1,Index compare register 1"
|
|
line.long 0x40 "INXCMP2,Index compare register 2"
|
|
group.long 0xFE0++0x03 "Interrupt registers"
|
|
line.long 0x00 "INTSTAT,Interrupt status register"
|
|
setclrfld.long 0x00 15. 0x0c 15. 0x08 15. " MAXPOS_INT_set/clr ,Indicates that the current position count goes through the MAXPOS value to zero or backwards" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x0c 14. 0x08 14. " REV2_INT_set/clr ,Indicates that the index 2 compare value is equal to the current index count" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x0c 13. 0x08 13. " REV1_INT_set/clr ,Indicates that the index 1 compare value is equal to the current index count" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x0c 12. 0x08 12. " POS2REV_INT_set/clr ,Combined position 2 and revolution count interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x0c 11. 0x08 11. " POS1REV_INT_set/clr ,Combined position 1 and revolution count interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x0c 10. 0x08 10. " POS0REV_INT_set/clr ,Combined position 0 and revolution count interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x0c 9. 0x08 9. " REV0_INT_set/clr ,Indicates that the index compare value is equal to the current index count" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x0c 8. 0x08 8. " POS2_INT_set/clr ,Indicates that the position 2 compare value is equal to the current position" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0c 7. 0x08 7. " POS1_INT_set/clr ,Indicates that the position 1 compare value is equal to the current position" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x0c 6. 0x08 6. " POS0_INT_set/clr ,Indicates that the position 0 compare value is equal to the current position" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x0c 5. 0x08 5. " ENCLK_INT_set/clr ,Indicates that and encoder clock pulse was detected" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x0c 4. 0x08 4. " ERR_INT_set/clr ,Indicates that an encoder phase error was detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x0c 3. 0x08 3. " DIR_INT_set/clr ,Indicates that a change of direction was detected" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x0c 2. 0x08 2. " VELC_INT_set/clr ,Indicates that captured velocity is less than compare velocity" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x0c 1. 0x08 1. " TIM_INT_set/clr ,Indicates that a velocity timer overflow occurred" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x0c 0. 0x08 0. " INX_INT_set/clr ,Indicates that an index pulse was detected" "No interrupt,Interrupt"
|
|
group.long 0xFE4++0x03
|
|
line.long 0x00 "IE,Interrupt enable register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x0c 15. " MAXPOS_INT_set/clr ,Indicates that the current position count goes through the MAXPOS value to zero or backwards" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x0c 14. " REV2_INT_set/clr ,Indicates that the index 2 compare value is equal to the current index count" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x0c 13. " REV1_INT_set/clr ,Indicates that the index 1 compare value is equal to the current index count" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x0c 12. " POS2REV_INT_set/clr ,Combined position 2 and revolution count interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x0c 11. " POS1REV_INT_set/clr ,Combined position 1 and revolution count interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x0c 10. " POS0REV_INT_set/clr ,Combined position 0 and revolution count interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x0c 9. " REV0_INT_set/clr ,Indicates that the index compare value is equal to the current index count" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x0c 8. " POS2_INT_set/clr ,Indicates that the position 2 compare value is equal to the current position" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x0c 7. " POS1_INT_set/clr ,Indicates that the position 1 compare value is equal to the current position" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x0c 6. " POS0_INT_set/clr ,Indicates that the position 0 compare value is equal to the current position" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x0c 5. " ENCLK_INT_set/clr ,Indicates that and encoder clock pulse was detected" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x0c 4. " ERR_INT_set/clr ,Indicates that an encoder phase error was detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x0c 3. " DIR_INT_set/clr ,Indicates that a change of direction was detected" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x0c 2. " VELC_INT_set/clr ,Indicates that captured velocity is less than compare velocity" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x0c 1. " TIM_INT_set/clr ,Indicates that a velocity timer overflow occurred" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x0c 0. " INX_INT_set/clr ,Indicates that an index pulse was detected" "Disabled,Enabled"
|
|
width 0x0b
|
|
tree.end
|
|
sif cpuis("LPC154?")
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0x1C00C000
|
|
width 14.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register"
|
|
rbitfld.long 0x00 28. " VBUSDEBOUNCED ,This bit indicates if VBUS is detected or not" "Not detected,Detected"
|
|
eventfld.long 0x00 26. " DRES_C ,Device status - reset change" "Not changed,Changed"
|
|
eventfld.long 0x00 25. " DSUS_C ,Device status - suspend change" "Not changed,Changed"
|
|
eventfld.long 0x00 24. " DCON_C ,Device status - connect change" "Not changed,Changed"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " LPM_REWP ,LPM Remote Wake-up Enabled by USB host" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " LPM_SUS ,Device status - LPM Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 17. " DSUS ,Device status - suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 16. " DCON ,Device status - connect" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTONNAK_CI ,Interrupt on NAK for control IN EP" "AK,AK/NAK"
|
|
bitfld.long 0x00 14. " INTONNAK_CO ,Interrupt on NAK for control OUT EP" "AK,AK/NAK"
|
|
bitfld.long 0x00 13. " INTONNAK_AI ,Interrupt on NAK for interrupt and bulk IN EP" "AK,AK/NAK"
|
|
bitfld.long 0x00 12. " INTONNAK_AO ,Interrupt on NAK for interrupt and bulk OUT EP" "AK,AK/NAK"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LPM_SUP ,LPM Support" "Not supported,Supported"
|
|
sif cpuis("lpc54*")
|
|
bitfld.long 0x00 9. " Normal ,Forces the NEEDCLK output to always be on" "Normal,Always 1"
|
|
else
|
|
bitfld.long 0x00 9. " PLL_ON ,Always PLL Clock on" "Functional,High"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " SETUP ,SETUP token received" "Not received,Received"
|
|
bitfld.long 0x00 7. " DEV_EN ,USB device enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " DEV_ADDR ,USB device address"
|
|
line.long 0x04 "INFO,USB Info register"
|
|
bitfld.long 0x04 11.--14. " ERR_CODE ,The error code which last occurred" "No error,PID encoding error,PID unknown,Packet unexpected,Token CRC error,Data CRC error,Time out,Babble,Truncated EOP,Sent/Received NAK,Sent Stall,Overrun,Sent empty packet,Bitstuff error,Sync error,Wrong data toggle"
|
|
hexmask.long.word 0x04 0.--10. 1. " FRAME_NR ,Frame number"
|
|
line.long 0x08 "EPLISTSTART,USB EP Command/Status List start address"
|
|
hexmask.long.tbyte 0x08 8.--31. 0x1 " EP_LIST ,Start address of the USB EP Command/Status List"
|
|
line.long 0x0c "DATABUFSTART,USB Data buffer start address"
|
|
hexmask.long.word 0x0c 22.--31. 0x40 " DA_BUF ,Start address of the buffer pointer page where all endpoint data buffers are located"
|
|
line.long 0x10 "LPM,Link Power Management register"
|
|
bitfld.long 0x10 8. " DATA_PENDING ,Handshake type" "ACK handshake,NYET handshake"
|
|
bitfld.long 0x10 4.--7. " HIRD_SW ,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x10 0.--3. " HIRD_HW ,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "EPSKIP,USB Endpoint skip"
|
|
bitfld.long 0x14 29. " SKIP[29] ,Endpoint 29 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 28. " [28] ,Endpoint 28 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 27. " [27] ,Endpoint 27 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 26. " [26] ,Endpoint 26 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 25. " [25] ,Endpoint 25 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 24. " [24] ,Endpoint 24 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 23. " [23] ,Endpoint 23 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 22. " [22] ,Endpoint 22 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 21. " [21] ,Endpoint 21 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 20. " [20] ,Endpoint 20 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 19. " [19] ,Endpoint 19 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 18. " [18] ,Endpoint 18 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 17. " [17] ,Endpoint 17 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 16. " [16] ,Endpoint 16 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 15. " [15] ,Endpoint 15 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 14. " [14] ,Endpoint 14 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 13. " [13] ,Endpoint 13 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 12. " [12] ,Endpoint 12 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 11. " [11] ,Endpoint 11 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 10. " [10] ,Endpoint 10 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 9. " [9] ,Endpoint 9 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 8. " [8] ,Endpoint 8 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 7. " [7] ,Endpoint 7 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 6. " [6] ,Endpoint 6 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 5. " [5] ,Endpoint 5 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 4. " [4] ,Endpoint 4 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 3. " [3] ,Endpoint 3 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 2. " [2] ,Endpoint 2 skip" "Not skipped,Skipped"
|
|
textline " "
|
|
bitfld.long 0x14 1. " [1] ,Endpoint 1 skip" "Not skipped,Skipped"
|
|
bitfld.long 0x14 0. " [0] ,Endpoint 0 skip" "Not skipped,Skipped"
|
|
line.long 0x18 "EPINUSE,USB Endpoint Buffer in use"
|
|
bitfld.long 0x18 9. " BUF[9] ,Buffer 9 in use" "Not used,Used"
|
|
bitfld.long 0x18 8. " [8] ,Buffer 8 in use" "Not used,Used"
|
|
bitfld.long 0x18 7. " [7] ,Buffer 7 in use" "Not used,Used"
|
|
bitfld.long 0x18 6. " [6] ,Buffer 6 in use" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x18 5. " [5] ,Buffer 5 in use" "Not used,Used"
|
|
bitfld.long 0x18 4. " [4] ,Buffer 4 in use" "Not used,Used"
|
|
bitfld.long 0x18 3. " [3] ,Buffer 3 in use" "Not used,Used"
|
|
bitfld.long 0x18 2. " [2] ,Buffer 2 in use" "Not used,Used"
|
|
line.long 0x1C "EPBUFCFG,USB Endpoint Buffer Configuration register"
|
|
bitfld.long 0x1C 9. " BUF_SB[9] ,Buffer 9 usage" "Single,Double"
|
|
bitfld.long 0x1C 8. " [8] ,Buffer 8 usage" "Single,Double"
|
|
bitfld.long 0x1C 7. " [7] ,Buffer 7 usage" "Single,Double"
|
|
bitfld.long 0x1C 6. " [6] ,Buffer 6 usage" "Single,Double"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " [5] ,Buffer 5 usage" "Single,Double"
|
|
bitfld.long 0x1C 4. " [4] ,Buffer 4 usage" "Single,Double"
|
|
bitfld.long 0x1C 3. " [3] ,Buffer 3 usage" "Single,Double"
|
|
bitfld.long 0x1C 2. " [2] ,Buffer 2 usage" "Single,Double"
|
|
line.long 0x20 "INTSTAT,USB interrupt status register"
|
|
eventfld.long 0x20 31. " DEV_INT ,Device interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 30. " FRAME_INT ,Frame interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 9. " EP4IN ,Interrupt status register bit for the EP4 IN direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 8. " EP4OUT ,Interrupt status register bit for the EP4 OUT direction" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x20 7. " EP3IN ,Interrupt status register bit for the EP3 IN direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 6. " EP3OUT ,Interrupt status register bit for the EP3 OUT direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 5. " EP2IN ,Interrupt status register bit for the EP2 IN direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 4. " EP2OUT ,Interrupt status register bit for the EP2 OUT direction" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x20 3. " EP1IN ,Interrupt status register bit for the EP1 IN direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 2. " EP1OUT ,Interrupt status register bit for the EP1 OUT direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 1. " EP0IN ,Interrupt status register bit for the EP0 IN direction" "No interrupt,Interrupt"
|
|
eventfld.long 0x20 0. " EP0OUT ,Interrupt status register bit for the EP0 OUT direction" "No interrupt,Interrupt"
|
|
line.long 0x24 "INTEN,USB interrupt enable register"
|
|
bitfld.long 0x24 31. " DEV_INT_EN ,Device interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 30. " FRAME_INT_EN ,Frame interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 9. " EP_INT_EN[9] ,Endpoint 9 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 8. " [8] ,Endpoint 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 7. " [7] ,Endpoint 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " [6] ,Endpoint 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " [5] ,Endpoint 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " [4] ,Endpoint 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " [3] ,Endpoint 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " [2] ,Endpoint 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " [1] ,Endpoint 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " [0] ,Endpoint 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x28 "INTSETSTAT,USB set interrupt status register"
|
|
bitfld.long 0x28 31. " DEV_SET_INT ,Device interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 30. " FRAME_SET_INT ,Frame interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 9. " EP_SET_INT[9] ,Endpoint 9 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 8. " [8] ,Endpoint 8 interrupt status set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x28 7. " [7] ,Endpoint 7 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 6. " [6] ,Endpoint 6 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 5. " [5] ,Endpoint 5 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 4. " [4] ,Endpoint 4 interrupt status set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x28 3. " [3] ,Endpoint 3 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 2. " [2] ,Endpoint 2 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 1. " [1] ,Endpoint 1 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 0. " [0] ,Endpoint 0 interrupt status set" "Not set,Set"
|
|
sif !cpuis("LPC54*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTROUTING,USB interrupt routing register"
|
|
bitfld.long 0x00 31. " ROUTE_INT[31] ,Select line for interrupt bit 31" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " [30] ,Select line for interrupt bit 30" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " [9] ,Select line for interrupt bit 9" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " [8] ,Select line for interrupt bit 8" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Select line for interrupt bit 7" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " [6] ,Select line for interrupt bit 6" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " [5] ,Select line for interrupt bit 5" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " [4] ,Select line for interrupt bit 4" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Select line for interrupt bit 3" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " [2] ,Select line for interrupt bit 2" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " [1] ,Select line for interrupt bit 1" "IRQ,FIQ"
|
|
bitfld.long 0x00 0. " [0] ,Select line for interrupt bit 0" "IRQ,FIQ"
|
|
endif
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "EPTOGGLE,USB Endpoint toggle register"
|
|
bitfld.long 0x00 9. " TOGGLE[9] ,Endpoint 9 data toggle" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Endpoint 8 data toggle" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Endpoint 7 data toggle" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Endpoint 6 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Endpoint 5 data toggle" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Endpoint 4 data toggle" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Endpoint 3 data toggle" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Endpoint 2 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Endpoint 1 data toggle" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Endpoint 0 data toggle" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "USART (Universal Synchronous-Asynchronous Receiver/Transmitter)"
|
|
tree "USART0"
|
|
base ad:0x40040000
|
|
width 11.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "CFG,USART Configuration register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPOL ,Output Enable polarity" "Low,High"
|
|
bitfld.long 0x00 20. " OESEL ,Output Enable Select" "Standard,RS-485"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic Address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output Enable Turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal,Loopback"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode Master select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of received data in synchronous mode" "Falling,Rising"
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32 kHz from RTC osc"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7 bit,8 bit,9 bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTL,USART Control register"
|
|
bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRCCONRX ,Clear Continuous Clock" "No effect,Auto-clear"
|
|
bitfld.long 0x04 8. " CC ,Continuous Clock generation" "On character,Continuous"
|
|
bitfld.long 0x04 6. " TXDIS ,Transmit Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ADDRDET ,Enable address detect mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TXBRKEN ,Break Enable" "Disabled,Enabled"
|
|
line.long 0x08 "STAT,USART Status register"
|
|
eventfld.long 0x08 16. " ABERR ,Auto baud Error" "No error,Error"
|
|
eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " PARITYERRINT ,Parity Error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " FRAMERRINT ,Framing Error interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 12. " START ,Start is detected on the receiver input" "Not detected,Detected"
|
|
eventfld.long 0x08 11. " DELTARXBRK ,Change in the state of receiver break detection occured" "Not changed,Changed"
|
|
rbitfld.long 0x08 10. " RXBRK ,Received Break" "No break,Break"
|
|
eventfld.long 0x08 8. " OVERRUNINT ,Overrun Error interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 6. " TXDISSTAT ,Transmitter Disabled Status flag" "UART TX not idle,UART TX idle"
|
|
eventfld.long 0x08 5. " DELTACTS ,Change in the state is detected for the CTS flag" "Not detected,Detected"
|
|
rbitfld.long 0x08 4. " CTS ,Current state of the CTS signal" "Low,High"
|
|
rbitfld.long 0x08 3. " TXIDLE ,Transmitter Idle" "Busy,Idle"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
rbitfld.long 0x08 1. " RXIDLE ,Receiver Idle" "Busy,Idle"
|
|
rbitfld.long 0x08 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTENSET,Interrupt Enable read and Set register"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERR_set/clr ,Auto baud Error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEINT_set/clr ,Received Noise interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERRINT_set/clr ,Parity Error interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERRINT_set/clr ,Framing Error interrupt interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " START_set/clr ,Start is detected on the receiver input interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRK_set/clr ,Change in the state of receiver break detection occured interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNINT_set/clr ,Overrun Error interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISSTAT_set/clr ,Transmitter Disabled Status interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTS_set/clr ,Change in the state is detected for the CTS interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLE_set/clr ,Transmitter Idle interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDY_set/clr ,Transmitter Ready interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDY_set/clr ,Receiver Ready interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RXDAT,Receiver Data register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATSTAT,Receiver Data with Status register"
|
|
in
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "TXDAT,Transmit Data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Transmit Data"
|
|
line.long 0x04 "BRG,Baud Rate Generator register"
|
|
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,This value is used to divide the USART input clock to determine the baud rate"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt status register"
|
|
bitfld.long 0x00 16. " ABERRINT ,Auto baud Error Interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 15. " RXNOISEINT ,Received Noise interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " PARITYERRINT ,Parity Error interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 13. " FRAMERRINT ,Framing Error interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " START ,This bit is set when a start is detected on the receiver input" "Not set,Set"
|
|
bitfld.long 0x00 11. " DELTARXBRK ,This bit is set when a change in the state of receiver break detection occurs" "Not set,Set"
|
|
bitfld.long 0x00 8. " OVERRUNINT ,Overrun Error interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 6. " TXDISINT ,Transmitter Disabled interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DELTACTS ,This bit is set when a change in the state of the CTS input is detected" "Not set,Set"
|
|
bitfld.long 0x00 3. " TXIDLE ,Transmitter Idle status flag" "Not set,Set"
|
|
bitfld.long 0x00 2. " TXRDY ,Transmitter Ready flag" "Not set,Set"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not set,Set"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
|
|
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample Selection Value" ",,,,5 periph clocks,6 periph clocks,7 periph clocks,8 periph clocks,9 periph clocks,10 periph clocks,11 periph clocks,12 periph clocks,13 periph clocks,14 periph clocks,15 periph clocks,16 periph clocks"
|
|
line.long 0x04 "ADDR,Address register for automatic address matching"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADDRESS ,8-bit address used with automatic address matching"
|
|
width 0x0b
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0x40044000
|
|
width 11.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "CFG,USART Configuration register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPOL ,Output Enable polarity" "Low,High"
|
|
bitfld.long 0x00 20. " OESEL ,Output Enable Select" "Standard,RS-485"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic Address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output Enable Turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal,Loopback"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode Master select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of received data in synchronous mode" "Falling,Rising"
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32 kHz from RTC osc"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7 bit,8 bit,9 bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTL,USART Control register"
|
|
bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRCCONRX ,Clear Continuous Clock" "No effect,Auto-clear"
|
|
bitfld.long 0x04 8. " CC ,Continuous Clock generation" "On character,Continuous"
|
|
bitfld.long 0x04 6. " TXDIS ,Transmit Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ADDRDET ,Enable address detect mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TXBRKEN ,Break Enable" "Disabled,Enabled"
|
|
line.long 0x08 "STAT,USART Status register"
|
|
eventfld.long 0x08 16. " ABERR ,Auto baud Error" "No error,Error"
|
|
eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " PARITYERRINT ,Parity Error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " FRAMERRINT ,Framing Error interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 12. " START ,Start is detected on the receiver input" "Not detected,Detected"
|
|
eventfld.long 0x08 11. " DELTARXBRK ,Change in the state of receiver break detection occured" "Not changed,Changed"
|
|
rbitfld.long 0x08 10. " RXBRK ,Received Break" "No break,Break"
|
|
eventfld.long 0x08 8. " OVERRUNINT ,Overrun Error interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 6. " TXDISSTAT ,Transmitter Disabled Status flag" "UART TX not idle,UART TX idle"
|
|
eventfld.long 0x08 5. " DELTACTS ,Change in the state is detected for the CTS flag" "Not detected,Detected"
|
|
rbitfld.long 0x08 4. " CTS ,Current state of the CTS signal" "Low,High"
|
|
rbitfld.long 0x08 3. " TXIDLE ,Transmitter Idle" "Busy,Idle"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
rbitfld.long 0x08 1. " RXIDLE ,Receiver Idle" "Busy,Idle"
|
|
rbitfld.long 0x08 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTENSET,Interrupt Enable read and Set register"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERR_set/clr ,Auto baud Error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEINT_set/clr ,Received Noise interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERRINT_set/clr ,Parity Error interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERRINT_set/clr ,Framing Error interrupt interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " START_set/clr ,Start is detected on the receiver input interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRK_set/clr ,Change in the state of receiver break detection occured interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNINT_set/clr ,Overrun Error interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISSTAT_set/clr ,Transmitter Disabled Status interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTS_set/clr ,Change in the state is detected for the CTS interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLE_set/clr ,Transmitter Idle interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDY_set/clr ,Transmitter Ready interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDY_set/clr ,Receiver Ready interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RXDAT,Receiver Data register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATSTAT,Receiver Data with Status register"
|
|
in
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "TXDAT,Transmit Data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Transmit Data"
|
|
line.long 0x04 "BRG,Baud Rate Generator register"
|
|
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,This value is used to divide the USART input clock to determine the baud rate"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt status register"
|
|
bitfld.long 0x00 16. " ABERRINT ,Auto baud Error Interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 15. " RXNOISEINT ,Received Noise interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " PARITYERRINT ,Parity Error interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 13. " FRAMERRINT ,Framing Error interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " START ,This bit is set when a start is detected on the receiver input" "Not set,Set"
|
|
bitfld.long 0x00 11. " DELTARXBRK ,This bit is set when a change in the state of receiver break detection occurs" "Not set,Set"
|
|
bitfld.long 0x00 8. " OVERRUNINT ,Overrun Error interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 6. " TXDISINT ,Transmitter Disabled interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DELTACTS ,This bit is set when a change in the state of the CTS input is detected" "Not set,Set"
|
|
bitfld.long 0x00 3. " TXIDLE ,Transmitter Idle status flag" "Not set,Set"
|
|
bitfld.long 0x00 2. " TXRDY ,Transmitter Ready flag" "Not set,Set"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not set,Set"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
|
|
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample Selection Value" ",,,,5 periph clocks,6 periph clocks,7 periph clocks,8 periph clocks,9 periph clocks,10 periph clocks,11 periph clocks,12 periph clocks,13 periph clocks,14 periph clocks,15 periph clocks,16 periph clocks"
|
|
line.long 0x04 "ADDR,Address register for automatic address matching"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADDRESS ,8-bit address used with automatic address matching"
|
|
width 0x0b
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x400C0000
|
|
width 11.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "CFG,USART Configuration register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPOL ,Output Enable polarity" "Low,High"
|
|
bitfld.long 0x00 20. " OESEL ,Output Enable Select" "Standard,RS-485"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic Address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output Enable Turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal,Loopback"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode Master select" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of received data in synchronous mode" "Falling,Rising"
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32 kHz from RTC osc"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7 bit,8 bit,9 bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTL,USART Control register"
|
|
bitfld.long 0x04 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRCCONRX ,Clear Continuous Clock" "No effect,Auto-clear"
|
|
bitfld.long 0x04 8. " CC ,Continuous Clock generation" "On character,Continuous"
|
|
bitfld.long 0x04 6. " TXDIS ,Transmit Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ADDRDET ,Enable address detect mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TXBRKEN ,Break Enable" "Disabled,Enabled"
|
|
line.long 0x08 "STAT,USART Status register"
|
|
eventfld.long 0x08 16. " ABERR ,Auto baud Error" "No error,Error"
|
|
eventfld.long 0x08 15. " RXNOISEINT ,Received Noise interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " PARITYERRINT ,Parity Error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " FRAMERRINT ,Framing Error interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 12. " START ,Start is detected on the receiver input" "Not detected,Detected"
|
|
eventfld.long 0x08 11. " DELTARXBRK ,Change in the state of receiver break detection occured" "Not changed,Changed"
|
|
rbitfld.long 0x08 10. " RXBRK ,Received Break" "No break,Break"
|
|
eventfld.long 0x08 8. " OVERRUNINT ,Overrun Error interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 6. " TXDISSTAT ,Transmitter Disabled Status flag" "UART TX not idle,UART TX idle"
|
|
eventfld.long 0x08 5. " DELTACTS ,Change in the state is detected for the CTS flag" "Not detected,Detected"
|
|
rbitfld.long 0x08 4. " CTS ,Current state of the CTS signal" "Low,High"
|
|
rbitfld.long 0x08 3. " TXIDLE ,Transmitter Idle" "Busy,Idle"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
rbitfld.long 0x08 1. " RXIDLE ,Receiver Idle" "Busy,Idle"
|
|
rbitfld.long 0x08 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTENSET,Interrupt Enable read and Set register"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " ABERR_set/clr ,Auto baud Error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " RXNOISEINT_set/clr ,Received Noise interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " PARITYERRINT_set/clr ,Parity Error interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " FRAMERRINT_set/clr ,Framing Error interrupt interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " START_set/clr ,Start is detected on the receiver input interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DELTARXBRK_set/clr ,Change in the state of receiver break detection occured interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " OVERRUNINT_set/clr ,Overrun Error interrupt interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TXDISSTAT_set/clr ,Transmitter Disabled Status interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DELTACTS_set/clr ,Change in the state is detected for the CTS interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIDLE_set/clr ,Transmitter Idle interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXRDY_set/clr ,Transmitter Ready interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDY_set/clr ,Receiver Ready interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RXDAT,Receiver Data register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RXDATSTAT,Receiver Data with Status register"
|
|
in
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "TXDAT,Transmit Data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Transmit Data"
|
|
line.long 0x04 "BRG,Baud Rate Generator register"
|
|
hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,This value is used to divide the USART input clock to determine the baud rate"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt status register"
|
|
bitfld.long 0x00 16. " ABERRINT ,Auto baud Error Interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 15. " RXNOISEINT ,Received Noise interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " PARITYERRINT ,Parity Error interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 13. " FRAMERRINT ,Framing Error interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " START ,This bit is set when a start is detected on the receiver input" "Not set,Set"
|
|
bitfld.long 0x00 11. " DELTARXBRK ,This bit is set when a change in the state of receiver break detection occurs" "Not set,Set"
|
|
bitfld.long 0x00 8. " OVERRUNINT ,Overrun Error interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 6. " TXDISINT ,Transmitter Disabled interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DELTACTS ,This bit is set when a change in the state of the CTS input is detected" "Not set,Set"
|
|
bitfld.long 0x00 3. " TXIDLE ,Transmitter Idle status flag" "Not set,Set"
|
|
bitfld.long 0x00 2. " TXRDY ,Transmitter Ready flag" "Not set,Set"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not set,Set"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
|
|
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample Selection Value" ",,,,5 periph clocks,6 periph clocks,7 periph clocks,8 periph clocks,9 periph clocks,10 periph clocks,11 periph clocks,12 periph clocks,13 periph clocks,14 periph clocks,15 periph clocks,16 periph clocks"
|
|
line.long 0x04 "ADDR,Address register for automatic address matching"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADDRESS ,8-bit address used with automatic address matching"
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 0"
|
|
base ad:0x40048000
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CFG,SPI Configuration register"
|
|
bitfld.long 0x00 11. " SPOL3 ,SSEL3 Polarity select" "Low,High"
|
|
bitfld.long 0x00 10. " SPOL2 ,SSEL2 Polarity select" "Low,High"
|
|
bitfld.long 0x00 9. " SPOL1 ,SSEL1 Polarity select" "Low,High"
|
|
bitfld.long 0x00 8. " SPOL0 ,SSEL0 Polarity select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPOL ,Clock Polarity select" "Low,High"
|
|
bitfld.long 0x00 4. " CPHA ,Clock Phase select" "Change,Capture"
|
|
bitfld.long 0x00 3. " LSBF ,LSB First mode" "Standard,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave,Master"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40048000))&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DLY,SPI Delay register"
|
|
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
bitfld.long 0x00 8.--11. " FRAME_DELAY ,Controls controls the minimum amount of time between the current frame and the next frame" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
bitfld.long 0x00 4.--7. " POST_DELAY ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
bitfld.long 0x00 0.--3. " PRE_DELAY ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "DLY,SPI Delay register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STAT,SPI Status register"
|
|
rbitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Busy,Idle"
|
|
eventfld.long 0x00 7. " ENDTRANSFER ,End Transfer control bit" "Transfer end,Force end"
|
|
rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not stalled,Stalled"
|
|
eventfld.long 0x00 5. " SSD ,Slave Select Deassert" "Not deasserted,Deasserted"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SSA ,Slave Select Assert" "Not asserted,Asserted"
|
|
eventfld.long 0x00 3. " TXUR ,Transmitter Underrun interrupt flag" "No underrun,Underrun"
|
|
eventfld.long 0x00 2. " RXOV ,Receiver Overrun interrupt flag" "No overrun,Overrun"
|
|
rbitfld.long 0x00 1. " TXRDY ,Transmitter Ready flag" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not ready,Ready"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTENSET,Interrupt Enable read and Set register"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN_set/clr ,Slave Select deasserted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN_set/clr ,Slave Select asserted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN_set/clr ,Transmitter Underrun occurred interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN_set/clr ,Receiver overrun occurred interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TXRDY_set/clr ,Transmitter Ready interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDY_set/clr ,Receiver Ready interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RXDAT,SPI Receive Data register"
|
|
in
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "TXDATCTL,SPI Transmit Data with Control"
|
|
bitfld.long 0x00 24.--27. " LEN ,Data Length" "1 bit,2 bit,3 bit,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
bitfld.long 0x00 22. " RXIGNORE ,Received data ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 21. " EOF ,End of Frame" "Not EOF,EOF"
|
|
bitfld.long 0x00 20. " EOT ,End of Transfer" "Transferring,End of transfer"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXSSEL3_N ,Transmit Slave Select 3" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " TXSSEL2_N ,Transmit Slave Select 2" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " TXSSEL1_N ,Transmit Slave Select 1" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " TXSSEL0_N ,Transmit Slave Select 0" "Not selected,Selected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit Data"
|
|
line.long 0x04 "TXDAT,SPI Transmit Data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit Data"
|
|
line.long 0x08 "TXCTL,SPI Transmit Control register"
|
|
bitfld.long 0x08 24.--27. " LEN ,Data Length" "1 bit,2 bit,3 bit,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
bitfld.long 0x08 22. " RXIGNORE ,Received data ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x08 21. " EOF ,End of Frame" "Not EOF,EOF"
|
|
bitfld.long 0x08 20. " EOT ,End of Transfer" "Transferring,End of transfer"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TXSSEL3_N ,Transmit Slave Select 3" "Not selected,Selected"
|
|
bitfld.long 0x08 18. " TXSSEL2_N ,Transmit Slave Select 2" "Not selected,Selected"
|
|
bitfld.long 0x08 17. " TXSSEL1_N ,Transmit Slave Select 1" "Not selected,Selected"
|
|
bitfld.long 0x08 16. " TXSSEL0_N ,Transmit Slave Select 0" "Not selected,Selected"
|
|
if (((per.l(ad:0x40048000))&0x4)==0x4)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DIV,SPI clock Divider register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DIV,SPI clock Divider register"
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "INTSTAT,SPI Interrupt Status register"
|
|
bitfld.long 0x00 5. " SSD ,Slave Select Deassert flag" "Not set,Set"
|
|
bitfld.long 0x00 4. " SSA ,Slave Select Assert flag" "Not set,Set"
|
|
bitfld.long 0x00 3. " TXUR ,Transmitter Underrun interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 2. " RXOV ,Receiver Overrun interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready flag" "Not set,Set"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not set,Set"
|
|
width 0x0b
|
|
tree.end
|
|
tree "SPI 1"
|
|
base ad:0x4008C000
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CFG,SPI Configuration register"
|
|
bitfld.long 0x00 11. " SPOL3 ,SSEL3 Polarity select" "Low,High"
|
|
bitfld.long 0x00 10. " SPOL2 ,SSEL2 Polarity select" "Low,High"
|
|
bitfld.long 0x00 9. " SPOL1 ,SSEL1 Polarity select" "Low,High"
|
|
bitfld.long 0x00 8. " SPOL0 ,SSEL0 Polarity select" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPOL ,Clock Polarity select" "Low,High"
|
|
bitfld.long 0x00 4. " CPHA ,Clock Phase select" "Change,Capture"
|
|
bitfld.long 0x00 3. " LSBF ,LSB First mode" "Standard,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave,Master"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4008C000))&0x4)==0x4)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DLY,SPI Delay register"
|
|
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that the SSEL is deasserted between transfers" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
bitfld.long 0x00 8.--11. " FRAME_DELAY ,Controls controls the minimum amount of time between the current frame and the next frame" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
bitfld.long 0x00 4.--7. " POST_DELAY ,Controls the amount of time between the end of a data transfer and SSEL deassertion" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
bitfld.long 0x00 0.--3. " PRE_DELAY ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "No additional,1 SPI clock time,2 SPI clock times,3 SPI clock times,4 SPI clock times,5 SPI clock times,6 SPI clock times,7 SPI clock times,8 SPI clock times,9 SPI clock times,10 SPI clock times,11 SPI clock times,12 SPI clock times,13 SPI clock times,14 SPI clock times,15 SPI clock times"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "DLY,SPI Delay register"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STAT,SPI Status register"
|
|
rbitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Busy,Idle"
|
|
eventfld.long 0x00 7. " ENDTRANSFER ,End Transfer control bit" "Transfer end,Force end"
|
|
rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not stalled,Stalled"
|
|
eventfld.long 0x00 5. " SSD ,Slave Select Deassert" "Not deasserted,Deasserted"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SSA ,Slave Select Assert" "Not asserted,Asserted"
|
|
eventfld.long 0x00 3. " TXUR ,Transmitter Underrun interrupt flag" "No underrun,Underrun"
|
|
eventfld.long 0x00 2. " RXOV ,Receiver Overrun interrupt flag" "No overrun,Overrun"
|
|
rbitfld.long 0x00 1. " TXRDY ,Transmitter Ready flag" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not ready,Ready"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTENSET,Interrupt Enable read and Set register"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SSDEN_set/clr ,Slave Select deasserted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SSAEN_set/clr ,Slave Select asserted interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXUREN_set/clr ,Transmitter Underrun occurred interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " RXOVEN_set/clr ,Receiver overrun occurred interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TXRDY_set/clr ,Transmitter Ready interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " RXRDY_set/clr ,Receiver Ready interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RXDAT,SPI Receive Data register"
|
|
in
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "TXDATCTL,SPI Transmit Data with Control"
|
|
bitfld.long 0x00 24.--27. " LEN ,Data Length" "1 bit,2 bit,3 bit,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
bitfld.long 0x00 22. " RXIGNORE ,Received data ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 21. " EOF ,End of Frame" "Not EOF,EOF"
|
|
bitfld.long 0x00 20. " EOT ,End of Transfer" "Transferring,End of transfer"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TXSSEL3_N ,Transmit Slave Select 3" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " TXSSEL2_N ,Transmit Slave Select 2" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " TXSSEL1_N ,Transmit Slave Select 1" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " TXSSEL0_N ,Transmit Slave Select 0" "Not selected,Selected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDAT ,Transmit Data"
|
|
line.long 0x04 "TXDAT,SPI Transmit Data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DATA ,Transmit Data"
|
|
line.long 0x08 "TXCTL,SPI Transmit Control register"
|
|
bitfld.long 0x08 24.--27. " LEN ,Data Length" "1 bit,2 bit,3 bit,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit"
|
|
bitfld.long 0x08 22. " RXIGNORE ,Received data ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x08 21. " EOF ,End of Frame" "Not EOF,EOF"
|
|
bitfld.long 0x08 20. " EOT ,End of Transfer" "Transferring,End of transfer"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TXSSEL3_N ,Transmit Slave Select 3" "Not selected,Selected"
|
|
bitfld.long 0x08 18. " TXSSEL2_N ,Transmit Slave Select 2" "Not selected,Selected"
|
|
bitfld.long 0x08 17. " TXSSEL1_N ,Transmit Slave Select 1" "Not selected,Selected"
|
|
bitfld.long 0x08 16. " TXSSEL0_N ,Transmit Slave Select 0" "Not selected,Selected"
|
|
if (((per.l(ad:0x4008C000))&0x4)==0x4)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DIV,SPI clock Divider register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DIV,SPI clock Divider register"
|
|
endif
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "INTSTAT,SPI Interrupt Status register"
|
|
bitfld.long 0x00 5. " SSD ,Slave Select Deassert flag" "Not set,Set"
|
|
bitfld.long 0x00 4. " SSA ,Slave Select Assert flag" "Not set,Set"
|
|
bitfld.long 0x00 3. " TXUR ,Transmitter Underrun interrupt flag" "Not set,Set"
|
|
bitfld.long 0x00 2. " RXOV ,Receiver Overrun interrupt flag" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready flag" "Not set,Set"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready flag" "Not set,Set"
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree "I2C-bus interface"
|
|
base ad:0x40050000
|
|
width 14.
|
|
group.long 0x00++0x07 "Common registers"
|
|
line.long 0x00 "CFG,Configuration for shared functions"
|
|
bitfld.long 0x00 4. " MONCLKSTR ,Monitor function Clock Stretching" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMEOUTEN ,I2C bus Time-out Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MONEN ,Monitor Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLVEN ,Slave Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTEN ,Master Enable" "Disabled,Enabled"
|
|
line.long 0x04 "STAT,Status register for Master/Slave/Monitor functions"
|
|
eventfld.long 0x04 25. " SCLTIMEOUT ,SCL Time-out Interrupt flag" "No time-out,Time-out"
|
|
eventfld.long 0x04 24. " EVENTTIMEOUT ,Event Time-out Interrupt flag" "No time-out,Time-out"
|
|
eventfld.long 0x04 19. " MONIDLE ,Monitor Idle flag" "Busy,Idle"
|
|
rbitfld.long 0x04 18. " MONACTIVE ,Monitor Active flag" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x04 17. " MONOV ,Monitor Overflow flag" "No overflow,Overflow"
|
|
rbitfld.long 0x04 16. " MONRDY ,Monitor Ready" "Not ready,Ready"
|
|
eventfld.long 0x04 15. " SLVDESEL ,Slave Deselected flag" "Not deselected,Deselected"
|
|
rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not selected,Selected"
|
|
textline " "
|
|
rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match Index" "0,1,2,3"
|
|
rbitfld.long 0x04 11. " SLVNOTSTR ,Slave Not Stretching" "Stretching,Not stretching"
|
|
rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave State code" "Address,Receive,Transmit,?..."
|
|
rbitfld.long 0x04 8. " SLVPENDING ,Slave Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 6. " MSTSTSTPERR ,Master Start/Stop Error flag" "No error,Error"
|
|
eventfld.long 0x04 4. " MSTARBLOSS ,Master Arbitration Loss flag" "No loss,Arbitration loss"
|
|
rbitfld.long 0x04 1.--3. " MSTSTATE ,Master State code" "Idle,Receive,Transmit,NACK Address,NACK Data,?..."
|
|
rbitfld.long 0x04 0. " MSTPENDING ,Master Pending" "Not pending,Pending"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INTENSET_CLR,Interrupt Enable Set Clear read register"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " SCLTIMEOUT_set/clr ,SCL time-out interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " EVENTTIMEOUT_set/clr ,Event time-out interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " MONIDLE_set/clr ,Monitor Idle interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " MONOV_set/clr ,Monitor Overrun interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " MONRDY_set/clr ,Monitor data Ready interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " SLVDESEL_set/clr ,Slave Deselect interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SLVNOTSTR_set/clr ,Slave Not Stretching interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SLVPENDING_set/clr ,Slave Pending interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " MSTSTSTPERR_set/clr ,Master Start/Stop Error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " MSTARBLOSS_set/clr ,Master Arbitration Loss interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " MSTPENDING_set/clr ,Master Pending interrupt" "No interrupt,Interrupt"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "TIMEOUT,Time-out value register"
|
|
hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out time value"
|
|
bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CLKDIV,Clock pre-divider for the entire I2C block"
|
|
hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt Status register for Master/Slave/Monitor functions"
|
|
bitfld.long 0x00 25. " SCLTIMEOUT ,SCL Time-out Interrupt flag" "No time-out,Time-out"
|
|
bitfld.long 0x00 24. " EVENTTIMEOUT ,Event Time-out Interrupt flag" "No time-out,Time-out"
|
|
bitfld.long 0x00 19. " MONIDLE ,Monitor Idle flag" "Busy,Idle"
|
|
bitfld.long 0x00 17. " MONOV ,Monitor Overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MONRDY ,Monitor Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "Not deselected,Deselected"
|
|
bitfld.long 0x00 14. " SLVSEL ,Slave selected flag" "Not selected,Seselected"
|
|
bitfld.long 0x00 11. " SLVNOTSTR ,Slave Not Stretching" "Stretching,Not stretching"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SLVPENDING ,Slave Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " MSTSTSTPERR ,Master Start/Stop Error flag" "No error,Error"
|
|
bitfld.long 0x00 4. " MSTARBLOSS ,Master Arbitration Loss flag" "No loss,Arbitration loss"
|
|
bitfld.long 0x00 0. " MSTPENDING ,Master Pending" "Not pending,Pending"
|
|
group.long 0x20++0x7 "Master function registers"
|
|
line.long 0x00 "MSTCTL,Master control register"
|
|
bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MSTSTOP ,Master Stop control" "No effect,Stop"
|
|
bitfld.long 0x00 1. " MSTSTART ,Master Start control" "No effect,Start"
|
|
bitfld.long 0x00 0. " MSTCONTINUE ,Master Continue" "No effect,Continue"
|
|
line.long 0x04 "MSTTIME,Master timing configuration"
|
|
bitfld.long 0x04 4.--6. " MSTSCLHIGH ,Master SCL High time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks"
|
|
bitfld.long 0x04 0.--2. " MSTSCLLOW ,Master SCL Low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register(receive)"
|
|
in
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register(transmit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Master function data register(for transmitting)"
|
|
group.long 0x40++0x3 "Slave function registers"
|
|
line.long 0x00 "SLVCTL,Slave control register"
|
|
bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLVNACK ,Slave NACK" "No effect,NACK"
|
|
bitfld.long 0x00 0. " SLVCONTINUE ,Slave Continue" "No effect,Continue"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register(receive)"
|
|
in
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register(transmit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Slave function data register(for transmitting)"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "SLVADR0,Slave address 0"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR ,Seven bit slave address that is compared to received address if enabled"
|
|
bitfld.long 0x00 0. " SADISABLE ,Slave Address 0 Disable" "No,Yes"
|
|
line.long 0x04 "SLVADR1,Slave address 1"
|
|
hexmask.long.byte 0x04 1.--7. 0x2 " SLVADR ,Seven bit slave address that is compared to received address if enabled"
|
|
bitfld.long 0x04 0. " SADISABLE ,Slave Address 1 Disable" "No,Yes"
|
|
line.long 0x08 "SLVADR2,Slave address 2"
|
|
hexmask.long.byte 0x08 1.--7. 0x2 " SLVADR ,Seven bit slave address that is compared to received address if enabled"
|
|
bitfld.long 0x08 0. " SADISABLE ,Slave Address 2 Disable" "No,Yes"
|
|
line.long 0x0c "SLVADR3,Slave address 3"
|
|
hexmask.long.byte 0x0c 1.--7. 0x2 " SLVADR ,Seven bit slave address that is compared to received address if enabled"
|
|
bitfld.long 0x0c 0. " SADISABLE ,Slave Address 3 Disable" "No,Yes"
|
|
line.long 0x10 "SLVQUAL0,Slave Qualification for address 0"
|
|
hexmask.long.byte 0x10 1.--7. 0x2 " SLVADR ,Slave address Qualifier for address 0"
|
|
hgroup.long 0x80++0x03 "Monitor function register"
|
|
hide.long 0x00 "MONRXDAT,Monitor receiver data register"
|
|
in
|
|
width 0x0b
|
|
tree.end
|
|
tree "C_CAN (Controller Area Network)"
|
|
base ad:0x400F0000
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CNTL,CAN control"
|
|
bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,Module interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal operation,Started"
|
|
line.long 0x04 "STAT,Status register"
|
|
bitfld.long 0x04 7. " BOFF ,Busoff status" "Not busoff,Busoff"
|
|
bitfld.long 0x04 6. " EWARN ,Warning status" "Below limit,At limit"
|
|
bitfld.long 0x04 5. " EPASS ,Error passive" "Active,Passive"
|
|
bitfld.long 0x04 4. " RXOK ,Received a message successfully" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TXOK ,Transmitted a message successfully" "Not transmitted,Transmitted"
|
|
bitfld.long 0x04 0.--2. " LEC ,Last error code" "No error,Stuff error,Form error,AckError,Bit1Error,Bit0Error,CRCError,Unused"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EC,Error counter"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "Below error lcl,At error lvl"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC6_0 ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC7_0 ,Transmit error counter"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "BT,Bit timing register"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,(Re)synchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INT,Interrupt register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID ,Interrupt ID"
|
|
if (((per.l(ad:0x400F0000))&0x80)==0x80)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEST,Test register"
|
|
rbitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controller,Sample point,Low,High"
|
|
bitfld.long 0x00 4. " LBACK ,Loop back mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TEST,Test register"
|
|
bitfld.long 0x00 7. " RX ,Monitors the actual value of the CAN_RXD pin" "Recessive,Dominant"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TXD pins" "Controller,Sample point,Low,High"
|
|
bitfld.long 0x00 4. " LBACK ,Loop back mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BASIC ,Basic mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BRPE,Baud rate prescaler extension register"
|
|
bitfld.long 0x00 0.--3. " BRPE ,Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0xf
|
|
line.long 0x00 "IF1_CMDREQ,Message interface 1 command request"
|
|
rbitfld.long 0x00 15. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 0.--5. " MN ,Message number" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x04 "IF1_CMDMSK_W,Message interface 1 command mask (write direction)"
|
|
bitfld.long 0x04 7. " WR_RD ,Write transfer" "No write,Write"
|
|
bitfld.long 0x04 6. " MASK ,Access mask bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 5. " ARB ,Access arbitration bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 4. " CTRL ,Access control bits" "Unchanged,Transfer"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXRQST ,Access transmission request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " DATA_A ,Access data bytes 0-3" "Unchanged,Transfer"
|
|
bitfld.long 0x04 0. " DATA_B ,Access data bytes 4-7" "Unchanged,Transfer"
|
|
line.long 0x04 "IF1_CMDMSK_R,Message interface 1 command mask (read direction)"
|
|
bitfld.long 0x04 7. " WR_RD ,Read transfer" "No read,Read"
|
|
bitfld.long 0x04 6. " MASK ,Access mask bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 5. " ARB ,Access arbitration bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 4. " CTRL ,Access control bits" "Unchanged,Transfer"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLRINTPND ,Clear interrupt pending bit" "Unchanged,Cleared"
|
|
bitfld.long 0x04 2. " NEWDAT ,Access new data bit" "Unchanged,Cleared"
|
|
bitfld.long 0x04 1. " DATA_A ,Access data bytes 0-3" "Unchanged,Transfer"
|
|
bitfld.long 0x04 0. " DATA_B ,Access data bytes 4-7" "Unchanged,Transfer"
|
|
line.long 0x08 "IF1_MSK1,Message interface 1 mask 1"
|
|
bitfld.long 0x08 15. " MSK15 ,Identifier mask bit 15" "Matched,Masked"
|
|
bitfld.long 0x08 14. " MSK14 ,Identifier mask bit 14" "Matched,Masked"
|
|
bitfld.long 0x08 13. " MSK13 ,Identifier mask bit 13" "Matched,Masked"
|
|
bitfld.long 0x08 12. " MSK12 ,Identifier mask bit 12" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSK11 ,Identifier mask bit 11" "Matched,Masked"
|
|
bitfld.long 0x08 10. " MSK10 ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x08 9. " MSK9 ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x08 8. " MSK8 ,Identifier mask bit 8" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSK7 ,Identifier mask bit 7" "Matched,Masked"
|
|
bitfld.long 0x08 6. " MSK6 ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x08 5. " MSK5 ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x08 4. " MSK4 ,Identifier mask bit 4" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSK3 ,Identifier mask bit 3" "Matched,Masked"
|
|
bitfld.long 0x08 2. " MSK2 ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x08 1. " MSK1 ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x08 0. " MSK0 ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x0c "IF1_MSK2,Message interface 1 mask 2"
|
|
bitfld.long 0x0c 15. " MXTD ,Mask extend identifier" "Without XTD,With XTD"
|
|
bitfld.long 0x0c 14. " MDIR ,Mask message direction" "Without DIR,With DIR"
|
|
bitfld.long 0x0c 12. " MSK28 ,Identifier mask bit 28" "Matched,Masked"
|
|
bitfld.long 0x0c 11. " MSK27 ,Identifier mask bit 27" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " MSK26 ,Identifier mask bit 26" "Matched,Masked"
|
|
bitfld.long 0x0c 9. " MSK25 ,Identifier mask bit 25" "Matched,Masked"
|
|
bitfld.long 0x0c 8. " MSK24 ,Identifier mask bit 24" "Matched,Masked"
|
|
bitfld.long 0x0c 7. " MSK23 ,Identifier mask bit 23" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " MSK22 ,Identifier mask bit 22" "Matched,Masked"
|
|
bitfld.long 0x0c 5. " MSK21 ,Identifier mask bit 21" "Matched,Masked"
|
|
bitfld.long 0x0c 4. " MSK20 ,Identifier mask bit 20" "Matched,Masked"
|
|
bitfld.long 0x0c 3. " MSK19 ,Identifier mask bit 19" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " MSK18 ,Identifier mask bit 18" "Matched,Masked"
|
|
bitfld.long 0x0c 1. " MSK17 ,Identifier mask bit 17" "Matched,Masked"
|
|
bitfld.long 0x0c 0. " MSK16 ,Identifier mask bit 16" "Matched,Masked"
|
|
if (((per.l((ad:0x400F0000+0x20+0x14)))&0x4000)==0x4000)
|
|
group.long (0x20+0x10)++0x07
|
|
line.long 0x00 "IF1_ARB1,Message interface 1 arbitration 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID15_0 ,Message identifier bits 0-15"
|
|
line.long 0x04 "IF1_ARB2,Message interface 1 arbitration 2"
|
|
bitfld.long 0x04 15. " MSGVAL ,Message valid" "Invalid,Valid"
|
|
bitfld.long 0x04 14. " XTD ,Extend identifier" "Standard,Extended"
|
|
bitfld.long 0x04 13. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 0.--12. 1. " ID28_16 ,Message identifier bits 16-28"
|
|
else
|
|
group.long (0x20+0x14)++0x03
|
|
line.long 0x00 "IF1_ARB2,Message interface 1 arbitration 2"
|
|
bitfld.long 0x00 15. " MSGVAL ,Message valid" "Invalid,Valid"
|
|
bitfld.long 0x00 14. " XTD ,Extend identifier" "Standard,Extended"
|
|
bitfld.long 0x00 13. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 2.--12. 1. " ID28_18 ,Message identifier bits 18-28"
|
|
endif
|
|
group.long (0x20+0x18)++0x13
|
|
line.long 0x00 "IF1_MCTRL,Message interface 1 message control"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Ignored,Used"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not waiting,Waiting"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "Not end,End"
|
|
bitfld.long 0x00 0.--3. " DLC3_0 ,Data length code 3:0" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
|
|
line.long 0x04 "IF1_DA1,Message interface 1 data A1"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "IF1_DA2,Message interface 1 data A2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA2 ,Data byte 2"
|
|
line.long 0x0c "IF1_DB1,Message interface 1 data B1"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DATA4 ,Data byte 4"
|
|
line.long 0x10 "IF1_DB2,Message interface 1 data B2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA6 ,Data byte 6"
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "IF2_CMDREQ,Message interface 2 command request"
|
|
rbitfld.long 0x00 15. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 0.--5. " MN ,Message number" "Invalid,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x04 "IF2_CMDMSK_W,Message interface 2 command mask (write direction)"
|
|
bitfld.long 0x04 7. " WR_RD ,Write transfer" "No write,Write"
|
|
bitfld.long 0x04 6. " MASK ,Access mask bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 5. " ARB ,Access arbitration bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 4. " CTRL ,Access control bits" "Unchanged,Transfer"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXRQST ,Access transmission request bit" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " DATA_A ,Access data bytes 0-3" "Unchanged,Transfer"
|
|
bitfld.long 0x04 0. " DATA_B ,Access data bytes 4-7" "Unchanged,Transfer"
|
|
line.long 0x04 "IF2_CMDMSK_R,Message interface 2 command mask (read direction)"
|
|
bitfld.long 0x04 7. " WR_RD ,Read transfer" "No read,Read"
|
|
bitfld.long 0x04 6. " MASK ,Access mask bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 5. " ARB ,Access arbitration bits" "Unchanged,Transfer"
|
|
bitfld.long 0x04 4. " CTRL ,Access control bits" "Unchanged,Transfer"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CLRINTPND ,Clear interrupt pending bit" "Unchanged,Cleared"
|
|
bitfld.long 0x04 2. " NEWDAT ,Access new data bit" "Unchanged,Cleared"
|
|
bitfld.long 0x04 1. " DATA_A ,Access data bytes 0-3" "Unchanged,Transfer"
|
|
bitfld.long 0x04 0. " DATA_B ,Access data bytes 4-7" "Unchanged,Transfer"
|
|
line.long 0x08 "IF2_MSK1,Message interface 2 mask 1"
|
|
bitfld.long 0x08 15. " MSK15 ,Identifier mask bit 15" "Matched,Masked"
|
|
bitfld.long 0x08 14. " MSK14 ,Identifier mask bit 14" "Matched,Masked"
|
|
bitfld.long 0x08 13. " MSK13 ,Identifier mask bit 13" "Matched,Masked"
|
|
bitfld.long 0x08 12. " MSK12 ,Identifier mask bit 12" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSK11 ,Identifier mask bit 11" "Matched,Masked"
|
|
bitfld.long 0x08 10. " MSK10 ,Identifier mask bit 10" "Matched,Masked"
|
|
bitfld.long 0x08 9. " MSK9 ,Identifier mask bit 9" "Matched,Masked"
|
|
bitfld.long 0x08 8. " MSK8 ,Identifier mask bit 8" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSK7 ,Identifier mask bit 7" "Matched,Masked"
|
|
bitfld.long 0x08 6. " MSK6 ,Identifier mask bit 6" "Matched,Masked"
|
|
bitfld.long 0x08 5. " MSK5 ,Identifier mask bit 5" "Matched,Masked"
|
|
bitfld.long 0x08 4. " MSK4 ,Identifier mask bit 4" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSK3 ,Identifier mask bit 3" "Matched,Masked"
|
|
bitfld.long 0x08 2. " MSK2 ,Identifier mask bit 2" "Matched,Masked"
|
|
bitfld.long 0x08 1. " MSK1 ,Identifier mask bit 1" "Matched,Masked"
|
|
bitfld.long 0x08 0. " MSK0 ,Identifier mask bit 0" "Matched,Masked"
|
|
line.long 0x0c "IF2_MSK2,Message interface 2 mask 2"
|
|
bitfld.long 0x0c 15. " MXTD ,Mask extend identifier" "Without XTD,With XTD"
|
|
bitfld.long 0x0c 14. " MDIR ,Mask message direction" "Without DIR,With DIR"
|
|
bitfld.long 0x0c 12. " MSK28 ,Identifier mask bit 28" "Matched,Masked"
|
|
bitfld.long 0x0c 11. " MSK27 ,Identifier mask bit 27" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " MSK26 ,Identifier mask bit 26" "Matched,Masked"
|
|
bitfld.long 0x0c 9. " MSK25 ,Identifier mask bit 25" "Matched,Masked"
|
|
bitfld.long 0x0c 8. " MSK24 ,Identifier mask bit 24" "Matched,Masked"
|
|
bitfld.long 0x0c 7. " MSK23 ,Identifier mask bit 23" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " MSK22 ,Identifier mask bit 22" "Matched,Masked"
|
|
bitfld.long 0x0c 5. " MSK21 ,Identifier mask bit 21" "Matched,Masked"
|
|
bitfld.long 0x0c 4. " MSK20 ,Identifier mask bit 20" "Matched,Masked"
|
|
bitfld.long 0x0c 3. " MSK19 ,Identifier mask bit 19" "Matched,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " MSK18 ,Identifier mask bit 18" "Matched,Masked"
|
|
bitfld.long 0x0c 1. " MSK17 ,Identifier mask bit 17" "Matched,Masked"
|
|
bitfld.long 0x0c 0. " MSK16 ,Identifier mask bit 16" "Matched,Masked"
|
|
if (((per.l((ad:0x400F0000+0x80+0x14)))&0x4000)==0x4000)
|
|
group.long (0x80+0x10)++0x07
|
|
line.long 0x00 "IF2_ARB1,Message interface 2 arbitration 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID15_0 ,Message identifier bits 0-15"
|
|
line.long 0x04 "IF2_ARB2,Message interface 2 arbitration 2"
|
|
bitfld.long 0x04 15. " MSGVAL ,Message valid" "Invalid,Valid"
|
|
bitfld.long 0x04 14. " XTD ,Extend identifier" "Standard,Extended"
|
|
bitfld.long 0x04 13. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 0.--12. 1. " ID28_16 ,Message identifier bits 16-28"
|
|
else
|
|
group.long (0x80+0x14)++0x03
|
|
line.long 0x00 "IF2_ARB2,Message interface 2 arbitration 2"
|
|
bitfld.long 0x00 15. " MSGVAL ,Message valid" "Invalid,Valid"
|
|
bitfld.long 0x00 14. " XTD ,Extend identifier" "Standard,Extended"
|
|
bitfld.long 0x00 13. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 2.--12. 1. " ID28_18 ,Message identifier bits 18-28"
|
|
endif
|
|
group.long (0x80+0x18)++0x13
|
|
line.long 0x00 "IF2_MCTRL,Message interface 2 message control"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Ignored,Used"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not waiting,Waiting"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EOB ,End of buffer" "Not end,End"
|
|
bitfld.long 0x00 0.--3. " DLC3_0 ,Data length code 3:0" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
|
|
line.long 0x04 "IF2_DA1,Message interface 2 data A1"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "IF2_DA2,Message interface 2 data A2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA2 ,Data byte 2"
|
|
line.long 0x0c "IF2_DB1,Message interface 2 data B1"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DATA4 ,Data byte 4"
|
|
line.long 0x10 "IF2_DB2,Message interface 2 data B2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA6 ,Data byte 6"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "TXREQ1,Transmission request 1"
|
|
bitfld.long 0x00 15. " TXRQST16 ,Transmission of object 16 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " TXRQST15 ,Transmission of object 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " TXRQST14 ,Transmission of object 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " TXRQST13 ,Transmission of object 13 request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXRQST12 ,Transmission of object 12 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " TXRQST11 ,Transmission of object 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " TXRQST10 ,Transmission of object 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " TXRQST9 ,Transmission of object 9 request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXRQST8 ,Transmission of object 8 request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " TXRQST7 ,Transmission of object 7 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " TXRQST6 ,Transmission of object 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " TXRQST5 ,Transmission of object 5 request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXRQST4 ,Transmission of object 4 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " TXRQST3 ,Transmission of object 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " TXRQST2 ,Transmission of object 2 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " TXRQST1 ,Transmission of object 1 request" "Not requested,Requested"
|
|
line.long 0x04 "TXREQ2,Transmission request 2"
|
|
bitfld.long 0x04 15. " TXRQST32 ,Transmission of object 32 request" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " TXRQST31 ,Transmission of object 31 request" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " TXRQST30 ,Transmission of object 30 request" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " TXRQST29 ,Transmission of object 29 request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 11. " TXRQST28 ,Transmission of object 28 request" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " TXRQST27 ,Transmission of object 27 request" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " TXRQST26 ,Transmission of object 26 request" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " TXRQST25 ,Transmission of object 25 request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TXRQST24 ,Transmission of object 24 request" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " TXRQST23 ,Transmission of object 23 request" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " TXRQST22 ,Transmission of object 22 request" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " TXRQST21 ,Transmission of object 21 request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TXRQST20 ,Transmission of object 20 request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " TXRQST19 ,Transmission of object 19 request" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " TXRQST18 ,Transmission of object 18 request" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " TXRQST17 ,Transmission of object 17 request" "Not requested,Requested"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "ND1,New data 1"
|
|
bitfld.long 0x00 15. " NEWDAT16 ,New data bit of message object 16" "No new data,New data"
|
|
bitfld.long 0x00 14. " NEWDAT15 ,New data bit of message object 15" "No new data,New data"
|
|
bitfld.long 0x00 13. " NEWDAT14 ,New data bit of message object 14" "No new data,New data"
|
|
bitfld.long 0x00 12. " NEWDAT13 ,New data bit of message object 13" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEWDAT12 ,New data bit of message object 12" "No new data,New data"
|
|
bitfld.long 0x00 10. " NEWDAT11 ,New data bit of message object 11" "No new data,New data"
|
|
bitfld.long 0x00 9. " NEWDAT10 ,New data bit of message object 10" "No new data,New data"
|
|
bitfld.long 0x00 8. " NEWDAT9 ,New data bit of message object 9" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NEWDAT8 ,New data bit of message object 8" "No new data,New data"
|
|
bitfld.long 0x00 6. " NEWDAT7 ,New data bit of message object 7" "No new data,New data"
|
|
bitfld.long 0x00 5. " NEWDAT6 ,New data bit of message object 6" "No new data,New data"
|
|
bitfld.long 0x00 4. " NEWDAT5 ,New data bit of message object 5" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NEWDAT4 ,New data bit of message object 4" "No new data,New data"
|
|
bitfld.long 0x00 2. " NEWDAT3 ,New data bit of message object 3" "No new data,New data"
|
|
bitfld.long 0x00 1. " NEWDAT2 ,New data bit of message object 2" "No new data,New data"
|
|
bitfld.long 0x00 0. " NEWDAT1 ,New data bit of message object 1" "No new data,New data"
|
|
line.long 0x04 "ND2,New data 2"
|
|
bitfld.long 0x04 15. " NEWDAT32 ,New data bit of message object 32" "No new data,New data"
|
|
bitfld.long 0x04 14. " NEWDAT31 ,New data bit of message object 31" "No new data,New data"
|
|
bitfld.long 0x04 13. " NEWDAT30 ,New data bit of message object 30" "No new data,New data"
|
|
bitfld.long 0x04 12. " NEWDAT29 ,New data bit of message object 29" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x04 11. " NEWDAT28 ,New data bit of message object 28" "No new data,New data"
|
|
bitfld.long 0x04 10. " NEWDAT27 ,New data bit of message object 27" "No new data,New data"
|
|
bitfld.long 0x04 9. " NEWDAT26 ,New data bit of message object 26" "No new data,New data"
|
|
bitfld.long 0x04 8. " NEWDAT25 ,New data bit of message object 25" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x04 7. " NEWDAT24 ,New data bit of message object 24" "No new data,New data"
|
|
bitfld.long 0x04 6. " NEWDAT23 ,New data bit of message object 23" "No new data,New data"
|
|
bitfld.long 0x04 5. " NEWDAT22 ,New data bit of message object 22" "No new data,New data"
|
|
bitfld.long 0x04 4. " NEWDAT21 ,New data bit of message object 21" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x04 3. " NEWDAT20 ,New data bit of message object 20" "No new data,New data"
|
|
bitfld.long 0x04 2. " NEWDAT19 ,New data bit of message object 19" "No new data,New data"
|
|
bitfld.long 0x04 1. " NEWDAT18 ,New data bit of message object 18" "No new data,New data"
|
|
bitfld.long 0x04 0. " NEWDAT17 ,New data bit of message object 17" "No new data,New data"
|
|
rgroup.long 0x140++0x07
|
|
line.long 0x00 "IR1,Interrupt pending 1"
|
|
bitfld.long 0x00 15. " INTPND16 ,Interrupt pending bit of message object 16" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " INTPND15 ,Interrupt pending bit of message object 15" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " INTPND14 ,Interrupt pending bit of message object 14" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " INTPND13 ,Interrupt pending bit of message object 13" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTPND12 ,Interrupt pending bit of message object 12" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " INTPND11 ,Interrupt pending bit of message object 11" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " INTPND10 ,Interrupt pending bit of message object 10" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " INTPND9 ,Interrupt pending bit of message object 9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTPND8 ,Interrupt pending bit of message object 8" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " INTPND7 ,Interrupt pending bit of message object 7" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " INTPND6 ,Interrupt pending bit of message object 6" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " INTPND5 ,Interrupt pending bit of message object 5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTPND4 ,Interrupt pending bit of message object 4" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " INTPND3 ,Interrupt pending bit of message object 3" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " INTPND2 ,Interrupt pending bit of message object 2" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " INTPND1 ,Interrupt pending bit of message object 1" "Not pending,Pending"
|
|
line.long 0x04 "IR2,Interrupt pending 2"
|
|
bitfld.long 0x04 15. " INTPND32 ,Interrupt pending bit of message object 32" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " INTPND31 ,Interrupt pending bit of message object 31" "Not pending,Pending"
|
|
bitfld.long 0x04 13. " INTPND30 ,Interrupt pending bit of message object 30" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " INTPND29 ,Interrupt pending bit of message object 29" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTPND28 ,Interrupt pending bit of message object 28" "Not pending,Pending"
|
|
bitfld.long 0x04 10. " INTPND27 ,Interrupt pending bit of message object 27" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " INTPND26 ,Interrupt pending bit of message object 26" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " INTPND25 ,Interrupt pending bit of message object 25" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTPND24 ,Interrupt pending bit of message object 24" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " INTPND23 ,Interrupt pending bit of message object 23" "Not pending,Pending"
|
|
bitfld.long 0x04 5. " INTPND22 ,Interrupt pending bit of message object 22" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " INTPND21 ,Interrupt pending bit of message object 21" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTPND20 ,Interrupt pending bit of message object 20" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " INTPND19 ,Interrupt pending bit of message object 19" "Not pending,Pending"
|
|
bitfld.long 0x04 1. " INTPND18 ,Interrupt pending bit of message object 18" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " INTPND17 ,Interrupt pending bit of message object 17" "Not pending,Pending"
|
|
rgroup.long 0x160++0x07
|
|
line.long 0x00 "MSGV1,Message valid 1"
|
|
bitfld.long 0x00 15. " MSGVAL16 ,Message valid bit of message object 16" "Invalid,Valid"
|
|
bitfld.long 0x00 14. " MSGVAL15 ,Message valid bit of message object 15" "Invalid,Valid"
|
|
bitfld.long 0x00 13. " MSGVAL14 ,Message valid bit of message object 14" "Invalid,Valid"
|
|
bitfld.long 0x00 12. " MSGVAL13 ,Message valid bit of message object 13" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MSGVAL12 ,Message valid bit of message object 12" "Invalid,Valid"
|
|
bitfld.long 0x00 10. " MSGVAL11 ,Message valid bit of message object 11" "Invalid,Valid"
|
|
bitfld.long 0x00 9. " MSGVAL10 ,Message valid bit of message object 10" "Invalid,Valid"
|
|
bitfld.long 0x00 8. " MSGVAL9 ,Message valid bit of message object 9" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSGVAL8 ,Message valid bit of message object 8" "Invalid,Valid"
|
|
bitfld.long 0x00 6. " MSGVAL7 ,Message valid bit of message object 7" "Invalid,Valid"
|
|
bitfld.long 0x00 5. " MSGVAL6 ,Message valid bit of message object 6" "Invalid,Valid"
|
|
bitfld.long 0x00 4. " MSGVAL5 ,Message valid bit of message object 5" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSGVAL4 ,Message valid bit of message object 4" "Invalid,Valid"
|
|
bitfld.long 0x00 2. " MSGVAL3 ,Message valid bit of message object 3" "Invalid,Valid"
|
|
bitfld.long 0x00 1. " MSGVAL2 ,Message valid bit of message object 2" "Invalid,Valid"
|
|
bitfld.long 0x00 0. " MSGVAL1 ,Message valid bit of message object 1" "Invalid,Valid"
|
|
line.long 0x04 "MSGV2,Message valid 2"
|
|
bitfld.long 0x04 15. " MSGVAL32 ,Message valid bit of message object 32" "Invalid,Valid"
|
|
bitfld.long 0x04 14. " MSGVAL31 ,Message valid bit of message object 31" "Invalid,Valid"
|
|
bitfld.long 0x04 13. " MSGVAL30 ,Message valid bit of message object 30" "Invalid,Valid"
|
|
bitfld.long 0x04 12. " MSGVAL29 ,Message valid bit of message object 29" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MSGVAL28 ,Message valid bit of message object 28" "Invalid,Valid"
|
|
bitfld.long 0x04 10. " MSGVAL27 ,Message valid bit of message object 27" "Invalid,Valid"
|
|
bitfld.long 0x04 9. " MSGVAL26 ,Message valid bit of message object 26" "Invalid,Valid"
|
|
bitfld.long 0x04 8. " MSGVAL25 ,Message valid bit of message object 25" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSGVAL24 ,Message valid bit of message object 24" "Invalid,Valid"
|
|
bitfld.long 0x04 6. " MSGVAL23 ,Message valid bit of message object 23" "Invalid,Valid"
|
|
bitfld.long 0x04 5. " MSGVAL22 ,Message valid bit of message object 22" "Invalid,Valid"
|
|
bitfld.long 0x04 4. " MSGVAL21 ,Message valid bit of message object 21" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MSGVAL20 ,Message valid bit of message object 20" "Invalid,Valid"
|
|
bitfld.long 0x04 2. " MSGVAL19 ,Message valid bit of message object 19" "Invalid,Valid"
|
|
bitfld.long 0x04 1. " MSGVAL18 ,Message valid bit of message object 18" "Invalid,Valid"
|
|
bitfld.long 0x04 0. " MSGVAL17 ,Message valid bit of message object 17" "Invalid,Valid"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CLKDIV,CAN clock divider register"
|
|
bitfld.long 0x00 0.--3. " CLKDIVVAL ,Clock divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
width 0x0b
|
|
tree.end
|
|
tree.open "ADC (12-bit Analog-Digital Converter)"
|
|
tree "ADC0"
|
|
base ad:0x40000000
|
|
width 13.
|
|
if (((per.l(ad:0x40000000))&0x100)==0x0)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,A/D Control Register"
|
|
bitfld.long 0x00 30. " CALMODE ,Writing a 1 to this bit initiates a self-calibration cycle" "Not initiated,Initiated"
|
|
bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE10BIT ,Enable 10-bit conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASYNMODE ,Select clock mode" "Synchronous,Asynchronous"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock divide value"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,A/D Control Register"
|
|
bitfld.long 0x00 30. " CALMODE ,Writing a 1 to this bit initiates a self-calibration cycle" "Not initiated,Initiated"
|
|
bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE10BIT ,Enable 10-bit conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASYNMODE ,Select clock mode" "Synchronous,Asynchronous"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INSEL,A/D Input Select Register"
|
|
bitfld.long 0x00 0.--3. " CHAN0SEL ,Input source for channel 0" "ADCn_0 pin,Core voltage regulator,Internal voltage reference,Temperature Sensor,VDDA/2,?..."
|
|
if (((per.l((ad:0x40000000+0x08)))&0x80000000)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register"
|
|
bitfld.long 0x00 31. " SEQA_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register"
|
|
bitfld.long 0x00 31. " SEQA_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
endif
|
|
if (((per.l((ad:0x40000000+0x0c)))&0x80000000)==0x0)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register"
|
|
bitfld.long 0x00 31. " SEQB_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register"
|
|
bitfld.long 0x00 31. " SEQB_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SEQA_GDAT,A/D Sequence-A Global Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
line.long 0x04 "SEQB_GDAT,A/D Sequence-B Global Data Register"
|
|
bitfld.long 0x04 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x04 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x04 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x04 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
width 7.
|
|
tree "Channels 0-11 Data Registers"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DAT0,A/D Channel 0 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DAT1,A/D Channel 1 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DAT2,A/D Channel 2 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAT3,A/D Channel 3 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DAT4,A/D Channel 4 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DAT5,A/D Channel 5 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "DAT6,A/D Channel 6 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "DAT7,A/D Channel 7 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DAT8,A/D Channel 8 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DAT9,A/D Channel 9 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "DAT10,A/D Channel 10 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DAT11,A/D Channel 11 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
tree.end
|
|
width 13.
|
|
textline " "
|
|
group.long 0x50++0x1F
|
|
line.long 0x00 "THR0_LOW,A/D Low Compare Threshold Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared"
|
|
line.long 0x04 "THR1_LOW,A/D Low Compare Threshold Register 1"
|
|
hexmask.long.word 0x04 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared"
|
|
line.long 0x08 "THR0_HIGH,A/D High Compare Threshold Register 0"
|
|
hexmask.long.word 0x08 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared"
|
|
line.long 0x0c "THR1_HIGH,A/D High Compare Threshold Register 1"
|
|
hexmask.long.word 0x0c 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared"
|
|
line.long 0x10 "CHAN_THRSEL,A/D Channel-Threshold Select Register"
|
|
bitfld.long 0x10 11. " CH11_THRSEL ,Threshold select by channel 11" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 10. " CH10_THRSEL ,Threshold select by channel 10" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 9. " CH9_THRSEL ,Threshold select by channel 9" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 8. " CH8_THRSEL ,Threshold select by channel 8" "Threshold 0,Threshold 1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CH7_THRSEL ,Threshold select by channel 7" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 6. " CH6_THRSEL ,Threshold select by channel 6" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 5. " CH5_THRSEL ,Threshold select by channel 5" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 4. " CH4_THRSEL ,Threshold select by channel 4" "Threshold 0,Threshold 1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CH3_THRSEL ,Threshold select by channel 3" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 2. " CH2_THRSEL ,Threshold select by channel 2" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 1. " CH1_THRSEL ,Threshold select by channel 1" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 0. " CH0_THRSEL ,Threshold select by channel 0" "Threshold 0,Threshold 1"
|
|
line.long 0x14 "INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x14 25.--26. " ADCMPINTEN11 ,Threshold comparison for channel 11 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 23.--24. " ADCMPINTEN10 ,Threshold comparison for channel 10 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 21.--22. " ADCMPINTEN9 ,Threshold comparison for channel 9 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 19.--20. " ADCMPINTEN8 ,Threshold comparison for channel 8 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
textline " "
|
|
bitfld.long 0x14 17.--18. " ADCMPINTEN7 ,Threshold comparison for channel 7 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 15.--16. " ADCMPINTEN6 ,Threshold comparison for channel 6 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 13.--14. " ADCMPINTEN5 ,Threshold comparison for channel 5 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 11.--12. " ADCMPINTEN4 ,Threshold comparison for channel 4 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
textline " "
|
|
bitfld.long 0x14 9.--10. " ADCMPINTEN3 ,Threshold comparison for channel 3 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 7.--8. " ADCMPINTEN2 ,Threshold comparison for channel 2 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 5.--6. " ADCMPINTEN1 ,Threshold comparison for channel 1 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 3.--4. " ADCMPINTEN0 ,Threshold comparison for channel 0 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
textline " "
|
|
bitfld.long 0x14 2. " OVR_INTEN ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " SEQB_INTEN ,Sequence B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " SEQA_INTEN ,Sequence A interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "FLAGS,A/D Flags Register"
|
|
bitfld.long 0x18 31. " OVR_INT ,Overrun interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 30. " THCMP_INT ,Threshold Comparison Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " SEQB_INT ,Sequence B interrupt/DMA trigger" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 28. " SEQA_INT ,Sequence A interrupt/DMA trigger" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 25. " SEQB_OVR ,Mirrors the global OVERRUN status flag in the SEQB_GDAT register" "No overrun,Overrun"
|
|
bitfld.long 0x18 24. " SEQA_OVR ,Mirrors the global OVERRUN status flag in the SEQA_GDAT register" "No overrun,Overrun"
|
|
bitfld.long 0x18 23. " OVERRUN11 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 11" "No overrun,Overrun"
|
|
bitfld.long 0x18 22. " OVERRUN10 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 10" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 21. " OVERRUN9 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 9" "No overrun,Overrun"
|
|
bitfld.long 0x18 20. " OVERRUN8 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 8" "No overrun,Overrun"
|
|
bitfld.long 0x18 19. " OVERRUN7 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 7" "No overrun,Overrun"
|
|
bitfld.long 0x18 18. " OVERRUN6 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 6" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 17. " OVERRUN5 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 5" "No overrun,Overrun"
|
|
bitfld.long 0x18 16. " OVERRUN4 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 4" "No overrun,Overrun"
|
|
bitfld.long 0x18 15. " OVERRUN3 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 3" "No overrun,Overrun"
|
|
bitfld.long 0x18 14. " OVERRUN2 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 2" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OVERRUN1 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x18 12. " OVERRUN0 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 0" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 11. " THCMP11 ,Threshold comparison event on Channel 11" "Not occurred,Occurred"
|
|
bitfld.long 0x18 10. " THCMP10 ,Threshold comparison event on Channel 10" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 9. " THCMP9 ,Threshold comparison event on Channel 9" "Not occurred,Occurred"
|
|
bitfld.long 0x18 8. " THCMP8 ,Threshold comparison event on Channel 8" "Not occurred,Occurred"
|
|
bitfld.long 0x18 7. " THCMP7 ,Threshold comparison event on Channel 7" "Not occurred,Occurred"
|
|
bitfld.long 0x18 6. " THCMP6 ,Threshold comparison event on Channel 6" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 5. " THCMP5 ,Threshold comparison event on Channel 5" "Not occurred,Occurred"
|
|
bitfld.long 0x18 4. " THCMP4 ,Threshold comparison event on Channel 4" "Not occurred,Occurred"
|
|
bitfld.long 0x18 3. " THCMP3 ,Threshold comparison event on Channel 3" "Not occurred,Occurred"
|
|
bitfld.long 0x18 2. " THCMP2 ,Threshold comparison event on Channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 1. " THCMP1 ,Threshold comparison event on Channel 1" "Not occurred,Occurred"
|
|
bitfld.long 0x18 0. " THCMP0 ,Threshold comparison event on Channel 0" "Not occurred,Occurred"
|
|
line.long 0x1C "TRM,ADC trim register"
|
|
bitfld.long 0x1C 5. " VRANGE ,Voltage supply range" "VDDA = 2.7 V to 3.6 V,VDDA = 2.4 V to 2.7 V"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC1"
|
|
base ad:0x40080000
|
|
width 13.
|
|
if (((per.l(ad:0x40080000))&0x100)==0x0)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,A/D Control Register"
|
|
bitfld.long 0x00 30. " CALMODE ,Writing a 1 to this bit initiates a self-calibration cycle" "Not initiated,Initiated"
|
|
bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE10BIT ,Enable 10-bit conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASYNMODE ,Select clock mode" "Synchronous,Asynchronous"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock divide value"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,A/D Control Register"
|
|
bitfld.long 0x00 30. " CALMODE ,Writing a 1 to this bit initiates a self-calibration cycle" "Not initiated,Initiated"
|
|
bitfld.long 0x00 10. " LPWRMODE ,Enable low-power ADC mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MODE10BIT ,Enable 10-bit conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASYNMODE ,Select clock mode" "Synchronous,Asynchronous"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INSEL,A/D Input Select Register"
|
|
bitfld.long 0x00 0.--3. " CHAN0SEL ,Input source for channel 0" "ADCn_0 pin,Core voltage regulator,Internal voltage reference,Temperature Sensor,VDDA/2,?..."
|
|
if (((per.l((ad:0x40080000+0x08)))&0x80000000)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register"
|
|
bitfld.long 0x00 31. " SEQA_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register"
|
|
bitfld.long 0x00 31. " SEQA_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
endif
|
|
if (((per.l((ad:0x40080000+0x0c)))&0x80000000)==0x0)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register"
|
|
bitfld.long 0x00 31. " SEQB_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
bitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register"
|
|
bitfld.long 0x00 31. " SEQB_ENA ,Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence"
|
|
bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched"
|
|
bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge"
|
|
bitfld.long 0x00 12.--15. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CHANNEL11 ,Include channel 11 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 10. " CHANNEL10 ,Include channel 12 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 9. " CHANNEL9 ,Include channel 9 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 8. " CHANNEL8 ,Include channel 8 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " CHANNEL7 ,Include channel 7 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 6. " CHANNEL6 ,Include channel 6 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 5. " CHANNEL5 ,Include channel 5 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 4. " CHANNEL4 ,Include channel 4 in conversion sequence" "Excluded,Included"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " CHANNEL3 ,Include channel 3 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 2. " CHANNEL2 ,Include channel 2 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 1. " CHANNEL1 ,Include channel 1 in conversion sequence" "Excluded,Included"
|
|
rbitfld.long 0x00 0. " CHANNEL0 ,Include channel 0 in conversion sequence" "Excluded,Included"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SEQA_GDAT,A/D Sequence-A Global Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
line.long 0x04 "SEQB_GDAT,A/D Sequence-B Global Data Register"
|
|
bitfld.long 0x04 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x04 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x04 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x04 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
width 7.
|
|
tree "Channels 0-11 Data Registers"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DAT0,A/D Channel 0 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DAT1,A/D Channel 1 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DAT2,A/D Channel 2 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAT3,A/D Channel 3 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DAT4,A/D Channel 4 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DAT5,A/D Channel 5 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "DAT6,A/D Channel 6 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "DAT7,A/D Channel 7 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DAT8,A/D Channel 8 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "DAT9,A/D Channel 9 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "DAT10,A/D Channel 10 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DAT11,A/D Channel 11 Data Register"
|
|
bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid"
|
|
bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun"
|
|
bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..."
|
|
hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion"
|
|
tree.end
|
|
width 13.
|
|
textline " "
|
|
group.long 0x50++0x1F
|
|
line.long 0x00 "THR0_LOW,A/D Low Compare Threshold Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared"
|
|
line.long 0x04 "THR1_LOW,A/D Low Compare Threshold Register 1"
|
|
hexmask.long.word 0x04 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared"
|
|
line.long 0x08 "THR0_HIGH,A/D High Compare Threshold Register 0"
|
|
hexmask.long.word 0x08 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared"
|
|
line.long 0x0c "THR1_HIGH,A/D High Compare Threshold Register 1"
|
|
hexmask.long.word 0x0c 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared"
|
|
line.long 0x10 "CHAN_THRSEL,A/D Channel-Threshold Select Register"
|
|
bitfld.long 0x10 11. " CH11_THRSEL ,Threshold select by channel 11" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 10. " CH10_THRSEL ,Threshold select by channel 10" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 9. " CH9_THRSEL ,Threshold select by channel 9" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 8. " CH8_THRSEL ,Threshold select by channel 8" "Threshold 0,Threshold 1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CH7_THRSEL ,Threshold select by channel 7" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 6. " CH6_THRSEL ,Threshold select by channel 6" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 5. " CH5_THRSEL ,Threshold select by channel 5" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 4. " CH4_THRSEL ,Threshold select by channel 4" "Threshold 0,Threshold 1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CH3_THRSEL ,Threshold select by channel 3" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 2. " CH2_THRSEL ,Threshold select by channel 2" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 1. " CH1_THRSEL ,Threshold select by channel 1" "Threshold 0,Threshold 1"
|
|
bitfld.long 0x10 0. " CH0_THRSEL ,Threshold select by channel 0" "Threshold 0,Threshold 1"
|
|
line.long 0x14 "INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x14 25.--26. " ADCMPINTEN11 ,Threshold comparison for channel 11 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 23.--24. " ADCMPINTEN10 ,Threshold comparison for channel 10 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 21.--22. " ADCMPINTEN9 ,Threshold comparison for channel 9 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 19.--20. " ADCMPINTEN8 ,Threshold comparison for channel 8 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
textline " "
|
|
bitfld.long 0x14 17.--18. " ADCMPINTEN7 ,Threshold comparison for channel 7 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 15.--16. " ADCMPINTEN6 ,Threshold comparison for channel 6 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 13.--14. " ADCMPINTEN5 ,Threshold comparison for channel 5 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 11.--12. " ADCMPINTEN4 ,Threshold comparison for channel 4 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
textline " "
|
|
bitfld.long 0x14 9.--10. " ADCMPINTEN3 ,Threshold comparison for channel 3 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 7.--8. " ADCMPINTEN2 ,Threshold comparison for channel 2 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 5.--6. " ADCMPINTEN1 ,Threshold comparison for channel 1 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
bitfld.long 0x14 3.--4. " ADCMPINTEN0 ,Threshold comparison for channel 0 interrupt enable" "Disabled,Outside threshold,Crossing threshold,?..."
|
|
textline " "
|
|
bitfld.long 0x14 2. " OVR_INTEN ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " SEQB_INTEN ,Sequence B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " SEQA_INTEN ,Sequence A interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "FLAGS,A/D Flags Register"
|
|
bitfld.long 0x18 31. " OVR_INT ,Overrun interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 30. " THCMP_INT ,Threshold Comparison Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " SEQB_INT ,Sequence B interrupt/DMA trigger" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 28. " SEQA_INT ,Sequence A interrupt/DMA trigger" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 25. " SEQB_OVR ,Mirrors the global OVERRUN status flag in the SEQB_GDAT register" "No overrun,Overrun"
|
|
bitfld.long 0x18 24. " SEQA_OVR ,Mirrors the global OVERRUN status flag in the SEQA_GDAT register" "No overrun,Overrun"
|
|
bitfld.long 0x18 23. " OVERRUN11 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 11" "No overrun,Overrun"
|
|
bitfld.long 0x18 22. " OVERRUN10 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 10" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 21. " OVERRUN9 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 9" "No overrun,Overrun"
|
|
bitfld.long 0x18 20. " OVERRUN8 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 8" "No overrun,Overrun"
|
|
bitfld.long 0x18 19. " OVERRUN7 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 7" "No overrun,Overrun"
|
|
bitfld.long 0x18 18. " OVERRUN6 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 6" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 17. " OVERRUN5 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 5" "No overrun,Overrun"
|
|
bitfld.long 0x18 16. " OVERRUN4 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 4" "No overrun,Overrun"
|
|
bitfld.long 0x18 15. " OVERRUN3 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 3" "No overrun,Overrun"
|
|
bitfld.long 0x18 14. " OVERRUN2 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 2" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OVERRUN1 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x18 12. " OVERRUN0 ,Mirrors the OVERRRUN status flag from the result register for A/D channel 0" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x18 11. " THCMP11 ,Threshold comparison event on Channel 11" "Not occurred,Occurred"
|
|
bitfld.long 0x18 10. " THCMP10 ,Threshold comparison event on Channel 10" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 9. " THCMP9 ,Threshold comparison event on Channel 9" "Not occurred,Occurred"
|
|
bitfld.long 0x18 8. " THCMP8 ,Threshold comparison event on Channel 8" "Not occurred,Occurred"
|
|
bitfld.long 0x18 7. " THCMP7 ,Threshold comparison event on Channel 7" "Not occurred,Occurred"
|
|
bitfld.long 0x18 6. " THCMP6 ,Threshold comparison event on Channel 6" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 5. " THCMP5 ,Threshold comparison event on Channel 5" "Not occurred,Occurred"
|
|
bitfld.long 0x18 4. " THCMP4 ,Threshold comparison event on Channel 4" "Not occurred,Occurred"
|
|
bitfld.long 0x18 3. " THCMP3 ,Threshold comparison event on Channel 3" "Not occurred,Occurred"
|
|
bitfld.long 0x18 2. " THCMP2 ,Threshold comparison event on Channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 1. " THCMP1 ,Threshold comparison event on Channel 1" "Not occurred,Occurred"
|
|
bitfld.long 0x18 0. " THCMP0 ,Threshold comparison event on Channel 0" "Not occurred,Occurred"
|
|
line.long 0x1C "TRM,ADC trim register"
|
|
bitfld.long 0x1C 5. " VRANGE ,Voltage supply range" "VDDA = 2.7 V to 3.6 V,VDDA = 2.4 V to 2.7 V"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DAC (12-bit Digital-Analog Converter)"
|
|
base ad:0x40004000
|
|
width 8.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "VAL,D/A Converter Value Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " VALUE ,The voltage on the DAC_OUT pin is VALUE * ((VREFP_DAC - VREFN)/4096) + VREFN"
|
|
line.long 0x04 "CTRL,DAC Control register"
|
|
rbitfld.long 0x04 9. " SHUTOFF_FLAG ,Shutoff flag" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SHUTOFF_ENA ,Shutoff enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DBLBUF_ENA ,Double-Buffer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TIMER_ENA ,Timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SYNC_BYPASS ,Bypass one synchronization flip-flop" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " POLARITY ,Polarity of the selected external trigger input" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TRIG_SRC2 ,Hardware Trigger Source 2" "Internal,Pin"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TRIG_SRC1 ,Hardware Trigger Source 1" "Internal,Pin"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TRIG_SRC0 ,Hardware Trigger Source 0" "Internal,Pin"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " INT_DMA_FLAG ,Interrupt/DMA request flag" "Not requested,Requested"
|
|
line.long 0x08 "CNTVAL,DAC Counter Value register"
|
|
hexmask.long.word 0x08 0.--15. 1. " CNTVAL ,16-bit reload value for the internal DAC interrupt/DMA timer"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Analog comparators"
|
|
base ad:0x40008000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Comparator block control register"
|
|
bitfld.long 0x00 9. " EXT_RESET ,Selects the reset source for the ROSC output" "Internal,ROSC_RESET"
|
|
bitfld.long 0x00 8. " ROSCCTL ,Selects which comparators set/reset the ROSC output" "ACMP1/ACMP0,ACMP0/ACMP1"
|
|
if (((per.l((ad:0x40008000+0x04)))&0x10000)==0x0)
|
|
group.long 0x04++0x03 "Analog comparator 0"
|
|
line.long 0x00 "CMP0,Comparator 0 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
|
|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17.--18. " INTEDGE ,Select edge triggered interrupt to be active on either high or low transitions" "Falling,Rising,Both,?..."
|
|
bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 0,ACMP_I1,ACMP_I2,ACMP0_I3,ACMP0_I4,Int 0.9V band gap ref,Temp sensor,ADC0_2"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 0,ACMP_I1,ACMP_I2,ACMP0_I3,ACMP0_I4,Int 0.9V band gap ref,Temp sensor,ADC0_2"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03 "Analog comparator 0"
|
|
line.long 0x00 "CMP0,Comparator 0 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
|
|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 0,ACMP_I1,ACMP_I2,ACMP0_I3,ACMP0_I4,Int 0.9V band gap ref,Temp sensor,ADC0_2"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 0,ACMP_I1,ACMP_I2,ACMP0_I3,ACMP0_I4,Int 0.9V band gap ref,Temp sensor,ADC0_2"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMPFILTR0,Comparator 0 pin filter set-up"
|
|
bitfld.long 0x00 2.--4. " CLKDIV ,Select clock divider for comparator clock CMP_PCLK" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 0.--1. " S_MODE ,Digital filter sample mode" "Bypassed,1 clock cycle,2 clock cycles,3 clock cycles"
|
|
if (((per.l((ad:0x40008000+0x0c)))&0x10000)==0x0)
|
|
group.long 0x0c++0x03 "Analog comparator 1"
|
|
line.long 0x00 "CMP1,Comparator 1 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
|
|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17.--18. " INTEDGE ,Select edge triggered interrupt to be active on either high or low transitions" "Falling,Rising,Both,?..."
|
|
bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 1,ACMP_I1,ACMP_I2,ACMP1_I3,ACMP1_I4,Int 0.9V band gap ref,ADC0_1,ADC0_3"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 1,ACMP_I1,ACMP_I2,ACMP1_I3,ACMP1_I4,Int 0.9V band gap ref,ADC0_1,ADC0_3"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0c++0x03 "Analog comparator 1"
|
|
line.long 0x00 "CMP1,Comparator 1 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
|
|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 1,ACMP_I1,ACMP_I2,ACMP1_I3,ACMP1_I4,Int 0.9V band gap ref,ADC0_1,ADC0_3"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 1,ACMP_I1,ACMP_I2,ACMP1_I3,ACMP1_I4,Int 0.9V band gap ref,ADC0_1,ADC0_3"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CMPFILTR1,Comparator 1 pin filter set-up"
|
|
bitfld.long 0x00 2.--4. " CLKDIV ,Select clock divider for comparator clock CMP_PCLK" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 0.--1. " S_MODE ,Digital filter sample mode" "Bypassed,1 clock cycle,2 clock cycles,3 clock cycles"
|
|
if (((per.l((ad:0x40008000+0x14)))&0x10000)==0x0)
|
|
group.long 0x14++0x03 "Analog comparator 2"
|
|
line.long 0x00 "CMP2,Comparator 2 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
|
|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17.--18. " INTEDGE ,Select edge triggered interrupt to be active on either high or low transitions" "Falling,Rising,Both,?..."
|
|
bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP2_I3,ACMP2_I4,Int 0.9V band gap ref,ADC0_0,ADC1_2"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP2_I3,ACMP2_I4,Int 0.9V band gap ref,ADC0_0,ADC1_2"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03 "Analog comparator 2"
|
|
line.long 0x00 "CMP2,Comparator 2 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
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|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
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bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
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textline " "
|
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bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
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bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
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bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
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bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
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|
textline " "
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP2_I3,ACMP2_I4,Int 0.9V band gap ref,ADC0_0,ADC1_2"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP2_I3,ACMP2_I4,Int 0.9V band gap ref,ADC0_0,ADC1_2"
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bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
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endif
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group.long 0x18++0x03
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line.long 0x00 "CMPFILTR2,Comparator 2 pin filter set-up"
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bitfld.long 0x00 2.--4. " CLKDIV ,Select clock divider for comparator clock CMP_PCLK" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
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bitfld.long 0x00 0.--1. " S_MODE ,Digital filter sample mode" "Bypassed,1 clock cycle,2 clock cycles,3 clock cycles"
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if (((per.l((ad:0x40008000+0x1c)))&0x10000)==0x0)
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group.long 0x1c++0x03 "Analog comparator 3"
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line.long 0x00 "CMP3,Comparator 3 source control"
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bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
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bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
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|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
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|
textline " "
|
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bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
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|
bitfld.long 0x00 17.--18. " INTEDGE ,Select edge triggered interrupt to be active on either high or low transitions" "Falling,Rising,Both,?..."
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bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP3_I3,ACMP3_I4,Int 0.9V band gap ref,ADC1_1,ADC1_3"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP3_I3,ACMP3_I4,Int 0.9V band gap ref,ADC1_1,ADC1_3"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1c++0x03 "Analog comparator 3"
|
|
line.long 0x00 "CMP3,Comparator 3 source control"
|
|
bitfld.long 0x00 29.--30. " DLY ,Propagation delay" "Shortest,1,Longest,?..."
|
|
bitfld.long 0x00 24.--28. " VSEL ,Voltage ladder value for comparator 0 = n x Vref / 31" "Vss,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Vref"
|
|
bitfld.long 0x00 22. " VLADREF ,Voltage reference select for comparator 0 voltage ladder" "VDDCMP,VDDA pin"
|
|
bitfld.long 0x00 20. " VLADEN ,Voltage ladder enable for comparator 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTFLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " INTTYPE ,Select interrupt type" "Edge,Level"
|
|
bitfld.long 0x00 15. " INTPOL ,Selects the polarity of the CMP output for purposes of generating level interrupts" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13.--14. " HYS ,Hysteresis control" "Off,5 mV,10 mV,15 mV"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " VP ,VP input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP3_I3,ACMP3_I4,Int 0.9V band gap ref,ADC1_1,ADC1_3"
|
|
bitfld.long 0x00 4.--6. " VM ,VM input select" "Vref divider 2,ACMP_I1,ACMP_I2,ACMP3_I3,ACMP3_I4,Int 0.9V band gap ref,ADC1_1,ADC1_3"
|
|
bitfld.long 0x00 3. " STAT ,Comparator status" "Low,High"
|
|
bitfld.long 0x00 2. " INTEN ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator enable control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPFILTR3,Comparator 3 pin filter set-up"
|
|
bitfld.long 0x00 2.--4. " CLKDIV ,Select clock divider for comparator clock CMP_PCLK" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,?..."
|
|
bitfld.long 0x00 0.--1. " S_MODE ,Digital filter sample mode" "Bypassed,1 clock cycle,2 clock cycles,3 clock cycles"
|
|
width 0x0b
|
|
tree.end
|
|
tree "CRC engine (Cyclic Redundancy Check engine)"
|
|
base ad:0x1C010000
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MODE,CRC mode register"
|
|
bitfld.long 0x00 5. " CMPL_SUM ,CRC sum complement" "1's complement for CRC_SUM,No 1's complement for CRC_SUM"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BIT_RVS_SUM ,CRC sum bit order" "Reverse for CRC_SUM,No reverse for CRC_SUM"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMPL_WR ,Data complement" "1's complement for CRC_WR_DATA,No 1's complement for CRC_WR_DATA"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BIT_RVS_WR ,Data bit order" "Reverse for CRC_WR_DATA,No reverse for CRC_WR_DATA"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CRC_POLY ,CRC polynom" "CRC-16,CRC-CCITT,CRC-32,CRC-32"
|
|
line.long 0x04 "SEED,CRC seed register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SUM,CRC checksum register"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WR_DATA,CRC data register"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Flash controller"
|
|
base ad:0x400BC000
|
|
width 10.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FMSSTART,Signature start address register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " START ,Signature generation start address"
|
|
line.long 0x04 "FMSSTOP,Signature stop address register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " STOPA ,Stop address for signature generation"
|
|
textline " "
|
|
bitfld.long 0x04 31. " STRTBIST ,Signature generation start" "Not started,Started"
|
|
rgroup.long 0x2c++0x03
|
|
line.long 0x00 "FMSW0,Signature word"
|
|
width 0x0b
|
|
tree.end
|
|
textline ""
|