2855 lines
176 KiB
Plaintext
2855 lines
176 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC11Dxx On-Chip Peripherals
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; @Props: Released
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; @Author: KOP, LUK
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; @Changelog: 2018-11-19 LUK
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: ES_LPC11D14.pdf (Rev. 2 2013-01-17)
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; LPC11D14.pdf (Rev. 2 2012-07-23)
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; LPC11Dxx_UM10398.pdf (Rev. 12.4 2016-12-22)
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; @Core: Cortex-M0
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; @Chip: LPC11D14
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perlpc11dxx.per 9959 2018-12-04 13:51:00Z mkolodziejczyk $
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config 16. 8.
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "SYSCON (System Configuration)"
|
|
base ad:0x40048000
|
|
width 15.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SYSMEMREMAP,System Memory Remap Register"
|
|
bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader,User RAM,User Flash,?..."
|
|
line.long 0x04 "PRESETCTRL,Peripheral Reset Control Register"
|
|
bitfld.long 0x04 2. " SSP1_RST_N ,SPI1 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset"
|
|
bitfld.long 0x04 0. " SSP0_RST_N ,SPI0 reset control" "Reset,No reset"
|
|
line.long 0x08 "SYSPLLCTRL,System PLL Control Register"
|
|
bitfld.long 0x08 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
|
|
bitfld.long 0x08 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SYSPLLSTAT,System PLL Status Register"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register"
|
|
bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled"
|
|
line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register"
|
|
bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency Fclkana" ",0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz"
|
|
bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
line.long 0x08 "IRCCTRL,Internal Resonant Crystal Control Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TRIM ,Trim value"
|
|
group.long 0x30++0x04
|
|
line.long 0x00 "SYSRSTSTAT,System Reset Status Register"
|
|
eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset"
|
|
eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset"
|
|
eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset"
|
|
eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC,System oscillator,?..."
|
|
line.long 0x04 "SYSPLLCLKUEN,System PLL Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC,PLL input,LF,PLL output"
|
|
line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled"
|
|
line.long 0x08 "SYSAHBCLKDIV,System AHB Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SYSAHBCLKCTRL,System AHB Clock Control Register"
|
|
bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ADC ,Clock for ADC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " UART ,Clock for UART enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSP0 ,Clock for SPI0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CT32B1 ,Clock for 32-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CT32B0 ,Clock for 32-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " CT16B1 ,Clock for 16-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CT16B0 ,Clock for 16-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GPIO ,Clock for GPIO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " I2C ,Clock for I2C enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " FLASHARRAY ,Clock for flash array access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FLASHREG ,Clock for flash register interface enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RAM ,Clock for RAM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 0. " SYS ,Clock for AHB to APB bridge enable" ",Enabled"
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "SPP0CLKDIV,SPI0 Clock Divider Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,SPI0_PCLK clock divider values"
|
|
line.long 0x04 "UARTCLKDIV,UART Clock Divider Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIV ,UART_PCLK clock divider values"
|
|
line.long 0x08 "SSP1CLKDIV,SPI1 Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,SSP1_PCLK clock divider values"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "WDTCLKSEL,WDT Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,WDT clock source" "IRC,Main clock,Watchdog,?..."
|
|
line.long 0x04 "WDTCLKUEN,WDT Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,WDT clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "WDTCLKDIV,WDT Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,WDT clock divider values"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC,System,Watchdog,Main clock"
|
|
line.long 0x04 "CLKOUTUEN,CLKOUT Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "CLKOUTDIV,CLKOUT Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0"
|
|
bitfld.long 0x00 31. " CAPPIO2[7] ,Raw reset status input PIO2_7" "Low,High"
|
|
bitfld.long 0x00 30. " [6] ,Raw reset status input PIO2_6" "Low,High"
|
|
bitfld.long 0x00 29. " [5] ,Raw reset status input PIO2_5" "Low,High"
|
|
bitfld.long 0x00 28. " [4] ,Raw reset status input PIO2_4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [3] ,Raw reset status input PIO2_3" "Low,High"
|
|
bitfld.long 0x00 26. " [2] ,Raw reset status input PIO2_2" "Low,High"
|
|
bitfld.long 0x00 25. " [1] ,Raw reset status input PIO2_1" "Low,High"
|
|
bitfld.long 0x00 24. " [0] ,Raw reset status input PIO2_0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " CAPPIO1[11] ,Raw reset status input PIO1_11" "Low,High"
|
|
bitfld.long 0x00 22. " [10] ,Raw reset status input PIO1_10" "Low,High"
|
|
bitfld.long 0x00 21. " [9] ,Raw reset status input PIO1_9" "Low,High"
|
|
bitfld.long 0x00 20. " [8] ,Raw reset status input PIO1_8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [7] ,Raw reset status input PIO1_7" "Low,High"
|
|
bitfld.long 0x00 18. " [6] ,Raw reset status input PIO1_6" "Low,High"
|
|
bitfld.long 0x00 17. " [5] ,Raw reset status input PIO1_5" "Low,High"
|
|
bitfld.long 0x00 16. " [4] ,Raw reset status input PIO1_4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [3] ,Raw reset status input PIO1_3" "Low,High"
|
|
bitfld.long 0x00 14. " [2] ,Raw reset status input PIO1_2" "Low,High"
|
|
bitfld.long 0x00 13. " [1] ,Raw reset status input PIO1_1" "Low,High"
|
|
bitfld.long 0x00 12. " [0] ,Raw reset status input PIO1_0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " CAPPIO0[11] ,Raw reset status input PIO0_11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Raw reset status input PIO0_10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Raw reset status input PIO0_9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Raw reset status input PIO0_8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Raw reset status input PIO0_7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Raw reset status input PIO0_6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Raw reset status input PIO0_5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Raw reset status input PIO0_4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Raw reset status input PIO0_3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Raw reset status input PIO0_2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Raw reset status input PIO0_1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Raw reset status input PIO0_0" "Low,High"
|
|
line.long 0x04 "PIOPORCAP1,POR Captured PIO Status Register 1"
|
|
bitfld.long 0x04 9. " CAPPIO3[5] ,Raw reset status input PIO3_5" "Low,High"
|
|
bitfld.long 0x04 8. " [4] ,Raw reset status input PIO3_4" "Low,High"
|
|
bitfld.long 0x04 7. " [3] ,Raw reset status input PIO3_3" "Low,High"
|
|
bitfld.long 0x04 6. " [2] ,Raw reset status input PIO3_2" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 5. " [1] ,Raw reset status input PIO3_1" "Low,High"
|
|
bitfld.long 0x04 4. " [0] ,Raw reset status input PIO3_0" "Low,High"
|
|
bitfld.long 0x04 3. " CAPPI2[11] ,Raw reset status input PIO2_11" "Low,High"
|
|
bitfld.long 0x04 2. " [10] ,Raw reset status input PIO2_10" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 1. " [9] ,Raw reset status input PIO2_9" "Low,High"
|
|
bitfld.long 0x04 0. " [8] ,Raw reset status input PIO2_8" "Low,High"
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "BODCTRL,BOD Control Register"
|
|
bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",2.22V/2.35V,2.52V/2.66V,2.80V/2.90V"
|
|
bitfld.long 0x00 0.--1. " BODRSTLEV , BOD reset level" "1.46V/1.63V,2.06V/2.15V,2.35V/2.43V,2.63V/2.71V"
|
|
line.long 0x04 "SYSTCKCAL,System Tick Timer Calibration Register"
|
|
hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value"
|
|
group.long 0x170++0x07
|
|
line.long 0x00 "IRQLATENCY,IRQ Latency Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value"
|
|
line.long 0x04 "NMISRC,NMI Source Selection Register"
|
|
bitfld.long 0x04 31. " NMIEN ,Non-maskable Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--4. " IRQNO ,IRQ number of the interrupt" "PIN0_0_INT0,PIN0_1_INT1,PIN0_2_INT2,PIN0_3_INT3,PIN0_4_INT4,PIN0_5_INT5,PIN0_6_INT6,PIN0_7_INT7,PIN0_8_INT8,PIN0_9_INT9,PIN0_10_INT10,PIN0_11_INT11,PIN1_0_INT12,C_CAN,SPI/SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SPI/SSP0,UART,,,ADC,WDT,BOD,,PIO_3,PIO_2,PIO_1,PIO_0"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "STARTAPRP0,Start Logic Edge Control Register 0"
|
|
bitfld.long 0x00 12. " APRPIO1[0] ,Edge select for start logic input PI1_0" "Falling,Rising"
|
|
bitfld.long 0x00 11. " APRPIO0[11] ,Edge select for start logic input PIO0_11" "Falling,Rising"
|
|
bitfld.long 0x00 10. " [10] ,Edge select for start logic input PIO0_10" "Falling,Rising"
|
|
bitfld.long 0x00 9. " [9] ,Edge select for start logic input PIO0_9" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,Edge select for start logic input PIO0_8" "Falling,Rising"
|
|
bitfld.long 0x00 7. " [7] ,Edge select for start logic input PIO0_7" "Falling,Rising"
|
|
bitfld.long 0x00 6. " [6] ,Edge select for start logic input PIO0_6" "Falling,Rising"
|
|
bitfld.long 0x00 5. " [5] ,Edge select for start logic input PIO0_5" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Edge select for start logic input PIO0_4" "Falling,Rising"
|
|
bitfld.long 0x00 3. " [3] ,Edge select for start logic input PIO0_3" "Falling,Rising"
|
|
bitfld.long 0x00 2. " [2] ,Edge select for start logic input PIO0_2" "Falling,Rising"
|
|
bitfld.long 0x00 1. " [1] ,Edge select for start logic input PIO0_2" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Edge select for start logic input PI0_0" "Falling,Rising"
|
|
line.long 0x04 "STARTERP0,Start Logic Signal Enable Register 0"
|
|
bitfld.long 0x04 12. " ERPIO1[0] ,Enable start signal for start logic PIO1_0" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ERPIO0[11] ,Enable start signal for start logic PIO0_11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Enable start signal for start logic PIO0_10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Enable start signal for start logic PIO0_9" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " [8] ,Enable start signal for start logic PIO0_8" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [7] ,Enable start signal for start logic PIO0_7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Enable start signal for start logic PIO0_6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Enable start signal for start logic PIO0_5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Enable start signal for start logic PIO0_4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [3] ,Enable start signal for start logic PIO0_3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Enable start signal for start logic PIO0_2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Enable start signal for start logic PIO0_2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,Enable start signal for start logic PIO0_0" "Disabled,Enabled"
|
|
wgroup.long 0x208++0x03
|
|
line.long 0x00 "STARTRSRP0CLR,Start Logic Reset Register 0"
|
|
bitfld.long 0x00 12. " RSRPIO1[0] ,Start signal reset for start logic input PIO1_0" "No reset,Reset"
|
|
bitfld.long 0x00 11. " RSRPIO0[11] ,Start signal reset for start logic input PIO0_11" "No reset,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Start signal reset for start logic input PIO0_10" "No reset,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Start signal reset for start logic input PIO0_9" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,Start signal reset for start logic input PIO0_8" "No reset,Reset"
|
|
bitfld.long 0x00 7. " [7] ,Start signal reset for start logic input PIO0_7" "No reset,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Start signal reset for start logic input PIO0_6" "No reset,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Start signal reset for start logic input PIO0_5" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Start signal reset for start logic input PIO0_4" "No reset,Reset"
|
|
bitfld.long 0x00 3. " [3] ,Start signal reset for start logic input PIO0_3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Start signal reset for start logic input PIO0_2" "No reset,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Start signal reset for start logic input PIO0_1" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Start signal reset for start logic input PIO0_0" "No reset,Reset"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "STARTSRP0,Start Logic Status Register 0"
|
|
bitfld.long 0x00 12. " SRPIO1[0] ,Start signal status for start logic input PIO1_0" "Not started,Started"
|
|
bitfld.long 0x00 11. " SRPIO0[11] ,Start signal status for start logic input PIO0_11" "Not started,Started"
|
|
bitfld.long 0x00 10. " [10] ,Start signal status for start logic input PIO0_10" "Not started,Started"
|
|
bitfld.long 0x00 9. " [9] ,Start signal status for start logic input PIO0_9" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,Start signal status for start logic input PIO0_8" "Not started,Started"
|
|
bitfld.long 0x00 7. " [7] ,Start signal status for start logic input PIO0_7" "Not started,Started"
|
|
bitfld.long 0x00 6. " [6] ,Start signal status for start logic input PIO0_6" "Not started,Started"
|
|
bitfld.long 0x00 5. " [5] ,Start signal status for start logic input PIO0_5" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Start signal status for start logic input PIO0_4" "Not started,Started"
|
|
bitfld.long 0x00 3. " [3] ,Start signal status for start logic input PIO0_3" "Not started,Started"
|
|
bitfld.long 0x00 2. " [2] ,Start signal status for start logic input PIO0_2" "Not started,Started"
|
|
bitfld.long 0x00 1. " [1] ,Start signal status for start logic input PIO0_2" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Start signal status for start logic input PIO0_0" "Not started,Started"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "PDSLEEPCFG,Deep-sleep Configuration Register"
|
|
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power control in deep-sleep mode" "Powered,Powered down"
|
|
bitfld.long 0x00 3. " BOD_PD ,BOD power-down control in deep-sleep mode" "Powered,Powered down"
|
|
line.long 0x04 "PDAWAKECFG,Wake-up Configuration Register"
|
|
bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 5. " SYSOSC_PD ,System oscillator wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down"
|
|
newline
|
|
bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 1. " IRC_PD ,IRC oscillator power-down wake-up configuration" "Powered,Powered down"
|
|
bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down"
|
|
line.long 0x08 "PDRUNCFG,Power Configuration Register"
|
|
bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 5. " SYS0SC_PD ,System oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down"
|
|
newline
|
|
bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down"
|
|
rgroup.long 0x3F4++0x03
|
|
line.long 0x00 "DEVICE_ID,Device ID Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMU (Power Monitor Unit)"
|
|
base ad:0x40038000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCON,Power Control Register"
|
|
eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not entered,Entered"
|
|
eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not entered,Entered"
|
|
bitfld.long 0x00 1. " DPDEN ,Deep power-down mode enable" "Disabled,Enabled"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPREG0,General Purpose Register 0"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPREG2,General Purpose Register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPREG3,General Purpose Register 3"
|
|
group.long 0x0014++0x03
|
|
line.long 0x00 "GPREG4,General Purpose Register $2"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during Deep power-down mode"
|
|
bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IOCONFIG (I/O Configuration)"
|
|
base ad:0x40044000
|
|
width 24.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IOCON_PIO2_6,I/O Configuration For Pin PIO2_6"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_6,?..."
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "IOCON_PIO2_0,I/O Configuration For Pin PIO2_0/DTR/SSEL1"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_0,DTR,SSEL1,?..."
|
|
line.long 0x04 "IOCON_PIO_RESET_PIO0_0,I/O Configuration For Pin RESET/PIO0_0"
|
|
bitfld.long 0x04 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "Reset,PIO0_0,?..."
|
|
line.long 0x08 "IOCON_PIO0_1,I/O Configuration For Pin PIO0_1/CLKOUT/CT32B0_MAT2"
|
|
bitfld.long 0x08 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_1,CLKOUT,CT32B0_MAT2,?..."
|
|
line.long 0x0C "IOCON_PIO1_8,I/O Configuration For Pin PIO1_8/CT16B1_CAP0"
|
|
bitfld.long 0x0C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_8,CT16B1_CAP0,?..."
|
|
group.long 0x1C++0x13
|
|
line.long 0x00 "IOCON_PIO0_2, I/O Configuration For Pin PIO0_2/SSEL0/CT16B0_CAP0"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_2,SSEL0,CT16B0_CAP0,?..."
|
|
line.long 0x04 "IOCON_PIO2_7,I/O Configuration For Pin PIO2_7"
|
|
bitfld.long 0x04 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_7,?..."
|
|
line.long 0x08 "IOCON_PIO2_8,I/O Configuration For Pin PIO2_8"
|
|
bitfld.long 0x08 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_8,?..."
|
|
line.long 0x0C "IOCON_PIO2_1,I/O Configuration For Pin PIO2_1/DSR/SCK1"
|
|
bitfld.long 0x0C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_1,DSR,SCK1,?..."
|
|
line.long 0x10 "IOCON_PIO0_3,I/O Configuration For Pin PIO0_3"
|
|
bitfld.long 0x10 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_3,?..."
|
|
if (((per.l(ad:0x40044000+0x30))&0x07)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IOCON_PIO0_4,I/O Configuration For Pin PIO0_4/SCL"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,Selects I2C mode" "Standard mode/Fast-mode I2C,Standard I/O functionality,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C/SCL,?..."
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IOCON_PIO0_4,I/O Configuration For Pin PIO0_4/SCL"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,Selects I2C mode" "Standard mode/Fast-mode I2C,Standard I/O functionality,Fast-mode plus I2C,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C/SCL,?..."
|
|
endif
|
|
if (((per.l(ad:0x40044000+0x34))&0x07)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IOCON_PIO0_5,I/O Configuration For Pin PIO0_5/SDA"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,Selects I2C mode" "Standard mode/Fast-mode I2C,Standard I/O functionality,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C/SDA,?..."
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IOCON_PIO0_5,I/O Configuration For Pin PIO0_5/SDA"
|
|
bitfld.long 0x00 8.--9. " I2CMODE ,Selects I2C mode" "Standard mode/Fast-mode I2C,Standard I/O functionality,Fast-mode plus I2C,?..."
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C/SDA,?..."
|
|
endif
|
|
group.long 0x38++0x13
|
|
line.long 0x00 "IOCON_PIO1_9,I/O Configuration For Pin PIO1_9/CT16B1_MAT0"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_9,CT16B1_MAT0,?..."
|
|
line.long 0x04 "IOCON_PIO3_4,I/O Configuration For Pin PIO3_4"
|
|
bitfld.long 0x04 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO3_4,?..."
|
|
line.long 0x08 "IOCON_PIO2_4,I/O Configuration For Pin PIO2_4"
|
|
bitfld.long 0x08 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_4,?..."
|
|
line.long 0x0C "IOCON_PIO2_5,I/O Configuration For Pin PIO2_5"
|
|
bitfld.long 0x0C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_5,?..."
|
|
line.long 0x10 "IOCON_PIO3_5,I/O Configuration For Pin PIO3_5"
|
|
bitfld.long 0x10 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO3_5,?..."
|
|
if (((per.l(ad:0x40044000+0xB0))&0x03)==0x02)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IOCON_PIO0_6,I/O Configuration For Pin PIO0_6/SCK0"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_6,,SCK0,?..."
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IOCON_PIO0_6,I/O Configuration For Pin PIO0_6/SCK0"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_6,?..."
|
|
endif
|
|
group.long 0x50++0x17
|
|
line.long 0x00 "IOCON_PIO0_7,I/O Configuration For Pin PIO0_7/CTS"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_7,CTS,?..."
|
|
line.long 0x04 "IOCON_PIO2_9,I/O Configuration For Pin PIO2_9"
|
|
bitfld.long 0x04 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_9,?..."
|
|
line.long 0x08 "IOCON_PIO2_10,I/O Configuration For Pin PIO2_10"
|
|
bitfld.long 0x08 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_10,?..."
|
|
line.long 0x0C "IOCON_PIO2_2,I/O Configuration For Pin PIO2_2/DCD/MISO1"
|
|
bitfld.long 0x0C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_2,DCD,MISO1,?..."
|
|
line.long 0x10 "IOCON_PIO0_8,I/O Configuration For Pin PIO0_8/MISO0/CT16B0_MAT0"
|
|
bitfld.long 0x10 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_8,MISO0,CT16B0_MAT0,?..."
|
|
line.long 0x14 "IOCON_PIO0_9,I/O Configuration For Pin PIO0_9/MOSI0/CT16B0_MAT1"
|
|
bitfld.long 0x14 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO0_9,MOSI0,CT16B0_MAT1,?..."
|
|
if (((per.l(ad:0x40044000+0xB0))&0x03)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IOCON_SWCLK_PIO0_10,I/O Configuration For Pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "SWCLK,PIO0_10,SCK0,CT16B0_MAT2,?..."
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IOCON_SWCLK_PIO0_10,I/O Configuration For Pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "SWCLK,PIO0_10,,CT16B0_MAT2,?..."
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "IOCON_PIO1_10,I/O Configuration For Pin PIO1_10/AD6/CT16B1_MAT1"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 7. " ADMODE ,Selects analog/digital mode" "Analog,Digital"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_10,AD6,CT16B1_MAT1,?..."
|
|
if (((per.l(ad:0x40044000+0xB0))&0x13)==0x01)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IOCON_PIO2_11,I/O Configuration For Pin PIO2_11/SCK0"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_11,SCK,?..."
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IOCON_PIO2_11,I/O Configuration For Pin PIO2_11/SCK0"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_11,?..."
|
|
endif
|
|
group.long 0x74++0x4B
|
|
line.long 0x00 "IOCON_R_PIO0_11,I/O Configuration For Pin R/PIO0_11/AD0/CT32B0_MAT3"
|
|
bitfld.long 0x00 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x00 7. " ADMODE ,Selects analog/digital mode" "Analog,Digital"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" ",PIO0_11,AD0,CT32B0_MAT3,?..."
|
|
line.long 0x04 "IOCON_R_PIO1_0,I/O Configuration For Pin R/PIO1_0/AD1/CT32B1_CAP0"
|
|
bitfld.long 0x04 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x04 7. " ADMODE ,Selects analog/digital mode" "Analog,Digital"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" ",PIO1_0,AD1,CT32B1_CAP0,?..."
|
|
line.long 0x08 "IOCON_R_PIO1_1,I/O Configuration For Pin R/PIO1_1/AD2/CT32B1_MAT0"
|
|
bitfld.long 0x08 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x08 7. " ADMODE ,Selects analog/digital mode" "Analog,Digital"
|
|
bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" ",PIO1_1,AD2,CT32B1_MAT0,?..."
|
|
line.long 0x0C "IOCON_R_PIO1_2,I/O Configuration For Pin R/PIO1_2/AD3/CT32B1_MAT1"
|
|
bitfld.long 0x0C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x0C 7. " ADMODE ,Selects analog/digital mode" "Analog,Digital"
|
|
bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" ",PIO1_2,AD3,CT32B1_MAT1,?..."
|
|
line.long 0x10 "IOCON_PIO3_0,I/O Configuration For Pin PIO3_0/DTR"
|
|
bitfld.long 0x10 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO3_0,DTR,?..."
|
|
line.long 0x14 "IOCON_PIO3_1,I/O Configuration For Pin PIO3_1/DSR"
|
|
bitfld.long 0x14 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO3_1,DSR,?..."
|
|
line.long 0x18 "IOCON_PIO2_3,I/O Configuration For Pin PIO2_3/RI/MOSI1"
|
|
bitfld.long 0x18 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO2_3,RI,MOSI1,?..."
|
|
line.long 0x1C "IOCON_SWDIO_PIO1_3,I/O Configuration For Pin PIO1_3/RI/MOSI1"
|
|
bitfld.long 0x1C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x1C 7. " ADMODE ,Selects Analog/Digital mode" "Analog,Digital"
|
|
bitfld.long 0x1C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x1C 0.--2. " FUNC ,Selects pin function" "SWDIO,PIO1_3,AD4,CT32B1_MAT2,?..."
|
|
line.long 0x20 "IOCON_PIO1_4,I/O Configuration For Pin PIO1_4/AD5/CT32B1_MAT3"
|
|
bitfld.long 0x20 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x20 7. " ADMODE ,Selects Analog/Digital mode" "Analog,Digital"
|
|
bitfld.long 0x20 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x20 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x20 0.--2. " FUNC ,Selects pin function" "PIO1_4,AD5,CT32B1_MAT3,?..."
|
|
line.long 0x24 "IOCON_PIO1_11,I/O Configuration For Pin PIO1_11/AD7"
|
|
bitfld.long 0x24 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x24 7. " ADMODE ,Selects Analog/Digital mode" "Analog,Digital"
|
|
bitfld.long 0x24 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x24 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
newline
|
|
bitfld.long 0x24 0.--2. " FUNC ,Selects pin function" "PIO1_11,AD7,?..."
|
|
line.long 0x28 "IOCON_PIO3_2,I/O Configuration For Pin PIO3_2/DCD"
|
|
bitfld.long 0x28 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x28 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x28 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x28 0.--2. " FUNC ,Selects pin function" "PIO3_2,DCD,?..."
|
|
line.long 0x2C "IOCON_PIO1_5,I/O Configuration For Pin PIO1_5/RTS/CT32B0_CAP0"
|
|
bitfld.long 0x2C 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x2C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x2C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x2C 0.--2. " FUNC ,Selects pin function" "PIO1_5,RTS,CT32B0_CAP0,?..."
|
|
line.long 0x30 "IOCON_PIO1_6,I/O Configuration For Pin PIO1_6/RXD/CT32B0_MAT0"
|
|
bitfld.long 0x30 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x30 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x30 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x30 0.--2. " FUNC ,Selects pin function" "PIO1_6,RXD,CT32B0_MAT0,?..."
|
|
line.long 0x34 "IOCON_PIO1_7, I/O Configuration For Pin PIO1_7/TXD/CT32B0_MAT1"
|
|
bitfld.long 0x34 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x34 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x34 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x34 0.--2. " FUNC ,Selects pin function" "PIO1_7,TXD,CT32B0_MAT1,?..."
|
|
line.long 0x38 "IOCON_PIO3_3,I/O Configuration For Pin PIO3_3/RI"
|
|
bitfld.long 0x38 10. " OD ,Selects pseudo open-drain mode" "Standard GPIO,Open-drain"
|
|
bitfld.long 0x38 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x38 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x38 0.--2. " FUNC ,Selects pin function" "PIO3_3,RI,?..."
|
|
line.long 0x3C "IOCON_SCK_LOC,SCK Pin Location Select Register"
|
|
bitfld.long 0x3C 0.--1. " SCKLOC ,Selects pin location for SCK0 function" "SWCLK/PIO0_10/SCK0/CT16B0_MAT2,PIO2_11/SCK0,PIO0_6/SCK0,?..."
|
|
line.long 0x40 "IOCON_DSR_LOC, DSR Pin Location Select Register"
|
|
bitfld.long 0x40 0.--1. " DSRLOC ,Selects pin location for DSR function" "PIO2_1/DSR/SCK1,PIO3_1/DSR,?..."
|
|
line.long 0x44 "IOCON_DCD_LOC,DCD Pin Location Select Register"
|
|
bitfld.long 0x44 0.--1. " DCDLOC ,Selects pin location for DCD function" "PIO2_2/DCD/MISO1,PIO3_2/DCD,?..."
|
|
line.long 0x48 "IOCON_RI_LOC,RI Pin Location Register"
|
|
bitfld.long 0x48 0.--1. " RILOC ,Selects pin location for RI function" "PIO2_3/RI/MOSI1,PIO3_3/RI,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
tree "GPIO PORT 0"
|
|
base ad:0x50000000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO0DATA,GPIO0 Data Register"
|
|
bitfld.long 0x00 11. " DATA[11] ,PIO0_11 state" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,PIO0_10 state" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,PIO0_9 state" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,PIO0_8 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO0_7 state" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,PIO0_6 state" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,PIO0_5 state" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,PIO0_4 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PIO0_3 state" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,PIO0_2 state" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,PIO0_1 state" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,PIO0_0 state" "Low,High"
|
|
group.long 0x8000++0x13
|
|
line.long 0x00 "GPIO0DIR,GPIO0 Data Direction Register"
|
|
bitfld.long 0x00 11. " IO[11] ,PIO0_11 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,PIO0_10 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,PIO0_9 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,PIO0_8 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO0_7 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,PIO0_6 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,PIO0_5 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,PIO0_4 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PIO0_3 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,PIO0_2 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,PIO0_1 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,PIO0_0 input/output selection" "Input,Output"
|
|
line.long 0x04 "GPIO0IS,GPIO0 Interrupt Sense Register"
|
|
bitfld.long 0x04 11. " ISENSE[11] ,PIO0_11 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 10. " [10] ,PIO0_10 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 9. " [9] ,PIO0_9 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 8. " [8] ,PIO0_8 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,PIO0_7 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 6. " [6] ,PIO0_6 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 5. " [5] ,PIO0_5 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 4. " [4] ,PIO0_4 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PIO0_3 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 2. " [2] ,PIO0_2 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 1. " [1] ,PIO0_1 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 0. " [0] ,PIO0_0 interrupt sense" "Edge,Level"
|
|
line.long 0x08 "GPIO0IBE,GPIO0 Interrupt Both Edges Sense Register"
|
|
bitfld.long 0x08 11. " IBE[11] ,Pin PIO0_11 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 10. " [10] ,Pin PIO0_10 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 9. " [9] ,Pin PIO0_9 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 8. " [8] ,Pin PIO0_8 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Pin PIO0_7 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 6. " [6] ,Pin PIO0_6 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 5. " [5] ,Pin PIO0_5 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 4. " [4] ,Pin PIO0_4 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Pin PIO0_3 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 2. " [2] ,Pin PIO0_2 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 1. " [1] ,Pin PIO0_1 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 0. " [0] ,Pin PIO0_0 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
line.long 0x0C "GPIO0IEV,GPIO0 Interrupt Event Register"
|
|
bitfld.long 0x0C 11. " IEV[11] ,Pin PIO0_11 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 10. " [10] ,Pin PIO0_10 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 9. " [9] ,Pin PIO0_9 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 8. " [8] ,Pin PIO0_8 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Pin PIO0_7 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 6. " [6] ,Pin PIO0_6 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 5. " [5] ,Pin PIO0_5 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 4. " [4] ,Pin PIO0_4 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 3. " [3] ,Pin PIO0_3 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 2. " [2] ,Pin PIO0_2 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 1. " [1] ,Pin PIO0_1 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 0. " [0] ,Pin PIO0_0 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
line.long 0x10 "GPIO0IE,GPIO0 Interrupt Mask Register"
|
|
bitfld.long 0x10 11. " MASK[11] ,Pin PIO0_11 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 10. " [10] ,Pin PIO0_10 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 9. " [9] ,Pin PIO0_9 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 8. " [8] ,Pin PIO0_8 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [7] ,Pin PIO0_7 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 6. " [6] ,Pin PIO0_6 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 5. " [5] ,Pin PIO0_5 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 4. " [4] ,Pin PIO0_4 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 3. " [3] ,Pin PIO0_3 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " [2] ,Pin PIO0_2 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 1. " [1] ,Pin PIO0_1 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " [0] ,Pin PIO0_0 interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x8014++0x07
|
|
line.long 0x00 "GPIO0RIS,GPIO0 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt state on pin PIO0_11" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 10. " [10] ,Raw interrupt state on pin PIO0_10" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 9. " [9] ,Raw interrupt state on pin PIO0_9" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 8. " [8] ,Raw interrupt state on pin PIO0_8" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Raw interrupt state on pin PIO0_7" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 6. " [6] ,Raw interrupt state on pin PIO0_6" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 5. " [5] ,Raw interrupt state on pin PIO0_5" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 4. " [4] ,Raw interrupt state on pin PIO0_4" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Raw interrupt state on pin PIO0_3" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 2. " [2] ,Raw interrupt state on pin PIO0_2" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 1. " [1] ,Raw interrupt state on pin PIO0_1" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 0. " [0] ,Raw interrupt state on pin PIO0_0" "No interrupted,Interrupted"
|
|
line.long 0x04 "GPIO0MIS,GPIO0 Masked Interrupt Status Register"
|
|
bitfld.long 0x04 11. " MASK[11] ,Pin PIO0_11 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 10. " [10] ,Pin PIO0_10 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 9. " [9] ,Pin PIO0_9 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 8. " [8] ,Pin PIO0_8 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Pin PIO0_7 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 6. " [6] ,Pin PIO0_6 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 5. " [5] ,Pin PIO0_5 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 4. " [4] ,Pin PIO0_4 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Pin PIO0_3 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 2. " [2] ,Pin PIO0_2 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 1. " [1] ,Pin PIO0_1 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 0. " [0] ,Pin PIO0_0 interrupt mask" "No interrupted or masked,Interrupted"
|
|
wgroup.long 0x801C++0x03
|
|
line.long 0x00 "GPIO0IC,GPIO0 Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " CLR[11] ,Pin PIO0_11 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " [10] ,Pin PIO0_10 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " [9] ,Pin PIO0_9 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " [8] ,Pin PIO0_8 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin PIO0_7 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " [6] ,Pin PIO0_6 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " [5] ,Pin PIO0_5 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " [4] ,Pin PIO0_4 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Pin PIO0_3 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Pin PIO0_2 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Pin PIO0_1 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Pin PIO0_0 interrupt clear" "No effect,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PORT 1"
|
|
base ad:0x50010000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO1DATA,GPIO1 Data Register"
|
|
bitfld.long 0x00 11. " DATA[11] ,PIO1_11 state" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,PIO1_10 state" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,PIO1_9 state" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,PIO1_8 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO1_7 state" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,PIO1_6 state" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,PIO1_5 state" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,PIO1_4 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PIO1_3 state" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,PIO1_2 state" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,PIO1_1 state" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,PIO1_0 state" "Low,High"
|
|
group.long 0x8000++0x13
|
|
line.long 0x00 "GPIO1DIR,GPIO1 Data Direction Register"
|
|
bitfld.long 0x00 11. " IO[11] ,PIO1_11 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,PIO1_10 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,PIO1_9 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,PIO1_8 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO1_7 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,PIO1_6 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,PIO1_5 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,PIO1_4 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PIO1_3 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,PIO1_2 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,PIO1_1 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,PIO1_0 input/output selection" "Input,Output"
|
|
line.long 0x04 "GPIO1IS,GPIO1 Interrupt Sense Register"
|
|
bitfld.long 0x04 11. " ISENSE[11] ,PIO1_11 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 10. " [10] ,PIO1_10 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 9. " [9] ,PIO1_9 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 8. " [8] ,PIO1_8 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,PIO1_7 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 6. " [6] ,PIO1_6 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 5. " [5] ,PIO1_5 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 4. " [4] ,PIO1_4 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PIO1_3 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 2. " [2] ,PIO1_2 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 1. " [1] ,PIO1_1 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 0. " [0] ,PIO1_0 interrupt sense" "Edge,Level"
|
|
line.long 0x08 "GPIO1IBE,GPIO1 Interrupt Both Edges Sense Register"
|
|
bitfld.long 0x08 11. " IBE[11] ,Pin PIO1_11 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 10. " [10] ,Pin PIO1_10 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 9. " [9] ,Pin PIO1_9 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 8. " [8] ,Pin PIO1_8 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Pin PIO1_7 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 6. " [6] ,Pin PIO1_6 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 5. " [5] ,Pin PIO1_5 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 4. " [4] ,Pin PIO1_4 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Pin PIO1_3 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 2. " [2] ,Pin PIO1_2 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 1. " [1] ,Pin PIO1_1 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 0. " [0] ,Pin PIO1_0 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
line.long 0x0C "GPIO1IEV,GPIO1 Interrupt Event Register"
|
|
bitfld.long 0x0C 11. " IEV[11] ,Pin PIO1_11 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 10. " [10] ,Pin PIO1_10 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 9. " [9] ,Pin PIO1_9 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 8. " [8] ,Pin PIO1_8 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Pin PIO1_7 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 6. " [6] ,Pin PIO1_6 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 5. " [5] ,Pin PIO1_5 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 4. " [4] ,Pin PIO1_4 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 3. " [3] ,Pin PIO1_3 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 2. " [2] ,Pin PIO1_2 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 1. " [1] ,Pin PIO1_1 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 0. " [0] ,Pin PIO1_0 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
line.long 0x10 "GPIO1IE,GPIO1 Interrupt Mask Register"
|
|
bitfld.long 0x10 11. " MASK[11] ,Pin PIO1_11 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 10. " [10] ,Pin PIO1_10 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 9. " [9] ,Pin PIO1_9 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 8. " [8] ,Pin PIO1_8 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [7] ,Pin PIO1_7 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 6. " [6] ,Pin PIO1_6 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 5. " [5] ,Pin PIO1_5 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 4. " [4] ,Pin PIO1_4 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 3. " [3] ,Pin PIO1_3 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " [2] ,Pin PIO1_2 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 1. " [1] ,Pin PIO1_1 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " [0] ,Pin PIO1_0 interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x8014++0x07
|
|
line.long 0x00 "GPIO1RIS,GPIO1 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt state on pin PIO1_11" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 10. " [10] ,Raw interrupt state on pin PIO1_10" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 9. " [9] ,Raw interrupt state on pin PIO1_9" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 8. " [8] ,Raw interrupt state on pin PIO1_8" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Raw interrupt state on pin PIO1_7" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 6. " [6] ,Raw interrupt state on pin PIO1_6" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 5. " [5] ,Raw interrupt state on pin PIO1_5" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 4. " [4] ,Raw interrupt state on pin PIO1_4" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Raw interrupt state on pin PIO1_3" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 2. " [2] ,Raw interrupt state on pin PIO1_2" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 1. " [1] ,Raw interrupt state on pin PIO1_1" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 0. " [0] ,Raw interrupt state on pin PIO1_0" "No interrupted,Interrupted"
|
|
line.long 0x04 "GPIO1MIS,GPIO1 Masked Interrupt Status Register"
|
|
bitfld.long 0x04 11. " MASK[11] ,Pin PIO1_11 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 10. " [10] ,Pin PIO1_10 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 9. " [9] ,Pin PIO1_9 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 8. " [8] ,Pin PIO1_8 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Pin PIO1_7 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 6. " [6] ,Pin PIO1_6 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 5. " [5] ,Pin PIO1_5 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 4. " [4] ,Pin PIO1_4 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Pin PIO1_3 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 2. " [2] ,Pin PIO1_2 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 1. " [1] ,Pin PIO1_1 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 0. " [0] ,Pin PIO1_0 interrupt mask" "No interrupted or masked,Interrupted"
|
|
wgroup.long 0x801C++0x03
|
|
line.long 0x00 "GPIO1IC,GPIO1 Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " CLR[11] ,Pin PIO1_11 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " [10] ,Pin PIO1_10 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " [9] ,Pin PIO1_9 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " [8] ,Pin PIO1_8 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin PIO1_7 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " [6] ,Pin PIO1_6 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " [5] ,Pin PIO1_5 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " [4] ,Pin PIO1_4 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Pin PIO1_3 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Pin PIO1_2 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Pin PIO1_1 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Pin PIO1_0 interrupt clear" "No effect,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PORT 2"
|
|
base ad:0x50020000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO2DATA,GPIO2 Data Register"
|
|
bitfld.long 0x00 11. " DATA[11] ,PIO2_11 state" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,PIO2_10 state" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,PIO2_9 state" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,PIO2_8 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO2_7 state" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,PIO2_6 state" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,PIO2_5 state" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,PIO2_4 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PIO2_3 state" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,PIO2_2 state" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,PIO2_1 state" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,PIO2_0 state" "Low,High"
|
|
group.long 0x8000++0x13
|
|
line.long 0x00 "GPIO2DIR,GPIO2 Data Direction Register"
|
|
bitfld.long 0x00 11. " IO[11] ,PIO2_11 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 10. " [10] ,PIO2_10 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,PIO2_9 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,PIO2_8 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO2_7 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,PIO2_6 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,PIO2_5 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,PIO2_4 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PIO2_3 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,PIO2_2 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,PIO2_1 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,PIO2_0 input/output selection" "Input,Output"
|
|
line.long 0x04 "GPIO2IS,GPIO2 Interrupt Sense Register"
|
|
bitfld.long 0x04 11. " ISENSE[11] ,PIO2_11 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 10. " [10] ,PIO2_10 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 9. " [9] ,PIO2_9 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 8. " [8] ,PIO2_8 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,PIO2_7 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 6. " [6] ,PIO2_6 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 5. " [5] ,PIO2_5 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 4. " [4] ,PIO2_4 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,PIO2_3 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 2. " [2] ,PIO2_2 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 1. " [1] ,PIO2_1 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 0. " [0] ,PIO2_0 interrupt sense" "Edge,Level"
|
|
line.long 0x08 "GPIO2IBE,GPIO2 Interrupt Both Edges Sense Register"
|
|
bitfld.long 0x08 11. " IBE[11] ,Pin PIO2_11 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 10. " [10] ,Pin PIO2_10 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 9. " [9] ,Pin PIO2_9 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 8. " [8] ,Pin PIO2_8 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Pin PIO2_7 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 6. " [6] ,Pin PIO2_6 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 5. " [5] ,Pin PIO2_5 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 4. " [4] ,Pin PIO2_4 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Pin PIO2_3 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 2. " [2] ,Pin PIO2_2 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 1. " [1] ,Pin PIO2_1 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 0. " [0] ,Pin PIO2_0 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
line.long 0x0C "GPIO2IEV,GPIO2 Interrupt Event Register"
|
|
bitfld.long 0x0C 11. " IEV[11] ,Pin PIO2_11 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 10. " [10] ,Pin PIO2_10 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 9. " [9] ,Pin PIO2_9 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 8. " [8] ,Pin PIO2_8 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Pin PIO2_7 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 6. " [6] ,Pin PIO2_6 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 5. " [5] ,Pin PIO2_5 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 4. " [4] ,Pin PIO2_4 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 3. " [3] ,Pin PIO2_3 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 2. " [2] ,Pin PIO2_2 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 1. " [1] ,Pin PIO2_1 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 0. " [0] ,Pin PIO2_0 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
line.long 0x10 "GPIO2IE,GPIO2 Interrupt Mask Register"
|
|
bitfld.long 0x10 11. " MASK[11] ,Pin PIO2_11 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 10. " [10] ,Pin PIO2_10 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 9. " [9] ,Pin PIO2_9 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 8. " [8] ,Pin PIO2_8 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [7] ,Pin PIO2_7 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 6. " [6] ,Pin PIO2_6 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 5. " [5] ,Pin PIO2_5 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 4. " [4] ,Pin PIO2_4 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 3. " [3] ,Pin PIO2_3 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " [2] ,Pin PIO2_2 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 1. " [1] ,Pin PIO2_1 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " [0] ,Pin PIO2_0 interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x8014++0x07
|
|
line.long 0x00 "GPIO2RIS,GPIO2 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 11. " RAWST[11] ,Raw interrupt state on pin PIO2_11" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 10. " [10] ,Raw interrupt state on pin PIO2_10" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 9. " [9] ,Raw interrupt state on pin PIO2_9" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 8. " [8] ,Raw interrupt state on pin PIO2_8" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Raw interrupt state on pin PIO2_7" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 6. " [6] ,Raw interrupt state on pin PIO2_6" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 5. " [5] ,Raw interrupt state on pin PIO2_5" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 4. " [4] ,Raw interrupt state on pin PIO2_4" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Raw interrupt state on pin PIO2_3" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 2. " [2] ,Raw interrupt state on pin PIO2_2" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 1. " [1] ,Raw interrupt state on pin PIO2_1" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 0. " [0] ,Raw interrupt state on pin PIO2_0" "No interrupted,Interrupted"
|
|
line.long 0x04 "GPIO2MIS,GPIO2 Masked Interrupt Status Register"
|
|
bitfld.long 0x04 11. " MASK[11] ,Pin PIO2_11 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 10. " [10] ,Pin PIO2_10 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 9. " [9] ,Pin PIO2_9 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 8. " [8] ,Pin PIO2_8 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Pin PIO2_7 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 6. " [6] ,Pin PIO2_6 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 5. " [5] ,Pin PIO2_5 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 4. " [4] ,Pin PIO2_4 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Pin PIO2_3 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 2. " [2] ,Pin PIO2_2 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 1. " [1] ,Pin PIO2_1 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 0. " [0] ,Pin PIO2_0 interrupt mask" "No interrupted or masked,Interrupted"
|
|
wgroup.long 0x801C++0x03
|
|
line.long 0x00 "GPIO2IC,GPIO2 Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " CLR[11] ,Pin PIO2_11 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " [10] ,Pin PIO2_10 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " [9] ,Pin PIO2_9 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " [8] ,Pin PIO2_8 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin PIO2_7 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " [6] ,Pin PIO2_6 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " [5] ,Pin PIO2_5 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " [4] ,Pin PIO2_4 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Pin PIO2_3 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Pin PIO2_2 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Pin PIO2_1 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Pin PIO2_0 interrupt clear" "No effect,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO PORT 3"
|
|
base ad:0x50030000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO3DATA,GPIO3 Data Register"
|
|
bitfld.long 0x00 5. " DATA[5] ,PIO3_5 state" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,PIO3_4 state" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,PIO3_3 state" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,PIO3_2 state" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,PIO3_1 state" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,PIO3_0 state" "Low,High"
|
|
group.long 0x8000++0x13
|
|
line.long 0x00 "GPIO3DIR,GPIO3 Data Direction Register"
|
|
bitfld.long 0x00 5. " IO[5] ,PIO3_5 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,PIO3_4 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,PIO3_3 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,PIO3_2 input/output selection" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,PIO3_1 input/output selection" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,PIO3_0 input/output selection" "Input,Output"
|
|
line.long 0x04 "GPIO3IS,GPIO3 Interrupt Sense Register"
|
|
bitfld.long 0x04 5. " ISENSE[5] ,PIO3_5 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 4. " [4] ,PIO3_4 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 3. " [3] ,PIO3_3 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 2. " [2] ,PIO3_2 interrupt sense" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,PIO3_1 interrupt sense" "Edge,Level"
|
|
bitfld.long 0x04 0. " [0] ,PIO3_0 interrupt sense" "Edge,Level"
|
|
line.long 0x08 "GPIO3IBE,GPIO3 Interrupt Both Edges Sense Register"
|
|
bitfld.long 0x08 5. " IBE[5] ,Pin PIO3_5 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 4. " [4] ,Pin PIO3_4 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 3. " [3] ,Pin PIO3_3 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 2. " [2] ,Pin PIO3_2 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Pin PIO3_1 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
bitfld.long 0x08 0. " [0] ,Pin PIO3_0 interrupt triggered on both edges selection" "Controlled through GPIOIEV,On both edges"
|
|
line.long 0x0C "GPIO3IEV,GPIO3 Interrupt Event Register"
|
|
bitfld.long 0x0C 5. " IEV[5] ,Pin PIO3_5 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 4. " [4] ,Pin PIO3_4 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 3. " [3] ,Pin PIO3_3 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 2. " [2] ,Pin PIO3_2 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Pin PIO3_1 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
bitfld.long 0x0C 0. " [0] ,Pin PIO3_0 interrupt triggered by rising or falling edges selection" "Falling,Rising"
|
|
line.long 0x10 "GPIO3IE,GPIO3 Interrupt Mask Register"
|
|
bitfld.long 0x10 5. " MASK[5] ,Pin PIO3_5 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 4. " [4] ,Pin PIO3_4 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 3. " [3] ,Pin PIO3_3 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 2. " [2] ,Pin PIO3_2 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x10 1. " [1] ,Pin PIO3_1 interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x10 0. " [0] ,Pin PIO3_0 interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x8014++0x07
|
|
line.long 0x00 "GPIO3RIS,GPIO3 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 5. " RAWST[5] ,Raw interrupt state on pin PIO3_5" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 4. " [4] ,Raw interrupt state on pin PIO3_4" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 3. " [3] ,Raw interrupt state on pin PIO3_3" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 2. " [2] ,Raw interrupt state on pin PIO3_2" "No interrupted,Interrupted"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Raw interrupt state on pin PIO3_1" "No interrupted,Interrupted"
|
|
bitfld.long 0x00 0. " [0] ,Raw interrupt state on pin PIO3_0" "No interrupted,Interrupted"
|
|
line.long 0x04 "GPIO3MIS,GPIO3 Masked Interrupt Status Register"
|
|
bitfld.long 0x04 5. " MASK[5] ,Pin PIO3_5 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 4. " [4] ,Pin PIO3_4 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 3. " [3] ,Pin PIO3_3 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 2. " [2] ,Pin PIO3_2 interrupt mask" "No interrupted or masked,Interrupted"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Pin PIO3_1 interrupt mask" "No interrupted or masked,Interrupted"
|
|
bitfld.long 0x04 0. " [0] ,Pin PIO3_0 interrupt mask" "No interrupted or masked,Interrupted"
|
|
wgroup.long 0x801C++0x03
|
|
line.long 0x00 "GPIO3IC,GPIO3 Interrupt Clear Register"
|
|
bitfld.long 0x00 5. " CLR[5] ,Pin PIO3_5 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " [4] ,Pin PIO3_4 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " [3] ,Pin PIO3_3 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Pin PIO3_2 interrupt clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Pin PIO3_1 interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Pin PIO3_0 interrupt clear" "No effect,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
base ad:0x40008000
|
|
width 15.
|
|
if (((per.l(ad:0x40008000+0x0C))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register"
|
|
in
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of auto-baud interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
bitfld.long 0x00 2. " RXLIE ,RX line interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THREIE ,THRE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RBRIE ,RBR interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 3. " MSINTEN ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RLSINTEN ,Receive line status interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " THREINTEN ,THRE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RBRINTEN ,RBR interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,USART divisor latch LSB"
|
|
line.long 0x04 "DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLMSB ,USART divisor latch MSB"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt ID"
|
|
bitfld.long 0x00 9. " ABTOINT ,Auto-baud timeout interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " ABEOINT ,End of auto-baud interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6.--7. " FIFOEN ,FIFO enable" "0,1,2,3"
|
|
sif cpuis("LPC11C*")
|
|
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem interrupt,THRE,RDA,RLS,,,CTI,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem status,THRE,RDA,RLS,,,CTI,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0. " INTSTATUS ,Interrupt status" "Pending,Not pending"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTL ,Rx trigger level select" "Level 0,Level 1,Level 2,Level 3"
|
|
sif !cpuis("LPC11D14")&&!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11C*")
|
|
bitfld.long 0x00 3. " DMAMODE ,DMA mode enable" "Disable,Enable"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 2. " TXFIFORES ,Transmitter FIFO reset" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RXFIFORES ,Receiver FIFO reset" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FIFOEN ,FIFO enable" "Disable,Enable"
|
|
if (((per.l(ad:0x40008000+0x0C))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,USART0 Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Active,Inactive"
|
|
newline
|
|
bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Active,Inactive"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "LSR,Line Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "MSR,Modem Status Register"
|
|
in
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PAD ,A readable/writable byte"
|
|
line.long 0x04 "ACR,Auto-Baud Control Register"
|
|
bitfld.long 0x04 9. " ABTOINTCLR ,Auto-baud timeout interrupt clear bit" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " ABEOINTCLR ,End of auto-baud interrupt clear bit" "No effect,Cleared"
|
|
sif cpuis("LPC11C*")
|
|
bitfld.long 0x04 2. " AUTORESTART ,Automatic restart enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
|
|
else
|
|
bitfld.long 0x04 2. " AUTORESTART ,Start mode" "Not restarted,Restarted"
|
|
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 0. " START ,Auto-baud start" "Stopped,Started"
|
|
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICR,IrDA Control Register"
|
|
bitfld.long 0x00 3.--5. " PULSEDIV ,Pulse width configure" "3/(16*baud rate),2*Tpclk,4*Tpclk,8*Tpclk,16*Tpclk,32*Tpclk,64*Tpclk,128*Tpclk"
|
|
bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed pulse width mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRDAINV ,Serial input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " IRDAEN ,IrDA mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FDR,Fractional Divider Register"
|
|
bitfld.long 0x00 4.--7. " MULVAL ,Baud rate pre-scaler multiplier value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DIVADDVAL ,Baud rate pre-scaler divisor value" ",None,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
|
|
if (((per.l(ad:0x40008000+0x48))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "OSR,Oversampling Register"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "OSR,Oversampling Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
endif
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TER,Transmit Enable Register"
|
|
bitfld.long 0x00 7. " TXEN ,Transmission enable" "Disabled,Enabled"
|
|
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "HDEN,USART Half-Duplex Enable Register"
|
|
bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40008000+0x48))&0x04)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x4C++0x0B
|
|
line.long 0x00 "RS485CTRL,RS485 Control Register"
|
|
bitfld.long 0x00 5. " OINV ,Polarity control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto direction control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "RTS,DTR"
|
|
bitfld.long 0x00 2. " AADEN ,Auto address detect enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal multidrop mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "RS485ADRMATCH,RS485 Address Match Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x08 "RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DLY ,Direction control RTS or DTR delay value"
|
|
sif !cpuis("LPC11D14")&&!cpuis("LPC11C*")
|
|
if (((per.l(ad:0x40008000+0x58))&0x02)==0x02)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
|
|
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
|
|
newline
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
newline
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSP (Synchronous Serial Port)"
|
|
tree "SSP 0"
|
|
base ad:0x40040000
|
|
width 12.
|
|
if (((per.l(ad:0x40040000))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second"
|
|
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4bit,5bit,6bit,7bit,8bit,9bit,10bit,11bit,12bit,13bit,14bit,15bit,16bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP0CR0,SSP0 Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4bit,5bit,6bit,7bit,8bit,9bit,10bit,11bit,12bit,13bit,14bit,15bit,16bit"
|
|
endif
|
|
sif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")||cpuis("LPC11C*")
|
|
if (((per.l(ad:0x40040000+0x04))&0x06)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
elif (((per.l(ad:0x40040000+0x04))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
elif (((per.l(ad:0x40040000+0x04))&0x06)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
newline
|
|
rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40040000+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP0CR1,SSP0 Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP0DR,SSP0 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP0SR,SSP0 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
newline
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SSP0CPSR,SSP0 Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value"
|
|
line.long 0x04 "SSP0IMSC,SSP0 Interrupt Mask Set And Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,Tx FIFO half empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXIM ,Rx FIFO half full interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "SSP0RIS,SSP0 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive timeout raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "SSP0MIS,SSP0 Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,RX FIFO half full masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RTMIS ,Receive timeout masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full masked interrupt status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SSP0ICR,SSP0 Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Rx FIFO was not empty and has not been read for a timeout period interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Frame was received when RxFIFO was full interrupt clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSP 1"
|
|
base ad:0x40058000
|
|
width 12.
|
|
if (((per.l(ad:0x40058000))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP1CR0,SSP1 Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second"
|
|
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4bit,5bit,6bit,7bit,8bit,9bit,10bit,11bit,12bit,13bit,14bit,15bit,16bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSP1CR0,SSP1 Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4bit,5bit,6bit,7bit,8bit,9bit,10bit,11bit,12bit,13bit,14bit,15bit,16bit"
|
|
endif
|
|
sif cpuis("LPC111*")||cpuis("LPC11*LV")||cpuis("LPC110*")||cpuis("LPC112*")||cpuis("LPC11C*")
|
|
if (((per.l(ad:0x40058000+0x04))&0x06)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
elif (((per.l(ad:0x40058000+0x04))&0x06)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
elif (((per.l(ad:0x40058000+0x04))&0x06)==0x02)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
newline
|
|
rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal,Loopback"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40058000+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSP1CR1,SSP1 Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSP1DR,SSP1 Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSP1SR,SSP1 Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
newline
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SSP1CPSR,SSP1 Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value"
|
|
line.long 0x04 "SSP1IMSC,SSP1 Interrupt Mask Set And Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,Tx FIFO half empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXIM ,Rx FIFO half full interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "SSP1RIS,SSP1 Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive timeout raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full raw interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "SSP1MIS,SSP1 Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,RX FIFO half full masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RTMIS ,Receive timeout masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full masked interrupt status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SSP1ICR,SSP1 Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Rx FIFO was not empty and has not been read for a timeout period interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Frame was received when RxFIFO was full interrupt clear" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (I2C Bus Controller)"
|
|
base ad:0x40000000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C0CON,I2C0 Control Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_set/clr ,I2C interface enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_set/clr ,START flag" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stop"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_set/clr ,I2C interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_set/clr ,Assert acknowledge flag" "Not asserted,Asserted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "I2C0STAT,I2C0 Status Register"
|
|
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "Bus error/undefined,START transmitted,Repeated START transmitted,SLA+W transmitted/ACK,SLA+W transmitted/NOT ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Arbitration lost SLA+R/W/Data/NOT ACK,SLA+R transmitted/ACK,SLA+R transmitted/NOT ACK,Data received/ACK,Data received/NOT ACK,Own SLA+W received/ACK,Arbitration lost SLA+R/W/Own SLA+W received/ACK,GCA (0x00) received/ACK,Arbitration lost SLA+R/W/GCA received/ACK,Own SLV/DATA received/ACK,Own SLA/DATA received/NOT ACK,General Call/DATA received/ACK,General Call/DATA received/NOT ACK,STOP/repeated START received SLV/REC/SLV/TRX,Own SLA+R received/ACK,Arbitration lost SLA+R/W/Own SLA+R received/ACK,I2DAT transmitted/ACK,I2DAT transmitted/NOT ACK,Last I2DAT transmitted/ACK,,,,,,No information/SI = 0"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "I2C0DAT,I2C0 Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data that have been received or is to be transmitted"
|
|
line.long 0x04 "I2C0ADR0,I2C0 Slave Address Register"
|
|
hexmask.long.byte 0x04 1.--7. 0x2 " ADDRESS ,Slave mode address"
|
|
bitfld.long 0x04 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
line.long 0x08 "I2C0SCLH,I2C0 SCL High Duty Cycle Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL high time period selection"
|
|
line.long 0x0C "I2C0SCLL,I2C0 SCL Low Duty Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SCLL ,Count for SCL low time period selection"
|
|
if (((per.l(ad:0x40000000+0x1C))&0x01)==0x01)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C0MMCTRL,I2C0 Monitor Mode Control Register"
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C0MMCTRL,I2C0 Monitor Mode Control Register"
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "No effect,No effect"
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "No effect,No effect"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C0ADR1,I2C0 Slave Address Register 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C0ADR2,I2C0 Slave Address Register 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C0ADR3,I2C0 Slave Address Register 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "I2C0DATA_BUFFER,I2C0 Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Content of the DAT shift register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "I2C0MASK0,I2C0 Mask Register 0"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "I2C0MASK1,I2C0 Mask Register 1"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "I2C0MASK2,I2C0 Mask Register 2"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C0MASK3,I2C0 Mask Register 3"
|
|
bitfld.long 0x00 7. " MASK[7:0] ,Mask bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Mask bit 6" "0,1"
|
|
bitfld.long 0x00 4. ",Mask bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Mask bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Mask bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Mask bit 1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CT16B (16-bit counter/timer)"
|
|
tree "CT16B0"
|
|
base ad:0x4000C000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TMR16B0IR,CT16B0 Interrupt Register"
|
|
sif cpuis("LPC11*LV")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
elif cpuis("LPC112*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
eventfld.long 0x00 4. " CR0 ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 3. " MR[3] ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 0. " [0] ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TMR16B0TCR,CT16B0 Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Not reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TMR16B0TC,CT16B0 Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "TMR16B0PR,CT16B0 Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PR ,Prescale max value"
|
|
line.long 0x08 "TMR16B0PC,CT16B0 Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TMR16B0MCR,CT16B0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "TMR16B0MR0,CT16B0 Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "TMR16B0MR1,CT16B0 Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "TMR16B0MR2,CT16B0 Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "TMR16B0MR3,CT16B0 Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TMR16B0CCR,CT16B0 Capture Control Register"
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B(1)_CAP1 rising edge" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B0_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B0_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B0_CAP0 rising edge" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR16B0CR0,CT16B0 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TMR16B0EMR,CT16B0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
if (((per.l(ad:0x4000C000+0x70))&0x03)==0x00)&&(((per.l(ad:0x4000C000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x4000C000+0x70))&0x03)==0x00)&&(((per.l(ad:0x4000C000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x4000C000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x4000C000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x4000C000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x4000C000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000C000+0x70))&0x03)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B0CTCR,CT16B0 Count Control Register"
|
|
sif cpuis("LPC11C*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TMR16B0PWMC,CT16B0 PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN3 ,PWM channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWMEN2 ,PWM channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMEN1 ,PWM channel 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PWMEN0 ,PWM channel 0 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CT16B1"
|
|
base ad:0x40010000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TMR16B1IR,CT16B1 Interrupt Register"
|
|
sif cpuis("LPC11*LV")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
elif cpuis("LPC112*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
eventfld.long 0x00 4. " CR0 ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 3. " MR[3] ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 0. " [0] ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TMR16B1TCR,CT16B1 Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Not reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TMR16B1TC,CT16B1 Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "TMR16B1PR,CT16B1 Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PR ,Prescale max value"
|
|
line.long 0x08 "TMR16B1PC,CT16B1 Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TMR16B1MCR,CT16B1 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "TMR16B1MR0,CT16B1 Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "TMR16B1MR1,CT16B1 Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "TMR16B1MR2,CT16B1 Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "TMR16B1MR3,CT16B1 Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TMR16B1CCR,CT16B1 Capture Control Register"
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT16B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT16B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT16B(1)_CAP1 rising edge" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT16B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT16B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT16B1_CAP0 rising edge" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR16B1CR0,CT16B1 Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TMR16B1EMR,CT16B1 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
if (((per.l(ad:0x40010000+0x70))&0x03)==0x00)&&(((per.l(ad:0x40010000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40010000+0x70))&0x03)==0x00)&&(((per.l(ad:0x40010000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40010000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x40010000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40010000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x40010000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0x70))&0x03)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR16B1CTCR,CT16B1 Count Control Register"
|
|
sif cpuis("LPC11C*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TMR16B1PWMC,CT16B1 PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN3 ,PWM channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWMEN2 ,PWM channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMEN1 ,PWM channel 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PWMEN0 ,PWM channel 0 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "CT32B (32-bit counter/timer)"
|
|
tree "CT32B0"
|
|
base ad:0x40014000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TMR32B0IR,CT32B0 Interrupt Register"
|
|
sif cpuis("LPC11*LV")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
elif cpuis("LPC112*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
eventfld.long 0x00 4. " CR0 ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 3. " MR[3] ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 0. " [0] ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TMR32B0TCR,CT32B0 Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Not reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TMR32B0TC,CT32B0 Timer Counter Register"
|
|
line.long 0x04 "TMR32B0PR,CT32B0 Prescale Register"
|
|
line.long 0x08 "TMR32B0PC,CT32B0 Prescale Counter Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TMR32B0MCR,CT32B0 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "TMR32B0MR0,CT32B0 Match Register 0"
|
|
line.long 0x04 "TMR32B0MR1,CT32B0 Match Register 1"
|
|
line.long 0x08 "TMR32B0MR2,CT32B0 Match Register 2"
|
|
line.long 0x0C "TMR32B0MR3,CT32B0 Match Register 3"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TMR32B0CCR,CT32B0 Capture Control Register"
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B0_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B0_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B(1)_CAP1 rising edge" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B0_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B0_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B0_CAP0 rising edge" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR32B0CR0,CT32B0 Capture Register 0"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TMR32B0EMR,CT32B0 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
if (((per.l(ad:0x40014000+0x70))&0x03)==0x00)&&(((per.l(ad:0x40014000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40014000+0x70))&0x03)==0x00)&&(((per.l(ad:0x40014000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40014000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x40014000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40014000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x40014000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x70))&0x03)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B0CTCR,CT32B0 Count Control Register"
|
|
sif cpuis("LPC11C*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TMR32B0PWMC,CT32B0 PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN3 ,PWM channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWMEN2 ,PWM channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMEN1 ,PWM channel 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PWMEN0 ,PWM channel 0 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CT32B1"
|
|
base ad:0x40018000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TMR32B1IR,CT32B1 Interrupt Register"
|
|
sif cpuis("LPC11*LV")
|
|
eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
elif cpuis("LPC112*")
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
eventfld.long 0x00 4. " CR0 ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 3. " MR[3] ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 0. " [0] ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TMR32B1TCR,CT32B1 Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Not reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TMR32B1TC,CT32B1 Timer Counter Register"
|
|
line.long 0x04 "TMR32B1PR,CT32B1 Prescale Register"
|
|
line.long 0x08 "TMR32B1PC,CT32B1 Prescale Counter Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TMR32B1MCR,CT32B1 Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "TMR32B1MR0,CT32B1 Match Register 0"
|
|
line.long 0x04 "TMR32B1MR1,CT32B1 Match Register 1"
|
|
line.long 0x08 "TMR32B1MR2,CT32B1 Match Register 2"
|
|
line.long 0x0C "TMR32B1MR3,CT32B1 Match Register 3"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TMR32B1CCR,CT32B1 Capture Control Register"
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
bitfld.long 0x00 5. " CAP1I ,Interrupt on CT32B1_CAP1 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Capture on CT32B1_CAP1 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CAP1RE ,Capture on CT32B(1)_CAP1 rising edge" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " CAP0I ,Interrupt on CT32B1_CAP0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Capture on CT32B1_CAP0 falling edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Capture on CT32B1_CAP0 rising edge" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TMR32B1CR0,CT32B1 Capture Register 0"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TMR32B1EMR,CT32B1 External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC3 ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " EMC2 ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " EMC1 ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " EMC0 ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM3 ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " EM2 ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " EM1 ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " EM0 ,External match 0" "Low,High"
|
|
sif !cpuis("LPC1102")&&!cpuis("LPC1104")
|
|
sif cpuis("LPC112*")||cpuis("LPC11*LV")
|
|
if (((per.l(ad:0x40018000+0x70))&0x03)==0x00)&&(((per.l(ad:0x40018000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40018000+0x70))&0x03)==0x00)&&(((per.l(ad:0x40018000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40018000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x40018000+0x70))&0x10)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
elif (((per.l(ad:0x40018000+0x70))&0x03)!=0x00)&&(((per.l(ad:0x40018000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Selects which capture input cause clear" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " ENCC ,Timer clearing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40018000+0x70))&0x03)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TMR32B1CTCR,CT32B1 Count Control Register"
|
|
sif cpuis("LPC11C*")
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TMR32B1PWMC,CT32B1 PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN3 ,PWM channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWMEN2 ,PWM channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWMEN1 ,PWM channel 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PWMEN0 ,PWM channel 0 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (WatchDog Timer)"
|
|
base ad:0x40004000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WDMOD,Watchdog Mode Register"
|
|
rbitfld.long 0x00 3. " WDINT ,Watchdog interrupt flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 2. " WDTOF ,Watchdog time-out flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "WDTC,Watchdog Timer Constant Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out interval"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WDFEED,Watchdog Feed Sequence Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WDTV,Watchdog Timer Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x4001C000
|
|
width 10.
|
|
if (((per.l(ad:0x4001C000)&0x07000000)==0x00))||(((per.l(ad:0x4001C000)&0x07000000)==0x01000000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,A/D Control Register"
|
|
newline
|
|
sif cpuis("LPC1102")||cpuis("LPC1104")
|
|
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,,,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on CT16B0_CAP0,Edge on CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
|
|
endif
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
bitfld.long 0x00 16. " BURST ,Conversion control mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider"
|
|
newline
|
|
sif cpuis("LPC1102")||cpuis("LPC1104")
|
|
bitfld.long 0x00 4. " SEL[4] ,AD4 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start conversion edge" "Rising,Falling"
|
|
newline
|
|
sif cpuis("LPC1102")||cpuis("LPC1104")
|
|
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,,,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
|
|
else
|
|
bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on CT16B0_CAP0,Edge on CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1"
|
|
endif
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
bitfld.long 0x00 16. " BURST ,Conversion control mode" "Software,Repeated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider"
|
|
newline
|
|
sif cpuis("LPC1102")||cpuis("LPC1104")
|
|
bitfld.long 0x00 4. " SEL[4] ,AD4 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
|
|
else
|
|
bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,AD2 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
|
|
endif
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "GDR,A/D Global Data Register"
|
|
in
|
|
newline
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " ADGINTEN ,Source of generated interrupt" "Individual,Global"
|
|
newline
|
|
sif cpuis("LPC1102")||cpuis("LPC1104")
|
|
bitfld.long 0x00 4. " ADINTEN[4] ,Channel 4 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 conversion completion interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 conversion completion interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " ADINTEN[7] ,Channel 7 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 conversion completion interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 conversion completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 conversion completion interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "DR0,A/D Channel 0 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "DR1,A/D Channel 1 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "DR2,A/D Channel 2 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DR3,A/D Channel 3 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR4,A/D Channel 4 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DR5,A/D Channel 5 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "DR6,A/D Channel 6 Data Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DR7,A/D Channel 7 Data Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "STAT,A/D Status Register"
|
|
bitfld.long 0x00 16. " ADINT ,A/D interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("LPC1102")||cpuis("LPC1104")
|
|
bitfld.long 0x00 12. " OVERRUN[4] ,Mirrors OVERRUN status flag for channel 4" "No overrun,Overrun"
|
|
bitfld.long 0x00 11. " [3] ,Mirrors OVERRUN status flag for channel 3" "No overrun,Overrun"
|
|
bitfld.long 0x00 10. " [2] ,Mirrors OVERRUN status flag for channel 2" "No overrun,Overrun"
|
|
bitfld.long 0x00 9. " [1] ,Mirrors OVERRUN status flag for channel 1" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 8. " [0] ,Mirrors OVERRUN status flag for channel 0" "No overrun,Overrun"
|
|
bitfld.long 0x00 4. " DONE[4] ,Mirrors DONE status flag for channel 4" "Not done,Done"
|
|
bitfld.long 0x00 3. " [3] ,Mirrors DONE status flag for channel 3" "Not done,Done"
|
|
bitfld.long 0x00 2. " [2] ,Mirrors DONE status flag for channel 2" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Mirrors DONE status flag for channel 1" "Not done,Done"
|
|
bitfld.long 0x00 0. " [0] ,Mirrors DONE status flag for channel 0" "Not done,Done"
|
|
else
|
|
bitfld.long 0x00 15. " OVERRUN[7] ,Mirrors OVERRUN status flag for channel 7" "No overrun,Overrun"
|
|
bitfld.long 0x00 14. " [6] ,Mirrors OVERRUN status flag for channel 6" "No overrun,Overrun"
|
|
bitfld.long 0x00 13. " [5] ,Mirrors OVERRUN status flag for channel 5" "No overrun,Overrun"
|
|
bitfld.long 0x00 12. " [4] ,Mirrors OVERRUN status flag for channel 4" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,Mirrors OVERRUN status flag for channel 3" "No overrun,Overrun"
|
|
bitfld.long 0x00 10. " [2] ,Mirrors OVERRUN status flag for channel 2" "No overrun,Overrun"
|
|
bitfld.long 0x00 9. " [1] ,Mirrors OVERRUN status flag for channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x00 8. " [0] ,Mirrors OVERRUN status flag for channel 0" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 7. " DONE[7] ,Mirrors DONE status flag for channel 7" "Not done,Done"
|
|
bitfld.long 0x00 6. " [6] ,Mirrors DONE status flag for channel 6" "Not done,Done"
|
|
bitfld.long 0x00 5. " [5] ,Mirrors DONE status flag for channel 5" "Not done,Done"
|
|
bitfld.long 0x00 4. " [4] ,Mirrors DONE status flag for channel 4" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Mirrors DONE status flag for channel 3" "Not done,Done"
|
|
bitfld.long 0x00 2. " [2] ,Mirrors DONE status flag for channel 2" "Not done,Done"
|
|
bitfld.long 0x00 1. " [1] ,Mirrors DONE status flag for channel 1" "Not done,Done"
|
|
bitfld.long 0x00 0. " [0] ,Mirrors DONE status flag for channel 0" "Not done,Done"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
newline
|