3357 lines
208 KiB
Plaintext
3357 lines
208 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC11Axx On-Chip Peripherals
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; @Props: Released
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; @Author: MKO, KOP
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; @Changelog: 2018-10-24 KOP
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: LPC11Axx.svd
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; LPC11Axx_DS.pdf (Rev. 4 2012-10-30)
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; LPC11Axx_UM10527.pdf (Rev. 5 2013-01-21)
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; @Core: Cortex-M0
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; @Chip: LPC11A02, LPC11A04, LPC11A11, LPC11A12, LPC11A13, LPC11A14
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perlpc11axx.per 9960 2018-12-04 14:30:37Z mkolodziejczyk $
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config 16. 8.
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "System Configuration"
|
|
base ad:0x40048000
|
|
width 15.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SYSMEMREMAP,System Memory Remap Register"
|
|
bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader,User RAM,User Flash,?..."
|
|
line.long 0x04 "PRESETCTRL,Peripheral Reset Control Register"
|
|
bitfld.long 0x04 11. " ADC_RST_N ,ADC reset control" "Reset,No reset"
|
|
bitfld.long 0x04 10. " DAC_RST_N ,DAC reset control" "Reset,No reset"
|
|
bitfld.long 0x04 9. " ACOMP_RST_N ,Analog comparator reset control" "Reset,No reset"
|
|
newline
|
|
bitfld.long 0x04 8. " CT32B1_RST_N ,CT32B1 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 7. " CT32B0_RST_N ,CT32B0 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 6. " CT16B1_RST_N ,CT16B1 reset control" "Reset,No reset"
|
|
newline
|
|
bitfld.long 0x04 5. " CT16B0_RST_N ,CT16B0 reset control" "Reset,No reset"
|
|
bitfld.long 0x04 4. " UART_RST_N ,UART reset control" "Reset,No reset"
|
|
bitfld.long 0x04 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset"
|
|
newline
|
|
bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset"
|
|
bitfld.long 0x04 0. " SSP0_RST_N ,SSP reset control" "Reset,No reset"
|
|
line.long 0x08 "SYSPLLCTRL,System PLL Control Register"
|
|
bitfld.long 0x08 5.--6. " PSEL ,Post divider ratio" "1,2,4,8"
|
|
bitfld.long 0x08 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SYSPLLSTAT,System PLL Status Register"
|
|
bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register"
|
|
bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator enable" "Disabled,Enabled"
|
|
line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register"
|
|
bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency" ",0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz"
|
|
bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
line.long 0x08 "IRCCTRL,High-Frequency Oscillator Control Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TRIM ,Trim value"
|
|
line.long 0x0C "LFOSCCTRL,LF Oscillator Control Register"
|
|
bitfld.long 0x0C 5.--8. " FREQSEL ,Select watchdog oscillator analog output frequency" ",0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz"
|
|
bitfld.long 0x0C 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
line.long 0x10 "SYSRSTSTAT,System Reset Status Register"
|
|
eventfld.long 0x10 4. " SYSRST ,Software system reset" "No reset,Reset"
|
|
eventfld.long 0x10 3. " BOD ,Brown-out detect reset" "No reset,Reset"
|
|
eventfld.long 0x10 2. " WDT ,Watchdog reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x10 1. " EXTRST ,External reset" "No reset,Reset"
|
|
eventfld.long 0x10 0. " POR ,POR reset" "No reset,Reset"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC,XTAL,CLKIN,?..."
|
|
line.long 0x04 "SYSPLLCLKUEN,System PLL Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,System PLL clock source update enable" "Disabled,Enabled"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC,PLL input,LF,PLL output"
|
|
line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled"
|
|
line.long 0x08 "SYSAHBCLKDIV,System AHB Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SYSAHBCLKCTRL,System AHB Clock Control Register"
|
|
bitfld.long 0x00 24. " P1INT ,GPIO Port 1 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " P0INT ,GPIO Port 0 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DAC ,Enables clock for DAC" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " ACOMP ,Enables clock for ACOMP" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PINT ,GPIO Pin interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WDT ,Clock for WDT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ADC ,Clock for ADC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " USART ,Clock for UART enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSP0 ,Clock for SSP0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CT32B1 ,Clock for 32-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " CT32B0 ,Clock for 32-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CT16B1 ,Clock for 16-bit counter/timer 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CT16B0 ,Clock for 16-bit counter/timer 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " GPIO ,Clock for GPIO enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " I2C ,Clock for I2C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FLASHARRAY ,Clock for flash array access enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FLASHREG ,Clock for flash register interface enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RAM ,Clock for RAM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 0. " SYS ,Clock for AHB/APB bridge/Cortex-M0 FCLK and HCLK/SysCon/PMU" ",Enabled"
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "SSP0,SSP0 Clock Divider Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIV ,UART_PCLK clock divider values"
|
|
line.long 0x04 "UARTCLKDIV,UART Clock Divider Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DIV ,SSP0_PCLK clock divider values "
|
|
line.long 0x08 "SSP1CLKDIV,SPI1 Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,SSP1_PCLK clock divider values"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register"
|
|
bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC,XTAL,LF,Main clock"
|
|
line.long 0x04 "CLKOUTUEN,CLKOUT Clock Source Update Enable Register"
|
|
bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled"
|
|
line.long 0x08 "CLKOUTDIV,CLKOUT Clock Divider Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0"
|
|
bitfld.long 0x00 31. " PIOSTAT[31] ,State of PIO0_31 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,State of PIO0_31 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,State of PIO0_29 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,State of PIO0_28 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,State of PIO0_27 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,State of PIO0_26 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,State of PIO0_25 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,State of PIO0_24 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,State of PIO0_23 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,State of PIO0_22 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,State of PIO0_21 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,State of PIO0_20 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,State of PIO0_19 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,State of PIO0_18 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,State of PIO0_17 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,State of PIO0_16 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,State of PIO0_15 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,State of PIO0_14 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,State of PIO0_13 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,State of PIO0_12 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,State of PIO0_11 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,State of PIO0_10 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,State of PIO0_9 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,State of PIO0_8 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,State of PIO0_7 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,State of PIO0_6 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,State of PIO0_5 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,State of PIO0_4 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,State of PIO0_3 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,State of PIO0_2 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,State of PIO0_1 at power-on-reset" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,State of PIO0_0 at power-on-reset" "Low,High"
|
|
line.long 0x04 "PIOPORCAP1,POR Captured PIO Status Register 1"
|
|
bitfld.long 0x04 9. " PIOSTAT[9] ,State of PIO1_9 at power-on-reset" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,State of PIO1_8 at power-on-reset" "Low,High"
|
|
bitfld.long 0x04 7. " [7] ,State of PIO1_7 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,State of PIO1_6 at power-on-reset" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,State of PIO1_5 at power-on-reset" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,State of PIO1_4 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,State of PIO1_3 at power-on-reset" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,State of PIO1_2 at power-on-reset" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,State of PIO1_1 at power-on-reset" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,State of PIO1_0 at power-on-reset" "Low,High"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BODR,Brown-Out Detect Register"
|
|
bitfld.long 0x00 6. " BODINT ,BOD interrupt request" "Not requested,Requested"
|
|
bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt threshold" ",,2.52V/2.66V,2.80V/2.90V"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "SYSTCKCAL,System Tick Timer Calibration Register"
|
|
hexmask.long 0x00 0.--25. 1. " CAL ,System tick timer calibration value"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "NMISRC,NMI Source Selection Register"
|
|
bitfld.long 0x00 31. " NMIEN ,Non-maskable Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " IRQNO ,IRQ number of the interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "PINTSEL0,Pin Interrupt Select Register 0"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PINTSEL1,Pin Interrupt Select Register 1"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "PINTSEL2,Pin Interrupt Select Register 2"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "PINTSEL3,Pin Interrupt Select Register 3"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PINTSEL4,Pin Interrupt Select Register 4"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "PINTSEL5,Pin Interrupt Select Register 5"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "PINTSEL6,Pin Interrupt Select Register 6"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "PINTSEL7,Pin Interrupt Select Register 7"
|
|
bitfld.long 0x00 5. " INTPORT ,Select port" "P0,P1"
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number within the port identified by the INTPORT field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "PDRUNCFG,Power Configuration Register"
|
|
bitfld.long 0x00 16. " ACOMP_PD ,Analog Comparator power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 15. " TS_PD ,Temperature Sensor power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 14. " DAC_PD ,DAC power-down" "Powered,Powered down"
|
|
newline
|
|
bitfld.long 0x00 13. " LFOSC_PD ,Low frequency oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down"
|
|
newline
|
|
bitfld.long 0x00 5. " XTAL_PD ,Crystal oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 4. " ADC_PD ,ADC power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 2. " FLASH_PD ,Flash power-down" "Powered,Powered down"
|
|
newline
|
|
bitfld.long 0x00 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down"
|
|
bitfld.long 0x00 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down"
|
|
rgroup.long 0x3F4++0x03
|
|
line.long 0x00 "DEVICE_ID,Device ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " DEVICEID ,Device ID"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x4004C000
|
|
width 6.
|
|
tree "GPIO Pin Interrupts Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "ISEL,Pin Interrupt Mode register"
|
|
bitfld.long 0x00 7. " PMODE[7] ,PINTSEL7 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 6. " [6] ,PINTSEL6 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 5. " [5] ,PINTSEL5 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,PINTSEL4 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 3. " [3] ,PINTSEL3 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 2. " [2] ,PINTSEL2 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,PINTSEL1 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
bitfld.long 0x00 0. " [0] ,PINTSEL0 interrupt edge/level sensitive configuration" "Edge,Level"
|
|
line.long 0x04 "IENR,Pin Interrupt Enable (Rising) register"
|
|
setclrfld.long 0x04 7. 0x08 7. 0x0C 7. " IENR[7]_set/clr ,Rising edge or level interrupt for pin 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x08 6. 0x0C 6. " [6]_set/clr ,Rising edge or level interrupt for pin 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x0C 5. " [5]_set/clr ,Rising edge or level interrupt for pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 4. 0x08 4. 0x0C 4. " [4]_set/clr ,Rising edge or level interrupt for pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x0C 3. " [3]_set/clr ,Rising edge or level interrupt for pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0C 2. " [2]_set/clr ,Rising edge or level interrupt for pin 2 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " [1]_set/clr ,Rising edge or level interrupt for pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " [0]_set/clr ,Rising edge or level interrupt for pin 0 enable" "Disabled,Enabled"
|
|
line.long 0x10 "IENF,Pin Interrupt Active Level (Falling Edge) Interrupt Enable Register"
|
|
setclrfld.long 0x10 7. 0x14 7. 0x18 7. " IENF[7]_set/clr ,Falling edge or configures the active level interrupt for 7 enable" "Low,High"
|
|
setclrfld.long 0x10 6. 0x14 6. 0x18 6. " [6]_set/clr ,Falling edge or configures the active level interrupt for 6 enable" "Low,High"
|
|
setclrfld.long 0x10 5. 0x14 5. 0x18 5. " [5]_set/clr ,Falling edge or configures the active level interrupt for 5 enable" "Low,High"
|
|
newline
|
|
setclrfld.long 0x10 4. 0x14 4. 0x18 4. " [4]_set/clr ,Falling edge or configures the active level interrupt for 4 enable" "Low,High"
|
|
setclrfld.long 0x10 3. 0x14 3. 0x18 3. " [3]_set/clr ,Falling edge or configures the active level interrupt for 3 enable" "Low,High"
|
|
setclrfld.long 0x10 2. 0x14 2. 0x18 2. " [2]_set/clr ,Falling edge or configures the active level interrupt for 2 enable" "Low,High"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x14 1. 0x18 1. " [1]_set/clr ,Falling edge or configures the active level interrupt for 1 enable" "Low,High"
|
|
setclrfld.long 0x10 0. 0x14 0. 0x18 0. " [0]_set/clr ,Falling edge or configures the active level interrupt for 0 enable" "Low,High"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "RISE,Pin Interrupt Rising Edge Register"
|
|
eventfld.long 0x00 7. " RDET[7] ,PINTSEL7 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 6. " [6] ,PINTSEL6 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " [5] ,PINTSEL5 rising edge detect" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,PINTSEL4 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 3. " [3] ,PINTSEL3 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 2. " [2] ,PINTSEL2 rising edge detect" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,PINTSEL1 rising edge detect" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " [0] ,PINTSEL0 rising edge detect" "Not detected,Detected"
|
|
line.long 0x04 "FALL,Pin Interrupt Falling Edge Register"
|
|
eventfld.long 0x04 7. " FDET[7] ,PINTSEL7 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 6. " [6] ,PINTSEL6 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 5. " [5] ,PINTSEL5 falling edge detect" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 4. " [4] ,PINTSEL4 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 3. " [3] ,PINTSEL3 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 2. " [2] ,PINTSEL2 falling edge detect" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 1. " [1] ,PINTSEL1 falling edge detect" "Not detected,Detected"
|
|
eventfld.long 0x04 0. " [0] ,PINTSEL0 falling edge detect" "Not detected,Detected"
|
|
line.long 0x08 "IST,Pin Interrupt Status Register"
|
|
eventfld.long 0x08 7. " PSTAT[7] ,PINTSEL7 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 6. " [6] ,PINTSEL6 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 5. " [5] ,PINTSEL5 interrupt status" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x08 4. " [4] ,PINTSEL4 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 3. " [3] ,PINTSEL3 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 2. " [2] ,PINTSEL2 interrupt status" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x08 1. " [1] ,PINTSEL1 interrupt status" "Not requested,Requested"
|
|
eventfld.long 0x08 0. " [0] ,PINTSEL0 interrupt status" "Not requested,Requested"
|
|
tree.end
|
|
width 11.
|
|
tree "GPIO GROUP0 Interrupt Registers"
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "CTRL,Grouped Interrupt Control Register"
|
|
bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level"
|
|
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND"
|
|
bitfld.long 0x00 0. " INT ,Group interrupt status" "No interrupt,Interrupt"
|
|
group.long (0x10000+0x20)++0x07
|
|
line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity Register"
|
|
bitfld.long 0x00 31. " POL0[31] ,Pin polarity of PIO0_31 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin polarity of PIO0_30 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin polarity of PIO0_29 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Pin polarity of PIO0_28 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin polarity of PIO0_27 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin polarity of PIO0_26 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin polarity of PIO0_25 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin polarity of PIO0_24 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin polarity of PIO0_23 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin polarity of PIO0_22 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin polarity of PIO0_21 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin polarity of PIO0_20 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin polarity of PIO0_19 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin polarity of PIO0_18 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin polarity of PIO0_17 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Pin polarity of PIO0_16 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin polarity of PIO0_15 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin polarity of PIO0_14 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin polarity of PIO0_13 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin polarity of PIO0_12 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin polarity of PIO0_11 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Pin polarity of PIO0_10 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin polarity of PIO0_9 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin polarity of PIO0_8 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin polarity of PIO0_7 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin polarity of PIO0_6 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin polarity of PIO0_5 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin polarity of PIO0_4 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin polarity of PIO0_3 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin polarity of PIO0_2 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Pin polarity of PIO0_1 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin polarity of PIO0_0 for group interrupt configuration" "Low,High"
|
|
line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity Register"
|
|
bitfld.long 0x00 31. " POL1[31] ,Pin polarity of PIO1_31 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin polarity of PIO1_30 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin polarity of PIO1_29 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Pin polarity of PIO1_28 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin polarity of PIO1_27 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin polarity of PIO1_26 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin polarity of PIO1_25 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin polarity of PIO1_24 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin polarity of PIO1_23 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin polarity of PIO1_22 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin polarity of PIO1_21 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin polarity of PIO1_20 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin polarity of PIO1_19 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin polarity of PIO1_18 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin polarity of PIO1_17 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Pin polarity of PIO1_16 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin polarity of PIO1_15 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin polarity of PIO1_14 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin polarity of PIO1_13 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin polarity of PIO1_12 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin polarity of PIO1_11 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Pin polarity of PIO1_10 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin polarity of PIO1_9 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin polarity of PIO1_8 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin polarity of PIO1_7 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin polarity of PIO1_6 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin polarity of PIO1_5 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin polarity of PIO1_4 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin polarity of PIO1_3 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin polarity of PIO1_2 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Pin polarity of PIO1_1 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin polarity of PIO1_0 for group interrupt configuration" "Low,High"
|
|
group.long (0x10000+0x40)++0x07
|
|
line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register"
|
|
bitfld.long 0x00 31. " ENA0[31] ,Group interrupt for pin PIO0_31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Group interrupt for pin PIO0_30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Group interrupt for pin PIO0_29 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Group interrupt for pin PIO0_28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Group interrupt for pin PIO0_27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Group interrupt for pin PIO0_26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Group interrupt for pin PIO0_25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Group interrupt for pin PIO0_24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Group interrupt for pin PIO0_23 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Group interrupt for pin PIO0_22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Group interrupt for pin PIO0_21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Group interrupt for pin PIO0_20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Group interrupt for pin PIO0_19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Group interrupt for pin PIO0_18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Group interrupt for pin PIO0_17 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Group interrupt for pin PIO0_16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Group interrupt for pin PIO0_15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Group interrupt for pin PIO0_14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Group interrupt for pin PIO0_13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Group interrupt for pin PIO0_12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Group interrupt for pin PIO0_11 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Group interrupt for pin PIO0_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Group interrupt for pin PIO0_9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Group interrupt for pin PIO0_8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Group interrupt for pin PIO0_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Group interrupt for pin PIO0_6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Group interrupt for pin PIO0_5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Group interrupt for pin PIO0_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Group interrupt for pin PIO0_3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Group interrupt for pin PIO0_2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Group interrupt for pin PIO0_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Group interrupt for pin PIO0_0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register"
|
|
bitfld.long 0x00 31. " ENA1[31] ,Group interrupt for pin PIO1_31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Group interrupt for pin PIO1_30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Group interrupt for pin PIO1_29 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Group interrupt for pin PIO1_28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Group interrupt for pin PIO1_27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Group interrupt for pin PIO1_26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Group interrupt for pin PIO1_25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Group interrupt for pin PIO1_24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Group interrupt for pin PIO1_23 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Group interrupt for pin PIO1_22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Group interrupt for pin PIO1_21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Group interrupt for pin PIO1_20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Group interrupt for pin PIO1_19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Group interrupt for pin PIO1_18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Group interrupt for pin PIO1_17 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Group interrupt for pin PIO1_16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Group interrupt for pin PIO1_15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Group interrupt for pin PIO1_14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Group interrupt for pin PIO1_13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Group interrupt for pin PIO1_12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Group interrupt for pin PIO1_11 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Group interrupt for pin PIO1_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Group interrupt for pin PIO1_9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Group interrupt for pin PIO1_8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Group interrupt for pin PIO1_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Group interrupt for pin PIO1_6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Group interrupt for pin PIO1_5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Group interrupt for pin PIO1_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Group interrupt for pin PIO1_3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Group interrupt for pin PIO1_2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Group interrupt for pin PIO1_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Group interrupt for pin PIO1_0 enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "GPIO GROUP1 Interrupt Registers"
|
|
group.long 0x14000++0x03
|
|
line.long 0x00 "CTRL,Grouped Interrupt Control Register"
|
|
bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level"
|
|
bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND"
|
|
bitfld.long 0x00 0. " INT ,Group interrupt status" "No interrupt,Interrupt"
|
|
group.long (0x14000+0x20)++0x07
|
|
line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity Register"
|
|
bitfld.long 0x00 31. " POL0[31] ,Pin polarity of PIO0_31 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin polarity of PIO0_30 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin polarity of PIO0_29 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Pin polarity of PIO0_28 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin polarity of PIO0_27 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin polarity of PIO0_26 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin polarity of PIO0_25 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin polarity of PIO0_24 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin polarity of PIO0_23 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin polarity of PIO0_22 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin polarity of PIO0_21 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin polarity of PIO0_20 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin polarity of PIO0_19 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin polarity of PIO0_18 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin polarity of PIO0_17 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Pin polarity of PIO0_16 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin polarity of PIO0_15 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin polarity of PIO0_14 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin polarity of PIO0_13 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin polarity of PIO0_12 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin polarity of PIO0_11 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Pin polarity of PIO0_10 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin polarity of PIO0_9 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin polarity of PIO0_8 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin polarity of PIO0_7 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin polarity of PIO0_6 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin polarity of PIO0_5 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin polarity of PIO0_4 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin polarity of PIO0_3 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin polarity of PIO0_2 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Pin polarity of PIO0_1 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin polarity of PIO0_0 for group interrupt configuration" "Low,High"
|
|
line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity Register"
|
|
bitfld.long 0x00 31. " POL1[31] ,Pin polarity of PIO1_31 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin polarity of PIO1_30 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin polarity of PIO1_29 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Pin polarity of PIO1_28 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin polarity of PIO1_27 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin polarity of PIO1_26 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin polarity of PIO1_25 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin polarity of PIO1_24 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin polarity of PIO1_23 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin polarity of PIO1_22 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin polarity of PIO1_21 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin polarity of PIO1_20 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin polarity of PIO1_19 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin polarity of PIO1_18 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin polarity of PIO1_17 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Pin polarity of PIO1_16 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin polarity of PIO1_15 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin polarity of PIO1_14 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin polarity of PIO1_13 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin polarity of PIO1_12 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin polarity of PIO1_11 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Pin polarity of PIO1_10 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Pin polarity of PIO1_9 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin polarity of PIO1_8 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Pin polarity of PIO1_7 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin polarity of PIO1_6 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin polarity of PIO1_5 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin polarity of PIO1_4 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin polarity of PIO1_3 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin polarity of PIO1_2 for group interrupt configuration" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Pin polarity of PIO1_1 for group interrupt configuration" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin polarity of PIO1_0 for group interrupt configuration" "Low,High"
|
|
group.long (0x14000+0x40)++0x07
|
|
line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register"
|
|
bitfld.long 0x00 31. " ENA0[31] ,Group interrupt for pin PIO0_31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Group interrupt for pin PIO0_30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Group interrupt for pin PIO0_29 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Group interrupt for pin PIO0_28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Group interrupt for pin PIO0_27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Group interrupt for pin PIO0_26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Group interrupt for pin PIO0_25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Group interrupt for pin PIO0_24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Group interrupt for pin PIO0_23 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Group interrupt for pin PIO0_22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Group interrupt for pin PIO0_21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Group interrupt for pin PIO0_20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Group interrupt for pin PIO0_19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Group interrupt for pin PIO0_18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Group interrupt for pin PIO0_17 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Group interrupt for pin PIO0_16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Group interrupt for pin PIO0_15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Group interrupt for pin PIO0_14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Group interrupt for pin PIO0_13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Group interrupt for pin PIO0_12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Group interrupt for pin PIO0_11 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Group interrupt for pin PIO0_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Group interrupt for pin PIO0_9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Group interrupt for pin PIO0_8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Group interrupt for pin PIO0_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Group interrupt for pin PIO0_6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Group interrupt for pin PIO0_5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Group interrupt for pin PIO0_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Group interrupt for pin PIO0_3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Group interrupt for pin PIO0_2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Group interrupt for pin PIO0_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Group interrupt for pin PIO0_0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register"
|
|
bitfld.long 0x00 31. " ENA1[31] ,Group interrupt for pin PIO1_31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Group interrupt for pin PIO1_30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Group interrupt for pin PIO1_29 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Group interrupt for pin PIO1_28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Group interrupt for pin PIO1_27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Group interrupt for pin PIO1_26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Group interrupt for pin PIO1_25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Group interrupt for pin PIO1_24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Group interrupt for pin PIO1_23 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Group interrupt for pin PIO1_22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Group interrupt for pin PIO1_21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Group interrupt for pin PIO1_20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Group interrupt for pin PIO1_19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Group interrupt for pin PIO1_18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Group interrupt for pin PIO1_17 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Group interrupt for pin PIO1_16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Group interrupt for pin PIO1_15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Group interrupt for pin PIO1_14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Group interrupt for pin PIO1_13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Group interrupt for pin PIO1_12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Group interrupt for pin PIO1_11 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Group interrupt for pin PIO1_10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Group interrupt for pin PIO1_9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Group interrupt for pin PIO1_8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Group interrupt for pin PIO1_7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Group interrupt for pin PIO1_6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Group interrupt for pin PIO1_5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Group interrupt for pin PIO1_4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Group interrupt for pin PIO1_3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Group interrupt for pin PIO1_2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Group interrupt for pin PIO1_1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Group interrupt for pin PIO1_0 enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 18.
|
|
tree "GPIO Port Registers"
|
|
group.byte 0xFFB4000++0x00
|
|
line.byte 0x00 "B0,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4001++0x00
|
|
line.byte 0x00 "B1,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4002++0x00
|
|
line.byte 0x00 "B2,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4003++0x00
|
|
line.byte 0x00 "B3,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4004++0x00
|
|
line.byte 0x00 "B4,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4005++0x00
|
|
line.byte 0x00 "B5,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4006++0x00
|
|
line.byte 0x00 "B6,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4007++0x00
|
|
line.byte 0x00 "B7,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4008++0x00
|
|
line.byte 0x00 "B8,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4009++0x00
|
|
line.byte 0x00 "B9,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB400A++0x00
|
|
line.byte 0x00 "B10,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB400B++0x00
|
|
line.byte 0x00 "B11,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB400C++0x00
|
|
line.byte 0x00 "B12,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB400D++0x00
|
|
line.byte 0x00 "B13,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB400E++0x00
|
|
line.byte 0x00 "B14,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB400F++0x00
|
|
line.byte 0x00 "B15,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4010++0x00
|
|
line.byte 0x00 "B16,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4011++0x00
|
|
line.byte 0x00 "B17,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4012++0x00
|
|
line.byte 0x00 "B18,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4013++0x00
|
|
line.byte 0x00 "B19,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4014++0x00
|
|
line.byte 0x00 "B20,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4015++0x00
|
|
line.byte 0x00 "B21,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4016++0x00
|
|
line.byte 0x00 "B22,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4017++0x00
|
|
line.byte 0x00 "B23,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4018++0x00
|
|
line.byte 0x00 "B24,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4019++0x00
|
|
line.byte 0x00 "B25,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB401A++0x00
|
|
line.byte 0x00 "B26,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB401B++0x00
|
|
line.byte 0x00 "B27,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB401C++0x00
|
|
line.byte 0x00 "B28,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB401D++0x00
|
|
line.byte 0x00 "B29,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB401E++0x00
|
|
line.byte 0x00 "B30,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB401F++0x00
|
|
line.byte 0x00 "B31,GPIO Port 0 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4020++0x00
|
|
line.byte 0x00 "B32,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4021++0x00
|
|
line.byte 0x00 "B33,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4022++0x00
|
|
line.byte 0x00 "B34,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4023++0x00
|
|
line.byte 0x00 "B35,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4024++0x00
|
|
line.byte 0x00 "B36,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4025++0x00
|
|
line.byte 0x00 "B37,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4026++0x00
|
|
line.byte 0x00 "B38,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4027++0x00
|
|
line.byte 0x00 "B39,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4028++0x00
|
|
line.byte 0x00 "B40,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.byte 0xFFB4029++0x00
|
|
line.byte 0x00 "B41,GPIO Port 1 Byte Pin Register"
|
|
bitfld.byte 0x00 0. " PBYTE ,Port byte" "Low,High"
|
|
group.word 0xFFB5000++0x03
|
|
line.word 0x00 "W0,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5004++0x03
|
|
line.word 0x00 "W1,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5008++0x03
|
|
line.word 0x00 "W2,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB500C++0x03
|
|
line.word 0x00 "W3,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5010++0x03
|
|
line.word 0x00 "W4,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5014++0x03
|
|
line.word 0x00 "W5,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5018++0x03
|
|
line.word 0x00 "W6,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB501C++0x03
|
|
line.word 0x00 "W7,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5020++0x03
|
|
line.word 0x00 "W8,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5024++0x03
|
|
line.word 0x00 "W9,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5028++0x03
|
|
line.word 0x00 "W10,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB502C++0x03
|
|
line.word 0x00 "W11,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5030++0x03
|
|
line.word 0x00 "W12,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5034++0x03
|
|
line.word 0x00 "W13,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5038++0x03
|
|
line.word 0x00 "W14,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB503C++0x03
|
|
line.word 0x00 "W15,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5040++0x03
|
|
line.word 0x00 "W16,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5044++0x03
|
|
line.word 0x00 "W17,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5048++0x03
|
|
line.word 0x00 "W18,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB504C++0x03
|
|
line.word 0x00 "W19,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5050++0x03
|
|
line.word 0x00 "W20,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5054++0x03
|
|
line.word 0x00 "W21,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5058++0x03
|
|
line.word 0x00 "W22,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB505C++0x03
|
|
line.word 0x00 "W23,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5060++0x03
|
|
line.word 0x00 "W24,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5064++0x03
|
|
line.word 0x00 "W25,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5068++0x03
|
|
line.word 0x00 "W26,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB506C++0x03
|
|
line.word 0x00 "W27,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5070++0x03
|
|
line.word 0x00 "W28,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5074++0x03
|
|
line.word 0x00 "W29,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5078++0x03
|
|
line.word 0x00 "W30,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB507C++0x03
|
|
line.word 0x00 "W31,GPIO Port 0 Word Pin Register"
|
|
group.word 0xFFB5080++0x03
|
|
line.word 0x00 "W32,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB5084++0x03
|
|
line.word 0x00 "W33,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB5088++0x03
|
|
line.word 0x00 "W34,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB508C++0x03
|
|
line.word 0x00 "W35,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB5090++0x03
|
|
line.word 0x00 "W36,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB5094++0x03
|
|
line.word 0x00 "W37,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB5098++0x03
|
|
line.word 0x00 "W38,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB509C++0x03
|
|
line.word 0x00 "W39,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB50A0++0x03
|
|
line.word 0x00 "W40,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB50A4++0x03
|
|
line.word 0x00 "W41,GPIO Port 1 Word Pin Register"
|
|
group.word 0xFFB50A8++0x03
|
|
line.word 0x00 "W42,GPIO Port 1 Word Pin Register"
|
|
group.long 0xFFB6000++0x07
|
|
line.long 0x00 "DIR0,GPIO Direction Port 0 Register"
|
|
bitfld.long 0x00 31. " DIRP0[31] ,Selects pin direction for PIO0_31" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Selects pin direction for PIO0_30" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Selects pin direction for PIO0_29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Selects pin direction for PIO0_28" "Input,Output"
|
|
bitfld.long 0x00 27. " [27] ,Selects pin direction for PIO0_27" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Selects pin direction for PIO0_26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Selects pin direction for PIO0_25" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Selects pin direction for PIO0_24" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Selects pin direction for PIO0_23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Selects pin direction for PIO0_22" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Selects pin direction for PIO0_21" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Selects pin direction for PIO0_20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Selects pin direction for PIO0_19" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Selects pin direction for PIO0_18" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Selects pin direction for PIO0_17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Selects pin direction for PIO0_16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Selects pin direction for PIO0_15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Selects pin direction for PIO0_14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Selects pin direction for PIO0_13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Selects pin direction for PIO0_12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Selects pin direction for PIO0_11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Selects pin direction for PIO0_10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Selects pin direction for PIO0_9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Selects pin direction for PIO0_8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Selects pin direction for PIO0_7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Selects pin direction for PIO0_6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Selects pin direction for PIO0_5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Selects pin direction for PIO0_4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Selects pin direction for PIO0_3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Selects pin direction for PIO0_2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Selects pin direction for PIO0_1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Selects pin direction for PIO0_0" "Input,Output"
|
|
line.long 0x04 "DIR1,GPIO Direction Port 1 Register"
|
|
bitfld.long 0x04 31. " DIRP1[31] ,Selects pin direction for PIO1_31" "Input,Output"
|
|
bitfld.long 0x04 30. " [30] ,Selects pin direction for PIO1_30" "Input,Output"
|
|
bitfld.long 0x04 29. " [29] ,Selects pin direction for PIO1_29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Selects pin direction for PIO1_28" "Input,Output"
|
|
bitfld.long 0x04 27. " [27] ,Selects pin direction for PIO1_27" "Input,Output"
|
|
bitfld.long 0x04 26. " [26] ,Selects pin direction for PIO1_26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Selects pin direction for PIO1_25" "Input,Output"
|
|
bitfld.long 0x04 24. " [24] ,Selects pin direction for PIO1_24" "Input,Output"
|
|
bitfld.long 0x04 23. " [23] ,Selects pin direction for PIO1_23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Selects pin direction for PIO1_22" "Input,Output"
|
|
bitfld.long 0x04 21. " [21] ,Selects pin direction for PIO1_21" "Input,Output"
|
|
bitfld.long 0x04 20. " [20] ,Selects pin direction for PIO1_20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Selects pin direction for PIO1_19" "Input,Output"
|
|
bitfld.long 0x04 18. " [18] ,Selects pin direction for PIO1_18" "Input,Output"
|
|
bitfld.long 0x04 17. " [17] ,Selects pin direction for PIO1_17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Selects pin direction for PIO1_16" "Input,Output"
|
|
bitfld.long 0x04 15. " [15] ,Selects pin direction for PIO1_15" "Input,Output"
|
|
bitfld.long 0x04 14. " [14] ,Selects pin direction for PIO1_14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Selects pin direction for PIO1_13" "Input,Output"
|
|
bitfld.long 0x04 12. " [12] ,Selects pin direction for PIO1_12" "Input,Output"
|
|
bitfld.long 0x04 11. " [11] ,Selects pin direction for PIO1_11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Selects pin direction for PIO1_10" "Input,Output"
|
|
bitfld.long 0x04 9. " [9] ,Selects pin direction for PIO1_9" "Input,Output"
|
|
bitfld.long 0x04 8. " [8] ,Selects pin direction for PIO1_8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Selects pin direction for PIO1_7" "Input,Output"
|
|
bitfld.long 0x04 6. " [6] ,Selects pin direction for PIO1_6" "Input,Output"
|
|
bitfld.long 0x04 5. " [5] ,Selects pin direction for PIO1_5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Selects pin direction for PIO1_4" "Input,Output"
|
|
bitfld.long 0x04 3. " [3] ,Selects pin direction for PIO1_3" "Input,Output"
|
|
bitfld.long 0x04 2. " [2] ,Selects pin direction for PIO1_2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Selects pin direction for PIO1_1" "Input,Output"
|
|
bitfld.long 0x04 0. " [0] ,Selects pin direction for PIO1_0" "Input,Output"
|
|
group.long 0xFFB6080++0x07
|
|
line.long 0x00 "MASK0,GPIO Mask Port 0 Register"
|
|
bitfld.long 0x00 31. " [31] ,Controls which bits corresponding to PIO0_31 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Controls which bits corresponding to PIO0_30 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Controls which bits corresponding to PIO0_29 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Controls which bits corresponding to PIO0_28 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Controls which bits corresponding to PIO0_27 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Controls which bits corresponding to PIO0_26 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Controls which bits corresponding to PIO0_25 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Controls which bits corresponding to PIO0_24 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Controls which bits corresponding to PIO0_23 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Controls which bits corresponding to PIO0_22 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Controls which bits corresponding to PIO0_21 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Controls which bits corresponding to PIO0_20 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Controls which bits corresponding to PIO0_19 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Controls which bits corresponding to PIO0_18 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Controls which bits corresponding to PIO0_17 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Controls which bits corresponding to PIO0_16 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Controls which bits corresponding to PIO0_15 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Controls which bits corresponding to PIO0_14 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Controls which bits corresponding to PIO0_13 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Controls which bits corresponding to PIO0_12 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Controls which bits corresponding to PIO0_11 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Controls which bits corresponding to PIO0_10 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Controls which bits corresponding to PIO0_9 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Controls which bits corresponding to PIO0_8 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Controls which bits corresponding to PIO0_7 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Controls which bits corresponding to PIO0_6 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Controls which bits corresponding to PIO0_5 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Controls which bits corresponding to PIO0_4 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Controls which bits corresponding to PIO0_3 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Controls which bits corresponding to PIO0_2 are active in the P0MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Controls which bits corresponding to PIO0_1 are active in the P0MPORT register" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Controls which bits corresponding to PIO0_0 are active in the P0MPORT register" "Low,High"
|
|
line.long 0x04 "MASK1,GPIO Mask Port 1 Register"
|
|
bitfld.long 0x04 31. " [31] ,Controls which bits corresponding to PIO1_31 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 30. " [30] ,Controls which bits corresponding to PIO1_30 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 29. " [29] ,Controls which bits corresponding to PIO1_29 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Controls which bits corresponding to PIO1_28 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 27. " [27] ,Controls which bits corresponding to PIO1_27 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 26. " [26] ,Controls which bits corresponding to PIO1_26 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Controls which bits corresponding to PIO1_25 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 24. " [24] ,Controls which bits corresponding to PIO1_24 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 23. " [23] ,Controls which bits corresponding to PIO1_23 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Controls which bits corresponding to PIO1_22 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 21. " [21] ,Controls which bits corresponding to PIO1_21 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 20. " [20] ,Controls which bits corresponding to PIO1_20 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Controls which bits corresponding to PIO1_19 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 18. " [18] ,Controls which bits corresponding to PIO1_18 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 17. " [17] ,Controls which bits corresponding to PIO1_17 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Controls which bits corresponding to PIO1_16 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 15. " [15] ,Controls which bits corresponding to PIO1_15 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Controls which bits corresponding to PIO1_14 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Controls which bits corresponding to PIO1_13 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Controls which bits corresponding to PIO1_12 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 11. " [11] ,Controls which bits corresponding to PIO1_11 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Controls which bits corresponding to PIO1_10 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Controls which bits corresponding to PIO1_9 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Controls which bits corresponding to PIO1_8 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Controls which bits corresponding to PIO1_7 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Controls which bits corresponding to PIO1_6 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Controls which bits corresponding to PIO1_5 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Controls which bits corresponding to PIO1_4 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 3. " [3] ,Controls which bits corresponding to PIO1_3 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Controls which bits corresponding to PIO1_2 are active in the P1MPORT register" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Controls which bits corresponding to PIO1_1 are active in the P1MPORT register" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Controls which bits corresponding to PIO1_0 are active in the P1MPORT register" "Low,High"
|
|
group.long 0xFFB6100++0x07
|
|
line.long 0x00 "PIN0,GPIO Port 0 Pin Register"
|
|
bitfld.long 0x00 31. " PORT0[31] ,Read pin state or loads output of PIO0_31" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Read pin state or loads output of PIO0_30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Read pin state or loads output of PIO0_29" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Read pin state or loads output of PIO0_28" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Read pin state or loads output of PIO0_27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Read pin state or loads output of PIO0_26" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Read pin state or loads output of PIO0_25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Read pin state or loads output of PIO0_24" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Read pin state or loads output of PIO0_23" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Read pin state or loads output of PIO0_22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Read pin state or loads output of PIO0_21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Read pin state or loads output of PIO0_20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Read pin state or loads output of PIO0_19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Read pin state or loads output of PIO0_18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Read pin state or loads output of PIO0_17" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Read pin state or loads output of PIO0_16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Read pin state or loads output of PIO0_15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Read pin state or loads output of PIO0_14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Read pin state or loads output of PIO0_13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Read pin state or loads output of PIO0_12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Read pin state or loads output of PIO0_11" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Read pin state or loads output of PIO0_10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Read pin state or loads output of PIO0_9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Read pin state or loads output of PIO0_8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Read pin state or loads output of PIO0_7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Read pin state or loads output of PIO0_6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Read pin state or loads output of PIO0_5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Read pin state or loads output of PIO0_4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Read pin state or loads output of PIO0_3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Read pin state or loads output of PIO0_2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Read pin state or loads output of PIO0_1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Read pin state or loads output of PIO0_0" "Low,High"
|
|
line.long 0x04 "PIN1,GPIO Port 1 Pin Register"
|
|
bitfld.long 0x04 31. " PORT1[31] ,Read pin state or loads output of PIO1_31" "Low,High"
|
|
bitfld.long 0x04 30. " [30] ,Read pin state or loads output of PIO1_30" "Low,High"
|
|
bitfld.long 0x04 29. " [29] ,Read pin state or loads output of PIO1_29" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Read pin state or loads output of PIO1_28" "Low,High"
|
|
bitfld.long 0x04 27. " [27] ,Read pin state or loads output of PIO1_27" "Low,High"
|
|
bitfld.long 0x04 26. " [26] ,Read pin state or loads output of PIO1_26" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Read pin state or loads output of PIO1_25" "Low,High"
|
|
bitfld.long 0x04 24. " [24] ,Read pin state or loads output of PIO1_24" "Low,High"
|
|
bitfld.long 0x04 23. " [23] ,Read pin state or loads output of PIO1_23" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Read pin state or loads output of PIO1_22" "Low,High"
|
|
bitfld.long 0x04 21. " [21] ,Read pin state or loads output of PIO1_21" "Low,High"
|
|
bitfld.long 0x04 20. " [20] ,Read pin state or loads output of PIO1_20" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Read pin state or loads output of PIO1_19" "Low,High"
|
|
bitfld.long 0x04 18. " [18] ,Read pin state or loads output of PIO1_18" "Low,High"
|
|
bitfld.long 0x04 17. " [17] ,Read pin state or loads output of PIO1_17" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Read pin state or loads output of PIO1_16" "Low,High"
|
|
bitfld.long 0x04 15. " [15] ,Read pin state or loads output of PIO1_15" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Read pin state or loads output of PIO1_14" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Read pin state or loads output of PIO1_13" "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Read pin state or loads output of PIO1_12" "Low,High"
|
|
bitfld.long 0x04 11. " [11] ,Read pin state or loads output of PIO1_11" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Read pin state or loads output of PIO1_10" "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Read pin state or loads output of PIO1_9" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Read pin state or loads output of PIO1_8" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Read pin state or loads output of PIO1_7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Read pin state or loads output of PIO1_6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Read pin state or loads output of PIO1_5" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Read pin state or loads output of PIO1_4" "Low,High"
|
|
bitfld.long 0x04 3. " [3] ,Read pin state or loads output of PIO1_3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Read pin state or loads output of PIO1_2" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Read pin state or loads output of PIO1_1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Read pin state or loads output of PIO1_0" "Low,High"
|
|
group.long 0xFFB6180++0x07
|
|
line.long 0x00 "MPIN0,GPIO Masked Port 0 Pin Register"
|
|
bitfld.long 0x00 31. " MPORTP0[31] ,PIO0_31 mask bit" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,PIO0_30 mask bit" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,PIO0_29 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,PIO0_28 mask bit" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,PIO0_27 mask bit" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,PIO0_26 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,PIO0_25 mask bit" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,PIO0_24 mask bit" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,PIO0_23 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,PIO0_22 mask bit" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,PIO0_21 mask bit" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,PIO0_20 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,PIO0_19 mask bit" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,PIO0_18 mask bit" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,PIO0_17 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,PIO0_16 mask bit" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,PIO0_15 mask bit" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,PIO0_14 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,PIO0_13 mask bit" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,PIO0_12 mask bit" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,PIO0_11 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,PIO0_10 mask bit" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,PIO0_9 mask bit" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,PIO0_8 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,PIO0_7 mask bit" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,PIO0_6 mask bit" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,PIO0_5 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,PIO0_4 mask bit" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,PIO0_3 mask bit" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,PIO0_2 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,PIO0_1 mask bit" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,PIO0_0 mask bit" "Low,High"
|
|
line.long 0x04 "MPIN1,GPIO Masked Port 1 Pin Register"
|
|
bitfld.long 0x04 31. " MPORTP1[31] ,PIO1_ mask bit" "Low,High"
|
|
bitfld.long 0x04 30. " [30] ,PIO1_30 mask bit" "Low,High"
|
|
bitfld.long 0x04 29. " [29] ,PIO1_29 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,PIO1_28 mask bit" "Low,High"
|
|
bitfld.long 0x04 27. " [27] ,PIO1_27 mask bit" "Low,High"
|
|
bitfld.long 0x04 26. " [26] ,PIO1_26 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,PIO1_25 mask bit" "Low,High"
|
|
bitfld.long 0x04 24. " [24] ,PIO1_24 mask bit" "Low,High"
|
|
bitfld.long 0x04 23. " [23] ,PIO1_23 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,PIO1_22 mask bit" "Low,High"
|
|
bitfld.long 0x04 21. " [21] ,PIO1_21 mask bit" "Low,High"
|
|
bitfld.long 0x04 20. " [20] ,PIO1_20 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,PIO1_19 mask bit" "Low,High"
|
|
bitfld.long 0x04 18. " [18] ,PIO1_18 mask bit" "Low,High"
|
|
bitfld.long 0x04 17. " [17] ,PIO1_17 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,PIO1_16 mask bit" "Low,High"
|
|
bitfld.long 0x04 15. " [15] ,PIO1_15 mask bit" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,PIO1_14 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,PIO1_13 mask bit" "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,PIO1_12 mask bit" "Low,High"
|
|
bitfld.long 0x04 11. " [11] ,PIO1_11 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,PIO1_10 mask bit" "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,PIO1_9 mask bit" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,PIO1_8 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,PIO1_7 mask bit" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,PIO1_6 mask bit" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,PIO1_5 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,PIO1_4 mask bit" "Low,High"
|
|
bitfld.long 0x04 3. " [3] ,PIO1_3 mask bit" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,PIO1_2 mask bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,PIO1_1 mask bit" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,PIO1_0 mask bit" "Low,High"
|
|
newline
|
|
group.long 0xFFB6200++0x03
|
|
line.long 0x00 "GPIOPORT_set/clr,GPIO Port Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " GPIOPORT_set/clr[31] ,GPIO port set/clear bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " GPIOPORT_set/clr[30] ,GPIO port set/clear bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " GPIOPORT_set/clr[29] ,GPIO port set/clear bit 29" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " GPIOPORT_set/clr[28] ,GPIO port set/clear bit 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " GPIOPORT_set/clr[27] ,GPIO port set/clear bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " GPIOPORT_set/clr[26] ,GPIO port set/clear bit 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " GPIOPORT_set/clr[25] ,GPIO port set/clear bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " GPIOPORT_set/clr[24] ,GPIO port set/clear bit 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " GPIOPORT_set/clr[23] ,GPIO port set/clear bit 23" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " GPIOPORT_set/clr[22] ,GPIO port set/clear bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " GPIOPORT_set/clr[21] ,GPIO port set/clear bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " GPIOPORT_set/clr[20] ,GPIO port set/clear bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " GPIOPORT_set/clr[19] ,GPIO port set/clear bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " GPIOPORT_set/clr[18] ,GPIO port set/clear bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " GPIOPORT_set/clr[17] ,GPIO port set/clear bit 17" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " GPIOPORT_set/clr[16] ,GPIO port set/clear bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " GPIOPORT_set/clr[15] ,GPIO port set/clear bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " GPIOPORT_set/clr[14] ,GPIO port set/clear bit 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " GPIOPORT_set/clr[13] ,GPIO port set/clear bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " GPIOPORT_set/clr[12] ,GPIO port set/clear bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " GPIOPORT_set/clr[11] ,GPIO port set/clear bit 11" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " GPIOPORT_set/clr[10] ,GPIO port set/clear bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " GPIOPORT_set/clr[9] ,GPIO port set/clear bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " GPIOPORT_set/clr[8] ,GPIO port set/clear bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " GPIOPORT_set/clr[7] ,GPIO port set/clear bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " GPIOPORT_set/clr[6] ,GPIO port set/clear bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " GPIOPORT_set/clr[5] ,GPIO port set/clear bit 5" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " GPIOPORT_set/clr[4] ,GPIO port set/clear bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " GPIOPORT_set/clr[3] ,GPIO port set/clear bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " GPIOPORT_set/clr[2] ,GPIO port set/clear bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " GPIOPORT_set/clr[1] ,GPIO port set/clear bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " GPIOPORT_set/clr[0] ,GPIO port set/clear bit 0" "Low,High"
|
|
newline
|
|
group.long 0xFFB6300++0x07
|
|
line.long 0x00 "NOT0,GPIO Toggle Port 0 Register"
|
|
bitfld.long 0x00 31. " NOTP0[31] ,Toggle output bit 31" "No operation,Toggle"
|
|
bitfld.long 0x00 30. " [30] ,Toggle output bit 30" "No operation,Toggle"
|
|
bitfld.long 0x00 29. " [29] ,Toggle output bit 29" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Toggle output bit 28" "No operation,Toggle"
|
|
bitfld.long 0x00 27. " [27] ,Toggle output bit 27" "No operation,Toggle"
|
|
bitfld.long 0x00 26. " [26] ,Toggle output bit 26" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Toggle output bit 25" "No operation,Toggle"
|
|
bitfld.long 0x00 24. " [24] ,Toggle output bit 24" "No operation,Toggle"
|
|
bitfld.long 0x00 23. " [23] ,Toggle output bit 23" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Toggle output bit 22" "No operation,Toggle"
|
|
bitfld.long 0x00 21. " [21] ,Toggle output bit 21" "No operation,Toggle"
|
|
bitfld.long 0x00 20. " [20] ,Toggle output bit 20" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Toggle output bit 19" "No operation,Toggle"
|
|
bitfld.long 0x00 18. " [18] ,Toggle output bit 18" "No operation,Toggle"
|
|
bitfld.long 0x00 17. " [17] ,Toggle output bit 17" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Toggle output bit 16" "No operation,Toggle"
|
|
bitfld.long 0x00 15. " [15] ,Toggle output bit 15" "No operation,Toggle"
|
|
bitfld.long 0x00 14. " [14] ,Toggle output bit 14" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Toggle output bit 13" "No operation,Toggle"
|
|
bitfld.long 0x00 12. " [12] ,Toggle output bit 12" "No operation,Toggle"
|
|
bitfld.long 0x00 11. " [11] ,Toggle output bit 11" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Toggle output bit 10" "No operation,Toggle"
|
|
bitfld.long 0x00 9. " [9] ,Toggle output bit 9" "No operation,Toggle"
|
|
bitfld.long 0x00 8. " [8] ,Toggle output bit 8" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Toggle output bit 7" "No operation,Toggle"
|
|
bitfld.long 0x00 6. " [6] ,Toggle output bit 6" "No operation,Toggle"
|
|
bitfld.long 0x00 5. " [5] ,Toggle output bit 5" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Toggle output bit 4" "No operation,Toggle"
|
|
bitfld.long 0x00 3. " [3] ,Toggle output bit 3" "No operation,Toggle"
|
|
bitfld.long 0x00 2. " [2] ,Toggle output bit 2" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Toggle output bit 1" "No operation,Toggle"
|
|
bitfld.long 0x00 0. " [0] ,Toggle output bit 0" "No operation,Toggle"
|
|
line.long 0x04 "NOT1,GPIO Toggle Port 1 Register"
|
|
bitfld.long 0x04 31. " NOTP1[31] ,Toggle output bit 31" "No operation,Toggle"
|
|
bitfld.long 0x04 30. " [30] ,Toggle output bit 30" "No operation,Toggle"
|
|
bitfld.long 0x04 29. " [29] ,Toggle output bit 29" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Toggle output bit 28" "No operation,Toggle"
|
|
bitfld.long 0x04 27. " [27] ,Toggle output bit 27" "No operation,Toggle"
|
|
bitfld.long 0x04 26. " [26] ,Toggle output bit 26" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Toggle output bit 25" "No operation,Toggle"
|
|
bitfld.long 0x04 24. " [24] ,Toggle output bit 24" "No operation,Toggle"
|
|
bitfld.long 0x04 23. " [23] ,Toggle output bit 23" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Toggle output bit 22" "No operation,Toggle"
|
|
bitfld.long 0x04 21. " [21] ,Toggle output bit 21" "No operation,Toggle"
|
|
bitfld.long 0x04 20. " [20] ,Toggle output bit 20" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Toggle output bit 19" "No operation,Toggle"
|
|
bitfld.long 0x04 18. " [18] ,Toggle output bit 18" "No operation,Toggle"
|
|
bitfld.long 0x04 17. " [17] ,Toggle output bit 17" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Toggle output bit 16" "No operation,Toggle"
|
|
bitfld.long 0x04 15. " [15] ,Toggle output bit 15" "No operation,Toggle"
|
|
bitfld.long 0x04 14. " [14] ,Toggle output bit 14" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Toggle output bit 13" "No operation,Toggle"
|
|
bitfld.long 0x04 12. " [12] ,Toggle output bit 12" "No operation,Toggle"
|
|
bitfld.long 0x04 11. " [11] ,Toggle output bit 11" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Toggle output bit 10" "No operation,Toggle"
|
|
bitfld.long 0x04 9. " [9] ,Toggle output bit 9" "No operation,Toggle"
|
|
bitfld.long 0x04 8. " [8] ,Toggle output bit 8" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Toggle output bit 7" "No operation,Toggle"
|
|
bitfld.long 0x04 6. " [6] ,Toggle output bit 6" "No operation,Toggle"
|
|
bitfld.long 0x04 5. " [5] ,Toggle output bit 5" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Toggle output bit 4" "No operation,Toggle"
|
|
bitfld.long 0x04 3. " [3] ,Toggle output bit 3" "No operation,Toggle"
|
|
bitfld.long 0x04 2. " [2] ,Toggle output bit 2" "No operation,Toggle"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Toggle output bit 1" "No operation,Toggle"
|
|
bitfld.long 0x04 0. " [0] ,Toggle output bit 0" "No operation,Toggle"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I/O Configuration"
|
|
base ad:0x40044000
|
|
width 15.
|
|
group.long 0x00++0xA7
|
|
line.long 0x00 "RESET_PIO0_0,I/O Configuration for Pin RESET/PIO0_0"
|
|
bitfld.long 0x00 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x00 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x00 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "RESET,PIO0_0,?..."
|
|
line.long 0x04 "PIO0_1,I/O Configuration for Pin PIO0_1/RXD/CLKOUT/CT32B0_MAT2/SSEL0/CLKIN"
|
|
bitfld.long 0x04 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x04 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x04 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_1,RXD,CLKOUT,CT32B0_MAT2,SSEL0,CLKIN,?..."
|
|
line.long 0x08 "PIO0_2,I/O Configuration for Pin PIO0_2/SCL/ACMP_O/TCK/SWCLK/CT16B0_CAP0"
|
|
bitfld.long 0x08 9. " HIDRIVE ,HIDRIVE" "4mA,20mA"
|
|
bitfld.long 0x08 8. " HS ,Disables I2C features for faster operation" "No,Yes"
|
|
bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_2,SCL,ACMP_O,TCK/SWCLK,CT16B0_CAP0,?..."
|
|
line.long 0x0C "PIO0_3,I/O Configuration for Pin PIO0_3/SDA/ACMP_O/SWDIO/CT16B1_CAP0"
|
|
bitfld.long 0x0C 9. " HIDRIVE ,HIDRIVE" "4mA,20mA"
|
|
bitfld.long 0x0C 8. " HS ,Disables I2C features for faster operation" "No,Yes"
|
|
bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_3,SDA,ACMP_O,SWDIO,CT16B1_CAP0,?..."
|
|
line.long 0x10 "PIO0_4,I/O Configuration for Pin PIO0_4/AOUT/CT16B0_MAT1/MOSI0"
|
|
bitfld.long 0x10 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x10 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x10 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x10 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x10 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_4,,AOUT,CT16B0_MAT1,MOSI0,?..."
|
|
line.long 0x14 "TCK_PIO0_5,I/O Configuration for Pin TCK/SWCLK/PIO0_5/VDDCMP/CT16B0_MAT2/SCK0"
|
|
bitfld.long 0x14 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x14 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x14 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x14 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x14 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "TCK/SWCLK,PIO0_5,VDDCMP,CT16B0_MAT2,SCK0,?..."
|
|
line.long 0x18 "TDI_PIO0_6,I/O Configuration for Pin TDI/PIO0_6/AD0/CT32B0_MAT3/MISO0"
|
|
bitfld.long 0x18 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x18 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x18 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x18 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x18 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "TDI,PIO0_6,AD0,CT32B0_MAT3,MISO0,?..."
|
|
line.long 0x1C "TMS_PIO0_7 ,I/O Configuration for Pin TMS/PIO0_7/AD1/CT32B1_CAP0/CT16B0_MAT0"
|
|
bitfld.long 0x1C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x1C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x1C 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x1C 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x1C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x1C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x1C 0.--2. " FUNC ,Selects pin function" "TMS,PIO0_7,AD1,CT32B1_CAP0,CT16B0_MAT0,?..."
|
|
line.long 0x20 "TDO_PIO0_8,I/O Configuration for Pin TDO/PIO0_8/AD2/CT32B1_MAT0/SCK1"
|
|
bitfld.long 0x20 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x20 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x20 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x20 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x20 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x20 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x20 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x20 0.--2. " FUNC ,Selects pin function" "TDO,PIO0_8,AD2,CT32B1_MAT0,SCK1,?..."
|
|
line.long 0x24 "TRST_PIO0_9,I/O Configuration for Pin TRST/PIO0_9/AD3/CT32B1_MAT1/CT16B0_MAT1/CTS"
|
|
bitfld.long 0x24 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x24 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x24 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x24 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x24 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x24 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x24 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x24 0.--2. " FUNC ,Selects pin function" "TRST,PIO0_9,AD3,CT32B1_MAT1,CT16B0_MAT1,CTS,?..."
|
|
line.long 0x28 "SWDIO_PIO0_10,I/O Configuration for Pin SWDIO/PIO0_10/AD4/CT32B1_MAT2/CT16B0_MAT2/RTS"
|
|
bitfld.long 0x28 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x28 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x28 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x28 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x28 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x28 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x28 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x28 0.--2. " FUNC ,Selects pin function" "SWDIO,PIO0_10,AD4,CT32B1_MAT2,CT16B0_MAT2,RTS,?..."
|
|
line.long 0x2C "PIO0_11,I/O Configuration for Pin PIO0_11/SCLK/AD5/CT32B1_MAT3/CT32B0_CAP0"
|
|
bitfld.long 0x2C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x2C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x2C 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x2C 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x2C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x2C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x2C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x2C 0.--2. " FUNC ,Selects pin function" "PIO0_11,SCLK,AD5,CT32B1_MAT3,CT32B0_CAP0,?..."
|
|
line.long 0x30 "PIO0_12,I/O Configuration for Pin PIO0_12/RXD/ACMP_O/CT32B0_MAT0/SCL/CLKIN"
|
|
bitfld.long 0x30 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x30 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x30 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x30 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x30 0.--2. " FUNC ,Selects pin function" "PIO0_12,RXD,ACMP_O,CT32B0_MAT0,SCL,CLKIN,?..."
|
|
line.long 0x34 "PIO0_13,I/O Configuration for Pin PIO0_13/TXD/ACMP_I2/CT32B0_MAT1/SDA"
|
|
bitfld.long 0x34 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x34 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x34 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x34 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x34 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x34 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x34 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x34 0.--2. " FUNC ,Selects pin function" "PIO0_13,TXD,ACMP_I2,CT32B0_MAT1,SDA,?..."
|
|
line.long 0x38 "PIO0_14,I/O Configuration for Pin PIO0_14/MISO1/AD6/CT32B0_CAP1/CT16B1_MAT1/VDDCMP"
|
|
bitfld.long 0x38 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x38 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x38 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x38 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x38 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x38 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x38 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x38 0.--2. " FUNC ,Selects pin function" "PIO0_14,MISO1,AD6,CT32B0_CAP1,CT16B1_MAT1,VDDCMP,?..."
|
|
line.long 0x3C "PIO0_15,I/O Configuration for Pin PIO0_15/TXD/AD7/CT32B0_CAP2/SDA"
|
|
bitfld.long 0x3C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x3C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x3C 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x3C 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x3C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x3C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x3C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x3C 0.--2. " FUNC ,Selects pin function" "PIO0_15,TXD,AD7,CT32B0_CAP2,SDA,?..."
|
|
line.long 0x40 "PIO0_16,I/O Configuration for Pin PIO0_16/ATRG0/ACMP_I3/CT16B0_CAP1/SCL"
|
|
bitfld.long 0x40 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x40 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x40 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x40 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x40 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x40 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x40 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x40 0.--2. " FUNC ,Selects pin function" "PIO0_16,ATRG0,ACMP_I3,CT16B0_CAP1,SCL,?..."
|
|
line.long 0x44 "PIO0_17,I/O Configuration for Pin PIO0_17/ATRG1/ACMP_I4/CT16B0_CAP2/CT16B0_MAT0"
|
|
bitfld.long 0x44 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x44 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x44 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x44 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x44 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x44 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x44 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x44 0.--2. " FUNC ,Selects pin function" "PIO0_17,ATRG1,ACMP_I4,CT16B0_CAP2,CT16B0_MAT0,?..."
|
|
line.long 0x48 "PIO0_18,I/O Configuration for Pin PIO0_18/SSEL0/CT16B0_CAP0/CT16B1_CAP1"
|
|
bitfld.long 0x48 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x48 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x48 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x48 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x48 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x48 0.--2. " FUNC ,Selects pin function" "PIO0_18,,SSEL0,CT16B0_CAP0,CT16B1_CAP1,?..."
|
|
line.long 0x4C "PIO0_19,I/O Configuration for Pin PIO0_19/CLKIN/CLKOUT/MOSI0/CT16B1_MAT0"
|
|
bitfld.long 0x4C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x4C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x4C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x4C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x4C 0.--2. " FUNC ,Selects pin function" "PIO0_19,CLKIN,CLKOUT,MOSI0,CT16B1_MAT0,?..."
|
|
line.long 0x50 "PIO0_20,I/O Configuration for Pin PIO0_20/SCK0/CT32B1_CAP0/CT16B1_MAT2"
|
|
bitfld.long 0x50 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x50 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x50 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x50 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x50 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x50 0.--2. " FUNC ,Selects pin function" "PIO0_20,,SCK0,CT32B1_CAP0,CT16B1_MAT2,?..."
|
|
line.long 0x54 "PIO0_21,I/O Configuration for Pin PIO0_21/CTS/ACMP_O/CT32B1_CAP1/SCLK"
|
|
bitfld.long 0x54 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x54 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x54 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x54 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x54 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x54 0.--2. " FUNC ,Selects pin function" "PIO0_21,CTS,ACMP_O,CT32B1_CAP1,SCLK,?..."
|
|
line.long 0x58 "PIO0_22,I/O Configuration for Pin PIO0_22/MISO0/ACMP_I5/CT32B1_MAT2/CT32B1_CAP2"
|
|
bitfld.long 0x58 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x58 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x58 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x58 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x58 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x58 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x58 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x58 0.--2. " FUNC ,Selects pin function" "PIO0_22,MISO0,ACMP_I5,CT32B1_MAT2,CT32B1_CAP2,?..."
|
|
line.long 0x5C "PIO0_23,I/O Configuration for Pin PIO0_23/RTS/ACMP_O/ CT32B0_CAP0/SCLK"
|
|
bitfld.long 0x5C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x5C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x5C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x5C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x5C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x5C 0.--2. " FUNC ,Selects pin function" "PIO0_23,RTS,ACMP_O,CT32B0_CAP0,SCLK,?..."
|
|
line.long 0x60 "PIO0_24,I/O Configuration for Pin PIO0_24/SCL/CLKIN/CT16B1_CAP0"
|
|
bitfld.long 0x60 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x60 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x60 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x60 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x60 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x60 0.--2. " FUNC ,Selects pin function" "PIO0_24,SCL,CLKIN,CT16B1_CAP0,?..."
|
|
line.long 0x64 "PIO0_25,I/O Configuration for Pin PIO0_25/SDA/SSEL1/CT16B1_MAT0"
|
|
bitfld.long 0x64 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x64 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x64 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x64 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x64 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x64 0.--2. " FUNC ,Selects pin function" "PIO0_25,SDA,SSEL1,CT16B1_MAT0,?..."
|
|
line.long 0x68 "PIO0_26,I/O Configuration for Pin PIO0_26/TXD/MISO1/CT16B1_CAP1/CT32B0_CAP2"
|
|
bitfld.long 0x68 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x68 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x68 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x68 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x68 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x68 0.--2. " FUNC ,Selects pin function" "PIO0_26,TXD,MISO1,CT16B1_CAP1,CT32B0_CAP2,?..."
|
|
line.long 0x6C "PIO0_27,I/O Configuration for Pin PIO0_27/MOSI1/ACMP_I1/CT32B1_MAT1/CT16B1_CAP2"
|
|
bitfld.long 0x6C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x6C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x6C 8. " FILTR ,Controls glitch filter" "Filtered,Not filtered"
|
|
bitfld.long 0x6C 7. " ADMODE ,Select analog/digital mode" "Analog,Digital"
|
|
newline
|
|
bitfld.long 0x6C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x6C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
bitfld.long 0x6C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x6C 0.--2. " FUNC ,Selects pin function" "PIO0_27,MOSI1,ACMP_I1,CT32B1_MAT1,CT16B1_CAP2,?..."
|
|
line.long 0x70 "PIO0_28,I/O Configuration for Pin PIO0_28/DTR/SSEL1/CT32B0_CAP0"
|
|
bitfld.long 0x70 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x70 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x70 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x70 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x70 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x70 0.--2. " FUNC ,Selects pin function" "PIO0_28,DTR,SSEL1,CT32B0_CAP0,?..."
|
|
line.long 0x74 "PIO0_29,I/O Configuration for Pin PIO0_29/DSR/SCK1/CT32B0_CAP1"
|
|
bitfld.long 0x74 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x74 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x74 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x74 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x74 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x74 0.--2. " FUNC ,Selects pin function" "PIO0_29,DSR,SCK1,CT32B0_CAP1,?..."
|
|
line.long 0x78 "PIO0_30,I/O Configuration for Pin PIO0_30/RI/MOSI1/CT32B0_MAT0/CT16B0_CAP0"
|
|
bitfld.long 0x78 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x78 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x78 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x78 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x78 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x78 0.--2. " FUNC ,Selects pin function" "PIO0_30,RI,MOSI1,CT32B0_MAT0,CT16B0_CAP0,?..."
|
|
line.long 0x7C "PIO0_31,I/O Configuration for Pin PIO0_31/RI/MOSI1/CT32B1_MAT0/CT16B1_CAP1"
|
|
bitfld.long 0x7C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x7C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x7C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x7C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x7C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x7C 0.--2. " FUNC ,Selects pin function" "PIO0_31,RI,MOSI1,CT32B1_MAT0,CT16B1_CAP1,?..."
|
|
line.long 0x80 "PIO1_0,I/O Configuration for Pin PIO1_0/DCD/SCK0/CT32B1_MAT3/CT16B0_MAT1"
|
|
bitfld.long 0x80 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x80 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x80 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x80 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x80 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x80 0.--2. " FUNC ,Selects pin function" "PIO1_0,DCD,SCK0,CT32B1_MAT3,CT16B0_MAT1,?..."
|
|
line.long 0x84 "PIO1_1,I/O Configuration for Pin PIO1_1/DTR/SSEL0/CT32B1_MAT3/CT16B1_MAT0"
|
|
bitfld.long 0x84 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x84 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x84 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x84 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x84 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x84 0.--2. " FUNC ,Selects pin function" "PIO1_1,DTR,SSEL0,CT32B1_MAT3,CT16B1_MAT0,?..."
|
|
line.long 0x88 "PIO1_2,I/O Configuration for Pin PIO1_2/DSR/MISO0/CT16B1_MAT2/CT16B1_MAT1"
|
|
bitfld.long 0x88 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x88 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x88 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x88 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x88 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x88 0.--2. " FUNC ,Selects pin function" "PIO1_2,DSR,MISO0,CT16B1_MAT2,CT16B1_MAT1,?..."
|
|
line.long 0x8C "PIO1_3,I/O Configuration for Pin PIO1_3/RI/MOSI0/CT16B1_CAP0"
|
|
bitfld.long 0x8C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x8C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x8C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x8C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x8C 0.--2. " FUNC ,Selects pin function" "PIO1_3,RI,MOSI0,CT16B1_CAP0,?..."
|
|
line.long 0x90 "PIO1_4,I/O Configuration for Pin PIO1_4/RXD/SSEL1/CT32B0_MAT1/CT32B1_CAP0/CT16B0_CAP1"
|
|
bitfld.long 0x90 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x90 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x90 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x90 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x90 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x90 0.--2. " FUNC ,Selects pin function" "PIO1_4,RXD,SSEL1,CT32B0_MAT1,CT32B1_CAP0,CT16B0_CAP1,?..."
|
|
line.long 0x94 "PIO1_5,I/O Configuration for Pin PIO1_5/TXD/SCK1/CT32B0_MAT2/CT32B1_CAP1/CT16B0_CAP2"
|
|
bitfld.long 0x94 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x94 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x94 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x94 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x94 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x94 0.--2. " FUNC ,Selects pin function" "PIO1_5,TXD,SCK1,CT32B0_MAT2,CT32B1_CAP1,CT16B0_CAP2,?..."
|
|
line.long 0x98 "PIO1_6,I/O Configuration for Pin PIO1_6/RTS/MOSI1/CT32B0_MAT3/CT32B1_CAP2/CT16B0_MAT0"
|
|
bitfld.long 0x98 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x98 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x98 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x98 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x98 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x98 0.--2. " FUNC ,Selects pin function" "PIO1_6,RTS,MOSI1,CT32B0_MAT3,CT32B1_CAP2,CT16B0_MAT0,?..."
|
|
line.long 0x9C "PIO1_7,I/O Configuration for Pin PIO1_7/CTS/MOSI0/CT32B1_MAT1/CT16B0_MAT2/CT16B1_CAP2"
|
|
bitfld.long 0x9C 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0x9C 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0x9C 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x9C 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x9C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0x9C 0.--2. " FUNC ,Selects pin function" "PIO1_7,CTS,MOSI0,CT32B1_MAT1,CT16B0_MAT2,CT16B1_CAP2,?..."
|
|
line.long 0xA0 "PIO1_8,I/O Configuration for Pin PIO1_8/RXD/MISO1/CT32B1_MAT0/CT16B1_MAT1"
|
|
bitfld.long 0xA0 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0xA0 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0xA0 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0xA0 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xA0 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0xA0 0.--2. " FUNC ,Selects pin function" "PIO1_8,RXD,MISO1,CT32B1_MAT0,CT16B1_MAT1,?..."
|
|
line.long 0xA4 "PIO1_9,I/O Configuration for Pin PIO1_9/DCD/CT32B1_MAT2/CT16B1_MAT2"
|
|
bitfld.long 0xA4 10. " OD ,Controls open-drain mode" "Totem-pole,Open-drain"
|
|
bitfld.long 0xA4 9. " SLEW ,Driver slew rate" "Slow,Fast"
|
|
bitfld.long 0xA4 6. " INV ,Input polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0xA4 5. " HYS ,Hysteresis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xA4 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater"
|
|
bitfld.long 0xA4 0.--2. " FUNC ,Selects pin function" "PIO1_9,DCD,,CT32B1_MAT2,CT16B1_MAT2,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
base ad:0x40008000
|
|
width 15.
|
|
if (((per.l(ad:0x40008000+0x0C))&0x80)==0x00)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RBR,Receiver Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RBR ,The oldest received byte in the USART0 RX FIFO"
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " THR ,USART transmit FIFO"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ABEOINTEN ,End of auto-baud interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MSINTEN ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RLSINTEN ,Receive line status interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " THREINTEN ,THRE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RBRINTEN ,RBR interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DLL,Divisor Latch LSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,USART divisor latch LSB"
|
|
line.long 0x04 "DLM,Divisor Latch MSB"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLMSB ,USART divisor latch MSB"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt ID"
|
|
bitfld.long 0x00 9. " ABTOINT ,Auto-baud timeout interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " ABEOINT ,End of auto-baud interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6.--7. " FIFOEN ,FIFO enable" "0,1,2,3"
|
|
bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem,THRE,RDA,RLS,,,CTI,?..."
|
|
newline
|
|
bitfld.long 0x00 0. " INTSTATUS ,Interrupt status" "Pending,Not pending"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXTL ,Rx trigger level select" "Level 0,Level 1,Level 2,Level 3"
|
|
bitfld.long 0x0 2. " TXFIFORES ,Transmitter FIFO reset" "No effect,Clear"
|
|
bitfld.long 0x0 1. " RXFIFORES ,Receiver FIFO reset" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " FIFOEN ,FIFO enable" "Disable,Enable"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,USART0 Modem Control Register"
|
|
bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LMS ,Loopback mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTSCON ,Source for modem output pin RTS" "Active,Inactive"
|
|
newline
|
|
bitfld.long 0x00 0. " DTRCON ,Source for modem output pin DTR" "Active,Inactive"
|
|
if (((per.l(ad:0x40008000+0x0C))&0x03)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,1.5 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0"
|
|
bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,2 bits"
|
|
bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x00 8. " TXERR ,TX error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " RXFE ,Error in RX FIFO" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " TEMT ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " THRE ,Transmitter holding register empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 4. " BI ,Break interrupt" "Inactive,Active"
|
|
bitfld.long 0x00 3. " FE ,Framing error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " PE ,Parity error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " OE ,Overrun error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " RDR ,Receiver data ready" "Empty,Filled"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x04 "MSR,Modem Status Register"
|
|
in
|
|
group.long 0x1C++0x17
|
|
line.long 0x00 "SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PAD ,A readable/writable byte"
|
|
line.long 0x04 "ACR,Auto-Baud Control Register"
|
|
bitfld.long 0x04 9. " ABTOINTCLR ,Auto-baud timeout interrupt clear bit" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " ABEOINTCLR ,End of auto-baud interrupt clear bit" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " AUTORESTART ,Start mode" "Not restarted,Restarted"
|
|
bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1"
|
|
newline
|
|
bitfld.long 0x04 0. " START ,Auto-baud start" "Stopped,Started"
|
|
line.long 0x08 "ICR,IrDA Control Register"
|
|
bitfld.long 0x08 3.--5. " PULSEDIV ,Pulse width configuration" "3/(16*baud rate),2*Tpclk,4*Tpclk,8*Tpclk,16*Tpclk,32*Tpclk,64*Tpclk,128*Tpclk"
|
|
bitfld.long 0x08 2. " FIXPULSEEN ,IrDA fixed pulse width mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " IRDAINV ,Serial input invert" "Not inverted,Inverted"
|
|
bitfld.long 0x08 0. " IRDAEN ,IrDA mode enable" "Disabled,Enabled"
|
|
line.long 0x0C "FDR,Fractional Divider Register"
|
|
bitfld.long 0x0C 4.--7. " MULVAL ,Baud rate pre-scaler multiplier value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " DIVADDVAL ,Baud rate pre-scaler divisor value" ",None,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
line.long 0x10 "OSR,Oversampling Register"
|
|
hexmask.long.byte 0x10 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field"
|
|
bitfld.long 0x10 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x10 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875"
|
|
line.long 0x14 "TER,Transmit Enable Register"
|
|
bitfld.long 0x14 7. " TXEN ,Transmission enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40008000+0x48))&0x04)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCICTRL,Smart Card Interface Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times"
|
|
bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1"
|
|
newline
|
|
bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4C++0x0B
|
|
line.long 0x00 "RS485CTRL,RS485 Control Register"
|
|
bitfld.long 0x00 5. " OINV ,Polarity control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 4. " DCTRL ,Auto direction control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEL ,Direction control pin select" "RTS,DTR"
|
|
bitfld.long 0x00 2. " AADEN ,Auto address detect enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " RXDIS ,The receiver enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " NMMEN ,Normal Multidrop Mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "RS485ADRMATCH,RS485 Address Match Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ADRMATCH ,Address match value"
|
|
line.long 0x08 "RS485DLY,RS-485 Delay Value Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DLY ,Direction control delay value"
|
|
if (((per.l(ad:0x40008000+0x58))&0x02)==0x02)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
|
|
bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register"
|
|
bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware"
|
|
bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent"
|
|
newline
|
|
bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling"
|
|
bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master"
|
|
bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C-Bus Interface"
|
|
base ad:0x40000000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONSET,Control Set Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_SET/CLR ,I2C-bus interface enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_SET/CLR ,START flag" "Not started,Started"
|
|
bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stopped"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_SET/CLR ,I2C interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_SET/CLR ,Assert acknowledge flag" "Not asserted,Asserted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,Status Register"
|
|
bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "0x00,0x08,0x10,0x18,0x20,0x28,0x30,0x38,0x40,0x48,0x50,0x58,0x60,0x68,0x70,0x78,0x80,0x88,0x90,0x98,0xA0,0xA8,0xB0,0xB8,0xC0,0xC8,,,,,,0xF8"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "DAT,Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data that have been received or is to be transmitted"
|
|
line.long 0x04 "ADR0,Slave Address Register"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Device address in slave mode"
|
|
bitfld.long 0x04 0. " GC ,General call enable bit" "Not recognized,Recognized"
|
|
line.long 0x08 "SCLH,SCL High Duty Cycle Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL high time period selection"
|
|
line.long 0x0C "SCLL,SCL Low Duty Cycle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SCLH ,Count for SCL low time period selection"
|
|
if (((per.l(ad:0x40000000+0x1C))&0x01)==0x01)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MMCTRL,Monitor Mode Control Register"
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address"
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MMCTRL,Monitor Mode Control Register"
|
|
bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "No effect,No effect"
|
|
bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "No effect,No effect"
|
|
bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR1,Slave Address Register 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADR2,Slave Address Register 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADR3,Slave Address Register 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode"
|
|
bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DATA_BUFFER,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Content of the DAT shift register"
|
|
newline
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MASK0,I2C Mask Register 0"
|
|
bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,I2C Mask Register 1"
|
|
bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MASK2,I2C Mask Register 2"
|
|
bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK3,I2C Mask Register 3"
|
|
bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSP (Synchronous Serial Port)"
|
|
sif (cpuis("LPC11A11*")||cpuis("LPC11A12*")||cpuis("LPC11A13*")||cpuis("LPC11A14*"))
|
|
tree "SSP/SSI0"
|
|
base ad:0x40040000
|
|
width 7.
|
|
if (((per.l(ad:0x40040000+0x00))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second"
|
|
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DR,Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
newline
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value"
|
|
line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,TX FIFO half empty interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXIM ,RX FIFO half full interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive timeout" "Not received,Received"
|
|
bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full" "Not received,Received"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,RX FIFO half full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RTMIS ,Receive timeout interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Receive timeout clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clear frame received when RxFIFO full" "No effect,Clear"
|
|
sif cpuis("LPC11U6*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSP/SSI1"
|
|
base ad:0x40058000
|
|
width 7.
|
|
if (((per.l(ad:0x40058000+0x00))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second"
|
|
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
endif
|
|
if (((per.l(ad:0x40058000+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DR,Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
newline
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value"
|
|
line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,TX FIFO half empty interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXIM ,RX FIFO half full interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive timeout" "Not received,Received"
|
|
bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full" "Not received,Received"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,RX FIFO half full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RTMIS ,Receive timeout interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Receive timeout clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clear frame received when RxFIFO full" "No effect,Clear"
|
|
sif cpuis("LPC11U6*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
base ad:0x40040000
|
|
width 7.
|
|
if (((per.l(ad:0x40040000+0x00))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second"
|
|
bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..."
|
|
bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DR,Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full"
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
newline
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value"
|
|
line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x04 3. " TXIM ,TX FIFO half empty interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXIM ,RX FIFO half full interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty" "Not half empty,Half empty"
|
|
bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full" "Not half full,Half full"
|
|
bitfld.long 0x00 1. " RTRIS ,Receive timeout" "Not received,Received"
|
|
bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full" "Not received,Received"
|
|
line.long 0x04 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXMIS ,RX FIFO half full interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " RTMIS ,Receive timeout interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Receive timeout clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clear frame received when RxFIFO full" "No effect,Clear"
|
|
sif cpuis("LPC11U6*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "CT16B0/1 (16-bit counter/timer)"
|
|
tree "CT16B0"
|
|
base ad:0x4000C000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TC,Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "PR,Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PCVAL ,Prescale value"
|
|
line.long 0x08 "PC,Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MCR,Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "MR0,Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "MR1,Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "MR2,Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "MR3,Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CCR,Capture Control Register"
|
|
bitfld.long 0x00 11. " CAP3I ,Generate interrupt on channel 3 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Falling edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Rising edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "CR0,Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x04 "CR1,Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x08 "CR2,Capture Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x0C "CR3,Capture Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CAP ,Timer counter capture value"
|
|
newline
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMR,External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,External match 0" "Low,High"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,Rising analog,Falling analog"
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CAP0,CAP1,CAP2,Analog comparator"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
line.long 0x04 "PWMC,PWM Control register"
|
|
bitfld.long 0x04 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CT16B1"
|
|
base ad:0x40010000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TC,Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value"
|
|
line.long 0x04 "PR,Prescale Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PCVAL ,Prescale value"
|
|
line.long 0x08 "PC,Prescale Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MCR,Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "MR0,Match Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x04 "MR1,Match Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x08 "MR2,Match Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value"
|
|
line.long 0x0C "MR3,Match Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CCR,Capture Control Register"
|
|
bitfld.long 0x00 11. " CAP3I ,Generate interrupt on channel 3 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Falling edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Rising edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "CR0,Capture Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x04 "CR1,Capture Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x08 "CR2,Capture Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CAP ,Timer counter capture value"
|
|
line.long 0x0C "CR3,Capture Register 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CAP ,Timer counter capture value"
|
|
newline
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMR,External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,External match 0" "Low,High"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,Rising analog,Falling analog"
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CAP0,CAP1,CAP2,Analog comparator"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
line.long 0x04 "PWMC,PWM Control register"
|
|
bitfld.long 0x04 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CT32B0/1 (32-bit counter/timer)"
|
|
tree "CT32B0"
|
|
base ad:0x40014000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TC,Timer Counter Register"
|
|
line.long 0x04 "PR,Prescale Register"
|
|
line.long 0x08 "PC,Prescale Counter Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MCR,Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "MR0,Match Register 0"
|
|
line.long 0x04 "MR1,Match Register 1"
|
|
line.long 0x08 "MR2,Match Register 2"
|
|
line.long 0x0C "MR3,Match Register 3"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CCR,Capture Control Register"
|
|
bitfld.long 0x00 11. " CAP3I ,Generate interrupt on channel 3 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Falling edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Rising edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "CR0,Capture Register 0"
|
|
line.long 0x04 "CR1,Capture Register 1"
|
|
line.long 0x08 "CR2,Capture Register 2"
|
|
line.long 0x0C "CR3,Capture Register 3"
|
|
newline
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMR,External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,External match 0" "Low,High"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,Rising analog,Falling analog"
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CAP0,CAP1,CAP2,Analog comparator"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
line.long 0x04 "PWMC,PWM Control register"
|
|
bitfld.long 0x04 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CT32B1"
|
|
base ad:0x40018000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
eventfld.long 0x00 7. " CR3INT ,Interrupt flag for capture channel 3 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "TC,Timer Counter Register"
|
|
line.long 0x04 "PR,Prescale Register"
|
|
line.long 0x08 "PC,Prescale Counter Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MCR,Match Control Register"
|
|
bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "MR0,Match Register 0"
|
|
line.long 0x04 "MR1,Match Register 1"
|
|
line.long 0x08 "MR2,Match Register 2"
|
|
line.long 0x0C "MR3,Match Register 3"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CCR,Capture Control Register"
|
|
bitfld.long 0x00 11. " CAP3I ,Generate interrupt on channel 3 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAP3FE ,Falling edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAP3RE ,Rising edge of capture channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "CR0,Capture Register 0"
|
|
line.long 0x04 "CR1,Capture Register 1"
|
|
line.long 0x08 "CR2,Capture Register 2"
|
|
line.long 0x0C "CR3,Capture Register 3"
|
|
newline
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMR,External Match Register"
|
|
bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled"
|
|
bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,External match 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,External match 0" "Low,High"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,Rising analog,Falling analog"
|
|
bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CIS ,Count input select" "CAP0,CAP1,CAP2,Analog comparator"
|
|
bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both"
|
|
line.long 0x04 "PWMC,PWM Control register"
|
|
bitfld.long 0x04 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SYSTICK (System Tick Timer)"
|
|
base ad:0xE000E000
|
|
width 8.
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "CTRL,System Timer Control And Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,System tick counted to zero" "Not counted,Counted"
|
|
sif cpuis("LPC11D14")||cpuis("LPC11C*")
|
|
bitfld.long 0x00 2. " CLKSOURCE ,System tick clock selection" "System clock/2,System clock"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " TICKINT ,System tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,System tick counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "RELOAD,System Timer Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value loaded into the system tick counter when it counts to 0"
|
|
line.long 0x08 "CURR,System Timer Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current value of the system tick counter"
|
|
line.long 0x0C "CALIB,System Timer Calibration Value Register"
|
|
bitfld.long 0x0C 31. " NOREF ,Indicates that no separate reference clock is provided." "Not provided,Provided"
|
|
bitfld.long 0x0C 30. " SKEW ,SKEW" "Low,High"
|
|
newline
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " TENMS ,System tick calibration value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40004000
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MOD,Watchdog Mode Register"
|
|
bitfld.long 0x00 5. " LOCK ,Prevents disabling or powering down the watchdog oscillator" "Not prevented,Prevented"
|
|
newline
|
|
bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Flexible,Threshold"
|
|
newline
|
|
bitfld.long 0x00 3. " WDINT ,Warning interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 2. " WDTOF ,Watchdog time-out flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " WDEN ,Watchdog enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "TC,Watchdog Timer Constant Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out interval"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FEED,Watchdog Feed Sequence Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value should be 0xAA followed by 0x55"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TV,Watchdog Timer Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CLKSEL,Watchdog Clock Select Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks clock source changing" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,WDOSC"
|
|
line.long 0x04 "WARNINT,Watchdog Timer Warning Interrupt Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value"
|
|
line.long 0x08 "WINDOW,Watchdog Timer Window Register "
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " WINDOW ,Watchdog window value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analog To Digital Converter)"
|
|
base ad:0x4001C000
|
|
width 10.
|
|
if ((per.l(ad:0x4001C000)&0x07800000)==(0x00||0x01000000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,A/D Control Register"
|
|
newline
|
|
bitfld.long 0x00 23.--26. " START ,Start conversion control" "Not started,,Started,,Edge on ATRG0,Edge on AC output,Edge on ATRG1,,Edge on CT32B0_MAT0,,Edge on CT32B0_MAT1,,Edge on CT16B0_MAT0,,Edge on CT16B0_MAT1,?..."
|
|
bitfld.long 0x00 20. " SINGLE_BURST ,Single-burst mode" "Continuous,Single-burst"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
bitfld.long 0x00 16. " BURST ,Burst mode" "Software,Hardware"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider"
|
|
bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,AD.2 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,A/D Control Register"
|
|
bitfld.long 0x00 27. " EDGE ,Start conversion edge" "Rising,Falling"
|
|
newline
|
|
bitfld.long 0x00 23.--26. " START ,Start conversion control" "Not started,,Started,,Edge on ATRG0,Edge on AC output,Edge on ATRG1,,Edge on CT32B0_MAT0,,Edge on CT32B0_MAT1,,Edge on CT16B0_MAT0,,Edge on CT16B0_MAT1,?..."
|
|
bitfld.long 0x00 20. " SINGLE_BURST ,Single-burst mode" "Continuous,Single-burst"
|
|
bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits"
|
|
bitfld.long 0x00 16. " BURST ,Burst mode" "Software,Hardware"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider"
|
|
bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,AD.2 sampling and conversion" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion" "Not selected,Selected"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "GDR,A/D Global Data Register"
|
|
in
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SEL,Select Register"
|
|
bitfld.long 0x00 14.--15. " AD7SEL ,Channel 7 source signal" "AD7,No connection,Temperature sensor,?..."
|
|
bitfld.long 0x00 12.--13. " AD6SEL ,Channel 6 source signal" "AD6,No connection,Internal voltage,?..."
|
|
bitfld.long 0x00 10.--11. " AD5SEL ,Channel 5 source signal" "AD5,No connection,Core voltage,?..."
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "STAT,A/D Status Register"
|
|
bitfld.long 0x00 16. " ADINT ,A/D interrupted flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " OVERRUN[7] ,Mirrors overrun status flag for channel 7" "No overrun,Overrun"
|
|
bitfld.long 0x00 14. " [6] ,Mirrors overrun status flag for channel 6" "No overrun,Overrun"
|
|
bitfld.long 0x00 13. " [5] ,Mirrors overrun status flag for channel 5" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 12. " [4] ,Mirrors overrun status flag for channel 4" "No overrun,Overrun"
|
|
bitfld.long 0x00 11. " [3] ,Mirrors overrun status flag for channel 3" "No overrun,Overrun"
|
|
bitfld.long 0x00 10. " [2] ,Mirrors overrun status flag for channel 2" "No overrun,Overrun"
|
|
bitfld.long 0x00 9. " [1] ,Mirrors overrun status flag for channel 1" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 8. " [0] ,Mirrors overrun status flag for channel 0" "No overrun,Overrun"
|
|
bitfld.long 0x00 7. " DONE[7] ,Mirrors done status flag for channel 7" "Not done,Done"
|
|
bitfld.long 0x00 6. " [6] ,Mirrors done status flag for channel 6" "Not done,Done"
|
|
bitfld.long 0x00 5. " [5] ,Mirrors done status flag for channel 5" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Mirrors done status flag for channel 4" "Not done,Done"
|
|
bitfld.long 0x00 3. " [3] ,Mirrors done status flag for channel 3" "Not done,Done"
|
|
bitfld.long 0x00 2. " [2] ,Mirrors done status flag for channel 2" "Not done,Done"
|
|
bitfld.long 0x00 1. " [1] ,Mirrors done status flag for channel 1" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Mirrors done status flag for channel 0" "Not done,Done"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "INTEN,A/D Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " ADGINTEN ,Source of generated interrupt" "Individual,Global"
|
|
bitfld.long 0x00 7. " ADINTEN[7] ,Conversion completion interrupts for channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Conversion completion interrupts for channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Conversion completion interrupts for channel 5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Conversion completion interrupts for channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Conversion completion interrupts for channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Conversion completion interrupts for channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Conversion completion interrupts for channel 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Conversion completion interrupts for channel 0 enable" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "DR0,A/D Channel 0 Data Register"
|
|
in
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "DR1,A/D Channel 1 Data Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "DR2,A/D Channel 2 Data Register"
|
|
in
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "DR3,A/D Channel 3 Data Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR4,A/D Channel 4 Data Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DR5,A/D Channel 5 Data Register"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "DR6,A/D Channel 6 Data Register"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "DR7,A/D Channel 7 Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC (Digital To Analog Converter)"
|
|
base ad:0x40024000
|
|
width 4.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,D/A Converter Register"
|
|
bitfld.long 0x00 23. " TRIGERD ,Triggered conversion" "Not triggered,Triggered"
|
|
bitfld.long 0x00 21.--22. " EDGESEL ,Trigger edge selection" "Falling,Rising,Both,Both"
|
|
bitfld.long 0x00 17.--19. " TRIG ,Conversion trigger" "Begin on write,AC output,ATRG0,ATRG1,CT32B1_MAT0,CT32B1_MAT1,CT16B1_MAT0,CT16B1_MAT1"
|
|
bitfld.long 0x00 16. " BIAS ,Settling time" "1 us,2.5 us"
|
|
newline
|
|
hexmask.long.word 0x00 6.--15. 1. " VALUE ,Voltage on the AOUT pin"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AC (Analog Comparator)"
|
|
base ad:0x40028000
|
|
width 5.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTL,Comparator Control Register"
|
|
bitfld.long 0x00 25.--26. " HYS ,Controls the hysteresis of the comparator" "None,5 mV,10 mV,20 mV"
|
|
bitfld.long 0x00 23. " COMPEDGE ,Comparator edge-detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " COMPSTAT ,Comparator status" "0,1"
|
|
bitfld.long 0x00 20. " EDGECLR ,Interrupt clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--13. " COMP_VM_SEL ,Selects negative voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACP_I4,ACMP_I5,Internal reference voltage,?..."
|
|
bitfld.long 0x00 8.--10. " COMP_VP_SEL ,Selects positive voltage input" "Voltage ladder output,ACMP_I1,ACMP_I2,ACMP_I3,ACP_I4,ACMP_I5,Internal reference voltage,Temperature sensor"
|
|
bitfld.long 0x00 6. " COMPSA ,Comparator output control" "Directly,Bus clock"
|
|
bitfld.long 0x00 3.--4. " EDGESEL ,This field controls which edges on the comparator output set the COMPEDGE bit" "Falling,Rising,Both,Both"
|
|
line.long 0x04 "LAD,Voltage Ladder Register"
|
|
bitfld.long 0x04 6. " LADREF ,Selects the reference voltage Vref for the voltage ladder" "VDD/VDD(3V3),VDDCMP"
|
|
bitfld.long 0x04 1.--5. " LADSEL ,Voltage ladder value" "V_SS,1xV_ref/31,2xV_ref/31,3xV_ref/31,4xV_ref/31,5xV_ref/31,6xV_ref/31,7xV_ref/31,8xV_ref/31,9xV_ref/31,10xV_ref/31,11xV_ref/31,12xV_ref/31,13xV_ref/31,14xV_ref/31,15xV_ref/31,16xV_ref/31,17xV_ref/31,18xV_ref/31,19xV_ref/31,20xV_ref/31,21xV_ref/31,22xV_ref/31,23xV_ref/31,24xV_ref/31,25xV_ref/31,26xV_ref/31,27xV_ref/31,28xV_ref/31,29xV_ref/31,30xV_ref/31,V_ref"
|
|
bitfld.long 0x04 0. " LADEN ,Voltage ladder enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FMC (Flash Controller)"
|
|
base ad:0x4003C000
|
|
width 11.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FLASHCFG,Flash Configuration Register"
|
|
bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..."
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FMSSTART,Flash Module Signature Start Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 0x01 " START ,Signature generation start address"
|
|
line.long 0x04 "FMSSTOP,Flash Module Signature Stop Register"
|
|
bitfld.long 0x04 17. " SIG_START ,Start control bit for signature generation" "Not started,Started"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " STOP ,BIST stop address divided by 16"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "FMSW0,FMSW0 Register"
|
|
line.long 0x04 "FMSW1,FMSW1 Register"
|
|
line.long 0x08 "FMSW2,FMSW2 Register"
|
|
line.long 0x0C "FMSW3,FMSW3 Register"
|
|
group.long 0x9C++0x07
|
|
line.long 0x00 "EEMSSTART,EEPROM BIST Start Address Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " STARTA ,BIST start address"
|
|
line.long 0x04 "EEMSSTOP,EEPROM BIST Stop Address Register"
|
|
bitfld.long 0x04 31. " STRTBIST ,BIST start bit" "Stopped,Started"
|
|
bitfld.long 0x04 30. " DEVSEL ,BIST device select bit" "Total memory,Single device"
|
|
hexmask.long.word 0x04 0.--13. 0x01 " STOPA ,BIST stop address"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "EEMSSIG,EEPROM BIST Signature Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PARITY_SIG ,BIST 16-bit signature calculated from only the parity bits of the data bytes"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_SIG ,BIST 16-bit signature calculated from only the data bytes"
|
|
rgroup.long 0x0FE0++0x03
|
|
line.long 0x00 "FMSTAT,Flash module status register"
|
|
bitfld.long 0x00 2. " SIG_DONE ,Signature generation completion flag" "Not occurred,Occurred"
|
|
wgroup.long 0x0FE8++0x3
|
|
line.long 0x00 "FMSTATCLR,Flash module status clear register"
|
|
bitfld.long 0x00 2. " SIG_DONE_CLR ,Signature generation completion flag clear" ",Clear"
|
|
width 0x0B
|
|
tree.end
|
|
newline
|