40541 lines
3.2 MiB
40541 lines
3.2 MiB
; --------------------------------------------------------------------------------
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; @Title: K32L On-Chip Peripherals
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; @Props: Released
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; @Author: KMB, PIW
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; @Changelog: 2021-09-10 KMB
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; 2022-02-23 PIW
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: SVD generated, based on: K32L2A31A.svd, K32L2A41A.svd, K32L2B11A.svd,
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; K32L2B21A.svd, K32L2B31A.svd,
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; K32L3A60_cm0plus.svd, K32L3A60_cm4.svd
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; @Core: Cortex-M4, Cortex-M0+
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; @Chip: K32L2A31VLH1A, K32L2A31VLL1A, K32L2A41VLH1A, K32L2A41VLL1A,
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; K32L2B11VFM0A ,K32L2B11VFT0A, K32L2B11VLH0A, K32L2B11VMP0A,
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; K32L2B21VFM0A, K32L2B21VFT0A, K32L2B21VLH0A, K32L2B21VMP0A,
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; K32L2B31VFM0A, K32L2B31VFT0A, K32L2B31VLH0A, K32L2B31VMP0A,
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; K32L3A60VPJ1A-CM0+, K32L3A60VPJ1A-CM4
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perkinetisk32l.per 17736 2024-04-08 09:26:07Z kwisniewski $
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sif (CORENAME()=="CORTEXM0+")
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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|
else
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|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
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|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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|
hgroup.long 0xDA0++0x03
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|
saveout 0xD98 %l 0x2
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|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXM4")
|
|
tree.close "Core Registers (Cortex-M4)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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|
textline " "
|
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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width 6.
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tree "CoreSight Identification Registers"
|
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rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
config 16. 8.
|
|
autoindent.on center tree
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "ADC0 (Analog-to-Digital Converter)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40066000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4003B000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DIFF,Differential Mode Enable" "0: Single-ended conversions and input channels..,1: Differential conversions and input channels.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: When DIFF=0 DADP0 is selected as input when..,1: When DIFF=0 DADP1 is selected as input when..,2: When DIFF=0 DADP2 is selected as input when..,3: When DIFF=0 DADP3 is selected as input when..,4: When DIFF=0 AD4 is selected as input when..,5: When DIFF=0 AD5 is selected as input when..,6: When DIFF=0 AD6 is selected as input when..,7: When DIFF=0 AD7 is selected as input when..,8: When DIFF=0 AD8 is selected as input when..,9: When DIFF=0 AD9 is selected as input when..,10: When DIFF=0 AD10 is selected as input when..,11: When DIFF=0 AD11 is selected as input when..,12: When DIFF=0 AD12 is selected as input when..,13: When DIFF=0 AD13 is selected as input when..,14: When DIFF=0 AD14 is selected as input when..,15: When DIFF=0 AD15 is selected as input when..,16: When DIFF=0 AD16 is selected as input when..,17: When DIFF=0 AD17 is selected as input when..,18: When DIFF=0 AD18 is selected as input when..,19: When DIFF=0 AD19 is selected as input when..,20: When DIFF=0 AD20 is selected as input when..,21: When DIFF=0 AD21 is selected as input when..,22: When DIFF=0 AD22 is selected as input when..,23: When DIFF=0 AD23 is selected as input when..,?,?,26: When DIFF=0 Temp Sensor (single-ended) is..,27: When DIFF=0 Bandgap (single-ended) is..,?,29: When DIFF=0 VREFSH is selected as input when..,30: When DIFF=0 VREFSL is selected as input when..,31: Module is disabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Registers 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DIFF,Differential Mode Enable" "0: Single-ended conversions and input channels..,1: Differential conversions and input channels.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: When DIFF=0 DADP0 is selected as input when..,1: When DIFF=0 DADP1 is selected as input when..,2: When DIFF=0 DADP2 is selected as input when..,3: When DIFF=0 DADP3 is selected as input when..,4: When DIFF=0 AD4 is selected as input when..,5: When DIFF=0 AD5 is selected as input when..,6: When DIFF=0 AD6 is selected as input when..,7: When DIFF=0 AD7 is selected as input when..,8: When DIFF=0 AD8 is selected as input when..,9: When DIFF=0 AD9 is selected as input when..,10: When DIFF=0 AD10 is selected as input when..,11: When DIFF=0 AD11 is selected as input when..,12: When DIFF=0 AD12 is selected as input when..,13: When DIFF=0 AD13 is selected as input when..,14: When DIFF=0 AD14 is selected as input when..,15: When DIFF=0 AD15 is selected as input when..,16: When DIFF=0 AD16 is selected as input when..,17: When DIFF=0 AD17 is selected as input when..,18: When DIFF=0 AD18 is selected as input when..,19: When DIFF=0 AD19 is selected as input when..,20: When DIFF=0 AD20 is selected as input when..,21: When DIFF=0 AD21 is selected as input when..,22: When DIFF=0 AD22 is selected as input when..,23: When DIFF=0 AD23 is selected as input when..,?,?,26: When DIFF=0 Temp Sensor (single-ended) is..,27: When DIFF=0 Bandgap (single-ended) is..,?,29: When DIFF=0 VREFSH is selected as input when..,30: When DIFF=0 VREFSL is selected as input when..,31: Module is disabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 7. "ADLPC,Low-Power Configuration" "0: Normal power configuration,1: Low-power configuration"
|
|
bitfld.long 0x00 5.--6. "ADIV,Clock Divide Select" "0: The divide ratio is 1 and the clock rate is..,1: The divide ratio is 2 and the clock rate is..,2: The divide ratio is 4 and the clock rate is..,3: The divide ratio is 8 and the clock rate is.."
|
|
newline
|
|
bitfld.long 0x00 4. "ADLSMP,Sample Time Configuration" "0: Short sample time,1: Long sample time"
|
|
bitfld.long 0x00 2.--3. "MODE,Conversion mode selection" "0: When DIFF=0,1: When DIFF=0,2: When DIFF=0,3: When DIFF=0"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ADICLK,Input Clock Select" "0: Bus clock,1: Bus clock divided by 2(BUSCLK/2),2: Alternate clock (ALTCLK),3: Asynchronous clock (ADACK)"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFG2,ADC Configuration Register 2"
|
|
bitfld.long 0x00 4. "MUXSEL,ADC Mux Select" "0: ADxxa channels are selected,1: ADxxb channels are selected"
|
|
bitfld.long 0x00 3. "ADACKEN,Asynchronous Clock Output Enable" "0: Asynchronous clock output disabled..,1: Asynchronous clock and clock output is.."
|
|
newline
|
|
bitfld.long 0x00 2. "ADHSC,High-Speed Configuration" "0: Normal conversion sequence selected,1: High-speed conversion sequence selected with.."
|
|
bitfld.long 0x00 0.--1. "ADLSTS,Long Sample Time Select" "0: Default longest sample time 20 extra ADCK..,1: 12 extra ADCK cycles 16 ADCK cycles total..,2: 6 extra ADCK cycles 10 ADCK cycles total..,3: 2 extra ADCK cycles 6 ADCK cycles total.."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RA,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "D,Data result"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RB,ADC Data Result Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "D,Data result"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "CV$1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. "CV,Compare Value"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x00 7. "ADACT,Conversion Active" "0: Conversion not in progress,1: Conversion in progress"
|
|
bitfld.long 0x00 6. "ADTRG,Conversion Trigger Select" "0: Software trigger selected,1: Hardware trigger selected"
|
|
newline
|
|
bitfld.long 0x00 5. "ACFE,Compare Function Enable" "0: Compare function disabled,1: Compare function enabled"
|
|
bitfld.long 0x00 4. "ACFGT,Compare Function Greater Than Enable" "0: Configures less than threshold outside range..,1: Configures greater than or equal to threshold.."
|
|
newline
|
|
bitfld.long 0x00 3. "ACREN,Compare Function Range Enable" "0: Range function disabled,1: Range function enabled"
|
|
bitfld.long 0x00 2. "DMAEN,DMA Enable" "0: DMA is disabled,1: DMA is enabled and will assert the ADC DMA.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "REFSEL,Voltage Reference Selection" "0: Default voltage reference pin pair that is..,1: Alternate reference pair that is VALTH and..,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC3,Status and Control Register 3"
|
|
bitfld.long 0x00 7. "CAL,Calibration" "0,1"
|
|
bitfld.long 0x00 6. "CALF,Calibration Failed Flag" "0: Calibration completed normally,1: Calibration failed"
|
|
newline
|
|
bitfld.long 0x00 3. "ADCO,Continuous Conversion Enable" "0: One conversion or one set of conversions if..,1: Continuous conversions or sets of conversions.."
|
|
bitfld.long 0x00 2. "AVGE,Hardware Average Enable" "0: Hardware average function disabled,1: Hardware average function enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "AVGS,Hardware Average Select" "0: 4 samples averaged,1: 8 samples averaged,2: 16 samples averaged,3: 32 samples averaged"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "OFS,Offset Error Correction Value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PG,ADC Plus-Side Gain Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PG,Plus-Side Gain"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MG,ADC Minus-Side Gain Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MG,Minus-Side Gain"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CLPD,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. "CLPD,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CLPS,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. "CLPS,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CLP4,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLP4,Calibration Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CLP3,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "CLP3,Calibration Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CLP2,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLP2,Calibration Value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CLP1,ADC Plus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLP1,Calibration Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CLP0,ADC Plus-Side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. "CLP0,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CLMD,ADC Minus-Side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. "CLMD,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CLMS,ADC Minus-Side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. "CLMS,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CLM4,ADC Minus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLM4,Calibration Value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CLM3,ADC Minus-Side General Calibration Value Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "CLM3,Calibration Value"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CLM2,ADC Minus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLM2,Calibration Value"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CLM1,ADC Minus-Side General Calibration Value Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLM1,Calibration Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLM0,ADC Minus-Side General Calibration Value Register"
|
|
bitfld.long 0x00 0.--5. "CLM0,Calibration Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "AXBS"
|
|
base ad:0x40004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRS0,Priority Slave Registers"
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRS0,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 30. "HLP,Halt Low Priority" "0: The low power mode request has the highest..,1: The low power mode request has the lowest.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin or rotating priority,?..."
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PRS1,Priority Slave Registers"
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CRS1,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 30. "HLP,Halt Low Priority" "0: The low power mode request has the highest..,1: The low power mode request has the lowest.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin or rotating priority,?..."
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PRS2,Priority Slave Registers"
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CRS2,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 30. "HLP,Halt Low Priority" "0: The low power mode request has the highest..,1: The low power mode request has the lowest.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin or rotating priority,?..."
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PRS3,Priority Slave Registers"
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "CRS3,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 30. "HLP,Halt Low Priority" "0: The low power mode request has the highest..,1: The low power mode request has the lowest.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin or rotating priority,?..."
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PRS4,Priority Slave Registers"
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "CRS4,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 30. "HLP,Halt Low Priority" "0: The low power mode request has the highest..,1: The low power mode request has the lowest.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin or rotating priority,?..."
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x00 0x100 0x200 0x300 0x400 0x500 )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "MGPCR$1,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. "AULB,Arbitrates On Undefined Length Bursts" "0: No arbitration is allowed during an undefined..,1: Arbitration is allowed at any time during an..,2: Arbitration is allowed after four beats of an..,3: Arbitration is allowed after eight beats of..,4: Arbitration is allowed after 16 beats of an..,?..."
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "CAU (Memory Mapped Cryptographic Acceleration Unit (MMCAU))"
|
|
tree "CAU0"
|
|
base ad:0xF0005000
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CAU_DIRECT0,Direct access register 0"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT0,Direct register 0"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CAU_DIRECT1,Direct access register 1"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT1,Direct register 1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CAU_DIRECT2,Direct access register 2"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT2,Direct register 2"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CAU_DIRECT3,Direct access register 3"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT3,Direct register 3"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CAU_DIRECT4,Direct access register 4"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT4,Direct register 4"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "CAU_DIRECT5,Direct access register 5"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT5,Direct register 5"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "CAU_DIRECT6,Direct access register 6"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT6,Direct register 6"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CAU_DIRECT7,Direct access register 7"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT7,Direct register 7"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "CAU_DIRECT8,Direct access register 8"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT8,Direct register 8"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "CAU_DIRECT9,Direct access register 9"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT9,Direct register 9"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "CAU_DIRECT10,Direct access register 10"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT10,Direct register 10"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "CAU_DIRECT11,Direct access register 11"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT11,Direct register 11"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "CAU_DIRECT12,Direct access register 12"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT12,Direct register 12"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "CAU_DIRECT13,Direct access register 13"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT13,Direct register 13"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "CAU_DIRECT14,Direct access register 14"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT14,Direct register 14"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "CAU_DIRECT15,Direct access register 15"
|
|
hexmask.long 0x00 0.--31. 1. "CAU_DIRECT15,Direct register 15"
|
|
wgroup.long 0x840++0x03
|
|
line.long 0x00 "CAU_LDR_CASR,Status register - Load Register command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0x844++0x03
|
|
line.long 0x00 "CAU_LDR_CAA,Accumulator register - Load Register command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0x848++0x03
|
|
line.long 0x00 "CAU_LDR_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0x84C++0x03
|
|
line.long 0x00 "CAU_LDR_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0x850++0x03
|
|
line.long 0x00 "CAU_LDR_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0x854++0x03
|
|
line.long 0x00 "CAU_LDR_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0x858++0x03
|
|
line.long 0x00 "CAU_LDR_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0x85C++0x03
|
|
line.long 0x00 "CAU_LDR_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0x860++0x03
|
|
line.long 0x00 "CAU_LDR_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0x864++0x03
|
|
line.long 0x00 "CAU_LDR_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0x868++0x03
|
|
line.long 0x00 "CAU_LDR_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "CAU_STR_CASR,Status register - Store Register command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
rgroup.long 0x884++0x03
|
|
line.long 0x00 "CAU_STR_CAA,Accumulator register - Store Register command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
rgroup.long 0x888++0x03
|
|
line.long 0x00 "CAU_STR_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
rgroup.long 0x88C++0x03
|
|
line.long 0x00 "CAU_STR_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
rgroup.long 0x890++0x03
|
|
line.long 0x00 "CAU_STR_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
rgroup.long 0x894++0x03
|
|
line.long 0x00 "CAU_STR_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
rgroup.long 0x898++0x03
|
|
line.long 0x00 "CAU_STR_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
rgroup.long 0x89C++0x03
|
|
line.long 0x00 "CAU_STR_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "CAU_STR_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
rgroup.long 0x8A4++0x03
|
|
line.long 0x00 "CAU_STR_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "CAU_STR_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
wgroup.long 0x8C0++0x03
|
|
line.long 0x00 "CAU_ADR_CASR,Status register - Add Register command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0x8C4++0x03
|
|
line.long 0x00 "CAU_ADR_CAA,Accumulator register - Add to register command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0x8C8++0x03
|
|
line.long 0x00 "CAU_ADR_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0x8CC++0x03
|
|
line.long 0x00 "CAU_ADR_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0x8D0++0x03
|
|
line.long 0x00 "CAU_ADR_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0x8D4++0x03
|
|
line.long 0x00 "CAU_ADR_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0x8D8++0x03
|
|
line.long 0x00 "CAU_ADR_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0x8DC++0x03
|
|
line.long 0x00 "CAU_ADR_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0x8E0++0x03
|
|
line.long 0x00 "CAU_ADR_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0x8E4++0x03
|
|
line.long 0x00 "CAU_ADR_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0x8E8++0x03
|
|
line.long 0x00 "CAU_ADR_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
wgroup.long 0x900++0x03
|
|
line.long 0x00 "CAU_RADR_CASR,Status register - Reverse and Add to Register command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0x904++0x03
|
|
line.long 0x00 "CAU_RADR_CAA,Accumulator register - Reverse and Add to Register command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0x908++0x03
|
|
line.long 0x00 "CAU_RADR_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0x90C++0x03
|
|
line.long 0x00 "CAU_RADR_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0x910++0x03
|
|
line.long 0x00 "CAU_RADR_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0x914++0x03
|
|
line.long 0x00 "CAU_RADR_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0x918++0x03
|
|
line.long 0x00 "CAU_RADR_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0x91C++0x03
|
|
line.long 0x00 "CAU_RADR_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0x920++0x03
|
|
line.long 0x00 "CAU_RADR_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0x924++0x03
|
|
line.long 0x00 "CAU_RADR_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0x928++0x03
|
|
line.long 0x00 "CAU_RADR_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
wgroup.long 0x980++0x03
|
|
line.long 0x00 "CAU_XOR_CASR,Status register - Exclusive Or command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0x984++0x03
|
|
line.long 0x00 "CAU_XOR_CAA,Accumulator register - Exclusive Or command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0x988++0x03
|
|
line.long 0x00 "CAU_XOR_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0x98C++0x03
|
|
line.long 0x00 "CAU_XOR_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0x990++0x03
|
|
line.long 0x00 "CAU_XOR_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0x994++0x03
|
|
line.long 0x00 "CAU_XOR_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0x998++0x03
|
|
line.long 0x00 "CAU_XOR_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0x99C++0x03
|
|
line.long 0x00 "CAU_XOR_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0x9A0++0x03
|
|
line.long 0x00 "CAU_XOR_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0x9A4++0x03
|
|
line.long 0x00 "CAU_XOR_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0x9A8++0x03
|
|
line.long 0x00 "CAU_XOR_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
wgroup.long 0x9C0++0x03
|
|
line.long 0x00 "CAU_ROTL_CASR,Status register - Rotate Left command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0x9C4++0x03
|
|
line.long 0x00 "CAU_ROTL_CAA,Accumulator register - Rotate Left command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0x9C8++0x03
|
|
line.long 0x00 "CAU_ROTL_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0x9CC++0x03
|
|
line.long 0x00 "CAU_ROTL_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0x9D0++0x03
|
|
line.long 0x00 "CAU_ROTL_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0x9D4++0x03
|
|
line.long 0x00 "CAU_ROTL_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0x9D8++0x03
|
|
line.long 0x00 "CAU_ROTL_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0x9DC++0x03
|
|
line.long 0x00 "CAU_ROTL_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0x9E0++0x03
|
|
line.long 0x00 "CAU_ROTL_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0x9E4++0x03
|
|
line.long 0x00 "CAU_ROTL_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0x9E8++0x03
|
|
line.long 0x00 "CAU_ROTL_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
wgroup.long 0xB00++0x03
|
|
line.long 0x00 "CAU_AESC_CASR,Status register - AES Column Operation command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0xB04++0x03
|
|
line.long 0x00 "CAU_AESC_CAA,Accumulator register - AES Column Operation command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0xB08++0x03
|
|
line.long 0x00 "CAU_AESC_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0xB0C++0x03
|
|
line.long 0x00 "CAU_AESC_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0xB10++0x03
|
|
line.long 0x00 "CAU_AESC_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0xB14++0x03
|
|
line.long 0x00 "CAU_AESC_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0xB18++0x03
|
|
line.long 0x00 "CAU_AESC_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0xB1C++0x03
|
|
line.long 0x00 "CAU_AESC_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0xB20++0x03
|
|
line.long 0x00 "CAU_AESC_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0xB24++0x03
|
|
line.long 0x00 "CAU_AESC_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0xB28++0x03
|
|
line.long 0x00 "CAU_AESC_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
wgroup.long 0xB40++0x03
|
|
line.long 0x00 "CAU_AESIC_CASR,Status register - AES Inverse Column Operation command"
|
|
bitfld.long 0x00 28.--31. "VER,CAU version" "?,1: Initial CAU version,2: Second version added support for SHA-256..,?..."
|
|
bitfld.long 0x00 1. "DPE,no description available" "0: No error detected,1: DES key parity error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,no description available" "0: No illegal commands issued,1: Illegal command issued"
|
|
wgroup.long 0xB44++0x03
|
|
line.long 0x00 "CAU_AESIC_CAA,Accumulator register - AES Inverse Column Operation command"
|
|
hexmask.long 0x00 0.--31. 1. "ACC,ACC"
|
|
wgroup.long 0xB48++0x03
|
|
line.long 0x00 "CAU_AESIC_CA0,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA0,CA0"
|
|
wgroup.long 0xB4C++0x03
|
|
line.long 0x00 "CAU_AESIC_CA1,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA1,CA1"
|
|
wgroup.long 0xB50++0x03
|
|
line.long 0x00 "CAU_AESIC_CA2,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA2,CA2"
|
|
wgroup.long 0xB54++0x03
|
|
line.long 0x00 "CAU_AESIC_CA3,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA3,CA3"
|
|
wgroup.long 0xB58++0x03
|
|
line.long 0x00 "CAU_AESIC_CA4,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA4,CA4"
|
|
wgroup.long 0xB5C++0x03
|
|
line.long 0x00 "CAU_AESIC_CA5,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA5,CA5"
|
|
wgroup.long 0xB60++0x03
|
|
line.long 0x00 "CAU_AESIC_CA6,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA6,CA6"
|
|
wgroup.long 0xB64++0x03
|
|
line.long 0x00 "CAU_AESIC_CA7,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA7,CA7"
|
|
wgroup.long 0xB68++0x03
|
|
line.long 0x00 "CAU_AESIC_CA8,General Purpose Register"
|
|
hexmask.long 0x00 0.--31. 1. "CA8,CA8"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "CAU3"
|
|
base ad:0x41028000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PCT,Processor Core Type"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ID,Module ID number"
|
|
bitfld.long 0x00 4.--7. "X,Major version number" "0: Major version number,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "Y,Minor version number" "0: Minor version number,?..."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MCFG,Memory Configuration"
|
|
bitfld.long 0x00 24.--27. "IRAM_SZ,Instruction RAM Size" "0: No memory module,?,?,?,4: IRAM_SZ_4,5: IRAM_SZ_5,6: IRAM_SZ_6,7: IRAM_SZ_7,8: IRAM_SZ_8,9: IRAM_SZ_9,10: IRAM_SZ_10,11: IRAM_SZ_11,12: IRAM_SZ_12,13: IRAM_SZ_13,14: IRAM_SZ_14,15: IRAM_SZ_15"
|
|
bitfld.long 0x00 16.--19. "IROM_SZ,Instruction ROM Size" "0: No memory module,?,?,?,4: IROM_SZ_4,5: IROM_SZ_5,6: IROM_SZ_6,7: IROM_SZ_7,8: IROM_SZ_8,9: IROM_SZ_9,10: IROM_SZ_10,11: IROM_SZ_11,12: IROM_SZ_12,13: IROM_SZ_13,14: IROM_SZ_14,15: IROM_SZ_15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DRAM_SZ,Data RAM Size" "0: No memory module,?,?,?,4: DRAM_SZ_4,5: DRAM_SZ_5,6: DRAM_SZ_6,7: DRAM_SZ_7,8: DRAM_SZ_8,9: DRAM_SZ_9,10: DRAM_SZ_10,11: DRAM_SZ_11,12: DRAM_SZ_12,13: DRAM_SZ_13,14: DRAM_SZ_14,15: DRAM_SZ_15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: CAU3 exits from low power mode,1: CAU3 enters low power mode"
|
|
bitfld.long 0x00 30. "DAESI,Disable AES Instructions" "0: AES instructions are enabled,1: AES instructions are disabled"
|
|
newline
|
|
bitfld.long 0x00 29. "DDESI,Disable DES Instructions" "0: DES instructions are enabled,1: DES instructions are disabled"
|
|
bitfld.long 0x00 28. "DSHFI,Disable Secure Hash Function Instructions" "0: Secure Hash Functions are enabled,1: Secure Hash Functions are disabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DTCCFG,Default Task Completion Configuration" "0: no explicit action,1: Issue an Interrupt Request,2: Assert Event Completion Signal,?,4: Issue a DMA request,?..."
|
|
bitfld.long 0x00 16. "FSV,Force Security Violation Test" "0: no violation is forced,1: force security violation"
|
|
newline
|
|
bitfld.long 0x00 15. "MRST,Module Reset" "0: no action,1: MRST_1"
|
|
bitfld.long 0x00 12.--13. "RSTSM4,Reset Semaphore" "0: Idle state,1: Wait for second,2: Clears semaphore if previous state was 01,?..."
|
|
newline
|
|
bitfld.long 0x00 7. "TCIE,Task completion with no error interrupt enable" "0: Disables task completion with no error to..,1: Enables task completion with no error to.."
|
|
bitfld.long 0x00 6. "SVIE,Security Violation Interrupt Enable" "0: Security violation interruption is not enabled,1: Security violation interruption is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DIADIE,DMEM Illegal Address Interrupt Enable" "0: DMEM illegal address interruption is not..,1: DMEM illegal address interruption is enabled"
|
|
bitfld.long 0x00 4. "IIADIE,IMEM Illegal Address Interrupt Enable" "0: IMEM illegal address interruption is not..,1: IMEM illegal address interruption is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "ASREIE,AHB Slave Response Error Interrupt Enable" "0: AHB slave response error interruption is not..,1: AHB slave response error interruption is.."
|
|
bitfld.long 0x00 1. "ILLIE,Illegal Instruction Interrupt Enable" "0: Illegal instruction interrupt requests are..,1: illegal Instruction interrupt requests are.."
|
|
newline
|
|
bitfld.long 0x00 0. "TCSEIE,Task completion with software error interrupt enable" "0: Disables task completion with software error..,1: Enables task completion with software error.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 31. "MDISF,Module disable flag" "0: CCore is not in low power mode,1: CCore is in low power mode"
|
|
rbitfld.long 0x00 24.--26. "TCCFG,Task completion configuration" "0: No action,1: Assert an interrupt request,2: Assert the Event Completion Signal,?,4: Issue a DMA request,?..."
|
|
newline
|
|
rbitfld.long 0x00 17. "DBG,Debug mode" "0: CAU3 is not in debug mode,1: CAU3 is in debug mode"
|
|
rbitfld.long 0x00 16. "SVF,Security violation flag" "0: SoC security violation is not asserted,1: SoC security violation was asserted"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TKCS,Task completion status" "0: Initialization RUN,1: Running,2: Debug Halted,?,?,?,?,?,?,9: Stop - Error Free,10: Stop - Error,?,?,?,14: Stop - Security Violation assert security..,15: Stop - Security Violation and set SVIRQ"
|
|
eventfld.long 0x00 7. "TCIRQ,Task completion with no error interrupt request" "0: Task not finished or finished with error,1: Task execution finished with no error"
|
|
newline
|
|
eventfld.long 0x00 6. "SVIRQ,Security violation interrupt request" "0: No security violation,1: Security violation"
|
|
eventfld.long 0x00 5. "DIADIRQ,DMEM illegal access interrupt request" "0: no illegal address,1: illegal address"
|
|
newline
|
|
eventfld.long 0x00 4. "IIADIRQ,IMEM Illegal address interrupt request" "0: IIADIRQ_0,1: illegal IMEM address detected"
|
|
eventfld.long 0x00 3. "ASREIRQ,AHB slave response error interrupt Request" "0: ASREIRQ_0,1: AHB slave response error detected"
|
|
newline
|
|
eventfld.long 0x00 1. "ILLIRQ,Illegal instruction interrupt request" "0: ILLIRQ_0,1: illegal instruction detected"
|
|
eventfld.long 0x00 0. "TCSEIRQ,Task completion with software error interrupt request" "0: Task not finished or finished with no..,1: Task execution finished with software error"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DBGCSR,Debug Control/Status Register"
|
|
rbitfld.long 0x00 31. "CHLTF,CryptoCore is Halted Status Flag" "0: CryptoCore is not halted,1: CryptoCore is halted"
|
|
rbitfld.long 0x00 30. "CSTPF,CryptoCore is Stopped Status Flag" "0: CryptoCore is not stopped,1: CryptoCore is stopped"
|
|
newline
|
|
rbitfld.long 0x00 18. "HLTIF,CryptoCore is Halted due to HALT Instruction" "0: CryptoCore is not in software breakpoint,1: CryptoCore is in software breakpoint"
|
|
rbitfld.long 0x00 17. "SIMHF,CryptoCore is Halted due to Single Instruction Step" "0: CryptoCore is not in a single step halt,1: CryptoCore is in a single step halt"
|
|
newline
|
|
rbitfld.long 0x00 16. "PCBHF,CryptoCore is Halted due to Hardware Breakpoint" "0: CryptoCore is not halted due to a hardware..,1: CryptoCore is halted due to a hardware.."
|
|
bitfld.long 0x00 12. "DBGGO,Debug Go" "0: No action,1: Resume program execution"
|
|
newline
|
|
bitfld.long 0x00 8. "FRCH,Force Debug Halt" "0: Halt state not forced,1: Force halt state"
|
|
bitfld.long 0x00 5. "SIM,Single Instruction Mode" "0: Single instruction mode is disabled,1: Single instruction mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "PBREN,PC Breakpoint Register Enable" "0: PC breakpoint register (DBGPBR) is disabled,1: PC breakpoint register (DBGPBR) is enabled"
|
|
bitfld.long 0x00 1. "DDBGMC,Disable Debug Memory Commands" "0: IPS access to IMEM and DMEM are enabled,1: IPS access to IMEM and DMEM are disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "DDBG,Debug Disable" "0: debug is enabled,1: debug is disabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DBGPBR,Debug PC Breakpoint Register"
|
|
hexmask.long.tbyte 0x00 2.--19. 1. "PCBKPT,PC Breakpoint"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DBGMCMD,Debug Memory Command Register"
|
|
rbitfld.long 0x00 31. "R_1,Read always as 1" "0,1"
|
|
rbitfld.long 0x00 30. "R_0,Read always as 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "BV,Byte Reversal Control" "0: DMEM bytes are not reversed,1: DMEM bytes are reversed"
|
|
rbitfld.long 0x00 27. "Rb_1,Read always as 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "IA,Increment Address" "0: Address is not incremented,1: Address is incremented after the access"
|
|
bitfld.long 0x00 24. "DM,Instruction/Data Memory Selection" "0: IMEM is selected,1: DMEM is selected"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DBGMADR,Debug Memory Address Register"
|
|
hexmask.long 0x00 2.--31. 1. "DMADDR,Debug Memory Address"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DBGMDR,Debug Memory Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMDATA,Debug Memory Data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "SEMA4,Semaphore Register"
|
|
bitfld.long 0x00 31. "LK,Semaphore Lock and Release Control" "0: Semaphore release,1: Semaphore lock"
|
|
rbitfld.long 0x00 8.--13. "MSTRN,Master Number of Locked Semaphore Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 7. "NS,Non Secure Attribute of the Locked Semaphore Owner" "0: If semaphore is locked owner is operating in..,1: If semaphore is locked owner is operating in.."
|
|
rbitfld.long 0x00 6. "PR,Privilege Attribute of Locked Semaphore Owner" "0: If semaphore is locked then owner is..,1: If semaphore is locked then owner is.."
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "DID,Domain ID of Locked Semaphore Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "SMOWNR,Semaphore Ownership Register"
|
|
bitfld.long 0x00 31. "NOWNER,Semaphore Ownership" "0: The host making the current read access is..,1: The host making the current read access is.."
|
|
bitfld.long 0x00 0. "LOCK,Semaphore Locked" "0: Semaphore not locked,1: Semaphore locked"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ARR,Address Remap Register"
|
|
hexmask.long 0x00 0.--31. 1. "ARRL,Address Remap Register List"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "CC_R$1,CryptoCore General Purpose Registers"
|
|
hexmask.long 0x00 0.--31. 1. "R,CryptoCore general purpose register R"
|
|
repeat.end
|
|
repeat 14. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "CC_R$1,CryptoCore General Purpose Registers"
|
|
hexmask.long 0x00 0.--31. 1. "R,CryptoCore general purpose register R"
|
|
repeat.end
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CC_R30,General Purpose R30"
|
|
hexmask.long 0x00 0.--31. 1. "SP,Stack Pointer"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CC_R31,General Purpose R31"
|
|
hexmask.long 0x00 0.--31. 1. "LR,Link"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CC_PC,Program Counter"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "PC,Program Counter"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CC_CMD,Start Command Register"
|
|
bitfld.long 0x00 16.--18. "CMD,Command" "0: Use CR[DTCCFG] for task completion..,1: Issue an interrupt request,2: Assert Event Completion Signal,?,4: Issue a DMA request,?..."
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "CC_CF,Condition Flag"
|
|
bitfld.long 0x00 3. "N,Negative flag" "0,1"
|
|
bitfld.long 0x00 2. "Z,Zero flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "V,Overflow flag" "0,1"
|
|
bitfld.long 0x00 0. "C,Carry flag" "0,1"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "MDPK,Mode Register (PublicKey)"
|
|
bitfld.long 0x00 20.--23. "ALG,Algorithm" "?,?,?,?,?,?,?,?,8: PKHA,?..."
|
|
bitfld.long 0x00 16.--19. "PKHA_MODE_MS,PKHA_MODE most-significant 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "PKHA_MODE_LS,PKHA_MODE least significant 12 bits"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "COM,Command Register"
|
|
bitfld.long 0x00 6. "PK,Reset PKHA" "0: Do Not Reset,1: Reset Public Key Hardware Accelerator"
|
|
bitfld.long 0x00 0. "ALL,Reset All Internal Logic" "0: Do Not Reset,1: Reset PKHA engine and registers"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 4. "PDE,PKHA Register DMA Enable" "0: DMA Request and Done signals disabled for the..,1: DMA Request and Done signals enabled for the.."
|
|
bitfld.long 0x00 0. "IM,Interrupt Mask" "0: Interrupt not masked,1: Interrupt masked"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "CW,Clear Written Register"
|
|
bitfld.long 0x00 15. "CPKE,Clear the PKHA E Size Register" "0,1"
|
|
bitfld.long 0x00 14. "CPKN,Clear the PKHA N Size Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CPKB,Clear the PKHA B Size Register" "0,1"
|
|
bitfld.long 0x00 12. "CPKA,Clear the PKHA A Size Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CM,Clear the Mode Register" "0,1"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "STA,Status Register"
|
|
rbitfld.long 0x00 30. "PKZ,Public Key Operation is Zero" "0,1"
|
|
rbitfld.long 0x00 29. "PKO,Public Key Operation is One" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 28. "PKP,Public Key is Prime" "0,1"
|
|
rbitfld.long 0x00 20. "EI,Error Interrupt" "0: NOT_ERROR_INT,1: Error Interrupt"
|
|
newline
|
|
eventfld.long 0x00 16. "DI,Done Interrupt" "0,1"
|
|
rbitfld.long 0x00 6. "PB,PKHA Busy" "0: PKHA_IDLE,1: PKHA Busy"
|
|
rgroup.long 0x44C++0x03
|
|
line.long 0x00 "ESTA,Error Status Register"
|
|
bitfld.long 0x00 8.--11. "CL1,algorithms" "0: General Error,?,?,?,?,?,?,?,8: PKHA_ERROR,?..."
|
|
bitfld.long 0x00 0.--3. "ERRID1,Error ID 1" "?,1: MODE_ERROR,2: PKHA N Register Size Error,3: PKHA E Register Size Error,4: PKHA A Register Size Error,5: PKHA B Register Size Error,6: PKHA C input (as contained in the PKHA B0..,7: PKHA Divide by Zero Error,8: PKHA Modulus Even Error,?,?,?,?,?,?,15: Invalid Crypto Engine Selected"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "PKASZ,PKHA A Size Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PKASZ,PKHA A Size"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "PKBSZ,PKHA B Size Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PKBSZ,PKHA B Size"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "PKNSZ,PKHA N Size Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PKNSZ,PKHA N Size"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "PKESZ,PKHA E Size Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PKESZ,PKHA E Size"
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "PKHA_VID1,PKHA Revision ID 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "IP_ID,Hardware Revision ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MAJ_REV,Major Revision Number"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "MIN_REV,Minor Revision Number"
|
|
rgroup.long 0x4F4++0x03
|
|
line.long 0x00 "PKHA_VID2,PKHA Revision ID 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ARCH_ERA,Architecture ERA"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ECO_REV,ECO Revision Number"
|
|
rgroup.long 0x4F8++0x03
|
|
line.long 0x00 "CHA_VID,CHA Revision ID"
|
|
bitfld.long 0x00 20.--23. "PKHAVID,PK Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PKHAREV,PK Revision NUmber" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "PKHA_CCR,PKHA Clock Control Register"
|
|
bitfld.long 0x00 31. "ECT,Enable Clock Throttle" "0: PKHA clock throttle disabled meaning that..,1: PKHA clock throttle enabled"
|
|
bitfld.long 0x00 30. "ECJ,Enable Clock Jitter" "0: Clock Jitter is disabled,1: Clock jitter is enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "ELFR,Enable Linear Feedback Shift Register" "0: LFSR is only enabled if ECT = 1 and ECJ = 1,1: LFSR is enabled independently of ECT and ECJ"
|
|
bitfld.long 0x00 24. "LK,Register Lock" "0: Register is unlocked,1: Register is locked"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CKTHRT,Clock Throttle selection" "0: PKHA clock division rate is 8/8 - full speed,1: PKHA clock division rate is 1/8,2: PKHA clock division rate is 2/8,3: PKHA clock division rate is 3/8,4: PKHA clock division rate is 4/8,5: PKHA clock division rate is 5/8,6: PKHA clock division rate is 6/8,7: PKHA clock division rate is 7/8"
|
|
rgroup.long 0x604++0x03
|
|
line.long 0x00 "GSR,Global Status Register"
|
|
bitfld.long 0x00 31. "PBSY,PKHA Busy" "0: PKHA not busy,1: PKHA busy"
|
|
bitfld.long 0x00 15. "PEI,PKHA Done or Error Interrupt" "0: PKHA interrupt did not occur,1: PKHA interrupt had occurred"
|
|
newline
|
|
bitfld.long 0x00 14. "CEI,CAU3 Error Interrupt" "0: CAU3 Error Interrupt did not occur,1: CAU3 Error Interrupt occurred"
|
|
bitfld.long 0x00 10. "CDI,CAU3 Done Interrupt occurred" "0: CAU3 Done Interrupt did not occur,1: CAU3 Done Interrupt occurred"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "CKLFSR,Clock Linear Feedback Shift Register"
|
|
hexmask.long 0x00 0.--31. 1. "LFSR,Linear Feedback Shift Register"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "PKA0_$1,PKHA A0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A0,A0 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x840)++0x03
|
|
line.long 0x00 "PKA0_$1,PKHA A0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A0,A0 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "PKA1_$1,PKHA A1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A1,A1 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x8C0)++0x03
|
|
line.long 0x00 "PKA1_$1,PKHA A1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A1,A1 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x900)++0x03
|
|
line.long 0x00 "PKA2_$1,PKHA A2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A2,A2 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x940)++0x03
|
|
line.long 0x00 "PKA2_$1,PKHA A2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A2,A2 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x980)++0x03
|
|
line.long 0x00 "PKA3_$1,PKHA A3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A3,A3 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x9C0)++0x03
|
|
line.long 0x00 "PKA3_$1,PKHA A3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_A3,A3 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xA00)++0x03
|
|
line.long 0x00 "PKB0_$1,PKHA B0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B0,B0 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xA40)++0x03
|
|
line.long 0x00 "PKB0_$1,PKHA B0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B0,B0 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xA80)++0x03
|
|
line.long 0x00 "PKB1_$1,PKHA B1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B1,B1 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xAC0)++0x03
|
|
line.long 0x00 "PKB1_$1,PKHA B1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B1,B1 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xB00)++0x03
|
|
line.long 0x00 "PKB2_$1,PKHA B2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B2,B2 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xB40)++0x03
|
|
line.long 0x00 "PKB2_$1,PKHA B2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B2,B2 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xB80)++0x03
|
|
line.long 0x00 "PKB3_$1,PKHA B3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B3,B3 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xBC0)++0x03
|
|
line.long 0x00 "PKB3_$1,PKHA B3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_B3,B3 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xC00)++0x03
|
|
line.long 0x00 "PKN0_$1,PKHA N0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N0,N0 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xC40)++0x03
|
|
line.long 0x00 "PKN0_$1,PKHA N0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N0,N0 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xC80)++0x03
|
|
line.long 0x00 "PKN1_$1,PKHA N1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N1,N1 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xCC0)++0x03
|
|
line.long 0x00 "PKN1_$1,PKHA N1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N1,N1 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xD00)++0x03
|
|
line.long 0x00 "PKN2_$1,PKHA N2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N2,N2 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xD40)++0x03
|
|
line.long 0x00 "PKN2_$1,PKHA N2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N2,N2 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xD80)++0x03
|
|
line.long 0x00 "PKN3_$1,PKHA N3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N3,N3 VALUE"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xDC0)++0x03
|
|
line.long 0x00 "PKN3_$1,PKHA N3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_N3,N3 VALUE"
|
|
repeat.end
|
|
repeat 128. (increment 0 1) (increment 0 0x04)
|
|
wgroup.long ($2+0xE00)++0x03
|
|
line.long 0x00 "PKE_[$1],PKHA E Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "PKHA_E,E VALUE"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "CMP (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX))"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "CMP0"
|
|
base ad:0x4006E000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: One sample must agree,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.byte 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3"
|
|
sif cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: One sample must agree,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.byte 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "CR1,CMP Control Register 1"
|
|
bitfld.byte 0x00 7. "SE,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
|
|
bitfld.byte 0x00 6. "WE,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
|
|
newline
|
|
bitfld.byte 0x00 5. "TRIGM,Trigger Mode Enable" "0: Trigger mode is disabled,1: Trigger mode is enabled"
|
|
bitfld.byte 0x00 4. "PMODE,Power Mode Select" "0: Low-Speed (LS) Comparison mode selected,1: High-Speed (HS) Comparison mode selected"
|
|
newline
|
|
bitfld.byte 0x00 3. "INV,Comparator INVERT" "0: Does not invert the comparator output,1: Inverts the comparator output"
|
|
bitfld.byte 0x00 2. "COS,Comparator Output Select" "0: Set the filtered comparator output (CMPO) to..,1: Set the unfiltered comparator output (CMPO).."
|
|
newline
|
|
bitfld.byte 0x00 1. "OPE,Comparator Output Pin Enable" "0: CMPO is not available on the associated CMPO..,1: CMPO is available on the associated CMPO.."
|
|
bitfld.byte 0x00 0. "EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "FPR,CMP Filter Period Register"
|
|
hexmask.byte 0x00 0.--7. 1. "FILT_PER,Filter Sample Period"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SCR,CMP Status and Control Register"
|
|
bitfld.byte 0x00 6. "DMAEN,DMA Enable Control" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.byte 0x00 4. "IER,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. "IEF,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.byte 0x00 2. "CFR,Analog Comparator Flag Rising" "0: Rising-edge on COUT has not been detected,1: Rising-edge on COUT has occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. "CFF,Analog Comparator Flag Falling" "0: Falling-edge on COUT has not been detected,1: Falling-edge on COUT has occurred"
|
|
rbitfld.byte 0x00 0. "COUT,Analog Comparator Output" "0,1"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DACCR,DAC Control Register"
|
|
bitfld.byte 0x00 7. "DACEN,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
|
|
bitfld.byte 0x00 6. "VRSEL,Supply Voltage Reference Source Select" "0: Vin1 is selected as resistor ladder network..,1: Vin2 is selected as resistor ladder network.."
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "VOSEL,DAC Output Voltage Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MUXCR,MUX Control Register"
|
|
bitfld.byte 0x00 7. "PSTM,Pass Through Mode Enable" "0: Pass Through Mode is disabled,1: Pass Through Mode is enabled"
|
|
bitfld.byte 0x00 3.--5. "PSEL,Plus Input Mux Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "MSEL,Minus Input Mux Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "CMP0"
|
|
base ad:0x40073000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: One sample must agree,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.byte 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3"
|
|
sif cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: One sample must agree,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.byte 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "CR1,CMP Control Register 1"
|
|
bitfld.byte 0x00 7. "SE,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
|
|
bitfld.byte 0x00 6. "WE,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
|
|
newline
|
|
bitfld.byte 0x00 5. "TRIGM,Trigger Mode Enable" "0: Trigger mode is disabled,1: Trigger mode is enabled"
|
|
bitfld.byte 0x00 4. "PMODE,Power Mode Select" "0: Low-Speed (LS) Comparison mode selected,1: High-Speed (HS) Comparison mode selected"
|
|
newline
|
|
bitfld.byte 0x00 3. "INV,Comparator INVERT" "0: Does not invert the comparator output,1: Inverts the comparator output"
|
|
bitfld.byte 0x00 2. "COS,Comparator Output Select" "0: Set the filtered comparator output (CMPO) to..,1: Set the unfiltered comparator output (CMPO).."
|
|
newline
|
|
bitfld.byte 0x00 1. "OPE,Comparator Output Pin Enable" "0: CMPO is not available on the associated CMPO..,1: CMPO is available on the associated CMPO.."
|
|
bitfld.byte 0x00 0. "EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "FPR,CMP Filter Period Register"
|
|
hexmask.byte 0x00 0.--7. 1. "FILT_PER,Filter Sample Period"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SCR,CMP Status and Control Register"
|
|
bitfld.byte 0x00 6. "DMAEN,DMA Enable Control" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.byte 0x00 4. "IER,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. "IEF,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.byte 0x00 2. "CFR,Analog Comparator Flag Rising" "0: Rising-edge on COUT has not been detected,1: Rising-edge on COUT has occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. "CFF,Analog Comparator Flag Falling" "0: Falling-edge on COUT has not been detected,1: Falling-edge on COUT has occurred"
|
|
rbitfld.byte 0x00 0. "COUT,Analog Comparator Output" "0,1"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DACCR,DAC Control Register"
|
|
bitfld.byte 0x00 7. "DACEN,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
|
|
bitfld.byte 0x00 6. "VRSEL,Supply Voltage Reference Source Select" "0: Vin1 is selected as resistor ladder network..,1: Vin2 is selected as resistor ladder network.."
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "VOSEL,DAC Output Voltage Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MUXCR,MUX Control Register"
|
|
bitfld.byte 0x00 7. "PSTM,Pass Through Mode Enable" "0: Pass Through Mode is disabled,1: Pass Through Mode is enabled"
|
|
bitfld.byte 0x00 3.--5. "PSEL,Plus Input Mux Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "MSEL,Minus Input Mux Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "CMP1"
|
|
base ad:0x400EF000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR0,CMP Control Register 0"
|
|
bitfld.byte 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: One sample must agree,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.byte 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "CR1,CMP Control Register 1"
|
|
bitfld.byte 0x00 7. "SE,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
|
|
bitfld.byte 0x00 6. "WE,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
|
|
newline
|
|
bitfld.byte 0x00 5. "TRIGM,Trigger Mode Enable" "0: Trigger mode is disabled,1: Trigger mode is enabled"
|
|
bitfld.byte 0x00 4. "PMODE,Power Mode Select" "0: Low-Speed (LS) Comparison mode selected,1: High-Speed (HS) Comparison mode selected"
|
|
newline
|
|
bitfld.byte 0x00 3. "INV,Comparator INVERT" "0: Does not invert the comparator output,1: Inverts the comparator output"
|
|
bitfld.byte 0x00 2. "COS,Comparator Output Select" "0: Set the filtered comparator output (CMPO) to..,1: Set the unfiltered comparator output (CMPO).."
|
|
newline
|
|
bitfld.byte 0x00 1. "OPE,Comparator Output Pin Enable" "0: CMPO is not available on the associated CMPO..,1: CMPO is available on the associated CMPO.."
|
|
bitfld.byte 0x00 0. "EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "FPR,CMP Filter Period Register"
|
|
hexmask.byte 0x00 0.--7. 1. "FILT_PER,Filter Sample Period"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "SCR,CMP Status and Control Register"
|
|
bitfld.byte 0x00 6. "DMAEN,DMA Enable Control" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.byte 0x00 4. "IER,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. "IEF,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.byte 0x00 2. "CFR,Analog Comparator Flag Rising" "0: Rising-edge on COUT has not been detected,1: Rising-edge on COUT has occurred"
|
|
newline
|
|
bitfld.byte 0x00 1. "CFF,Analog Comparator Flag Falling" "0: Falling-edge on COUT has not been detected,1: Falling-edge on COUT has occurred"
|
|
rbitfld.byte 0x00 0. "COUT,Analog Comparator Output" "0,1"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DACCR,DAC Control Register"
|
|
bitfld.byte 0x00 7. "DACEN,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
|
|
bitfld.byte 0x00 6. "VRSEL,Supply Voltage Reference Source Select" "0: Vin1 is selected as resistor ladder network..,1: Vin2 is selected as resistor ladder network.."
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "VOSEL,DAC Output Voltage Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MUXCR,MUX Control Register"
|
|
bitfld.byte 0x00 7. "PSTM,Pass Through Mode Enable" "0: Pass Through Mode is disabled,1: Pass Through Mode is enabled"
|
|
bitfld.byte 0x00 3.--5. "PSEL,Plus Input Mux Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "MSEL,Minus Input Mux Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "COREDEBUG (Core Debug Registers)"
|
|
base ad:0xE000EDF0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DHCSR_Read,Debug Halting Control and Status Register"
|
|
rbitfld.long 0x00 25. "S_RESET_ST,S_RESET_ST bit" "0: No reset since last DHCSR,1: At least one reset since last DHCSR"
|
|
rbitfld.long 0x00 24. "S_RETIRE_ST,S_RETIRE_ST bit" "0: No instruction retired since last DHCSR,1: At least one instruction retired since last.."
|
|
newline
|
|
rbitfld.long 0x00 19. "S_LOCKUP,S_LOCKUP bit" "0: Not locked up,1: S_LOCKUP_1"
|
|
rbitfld.long 0x00 18. "S_SLEEP,S_SLEEP bit" "0: Not sleeping,1: S_SLEEP_1"
|
|
newline
|
|
rbitfld.long 0x00 17. "S_HALT,S_HALT bit" "0: Not in Debug state,1: In Debug state"
|
|
rbitfld.long 0x00 16. "S_REGRDY,S_REGRDY bit" "0: There has been a write to the DCRDR but the..,1: The transfer to or from the DCRDR is complete"
|
|
newline
|
|
bitfld.long 0x00 5. "C_SNAPSTALL,C_SNAPSTALL bit" "0: C_SNAPSTALL_0,1: Attempt to force any stalled load or store.."
|
|
bitfld.long 0x00 3. "C_MASKINTS,C_MASKINTS bit" "0: C_MASKINTS_0,1: Mask PenSV SysTick and external configurable.."
|
|
newline
|
|
bitfld.long 0x00 2. "C_STEP,Processor step bit" "0: No effect,1: Step the processor"
|
|
bitfld.long 0x00 1. "C_HALT,Processor halt bit" "0: No effect,1: Halt the processor"
|
|
newline
|
|
bitfld.long 0x00 0. "C_DEBUGEN,Halting debug enable bit" "0: C_DEBUGEN_0,1: C_DEBUGEN_1"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DHCSR_Write,Debug Halting Control and Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DBGKEY,Debug key: Software must write 0xA05F to this field to enable write accesses to bits [15:0] otherwise the processor ignores the write access"
|
|
bitfld.long 0x00 5. "C_SNAPSTALL,C_SNAPSTALL bit" "0: C_SNAPSTALL_0,1: Attempt to force any stalled load or store.."
|
|
newline
|
|
bitfld.long 0x00 3. "C_MASKINTS,C_MASKINTS bit" "0: C_MASKINTS_0,1: Mask PenSV SysTick and external configurable.."
|
|
bitfld.long 0x00 2. "C_STEP,Processor step bit" "0: No effect,1: Step the processor"
|
|
newline
|
|
bitfld.long 0x00 1. "C_HALT,Processor halt bit" "0: No effect,1: Halt the processor"
|
|
bitfld.long 0x00 0. "C_DEBUGEN,Halting debug enable bit" "0: C_DEBUGEN_0,1: C_DEBUGEN_1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. "REGWnR,REGWnR bit" "0: REGWnR_0,1: REGWnR_1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "REGSEL,REGSEL bits"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DBGTMP,DBGTMP bits"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. "TRCENA,TRCENA bit" "0: DWT and ITM blocks disabled,1: DWT and ITM blocks enabled"
|
|
bitfld.long 0x00 19. "MON_REQ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "MON_STEP,MON_STEP bit" "0: Do not step the processor,1: Step the processor"
|
|
bitfld.long 0x00 17. "MON_PEND,MON_PEND bit" "0: Clear the status of the DebugMonitor..,1: Set the status of the DebugMonitor exception.."
|
|
newline
|
|
bitfld.long 0x00 16. "MON_EN,MON_EN bit" "0: DebugMonitor exception disabled,1: DebugMonitor exception enabled"
|
|
bitfld.long 0x00 10. "VC_HARDERR,VC_HARDERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "VC_INTERR,VC_INTERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
bitfld.long 0x00 8. "VC_BUSERR,VC_BUSERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "VC_STATERR,VC_STATERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
bitfld.long 0x00 6. "VC_CHKERR,VC_CHKERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "VC_NOCPERR,VC_NOCPERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
bitfld.long 0x00 4. "VC_MMERR,VC_MMERR bit" "0: Halting debug trap disabled,1: Halting debug trap enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "VC_CORERESET,VC_CORERESET bit" "0: Reset Vector Catch disabled,1: Reset Vector Catch enabled"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "CRC"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x4002F000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HU,CRC High Upper Byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HL,CRC High Lower Byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LU,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LL,CRC Low Lower Byte"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x00 16.--31. 1. "HIGH,High Polynominal Half-word"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOW,Low Polynominal Half-word"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,CRC Control register"
|
|
bitfld.long 0x00 30.--31. "TOT,Type Of Transpose For Writes" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
bitfld.long 0x00 28.--29. "TOTR,Type Of Transpose For Read" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
newline
|
|
bitfld.long 0x00 26. "FXOR,Complement Read Of CRC Data Register" "0: No XOR on reading,1: Invert or complement the read value of the.."
|
|
bitfld.long 0x00 25. "WAS,Write CRC Data Register As Seed" "0: Writes to the CRC data register are data values,1: Writes to the CRC data register are seed values"
|
|
newline
|
|
bitfld.long 0x00 24. "TCRC,TCRC" "0: 16-bit CRC protocol,1: 32-bit CRC protocol"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40078000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HU,CRC High Upper Byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HL,CRC High Lower Byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LU,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LL,CRC Low Lower Byte"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x00 16.--31. 1. "HIGH,High Polynominal Half-word"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOW,Low Polynominal Half-word"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,CRC Control register"
|
|
bitfld.long 0x00 30.--31. "TOT,Type Of Transpose For Writes" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
bitfld.long 0x00 28.--29. "TOTR,Type Of Transpose For Read" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
newline
|
|
bitfld.long 0x00 26. "FXOR,Complement Read Of CRC Data Register" "0: No XOR on reading,1: Invert or complement the read value of the.."
|
|
bitfld.long 0x00 25. "WAS,Write CRC Data Register As Seed" "0: Writes to the CRC data register are data values,1: Writes to the CRC data register are seed values"
|
|
newline
|
|
bitfld.long 0x00 24. "TCRC,TCRC" "0: 16-bit CRC protocol,1: 32-bit CRC protocol"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "DAC0 (12-Bit Digital-to-Analog Converter)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4006A000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4003F000
|
|
endif
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DAT0L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "DAT0H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "DAT1L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "DAT1H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DAT2L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "DAT2H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "DAT3L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "DAT3H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "DAT4L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "DAT4H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "DAT5L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "DAT5H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "DAT6L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "DAT6H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "DAT7L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "DAT7H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "DAT8L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "DAT8H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "DAT9L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DAT9H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "DAT10L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DAT10H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "DAT11L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DAT11H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "DAT12L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "DAT12H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "DAT13L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "DAT13H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "DAT14L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "DAT14H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "DAT15L,DAC Data Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA0,DATA0"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "DAT15H,DAC Data High Register"
|
|
bitfld.byte 0x00 0.--3. "DATA1,DATA1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SR,DAC Status Register"
|
|
bitfld.byte 0x00 2. "DACBFWMF,DAC Buffer Watermark Flag" "0: The DAC buffer read pointer has not reached..,1: The DAC buffer read pointer has reached the.."
|
|
bitfld.byte 0x00 1. "DACBFRPTF,DAC Buffer Read Pointer Top Position Flag" "0: The DAC buffer read pointer is not zero,1: The DAC buffer read pointer is zero"
|
|
newline
|
|
bitfld.byte 0x00 0. "DACBFRPBF,DAC Buffer Read Pointer Bottom Position Flag" "0: The DAC buffer read pointer is not equal to..,1: The DAC buffer read pointer is equal to.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SR,DAC Status Register"
|
|
bitfld.byte 0x00 1. "DACBFRPTF,DAC Buffer Read Pointer Top Position Flag" "0: The DAC buffer read pointer is not zero,1: The DAC buffer read pointer is zero"
|
|
bitfld.byte 0x00 0. "DACBFRPBF,DAC Buffer Read Pointer Bottom Position Flag" "0: The DAC buffer read pointer is not equal to..,1: The DAC buffer read pointer is equal to.."
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "C0,DAC Control Register"
|
|
bitfld.byte 0x00 7. "DACEN,DAC Enable" "0: The DAC system is disabled,1: The DAC system is enabled"
|
|
bitfld.byte 0x00 6. "DACRFS,DAC Reference Select" "0: The DAC selects DACREF_1 as the reference..,1: The DAC selects DACREF_2 as the reference.."
|
|
newline
|
|
bitfld.byte 0x00 5. "DACTRGSEL,DAC Trigger Select" "0: The DAC hardware trigger is selected,1: The DAC software trigger is selected"
|
|
bitfld.byte 0x00 4. "DACSWTRG,DAC Software Trigger" "0: The DAC soft trigger is not valid,1: The DAC soft trigger is valid"
|
|
newline
|
|
bitfld.byte 0x00 3. "LPEN,DAC Low Power Control" "0: High-Power mode,1: Low-Power mode"
|
|
bitfld.byte 0x00 1. "DACBTIEN,DAC Buffer Read Pointer Top Flag Interrupt Enable" "0: The DAC buffer read pointer top flag..,1: The DAC buffer read pointer top flag.."
|
|
newline
|
|
bitfld.byte 0x00 0. "DACBBIEN,DAC Buffer Read Pointer Bottom Flag Interrupt Enable" "0: The DAC buffer read pointer bottom flag..,1: The DAC buffer read pointer bottom flag.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "C0,DAC Control Register"
|
|
bitfld.byte 0x00 7. "DACEN,DAC Enable" "0: The DAC system is disabled,1: The DAC system is enabled"
|
|
bitfld.byte 0x00 6. "DACRFS,DAC Reference Select" "0: The DAC selects DACREF_1 as the reference..,1: The DAC selects DACREF_2 as the reference.."
|
|
newline
|
|
bitfld.byte 0x00 5. "DACTRGSEL,DAC Trigger Select" "0: The DAC hardware trigger is selected,1: The DAC software trigger is selected"
|
|
bitfld.byte 0x00 4. "DACSWTRG,DAC Software Trigger" "0: The DAC soft trigger is not valid,1: The DAC soft trigger is valid"
|
|
newline
|
|
bitfld.byte 0x00 3. "LPEN,DAC Low Power Control" "0: High-Power mode,1: Low-Power mode"
|
|
bitfld.byte 0x00 2. "DACBWIEN,DAC Buffer Watermark Interrupt Enable" "0: The DAC buffer watermark interrupt is disabled,1: The DAC buffer watermark interrupt is enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. "DACBTIEN,DAC Buffer Read Pointer Top Flag Interrupt Enable" "0: The DAC buffer read pointer top flag..,1: The DAC buffer read pointer top flag.."
|
|
bitfld.byte 0x00 0. "DACBBIEN,DAC Buffer Read Pointer Bottom Flag Interrupt Enable" "0: The DAC buffer read pointer bottom flag..,1: The DAC buffer read pointer bottom flag.."
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. "DMAEN,DMA Enable Select" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.byte 0x00 3.--4. "DACBFWM,DAC Buffer Watermark Select" "0: 1 word,1: 2 words,2: 3 words,3: 4 words"
|
|
newline
|
|
bitfld.byte 0x00 1.--2. "DACBFMD,DAC Buffer Work Mode Select" "0: Normal mode,1: Swing mode,2: One-Time Scan mode,?..."
|
|
bitfld.byte 0x00 0. "DACBFEN,DAC Buffer Enable" "0: Buffer read pointer is disabled,1: Buffer read pointer is enabled"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "C1,DAC Control Register 1"
|
|
bitfld.byte 0x00 7. "DMAEN,DMA Enable Select" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.byte 0x00 1.--2. "DACBFMD,DAC Buffer Work Mode Select" "0: Normal mode,?,2: One-Time Scan mode,3: FIFO mode"
|
|
newline
|
|
bitfld.byte 0x00 0. "DACBFEN,DAC Buffer Enable" "0: Buffer read pointer is disabled,1: Buffer read pointer is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "C2,DAC Control Register 2"
|
|
bitfld.byte 0x00 4.--7. "DACBFRP,DAC Buffer Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "DACBFUP,DAC Buffer Upper Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "C2,DAC Control Register 2"
|
|
bitfld.byte 0x00 4. "DACBFRP,DAC Buffer Read Pointer" "0,1"
|
|
bitfld.byte 0x00 0. "DACBFUP,DAC Buffer Upper Limit" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "DMA (DMA Controller)"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "DMA"
|
|
base ad:0x40008000
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SAR0,Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SAR,SAR"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DAR0,Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DAR,DAR"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DSR_BCR0,DMA Status Register / Byte Count Register"
|
|
rbitfld.long 0x00 30. "CE,Configuration Error" "0: No configuration error exists,1: A configuration error has occurred"
|
|
rbitfld.long 0x00 29. "BES,Bus Error on Source" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
newline
|
|
rbitfld.long 0x00 28. "BED,Bus Error on Destination" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
rbitfld.long 0x00 26. "REQ,Request" "0: No request is pending or the channel is..,1: The DMA channel has a transfer remaining and.."
|
|
newline
|
|
rbitfld.long 0x00 25. "BSY,Busy" "0: DMA channel is inactive,1: BSY is set the first time the channel is.."
|
|
bitfld.long 0x00 24. "DONE,Transactions Done" "0: DMA transfer is not yet complete,1: DMA transfer completed"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "BCR,BCR"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "DSR0,DMA_DSR0 register"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DCR0,DMA Control Register"
|
|
bitfld.long 0x00 31. "EINT,Enable Interrupt on Completion of Transfer" "0: No interrupt is generated,1: Interrupt signal is enabled"
|
|
bitfld.long 0x00 30. "ERQ,Enable Peripheral Request" "0: Peripheral request is ignored,1: Enables peripheral request to initiate transfer"
|
|
newline
|
|
bitfld.long 0x00 29. "CS,Cycle Steal" "0: DMA continuously makes read/write transfers..,1: Forces a single read/write transfer per request"
|
|
bitfld.long 0x00 28. "AA,Auto-align" "0: Auto-align disabled,1: If SSIZE indicates a transfer no smaller than.."
|
|
newline
|
|
bitfld.long 0x00 23. "EADREQ,Enable asynchronous DMA requests" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 22. "SINC,Source Increment" "0: No change to SAR after a successful transfer,1: The SAR increments by 1 2 4 as determined by.."
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SSIZE,Source Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 19. "DINC,Destination Increment" "0: No change to the DAR after a successful..,1: The DAR increments by 1 2 4 depending upon.."
|
|
newline
|
|
bitfld.long 0x00 17.--18. "DSIZE,Destination Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 16. "START,Start Transfer" "0: DMA inactive,1: The DMA begins the transfer in accordance to.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "SMOD,Source Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
bitfld.long 0x00 8.--11. "DMOD,Destination Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
newline
|
|
bitfld.long 0x00 7. "D_REQ,Disable Request" "0: ERQ bit is not affected,1: ERQ bit is cleared when the BCR is exhausted"
|
|
bitfld.long 0x00 4.--5. "LINKCC,Link Channel Control" "0: No channel-to-channel linking,1: Perform a link to channel LCH1 after each..,2: Perform a link to channel LCH1 after each..,3: Perform a link to channel LCH1 after the BCR.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "LCH1,Link Channel 1" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
bitfld.long 0x00 0.--1. "LCH2,Link Channel 2" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SAR1,Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SAR,SAR"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DAR1,Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DAR,DAR"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DSR_BCR1,DMA Status Register / Byte Count Register"
|
|
rbitfld.long 0x00 30. "CE,Configuration Error" "0: No configuration error exists,1: A configuration error has occurred"
|
|
rbitfld.long 0x00 29. "BES,Bus Error on Source" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
newline
|
|
rbitfld.long 0x00 28. "BED,Bus Error on Destination" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
rbitfld.long 0x00 26. "REQ,Request" "0: No request is pending or the channel is..,1: The DMA channel has a transfer remaining and.."
|
|
newline
|
|
rbitfld.long 0x00 25. "BSY,Busy" "0: DMA channel is inactive,1: BSY is set the first time the channel is.."
|
|
bitfld.long 0x00 24. "DONE,Transactions Done" "0: DMA transfer is not yet complete,1: DMA transfer completed"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "BCR,BCR"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "DSR1,DMA_DSR1 register"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DCR1,DMA Control Register"
|
|
bitfld.long 0x00 31. "EINT,Enable Interrupt on Completion of Transfer" "0: No interrupt is generated,1: Interrupt signal is enabled"
|
|
bitfld.long 0x00 30. "ERQ,Enable Peripheral Request" "0: Peripheral request is ignored,1: Enables peripheral request to initiate transfer"
|
|
newline
|
|
bitfld.long 0x00 29. "CS,Cycle Steal" "0: DMA continuously makes read/write transfers..,1: Forces a single read/write transfer per request"
|
|
bitfld.long 0x00 28. "AA,Auto-align" "0: Auto-align disabled,1: If SSIZE indicates a transfer no smaller than.."
|
|
newline
|
|
bitfld.long 0x00 23. "EADREQ,Enable asynchronous DMA requests" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 22. "SINC,Source Increment" "0: No change to SAR after a successful transfer,1: The SAR increments by 1 2 4 as determined by.."
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SSIZE,Source Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 19. "DINC,Destination Increment" "0: No change to the DAR after a successful..,1: The DAR increments by 1 2 4 depending upon.."
|
|
newline
|
|
bitfld.long 0x00 17.--18. "DSIZE,Destination Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 16. "START,Start Transfer" "0: DMA inactive,1: The DMA begins the transfer in accordance to.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "SMOD,Source Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
bitfld.long 0x00 8.--11. "DMOD,Destination Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
newline
|
|
bitfld.long 0x00 7. "D_REQ,Disable Request" "0: ERQ bit is not affected,1: ERQ bit is cleared when the BCR is exhausted"
|
|
bitfld.long 0x00 4.--5. "LINKCC,Link Channel Control" "0: No channel-to-channel linking,1: Perform a link to channel LCH1 after each..,2: Perform a link to channel LCH1 after each..,3: Perform a link to channel LCH1 after the BCR.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "LCH1,Link Channel 1" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
bitfld.long 0x00 0.--1. "LCH2,Link Channel 2" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "SAR2,Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SAR,SAR"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DAR2,Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DAR,DAR"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DSR_BCR2,DMA Status Register / Byte Count Register"
|
|
rbitfld.long 0x00 30. "CE,Configuration Error" "0: No configuration error exists,1: A configuration error has occurred"
|
|
rbitfld.long 0x00 29. "BES,Bus Error on Source" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
newline
|
|
rbitfld.long 0x00 28. "BED,Bus Error on Destination" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
rbitfld.long 0x00 26. "REQ,Request" "0: No request is pending or the channel is..,1: The DMA channel has a transfer remaining and.."
|
|
newline
|
|
rbitfld.long 0x00 25. "BSY,Busy" "0: DMA channel is inactive,1: BSY is set the first time the channel is.."
|
|
bitfld.long 0x00 24. "DONE,Transactions Done" "0: DMA transfer is not yet complete,1: DMA transfer completed"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "BCR,BCR"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "DSR2,DMA_DSR2 register"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DCR2,DMA Control Register"
|
|
bitfld.long 0x00 31. "EINT,Enable Interrupt on Completion of Transfer" "0: No interrupt is generated,1: Interrupt signal is enabled"
|
|
bitfld.long 0x00 30. "ERQ,Enable Peripheral Request" "0: Peripheral request is ignored,1: Enables peripheral request to initiate transfer"
|
|
newline
|
|
bitfld.long 0x00 29. "CS,Cycle Steal" "0: DMA continuously makes read/write transfers..,1: Forces a single read/write transfer per request"
|
|
bitfld.long 0x00 28. "AA,Auto-align" "0: Auto-align disabled,1: If SSIZE indicates a transfer no smaller than.."
|
|
newline
|
|
bitfld.long 0x00 23. "EADREQ,Enable asynchronous DMA requests" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 22. "SINC,Source Increment" "0: No change to SAR after a successful transfer,1: The SAR increments by 1 2 4 as determined by.."
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SSIZE,Source Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 19. "DINC,Destination Increment" "0: No change to the DAR after a successful..,1: The DAR increments by 1 2 4 depending upon.."
|
|
newline
|
|
bitfld.long 0x00 17.--18. "DSIZE,Destination Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 16. "START,Start Transfer" "0: DMA inactive,1: The DMA begins the transfer in accordance to.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "SMOD,Source Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
bitfld.long 0x00 8.--11. "DMOD,Destination Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
newline
|
|
bitfld.long 0x00 7. "D_REQ,Disable Request" "0: ERQ bit is not affected,1: ERQ bit is cleared when the BCR is exhausted"
|
|
bitfld.long 0x00 4.--5. "LINKCC,Link Channel Control" "0: No channel-to-channel linking,1: Perform a link to channel LCH1 after each..,2: Perform a link to channel LCH1 after each..,3: Perform a link to channel LCH1 after the BCR.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "LCH1,Link Channel 1" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
bitfld.long 0x00 0.--1. "LCH2,Link Channel 2" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "SAR3,Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SAR,SAR"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DAR3,Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DAR,DAR"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DSR_BCR3,DMA Status Register / Byte Count Register"
|
|
rbitfld.long 0x00 30. "CE,Configuration Error" "0: No configuration error exists,1: A configuration error has occurred"
|
|
rbitfld.long 0x00 29. "BES,Bus Error on Source" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
newline
|
|
rbitfld.long 0x00 28. "BED,Bus Error on Destination" "0: No bus error occurred,1: The DMA channel terminated with a bus error.."
|
|
rbitfld.long 0x00 26. "REQ,Request" "0: No request is pending or the channel is..,1: The DMA channel has a transfer remaining and.."
|
|
newline
|
|
rbitfld.long 0x00 25. "BSY,Busy" "0: DMA channel is inactive,1: BSY is set the first time the channel is.."
|
|
bitfld.long 0x00 24. "DONE,Transactions Done" "0: DMA transfer is not yet complete,1: DMA transfer completed"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "BCR,BCR"
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "DSR3,DMA_DSR3 register"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DCR3,DMA Control Register"
|
|
bitfld.long 0x00 31. "EINT,Enable Interrupt on Completion of Transfer" "0: No interrupt is generated,1: Interrupt signal is enabled"
|
|
bitfld.long 0x00 30. "ERQ,Enable Peripheral Request" "0: Peripheral request is ignored,1: Enables peripheral request to initiate transfer"
|
|
newline
|
|
bitfld.long 0x00 29. "CS,Cycle Steal" "0: DMA continuously makes read/write transfers..,1: Forces a single read/write transfer per request"
|
|
bitfld.long 0x00 28. "AA,Auto-align" "0: Auto-align disabled,1: If SSIZE indicates a transfer no smaller than.."
|
|
newline
|
|
bitfld.long 0x00 23. "EADREQ,Enable asynchronous DMA requests" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 22. "SINC,Source Increment" "0: No change to SAR after a successful transfer,1: The SAR increments by 1 2 4 as determined by.."
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SSIZE,Source Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 19. "DINC,Destination Increment" "0: No change to the DAR after a successful..,1: The DAR increments by 1 2 4 depending upon.."
|
|
newline
|
|
bitfld.long 0x00 17.--18. "DSIZE,Destination Size" "0: 32-bit,1: 8-bit,2: 16-bit,3: Reserved (generates a configuration error.."
|
|
bitfld.long 0x00 16. "START,Start Transfer" "0: DMA inactive,1: The DMA begins the transfer in accordance to.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "SMOD,Source Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
bitfld.long 0x00 8.--11. "DMOD,Destination Address Modulo" "0: Buffer disabled,1: Circular buffer size is 16 bytes,2: Circular buffer size is 32 bytes,3: Circular buffer size is 64 bytes,4: Circular buffer size is 128 bytes,5: Circular buffer size is 256 bytes,6: Circular buffer size is 512 bytes,7: Circular buffer size is 1 KB,8: Circular buffer size is 2 KB,9: Circular buffer size is 4 KB,10: Circular buffer size is 8 KB,11: Circular buffer size is 16 KB,12: Circular buffer size is 32 KB,13: Circular buffer size is 64 KB,14: Circular buffer size is 128 KB,15: Circular buffer size is 256 KB"
|
|
newline
|
|
bitfld.long 0x00 7. "D_REQ,Disable Request" "0: ERQ bit is not affected,1: ERQ bit is cleared when the BCR is exhausted"
|
|
bitfld.long 0x00 4.--5. "LINKCC,Link Channel Control" "0: No channel-to-channel linking,1: Perform a link to channel LCH1 after each..,2: Perform a link to channel LCH1 after each..,3: Perform a link to channel LCH1 after the BCR.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "LCH1,Link Channel 1" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
bitfld.long 0x00 0.--1. "LCH2,Link Channel 2" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "DMA0"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
bitfld.long 0x00 17. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 16. "ECX,Error Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer in the.."
|
|
bitfld.long 0x00 7. "EMLM,Enable Minor Loop Mapping" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "CLM,Continuous Link Mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.."
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
newline
|
|
bitfld.long 0x00 4. "HOE,Halt On Error" "0: Normal operation,1: Any error causes the HALT bit to set"
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Fixed priority arbitration is used for..,1: Round robin arbitration is used for channel.."
|
|
newline
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: When in debug mode the DMA continues to operate,1: When in debug mode the DMA stalls the start.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. "VLD,VLD" "0: No ERR bits are set,1: At least one ERR bit is set indicating a.."
|
|
bitfld.long 0x00 16. "ECX,Transfer Canceled" "0: No canceled transfers,1: The last recorded entry was a canceled.."
|
|
newline
|
|
bitfld.long 0x00 14. "CPE,Channel Priority Error" "0: No channel priority error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 8.--11. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: The last recorded error was a bus error on a.."
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: The last recorded error was a bus error on a.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
bitfld.long 0x00 15. "ERQ15,Enable DMA Request 15" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 14. "ERQ14,Enable DMA Request 14" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 13. "ERQ13,Enable DMA Request 13" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 12. "ERQ12,Enable DMA Request 12" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 11. "ERQ11,Enable DMA Request 11" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 10. "ERQ10,Enable DMA Request 10" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 9. "ERQ9,Enable DMA Request 9" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 8. "ERQ8,Enable DMA Request 8" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 7. "ERQ7,Enable DMA Request 7" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 6. "ERQ6,Enable DMA Request 6" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "ERQ5,Enable DMA Request 5" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 4. "ERQ4,Enable DMA Request 4" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "ERQ3,Enable DMA Request 3" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 2. "ERQ2,Enable DMA Request 2" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "ERQ1,Enable DMA Request 1" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 0. "ERQ0,Enable DMA Request 0" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
bitfld.long 0x00 15. "EEI15,Enable Error Interrupt 15" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 14. "EEI14,Enable Error Interrupt 14" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 13. "EEI13,Enable Error Interrupt 13" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 12. "EEI12,Enable Error Interrupt 12" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 11. "EEI11,Enable Error Interrupt 11" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 10. "EEI10,Enable Error Interrupt 10" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 9. "EEI9,Enable Error Interrupt 9" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 8. "EEI8,Enable Error Interrupt 8" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 7. "EEI7,Enable Error Interrupt 7" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 6. "EEI6,Enable Error Interrupt 6" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 5. "EEI5,Enable Error Interrupt 5" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 4. "EEI4,Enable Error Interrupt 4" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 3. "EEI3,Enable Error Interrupt 3" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 2. "EEI2,Enable Error Interrupt 2" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 1. "EEI1,Enable Error Interrupt 1" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 0. "EEI0,Enable Error Interrupt 0" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEE,Clear All Enable Error Interrupts" "0: Clear only the EEI bit specified in the CEEI..,1: Clear all bits in EEI"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CEEI,Clear Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAEE,Sets All Enable Error Interrupts" "0: Set only the EEI bit specified in the SEEI..,1: Sets all bits in EEI"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SEEI,Set Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAER,Clear All Enable Requests" "0: Clear only the ERQ bit specified in the CERQ..,1: Clear all bits in ERQ"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CERQ,Clear Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAER,Set All Enable Requests" "0: Set only the ERQ bit specified in the SERQ..,1: Set all bits in ERQ"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SERQ,Set Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CADN,Clears All DONE Bits" "0: Clears only the TCDn_CSR[DONE] bit specified..,1: Clears all bits in TCDn_CSR[DONE]"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CDNE,Clear DONE Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAST,Set All START Bits (activates all channels)" "0: Set only the TCDn_CSR[START] bit specified in..,1: Set all bits in TCDn_CSR[START]"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SSRT,Set START Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "CERR,Clear Error Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEI,Clear All Error Indicators" "0: Clear only the ERR bit specified in the CERR..,1: Clear all bits in ERR"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CERR,Clear Error Indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAIR,Clear All Interrupt Requests" "0: Clear only the INT bit specified in the CINT..,1: Clear all bits in INT"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CINT,Clear Interrupt Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
eventfld.long 0x00 15. "INT15,Interrupt Request 15" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 14. "INT14,Interrupt Request 14" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 13. "INT13,Interrupt Request 13" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 12. "INT12,Interrupt Request 12" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 11. "INT11,Interrupt Request 11" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 10. "INT10,Interrupt Request 10" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 9. "INT9,Interrupt Request 9" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 8. "INT8,Interrupt Request 8" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 7. "INT7,Interrupt Request 7" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 6. "INT6,Interrupt Request 6" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 5. "INT5,Interrupt Request 5" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 4. "INT4,Interrupt Request 4" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 3. "INT3,Interrupt Request 3" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 2. "INT2,Interrupt Request 2" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 1. "INT1,Interrupt Request 1" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 0. "INT0,Interrupt Request 0" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
eventfld.long 0x00 15. "ERR15,Error In Channel 15" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 14. "ERR14,Error In Channel 14" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 13. "ERR13,Error In Channel 13" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 12. "ERR12,Error In Channel 12" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 11. "ERR11,Error In Channel 11" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 10. "ERR10,Error In Channel 10" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 9. "ERR9,Error In Channel 9" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 8. "ERR8,Error In Channel 8" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 7. "ERR7,Error In Channel 7" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 6. "ERR6,Error In Channel 6" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 5. "ERR5,Error In Channel 5" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 4. "ERR4,Error In Channel 4" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 3. "ERR3,Error In Channel 3" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 2. "ERR2,Error In Channel 2" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 1. "ERR1,Error In Channel 1" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 0. "ERR0,Error In Channel 0" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 15. "HRS15,Hardware Request Status Channel 15" "0: A hardware service request for channel 15 is..,1: A hardware service request for channel 15 is.."
|
|
bitfld.long 0x00 14. "HRS14,Hardware Request Status Channel 14" "0: A hardware service request for channel 14 is..,1: A hardware service request for channel 14 is.."
|
|
newline
|
|
bitfld.long 0x00 13. "HRS13,Hardware Request Status Channel 13" "0: A hardware service request for channel 13 is..,1: A hardware service request for channel 13 is.."
|
|
bitfld.long 0x00 12. "HRS12,Hardware Request Status Channel 12" "0: A hardware service request for channel 12 is..,1: A hardware service request for channel 12 is.."
|
|
newline
|
|
bitfld.long 0x00 11. "HRS11,Hardware Request Status Channel 11" "0: A hardware service request for channel 11 is..,1: A hardware service request for channel 11 is.."
|
|
bitfld.long 0x00 10. "HRS10,Hardware Request Status Channel 10" "0: A hardware service request for channel 10 is..,1: A hardware service request for channel 10 is.."
|
|
newline
|
|
bitfld.long 0x00 9. "HRS9,Hardware Request Status Channel 9" "0: A hardware service request for channel 9 is..,1: A hardware service request for channel 9 is.."
|
|
bitfld.long 0x00 8. "HRS8,Hardware Request Status Channel 8" "0: A hardware service request for channel 8 is..,1: A hardware service request for channel 8 is.."
|
|
newline
|
|
bitfld.long 0x00 7. "HRS7,Hardware Request Status Channel 7" "0: A hardware service request for channel 7 is..,1: A hardware service request for channel 7 is.."
|
|
bitfld.long 0x00 6. "HRS6,Hardware Request Status Channel 6" "0: A hardware service request for channel 6 is..,1: A hardware service request for channel 6 is.."
|
|
newline
|
|
bitfld.long 0x00 5. "HRS5,Hardware Request Status Channel 5" "0: A hardware service request for channel 5 is..,1: A hardware service request for channel 5 is.."
|
|
bitfld.long 0x00 4. "HRS4,Hardware Request Status Channel 4" "0: A hardware service request for channel 4 is..,1: A hardware service request for channel 4 is.."
|
|
newline
|
|
bitfld.long 0x00 3. "HRS3,Hardware Request Status Channel 3" "0: A hardware service request for channel 3 is..,1: A hardware service request for channel 3 is.."
|
|
bitfld.long 0x00 2. "HRS2,Hardware Request Status Channel 2" "0: A hardware service request for channel 2 is..,1: A hardware service request for channel 2 is.."
|
|
newline
|
|
bitfld.long 0x00 1. "HRS1,Hardware Request Status Channel 1" "0: A hardware service request for channel 1 is..,1: A hardware service request for channel 1 is.."
|
|
bitfld.long 0x00 0. "HRS0,Hardware Request Status Channel 0" "0: A hardware service request for channel 0 is..,1: A hardware service request for channel 0 is.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
bitfld.long 0x00 15. "EDREQ_15,Enable asynchronous DMA request in stop mode for channel 15" "0: Disable asynchronous DMA request for channel 15,1: Enable asynchronous DMA request for channel 15"
|
|
bitfld.long 0x00 14. "EDREQ_14,Enable asynchronous DMA request in stop mode for channel 14" "0: Disable asynchronous DMA request for channel 14,1: Enable asynchronous DMA request for channel 14"
|
|
newline
|
|
bitfld.long 0x00 13. "EDREQ_13,Enable asynchronous DMA request in stop mode for channel 13" "0: Disable asynchronous DMA request for channel 13,1: Enable asynchronous DMA request for channel 13"
|
|
bitfld.long 0x00 12. "EDREQ_12,Enable asynchronous DMA request in stop mode for channel 12" "0: Disable asynchronous DMA request for channel 12,1: Enable asynchronous DMA request for channel 12"
|
|
newline
|
|
bitfld.long 0x00 11. "EDREQ_11,Enable asynchronous DMA request in stop mode for channel 11" "0: Disable asynchronous DMA request for channel 11,1: Enable asynchronous DMA request for channel 11"
|
|
bitfld.long 0x00 10. "EDREQ_10,Enable asynchronous DMA request in stop mode for channel 10" "0: Disable asynchronous DMA request for channel 10,1: Enable asynchronous DMA request for channel 10"
|
|
newline
|
|
bitfld.long 0x00 9. "EDREQ_9,Enable asynchronous DMA request in stop mode for channel 9" "0: Disable asynchronous DMA request for channel 9,1: Enable asynchronous DMA request for channel 9"
|
|
bitfld.long 0x00 8. "EDREQ_8,Enable asynchronous DMA request in stop mode for channel 8" "0: Disable asynchronous DMA request for channel 8,1: Enable asynchronous DMA request for channel 8"
|
|
newline
|
|
bitfld.long 0x00 7. "EDREQ_7,Enable asynchronous DMA request in stop mode for channel 7" "0: Disable asynchronous DMA request for channel 7,1: Enable asynchronous DMA request for channel 7"
|
|
bitfld.long 0x00 6. "EDREQ_6,Enable asynchronous DMA request in stop mode for channel 6" "0: Disable asynchronous DMA request for channel 6,1: Enable asynchronous DMA request for channel 6"
|
|
newline
|
|
bitfld.long 0x00 5. "EDREQ_5,Enable asynchronous DMA request in stop mode for channel 5" "0: Disable asynchronous DMA request for channel 5,1: Enable asynchronous DMA request for channel 5"
|
|
bitfld.long 0x00 4. "EDREQ_4,Enable asynchronous DMA request in stop mode for channel 4" "0: Disable asynchronous DMA request for channel 4,1: Enable asynchronous DMA request for channel 4"
|
|
newline
|
|
bitfld.long 0x00 3. "EDREQ_3,Enable asynchronous DMA request in stop mode for channel 3" "0: Disable asynchronous DMA request for channel 3,1: Enable asynchronous DMA request for channel 3"
|
|
bitfld.long 0x00 2. "EDREQ_2,Enable asynchronous DMA request in stop mode for channel 2" "0: Disable asynchronous DMA request for channel 2,1: Enable asynchronous DMA request for channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "EDREQ_1,Enable asynchronous DMA request in stop mode for channel 1" "0: Disable asynchronous DMA request for channel 1,1: Enable asynchronous DMA request for channel 1"
|
|
bitfld.long 0x00 0. "EDREQ_0,Enable asynchronous DMA request in stop mode for channel 0" "0: Disable asynchronous DMA request for channel 0,1: Enable asynchronous DMA request for channel 0"
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI$1,Channel Priority Register"
|
|
bitfld.byte 0x00 7. "ECP,Enable Channel Preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.."
|
|
bitfld.byte 0x00 6. "DPA,Disable Preempt Ability" "0: Channel n can suspend a lower priority channel,1: Channel n cannot suspend any channel.."
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CHPRI,Channel n Arbitration Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1004++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1006++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1014++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x101C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x103C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1044++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1046++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1054++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x105C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1064++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1066++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1074++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x107C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1084++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1086++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1094++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x109C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10A4++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10A6++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10B4++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10BC++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10C4++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10C6++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10D4++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10DC++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10E4++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10E6++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10F4++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10FC++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1104++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1106++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1114++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x111C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1124++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1126++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1134++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x113C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1144++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1146++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x114C++0x03
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1154++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x115C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1164++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1166++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x116C++0x03
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1174++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x117C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1184++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1186++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x118C++0x03
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1194++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x119C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11A4++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11A6++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11B4++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11BC++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11C4++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11C6++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11CC++0x03
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11D4++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11DC++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11E4++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11E6++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11EC++0x03
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11F4++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11FC++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
tree.end
|
|
endif
|
|
tree "DMA0"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
bitfld.long 0x00 17. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 16. "ECX,Error Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer in the.."
|
|
bitfld.long 0x00 7. "EMLM,Enable Minor Loop Mapping" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "CLM,Continuous Link Mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.."
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
newline
|
|
bitfld.long 0x00 4. "HOE,Halt On Error" "0: Normal operation,1: Any error causes the HALT bit to set"
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Fixed priority arbitration is used for..,1: Round robin arbitration is used for channel.."
|
|
newline
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: When in debug mode the DMA continues to operate,1: When in debug mode the DMA stalls the start.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. "VLD,VLD" "0: No ERR bits are set,1: At least one ERR bit is set indicating a.."
|
|
bitfld.long 0x00 16. "ECX,Transfer Canceled" "0: No canceled transfers,1: The last recorded entry was a canceled.."
|
|
newline
|
|
bitfld.long 0x00 14. "CPE,Channel Priority Error" "0: No channel priority error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 8.--11. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: The last recorded error was a bus error on a.."
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: The last recorded error was a bus error on a.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
bitfld.long 0x00 15. "ERQ15,Enable DMA Request 15" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 14. "ERQ14,Enable DMA Request 14" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 13. "ERQ13,Enable DMA Request 13" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 12. "ERQ12,Enable DMA Request 12" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 11. "ERQ11,Enable DMA Request 11" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 10. "ERQ10,Enable DMA Request 10" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 9. "ERQ9,Enable DMA Request 9" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 8. "ERQ8,Enable DMA Request 8" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 7. "ERQ7,Enable DMA Request 7" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 6. "ERQ6,Enable DMA Request 6" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "ERQ5,Enable DMA Request 5" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 4. "ERQ4,Enable DMA Request 4" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "ERQ3,Enable DMA Request 3" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 2. "ERQ2,Enable DMA Request 2" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "ERQ1,Enable DMA Request 1" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 0. "ERQ0,Enable DMA Request 0" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
bitfld.long 0x00 15. "EEI15,Enable Error Interrupt 15" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 14. "EEI14,Enable Error Interrupt 14" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 13. "EEI13,Enable Error Interrupt 13" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 12. "EEI12,Enable Error Interrupt 12" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
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bitfld.long 0x00 11. "EEI11,Enable Error Interrupt 11" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 10. "EEI10,Enable Error Interrupt 10" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
newline
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bitfld.long 0x00 9. "EEI9,Enable Error Interrupt 9" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 8. "EEI8,Enable Error Interrupt 8" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
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bitfld.long 0x00 7. "EEI7,Enable Error Interrupt 7" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 6. "EEI6,Enable Error Interrupt 6" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
newline
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bitfld.long 0x00 5. "EEI5,Enable Error Interrupt 5" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 4. "EEI4,Enable Error Interrupt 4" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
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bitfld.long 0x00 3. "EEI3,Enable Error Interrupt 3" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 2. "EEI2,Enable Error Interrupt 2" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
newline
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bitfld.long 0x00 1. "EEI1,Enable Error Interrupt 1" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
bitfld.long 0x00 0. "EEI0,Enable Error Interrupt 0" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
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|
group.byte 0x18++0x00
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEE,Clear All Enable Error Interrupts" "0: Clear only the EEI bit specified in the CEEI..,1: Clear all bits in EEI"
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|
newline
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bitfld.byte 0x00 0.--3. "CEEI,Clear Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAEE,Sets All Enable Error Interrupts" "0: Set only the EEI bit specified in the SEEI..,1: Sets all bits in EEI"
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|
newline
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bitfld.byte 0x00 0.--3. "SEEI,Set Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAER,Clear All Enable Requests" "0: Clear only the ERQ bit specified in the CERQ..,1: Clear all bits in ERQ"
|
|
newline
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|
bitfld.byte 0x00 0.--3. "CERQ,Clear Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAER,Set All Enable Requests" "0: Set only the ERQ bit specified in the SERQ..,1: Set all bits in ERQ"
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|
newline
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bitfld.byte 0x00 0.--3. "SERQ,Set Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CADN,Clears All DONE Bits" "0: Clears only the TCDn_CSR[DONE] bit specified..,1: Clears all bits in TCDn_CSR[DONE]"
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|
newline
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bitfld.byte 0x00 0.--3. "CDNE,Clear DONE Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
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|
bitfld.byte 0x00 6. "SAST,Set All START Bits (activates all channels)" "0: Set only the TCDn_CSR[START] bit specified in..,1: Set all bits in TCDn_CSR[START]"
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|
newline
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bitfld.byte 0x00 0.--3. "SSRT,Set START Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "CERR,Clear Error Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEI,Clear All Error Indicators" "0: Clear only the ERR bit specified in the CERR..,1: Clear all bits in ERR"
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|
newline
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bitfld.byte 0x00 0.--3. "CERR,Clear Error Indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAIR,Clear All Interrupt Requests" "0: Clear only the INT bit specified in the CINT..,1: Clear all bits in INT"
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|
newline
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bitfld.byte 0x00 0.--3. "CINT,Clear Interrupt Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
eventfld.long 0x00 15. "INT15,Interrupt Request 15" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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|
eventfld.long 0x00 14. "INT14,Interrupt Request 14" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 13. "INT13,Interrupt Request 13" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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eventfld.long 0x00 12. "INT12,Interrupt Request 12" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 11. "INT11,Interrupt Request 11" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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eventfld.long 0x00 10. "INT10,Interrupt Request 10" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 9. "INT9,Interrupt Request 9" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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eventfld.long 0x00 8. "INT8,Interrupt Request 8" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 7. "INT7,Interrupt Request 7" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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eventfld.long 0x00 6. "INT6,Interrupt Request 6" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 5. "INT5,Interrupt Request 5" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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|
eventfld.long 0x00 4. "INT4,Interrupt Request 4" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 3. "INT3,Interrupt Request 3" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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eventfld.long 0x00 2. "INT2,Interrupt Request 2" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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newline
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eventfld.long 0x00 1. "INT1,Interrupt Request 1" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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|
eventfld.long 0x00 0. "INT0,Interrupt Request 0" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
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group.long 0x2C++0x03
|
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line.long 0x00 "ERR,Error Register"
|
|
eventfld.long 0x00 15. "ERR15,Error In Channel 15" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 14. "ERR14,Error In Channel 14" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
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|
newline
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eventfld.long 0x00 13. "ERR13,Error In Channel 13" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 12. "ERR12,Error In Channel 12" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
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|
newline
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eventfld.long 0x00 11. "ERR11,Error In Channel 11" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 10. "ERR10,Error In Channel 10" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
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|
newline
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eventfld.long 0x00 9. "ERR9,Error In Channel 9" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 8. "ERR8,Error In Channel 8" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
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eventfld.long 0x00 7. "ERR7,Error In Channel 7" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 6. "ERR6,Error In Channel 6" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
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eventfld.long 0x00 5. "ERR5,Error In Channel 5" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 4. "ERR4,Error In Channel 4" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
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eventfld.long 0x00 3. "ERR3,Error In Channel 3" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 2. "ERR2,Error In Channel 2" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
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eventfld.long 0x00 1. "ERR1,Error In Channel 1" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 0. "ERR0,Error In Channel 0" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 15. "HRS15,Hardware Request Status Channel 15" "0: A hardware service request for channel 15 is..,1: A hardware service request for channel 15 is.."
|
|
bitfld.long 0x00 14. "HRS14,Hardware Request Status Channel 14" "0: A hardware service request for channel 14 is..,1: A hardware service request for channel 14 is.."
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|
newline
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bitfld.long 0x00 13. "HRS13,Hardware Request Status Channel 13" "0: A hardware service request for channel 13 is..,1: A hardware service request for channel 13 is.."
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|
bitfld.long 0x00 12. "HRS12,Hardware Request Status Channel 12" "0: A hardware service request for channel 12 is..,1: A hardware service request for channel 12 is.."
|
|
newline
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bitfld.long 0x00 11. "HRS11,Hardware Request Status Channel 11" "0: A hardware service request for channel 11 is..,1: A hardware service request for channel 11 is.."
|
|
bitfld.long 0x00 10. "HRS10,Hardware Request Status Channel 10" "0: A hardware service request for channel 10 is..,1: A hardware service request for channel 10 is.."
|
|
newline
|
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bitfld.long 0x00 9. "HRS9,Hardware Request Status Channel 9" "0: A hardware service request for channel 9 is..,1: A hardware service request for channel 9 is.."
|
|
bitfld.long 0x00 8. "HRS8,Hardware Request Status Channel 8" "0: A hardware service request for channel 8 is..,1: A hardware service request for channel 8 is.."
|
|
newline
|
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bitfld.long 0x00 7. "HRS7,Hardware Request Status Channel 7" "0: A hardware service request for channel 7 is..,1: A hardware service request for channel 7 is.."
|
|
bitfld.long 0x00 6. "HRS6,Hardware Request Status Channel 6" "0: A hardware service request for channel 6 is..,1: A hardware service request for channel 6 is.."
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|
newline
|
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bitfld.long 0x00 5. "HRS5,Hardware Request Status Channel 5" "0: A hardware service request for channel 5 is..,1: A hardware service request for channel 5 is.."
|
|
bitfld.long 0x00 4. "HRS4,Hardware Request Status Channel 4" "0: A hardware service request for channel 4 is..,1: A hardware service request for channel 4 is.."
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|
newline
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bitfld.long 0x00 3. "HRS3,Hardware Request Status Channel 3" "0: A hardware service request for channel 3 is..,1: A hardware service request for channel 3 is.."
|
|
bitfld.long 0x00 2. "HRS2,Hardware Request Status Channel 2" "0: A hardware service request for channel 2 is..,1: A hardware service request for channel 2 is.."
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|
newline
|
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bitfld.long 0x00 1. "HRS1,Hardware Request Status Channel 1" "0: A hardware service request for channel 1 is..,1: A hardware service request for channel 1 is.."
|
|
bitfld.long 0x00 0. "HRS0,Hardware Request Status Channel 0" "0: A hardware service request for channel 0 is..,1: A hardware service request for channel 0 is.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
bitfld.long 0x00 15. "EDREQ_15,Enable asynchronous DMA request in stop mode for channel 15" "0: Disable asynchronous DMA request for channel 15,1: Enable asynchronous DMA request for channel 15"
|
|
bitfld.long 0x00 14. "EDREQ_14,Enable asynchronous DMA request in stop mode for channel 14" "0: Disable asynchronous DMA request for channel 14,1: Enable asynchronous DMA request for channel 14"
|
|
newline
|
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bitfld.long 0x00 13. "EDREQ_13,Enable asynchronous DMA request in stop mode for channel 13" "0: Disable asynchronous DMA request for channel 13,1: Enable asynchronous DMA request for channel 13"
|
|
bitfld.long 0x00 12. "EDREQ_12,Enable asynchronous DMA request in stop mode for channel 12" "0: Disable asynchronous DMA request for channel 12,1: Enable asynchronous DMA request for channel 12"
|
|
newline
|
|
bitfld.long 0x00 11. "EDREQ_11,Enable asynchronous DMA request in stop mode for channel 11" "0: Disable asynchronous DMA request for channel 11,1: Enable asynchronous DMA request for channel 11"
|
|
bitfld.long 0x00 10. "EDREQ_10,Enable asynchronous DMA request in stop mode for channel 10" "0: Disable asynchronous DMA request for channel 10,1: Enable asynchronous DMA request for channel 10"
|
|
newline
|
|
bitfld.long 0x00 9. "EDREQ_9,Enable asynchronous DMA request in stop mode for channel 9" "0: Disable asynchronous DMA request for channel 9,1: Enable asynchronous DMA request for channel 9"
|
|
bitfld.long 0x00 8. "EDREQ_8,Enable asynchronous DMA request in stop mode for channel 8" "0: Disable asynchronous DMA request for channel 8,1: Enable asynchronous DMA request for channel 8"
|
|
newline
|
|
bitfld.long 0x00 7. "EDREQ_7,Enable asynchronous DMA request in stop mode for channel 7" "0: Disable asynchronous DMA request for channel 7,1: Enable asynchronous DMA request for channel 7"
|
|
bitfld.long 0x00 6. "EDREQ_6,Enable asynchronous DMA request in stop mode for channel 6" "0: Disable asynchronous DMA request for channel 6,1: Enable asynchronous DMA request for channel 6"
|
|
newline
|
|
bitfld.long 0x00 5. "EDREQ_5,Enable asynchronous DMA request in stop mode for channel 5" "0: Disable asynchronous DMA request for channel 5,1: Enable asynchronous DMA request for channel 5"
|
|
bitfld.long 0x00 4. "EDREQ_4,Enable asynchronous DMA request in stop mode for channel 4" "0: Disable asynchronous DMA request for channel 4,1: Enable asynchronous DMA request for channel 4"
|
|
newline
|
|
bitfld.long 0x00 3. "EDREQ_3,Enable asynchronous DMA request in stop mode for channel 3" "0: Disable asynchronous DMA request for channel 3,1: Enable asynchronous DMA request for channel 3"
|
|
bitfld.long 0x00 2. "EDREQ_2,Enable asynchronous DMA request in stop mode for channel 2" "0: Disable asynchronous DMA request for channel 2,1: Enable asynchronous DMA request for channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "EDREQ_1,Enable asynchronous DMA request in stop mode for channel 1" "0: Disable asynchronous DMA request for channel 1,1: Enable asynchronous DMA request for channel 1"
|
|
bitfld.long 0x00 0. "EDREQ_0,Enable asynchronous DMA request in stop mode for channel 0" "0: Disable asynchronous DMA request for channel 0,1: Enable asynchronous DMA request for channel 0"
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI$1,Channel Priority Register"
|
|
bitfld.byte 0x00 7. "ECP,Enable Channel Preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.."
|
|
bitfld.byte 0x00 6. "DPA,Disable Preempt Ability" "0: Channel n can suspend a lower priority channel,1: Channel n cannot suspend any channel.."
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CHPRI,Channel n Arbitration Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1004++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1006++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1014++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x101C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x103C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1044++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1046++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1054++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x105C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1064++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1066++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1074++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x107C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1084++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1086++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1094++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x109C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10A4++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10A6++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10B4++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10BC++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10C4++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10C6++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10D4++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10DC++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10E4++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10E6++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10F4++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10FC++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1104++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1106++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1114++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x111C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1124++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1126++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1134++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x113C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1144++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1146++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x114C++0x03
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1154++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x115C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1164++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1166++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x116C++0x03
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1174++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x117C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1184++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1186++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x118C++0x03
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1194++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x119C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11A4++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11A6++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11B4++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11BC++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11C4++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11C6++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11CC++0x03
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11D4++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11DC++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11E4++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11E6++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: 16-byte burst,5: 32-byte burst,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11EC++0x03
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11F4++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11FC++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "DMA1"
|
|
base ad:0x41008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
bitfld.long 0x00 17. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 16. "ECX,Error Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer in the.."
|
|
bitfld.long 0x00 7. "EMLM,Enable Minor Loop Mapping" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "CLM,Continuous Link Mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.."
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
newline
|
|
bitfld.long 0x00 4. "HOE,Halt On Error" "0: Normal operation,1: Any error causes the HALT bit to set"
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Fixed priority arbitration is used for..,1: Round robin arbitration is used for channel.."
|
|
newline
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: When in debug mode the DMA continues to operate,1: When in debug mode the DMA stalls the start.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. "VLD,VLD" "0: No ERR bits are set,1: At least one ERR bit is set indicating a.."
|
|
bitfld.long 0x00 16. "ECX,Transfer Canceled" "0: No canceled transfers,1: The last recorded entry was a canceled.."
|
|
newline
|
|
bitfld.long 0x00 14. "CPE,Channel Priority Error" "0: No channel priority error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 8.--10. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: The last recorded error was a bus error on a.."
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: The last recorded error was a bus error on a.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
bitfld.long 0x00 7. "ERQ7,Enable DMA Request 7" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 6. "ERQ6,Enable DMA Request 6" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "ERQ5,Enable DMA Request 5" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 4. "ERQ4,Enable DMA Request 4" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "ERQ3,Enable DMA Request 3" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 2. "ERQ2,Enable DMA Request 2" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "ERQ1,Enable DMA Request 1" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 0. "ERQ0,Enable DMA Request 0" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
bitfld.long 0x00 7. "EEI7,Enable Error Interrupt 7" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 6. "EEI6,Enable Error Interrupt 6" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 5. "EEI5,Enable Error Interrupt 5" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 4. "EEI4,Enable Error Interrupt 4" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 3. "EEI3,Enable Error Interrupt 3" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 2. "EEI2,Enable Error Interrupt 2" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 1. "EEI1,Enable Error Interrupt 1" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 0. "EEI0,Enable Error Interrupt 0" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEE,Clear All Enable Error Interrupts" "0: Clear only the EEI bit specified in the CEEI..,1: Clear all bits in EEI"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "CEEI,Clear Enable Error Interrupt" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAEE,Sets All Enable Error Interrupts" "0: Set only the EEI bit specified in the SEEI..,1: Sets all bits in EEI"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "SEEI,Set Enable Error Interrupt" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAER,Clear All Enable Requests" "0: Clear only the ERQ bit specified in the CERQ..,1: Clear all bits in ERQ"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "CERQ,Clear Enable Request" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAER,Set All Enable Requests" "0: Set only the ERQ bit specified in the SERQ..,1: Set all bits in ERQ"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "SERQ,Set Enable Request" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CADN,Clears All DONE Bits" "0: Clears only the TCDn_CSR[DONE] bit specified..,1: Clears all bits in TCDn_CSR[DONE]"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "CDNE,Clear DONE Bit" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAST,Set All START Bits (activates all channels)" "0: Set only the TCDn_CSR[START] bit specified in..,1: Set all bits in TCDn_CSR[START]"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "SSRT,Set START Bit" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "CERR,Clear Error Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEI,Clear All Error Indicators" "0: Clear only the ERR bit specified in the CERR..,1: Clear all bits in ERR"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "CERR,Clear Error Indicator" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAIR,Clear All Interrupt Requests" "0: Clear only the INT bit specified in the CINT..,1: Clear all bits in INT"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "CINT,Clear Interrupt Request" "0,1,2,3,4,5,6,7"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
eventfld.long 0x00 7. "INT7,Interrupt Request 7" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 6. "INT6,Interrupt Request 6" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 5. "INT5,Interrupt Request 5" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 4. "INT4,Interrupt Request 4" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 3. "INT3,Interrupt Request 3" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 2. "INT2,Interrupt Request 2" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
eventfld.long 0x00 1. "INT1,Interrupt Request 1" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
eventfld.long 0x00 0. "INT0,Interrupt Request 0" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
eventfld.long 0x00 7. "ERR7,Error In Channel 7" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 6. "ERR6,Error In Channel 6" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 5. "ERR5,Error In Channel 5" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 4. "ERR4,Error In Channel 4" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 3. "ERR3,Error In Channel 3" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 2. "ERR2,Error In Channel 2" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
eventfld.long 0x00 1. "ERR1,Error In Channel 1" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
eventfld.long 0x00 0. "ERR0,Error In Channel 0" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 7. "HRS7,Hardware Request Status Channel 7" "0: A hardware service request for channel 7 is..,1: A hardware service request for channel 7 is.."
|
|
bitfld.long 0x00 6. "HRS6,Hardware Request Status Channel 6" "0: A hardware service request for channel 6 is..,1: A hardware service request for channel 6 is.."
|
|
newline
|
|
bitfld.long 0x00 5. "HRS5,Hardware Request Status Channel 5" "0: A hardware service request for channel 5 is..,1: A hardware service request for channel 5 is.."
|
|
bitfld.long 0x00 4. "HRS4,Hardware Request Status Channel 4" "0: A hardware service request for channel 4 is..,1: A hardware service request for channel 4 is.."
|
|
newline
|
|
bitfld.long 0x00 3. "HRS3,Hardware Request Status Channel 3" "0: A hardware service request for channel 3 is..,1: A hardware service request for channel 3 is.."
|
|
bitfld.long 0x00 2. "HRS2,Hardware Request Status Channel 2" "0: A hardware service request for channel 2 is..,1: A hardware service request for channel 2 is.."
|
|
newline
|
|
bitfld.long 0x00 1. "HRS1,Hardware Request Status Channel 1" "0: A hardware service request for channel 1 is..,1: A hardware service request for channel 1 is.."
|
|
bitfld.long 0x00 0. "HRS0,Hardware Request Status Channel 0" "0: A hardware service request for channel 0 is..,1: A hardware service request for channel 0 is.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
bitfld.long 0x00 7. "EDREQ_7,Enable asynchronous DMA request in stop mode for channel 7" "0: Disable asynchronous DMA request for channel 7,1: Enable asynchronous DMA request for channel 7"
|
|
bitfld.long 0x00 6. "EDREQ_6,Enable asynchronous DMA request in stop mode for channel 6" "0: Disable asynchronous DMA request for channel 6,1: Enable asynchronous DMA request for channel 6"
|
|
newline
|
|
bitfld.long 0x00 5. "EDREQ_5,Enable asynchronous DMA request in stop mode for channel 5" "0: Disable asynchronous DMA request for channel 5,1: Enable asynchronous DMA request for channel 5"
|
|
bitfld.long 0x00 4. "EDREQ_4,Enable asynchronous DMA request in stop mode for channel 4" "0: Disable asynchronous DMA request for channel 4,1: Enable asynchronous DMA request for channel 4"
|
|
newline
|
|
bitfld.long 0x00 3. "EDREQ_3,Enable asynchronous DMA request in stop mode for channel 3" "0: Disable asynchronous DMA request for channel 3,1: Enable asynchronous DMA request for channel 3"
|
|
bitfld.long 0x00 2. "EDREQ_2,Enable asynchronous DMA request in stop mode for channel 2" "0: Disable asynchronous DMA request for channel 2,1: Enable asynchronous DMA request for channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "EDREQ_1,Enable asynchronous DMA request in stop mode for channel 1" "0: Disable asynchronous DMA request for channel 1,1: Enable asynchronous DMA request for channel 1"
|
|
bitfld.long 0x00 0. "EDREQ_0,Enable asynchronous DMA request in stop mode for channel 0" "0: Disable asynchronous DMA request for channel 0,1: Enable asynchronous DMA request for channel 0"
|
|
repeat 8. (strings "3" "2" "1" "0" "7" "6" "5" "4" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 )
|
|
group.byte ($2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI$1,Channel Priority Register"
|
|
bitfld.byte 0x00 7. "ECP,Enable Channel Preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.."
|
|
bitfld.byte 0x00 6. "DPA,Disable Preempt Ability" "0: Channel n can suspend a lower priority channel,1: Channel n cannot suspend any channel.."
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|
newline
|
|
bitfld.byte 0x00 0.--2. "CHPRI,Channel n Arbitration Priority" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1004++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1006++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
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|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
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|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
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|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
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|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
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|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1014++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x101C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x103C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1044++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1046++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1054++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x105C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1064++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1066++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1074++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x107C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1084++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1086++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1094++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x109C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10A4++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10A6++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10B4++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10BC++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10C4++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10C6++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10D4++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10DC++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10E4++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10E6++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: SMOD_0,1: SMOD_1,2: SMOD_2,3: SMOD_3,4: SMOD_4,5: SMOD_5,6: SMOD_6,7: SMOD_7,8: SMOD_8,9: SMOD_9,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,?,4: SSIZE_4,5: SSIZE_5,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10F4++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10FC++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--10. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
rbitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: The channel's ERQ bit is not affected,1: The channel's ERQ bit is cleared when the.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--11. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "DMAMUX (DMA_CH_MUX)"
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "DMAMUX0"
|
|
base ad:0x40021000
|
|
repeat 16. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CHCFG[$1],Channel 0 Configuration Register $1"
|
|
bitfld.long 0x00 31. "ENBL,DMA Mux Channel Enable" "0: DMA Mux channel is disabled,1: DMA Mux channel is enabled"
|
|
bitfld.long 0x00 30. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled,1: Triggering is enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "A_ON,DMA Channel Always Enable" "0: DMA Channel Always ON function is disabled,1: DMA Channel Always ON function is enabled"
|
|
bitfld.long 0x00 0.--5. "SOURCE,DMA Channel Source (Slot Number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "DMAMUX0"
|
|
base ad:0x40021000
|
|
repeat 16. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CHCFG[$1],Channel 0 Configuration Register $1"
|
|
bitfld.long 0x00 31. "ENBL,DMA Mux Channel Enable" "0: DMA Mux channel is disabled,1: DMA Mux channel is enabled"
|
|
bitfld.long 0x00 30. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled,1: Triggering is enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "A_ON,DMA Channel Always Enable" "0: DMA Channel Always ON function is disabled,1: DMA Channel Always ON function is enabled"
|
|
bitfld.long 0x00 0.--5. "SOURCE,DMA Channel Source (Slot Number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "DMAMUX1"
|
|
base ad:0x41021000
|
|
repeat 8. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CHCFG[$1],Channel 0 Configuration Register $1"
|
|
bitfld.long 0x00 31. "ENBL,DMA Mux Channel Enable" "0: DMA Mux channel is disabled,1: DMA Mux channel is enabled"
|
|
bitfld.long 0x00 30. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled,1: Triggering is enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "A_ON,DMA Channel Always Enable" "0: DMA Channel Always ON function is disabled,1: DMA Channel Always ON function is enabled"
|
|
bitfld.long 0x00 0.--4. "SOURCE,DMA Channel Source (Slot Number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "DWT (Data Watchpoint and Trace Unit Registers)"
|
|
base ad:0xE0001000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. "NUMCOMP,NUMCOMP bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. "NOTRCPKT,NOTRCPKT bit" "0: Trace sampling and exception tracing supported,1: Trace sampling and exception tracing not.."
|
|
newline
|
|
rbitfld.long 0x00 26. "NOEXTTRIG,NOEXTRRIG bit" "0: CMPMATCH[N] supported,1: CMPMATCH[N] not supported"
|
|
rbitfld.long 0x00 25. "NOCYCCNT,NOCYCCNT bit" "0: Cycle counter supported,1: Cycle counter not supported"
|
|
newline
|
|
rbitfld.long 0x00 24. "NOPFRCNT,NOPFRCNT bit" "0: NOPFRCNT_0,1: Not supported"
|
|
bitfld.long 0x00 22. "CYCEVTENA,CYCEVTENA bit" "0: No POSTCNT underflow packets generated,1: POSTCNT underflow packets generated if.."
|
|
newline
|
|
bitfld.long 0x00 21. "FOLDEVTENA,FOLDEVTENA bit" "0: FOLDEVTENA_0,1: FOLDEVTENA_1"
|
|
bitfld.long 0x00 20. "LSUEVTENA,LSUEVTENA bit" "0: LSUEVTENA_0,1: LSUEVTENA_1"
|
|
newline
|
|
bitfld.long 0x00 19. "SLEEPEVTENA,SLEEPEVTENA bit" "0: SLEEPEVTENA_0,1: SLEEPEVTENA_1"
|
|
bitfld.long 0x00 18. "EXCEVTENA,EXCEVTENA bit" "0: EXCEVTENA_0,1: EXCEVTENA_1"
|
|
newline
|
|
bitfld.long 0x00 17. "CPIEVTENA,CPIEVTENA bit" "0: CPIEVTENA_0,1: CPIEVTENA_1"
|
|
bitfld.long 0x00 16. "EXCTRCENA,EXCTRCENA bit" "0: EXCTRCENA_0,1: EXCTRCENA_1"
|
|
newline
|
|
bitfld.long 0x00 12. "PCSAMPLENA,PCSAMPLENA bit" "0: No Periodic PC sample packets generated,1: Periodic PC sample packets generated"
|
|
bitfld.long 0x00 10.--11. "SYNCTAP,SYNCTAP bits" "0: Disabled,1: Synchronization counter tap at CYCCNT[24],2: Synchronization counter tap at CYCCNT[26],3: Synchronization counter tap at CYCCNT[28]"
|
|
newline
|
|
bitfld.long 0x00 9. "CYCTAP,CYCTAP bit" "0: POSTCNT tap at CYCCNT[6],1: POSTCNT tap at CYCCNT[10]"
|
|
bitfld.long 0x00 5.--8. "POSTINIT,POSTINIT bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "POSTPRESET,POSTPRESET bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "CYCCNTENA,CYCCNTENA bit" "0: CYCCNTENA_0,1: CYCCNTENA_1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CYCCNT,Cycle Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "CYCCNT,CYCCNT[31:0]"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CPICNT,CPICNT[7:0]"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EXCCNT,EXCCNT[7:0]"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SLEEPCNT,SLEEPCNT[7:0]"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LSUCNT,LSUCNT[7:0]"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FOLDCNT,FOLDCNT[7:0]"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PCSR,Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. "EIASAMPLE,EIASAMPLE[31:0]"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP0,Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,COMP[31:0]"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MASK0,Mask Register 0"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FUNCTION0,Function Register 0"
|
|
rbitfld.long 0x00 24. "MATCHED,MATCHED bit" "0: MATCHED_0,1: MATCHED_1"
|
|
bitfld.long 0x00 16.--19. "DATAVADDR1,DATAVADDR1[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,DATAVADDR0[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,DATAVSIZE[1:0]" "0: DATAVSIZE_0,1: DATAVSIZE_1,2: DATAVSIZE_2,?..."
|
|
newline
|
|
rbitfld.long 0x00 9. "LNK1ENA,LNK1ENA bit" "0: Second linked comparator not supported,1: Second linked comparator supported"
|
|
bitfld.long 0x00 8. "DATAVMATCH,DATAVMATCH bit" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 7. "CYCMATCH,CYCMATCH bit" "0: No comparison is performed,1: Compare DWT_COMP0 with the cycle counter.."
|
|
bitfld.long 0x00 5. "EMITRANGE,EMITRANGE bit" "0: Data trace address offset packets disabled,1: Enable Data trace address offset packet.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FUNCTION,FUNCTION[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP1,Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,COMP[31:0]"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,Mask Register 1"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FUNCTION1,Function Register 1"
|
|
rbitfld.long 0x00 24. "MATCHED,MATCHED bit" "0: MATCHED_0,1: MATCHED_1"
|
|
bitfld.long 0x00 16.--19. "DATAVADDR1,DATAVADDR1[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,DATAVADDR0[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,DATAVSIZE[1:0]" "0: DATAVSIZE_0,1: DATAVSIZE_1,2: DATAVSIZE_2,?..."
|
|
newline
|
|
rbitfld.long 0x00 9. "LNK1ENA,LNK1ENA bit" "0: Second linked comparator not supported,1: Second linked comparator supported"
|
|
bitfld.long 0x00 8. "DATAVMATCH,DATAVMATCH bit" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 5. "EMITRANGE,EMITRANGE bit" "0: Data trace address offset packets disabled,1: Enable Data trace address offset packet.."
|
|
bitfld.long 0x00 0.--3. "FUNCTION,FUNCTION[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "COMP2,Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,COMP[31:0]"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MASK2,Mask Register 2"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FUNCTION2,Function Register 2"
|
|
rbitfld.long 0x00 24. "MATCHED,MATCHED bit" "0: MATCHED_0,1: MATCHED_1"
|
|
bitfld.long 0x00 16.--19. "DATAVADDR1,DATAVADDR1[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,DATAVADDR0[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,DATAVSIZE[1:0]" "0: DATAVSIZE_0,1: DATAVSIZE_1,2: DATAVSIZE_2,?..."
|
|
newline
|
|
rbitfld.long 0x00 9. "LNK1ENA,LNK1ENA bit" "0: Second linked comparator not supported,1: Second linked comparator supported"
|
|
bitfld.long 0x00 8. "DATAVMATCH,DATAVMATCH bit" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 5. "EMITRANGE,EMITRANGE bit" "0: Data trace address offset packets disabled,1: Enable Data trace address offset packet.."
|
|
bitfld.long 0x00 0.--3. "FUNCTION,FUNCTION[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "COMP3,Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,COMP[31:0]"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MASK3,Mask Register 3"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FUNCTION3,Function Register 3"
|
|
rbitfld.long 0x00 24. "MATCHED,MATCHED bit" "0: MATCHED_0,1: MATCHED_1"
|
|
bitfld.long 0x00 16.--19. "DATAVADDR1,DATAVADDR1[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,DATAVADDR0[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,DATAVSIZE[1:0]" "0: DATAVSIZE_0,1: DATAVSIZE_1,2: DATAVSIZE_2,?..."
|
|
newline
|
|
rbitfld.long 0x00 9. "LNK1ENA,LNK1ENA bit" "0: Second linked comparator not supported,1: Second linked comparator supported"
|
|
bitfld.long 0x00 8. "DATAVMATCH,DATAVMATCH bit" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 5. "EMITRANGE,EMITRANGE bit" "0: Data trace address offset packets disabled,1: Enable Data trace address offset packet.."
|
|
bitfld.long 0x00 0.--3. "FUNCTION,FUNCTION[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
bitfld.long 0x00 4.--7. "c4KB,4KB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "JEP106,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "5" "6" "7" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PID$1,Peripheral Identification Register 5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PID0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber,Part Number [7:0]"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PID1,Peripheral Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "JEP106_identity_code,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PartNumber,Part Number [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PID2,Peripheral Identification Register 2"
|
|
bitfld.long 0x00 4.--7. "Revision,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PID3,Peripheral Identification Register 3"
|
|
bitfld.long 0x00 4.--7. "RevAnd,RevAnd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CustomerModified,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "CID0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CID1,Component Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "ComponentClass,Component class" "?,1: ComponentClass_1,?,?,?,?,?,?,?,9: CoreSight component,?,?,?,?,?,15: PrimeCell of system component with no.."
|
|
bitfld.long 0x00 0.--3. "Preamble,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "CID$1,Component Identification Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "EMVSIM"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "EMVSIM0"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4004E000
|
|
elif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x40038000
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VER_ID,Version ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "VER,Version ID of the module"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TX_FIFO_DEPTH,Transmit FIFO Depth"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_DEPTH,Receive FIFO Depth"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x00 10.--11. "GPCNT0_CLK_SEL,General Purpose Counter 0 Clock Select" "0: Disabled / Reset (default),1: GPCNT0_CLK_SEL_1,2: GPCNT0_CLK_SEL_2,3: ETU Clock (transmit clock)"
|
|
bitfld.long 0x00 8.--9. "GPCNT1_CLK_SEL,General Purpose Counter 1 Clock Select" "0: Disabled / Reset (default),1: GPCNT1_CLK_SEL_1,2: GPCNT1_CLK_SEL_2,3: ETU Clock (transmit clock)"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLK_PRSC,Clock Prescaler Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x00 10.--11. "GPCNT0_CLK_SEL,General Purpose Counter 0 Clock Select" "0: Disabled / Reset (default),1: Card Clock,2: Receive Clock,3: ETU Clock (transmit clock)"
|
|
bitfld.long 0x00 8.--9. "GPCNT1_CLK_SEL,General Purpose Counter 1 Clock Select" "0: Disabled / Reset (default),1: Card Clock,2: Receive Clock,3: ETU Clock (transmit clock)"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLK_PRSC,Clock Prescaler Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIVISOR,Baud Rate Divisor Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "DIVISOR_VALUE,Divisor (F/D) Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL,Control Register"
|
|
bitfld.long 0x00 31. "BWT_EN,Block Wait Time Counter Enable" "0: Disable BWT BGT Counters (default),1: Enable BWT BGT Counters"
|
|
bitfld.long 0x00 30. "XMT_CRC_LRC,Transmit CRC or LRC Enable" "0: No CRC or LRC value is transmitted (default),1: Transmit LRC or CRC info when FIFO empties.."
|
|
newline
|
|
bitfld.long 0x00 29. "CRC_EN,CRC Enable" "0: 16-bit Cyclic Redundancy Checking disabled..,1: 16-bit Cyclic Redundancy Checking enabled"
|
|
bitfld.long 0x00 28. "LRC_EN,LRC Enable" "0: 8-bit Linear Redundancy Checking disabled..,1: 8-bit Linear Redundancy Checking enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "CWT_EN,Character Wait Time Counter Enable" "0: Character Wait time Counter is disabled..,1: Character Wait time counter is enabled"
|
|
bitfld.long 0x00 26. "CRC_IN_FLIP,CRC Input Byte's Bit Reversal or Flip Control" "0: Bits in the input byte will not be reversed..,1: Bits in the input byte will be reversed (i.e.."
|
|
newline
|
|
bitfld.long 0x00 25. "CRC_OUT_FLIP,CRC Output Value Bit Reversal or Flip" "0: Bits within the CRC output bytes will not be..,1: Bits within the CRC output bytes will be.."
|
|
bitfld.long 0x00 24. "INV_CRC_VAL,Invert bits in the CRC Output Value" "0: Bits in CRC Output value will not be inverted,1: Bits in CRC Output value will be inverted"
|
|
newline
|
|
bitfld.long 0x00 20. "TX_DMA_EN,Transmit DMA Enable" "0: No DMA Write Request asserted for Transmitter..,1: DMA Write Request asserted for Transmitter"
|
|
bitfld.long 0x00 19. "RX_DMA_EN,Receive DMA Enable" "0: No DMA Read Request asserted for Receiver..,1: DMA Read Request asserted for Receiver"
|
|
newline
|
|
bitfld.long 0x00 18. "RCVR_11,Receiver 11 ETU Mode Enable" "0: Receiver configured for 12 ETU operation mode..,1: Receiver configured for 11 ETU operation mode"
|
|
bitfld.long 0x00 17. "XMT_EN,Transmitter Enable" "0: EMV SIM Transmitter disabled (default),1: EMV SIM Transmitter enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "RCV_EN,Receiver Enable" "0: EMV SIM Receiver disabled (default),1: EMV SIM Receiver enabled"
|
|
bitfld.long 0x00 13. "STOP_EN,STOP Enable" "0: STOP instruction shuts down all EMV SIM..,1: STOP instruction shuts down all clocks except.."
|
|
newline
|
|
bitfld.long 0x00 12. "DOZE_EN,Doze Enable" "0: DOZE instruction will gate all internal EMV..,1: DOZE instruction has no effect on EMV SIM.."
|
|
bitfld.long 0x00 11. "KILL_CLOCKS,Kill all internal clocks" "0: EMV SIM input clock enabled (default),1: EMV SIM input clock is disabled"
|
|
newline
|
|
bitfld.long 0x00 10. "SW_RST,Software Reset Bit" "0: EMV SIM Normal operation (default),1: EMV SIM held in Reset"
|
|
bitfld.long 0x00 9. "FLSH_TX,Flush Transmitter Bit" "0: EMV SIM Transmitter normal operation (default),1: EMV SIM Transmitter held in Reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FLSH_RX,Flush Receiver Bit" "0: EMV SIM Receiver normal operation (default),1: EMV SIM Receiver held in Reset"
|
|
bitfld.long 0x00 3. "ONACK,Overrun NACK Enable" "0: NACK generation on overrun is disabled..,1: NACK generation on overrun is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "ANACK,Auto NACK Enable" "0: NACK generation on errors disabled,1: NACK generation on errors enabled (default)"
|
|
bitfld.long 0x00 1. "ICM,Initial Character Mode" "0: Initial Character Mode disabled,1: Initial Character Mode enabled (default)"
|
|
newline
|
|
bitfld.long 0x00 0. "IC,Inverse Convention" "0: Direction convention transfers enabled..,1: Inverse convention transfers enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INT_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x00 15. "PEF_IM,Parity Error Interrupt Mask" "0: PEF interrupt enabled,1: PEF interrupt masked (default)"
|
|
bitfld.long 0x00 14. "RX_DATA_IM,Receive Data Interrupt Mask" "0: RX_DATA interrupt enabled,1: RX_DATA interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 13. "GPCNT1_IM,General Purpose Counter 1 Timeout Interrupt Mask" "0: GPCNT1_TO interrupt enabled,1: GPCNT1_TO interrupt masked (default)"
|
|
bitfld.long 0x00 12. "BGT_ERR_IM,Block Guard Time Error Interrupt" "0: BGT_ERR interrupt enabled,1: BGT_ERR interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 11. "BWT_ERR_IM,Block Wait Time Error Interrupt Mask" "0: BWT_ERR interrupt enabled,1: BWT_ERR interrupt masked (default)"
|
|
bitfld.long 0x00 10. "RNACK_IM,Receiver NACK Threshold Interrupt Mask" "0: RTE interrupt enabled,1: RTE interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 9. "CWT_ERR_IM,Character Wait Time Error Interrupt Mask" "0: CWT_ERR interrupt enabled,1: CWT_ERR interrupt masked (default)"
|
|
bitfld.long 0x00 8. "GPCNT0_IM,General Purpose Timer 0 Timeout Interrupt Mask" "0: GPCNT0_TO interrupt enabled,1: GPCNT0_TO interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 7. "TDT_IM,Transmit Data Threshold Interrupt Mask" "0: TDTF interrupt enabled,1: TDTF interrupt masked (default)"
|
|
bitfld.long 0x00 6. "TFF_IM,Transmit FIFO Full Interrupt Mask" "0: TFF interrupt enabled,1: TFF interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 5. "TNACK_IM,Transmit NACK Threshold Interrupt Mask" "0: TNTE interrupt enabled,1: TNTE interrupt masked (default)"
|
|
bitfld.long 0x00 4. "TFE_IM,Transmit FIFO Empty Interrupt Mask" "0: TFE interrupt enabled,1: TFE interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 3. "ETC_IM,Early Transmit Complete Interrupt Mask" "0: ETC interrupt enabled,1: ETC interrupt masked (default)"
|
|
bitfld.long 0x00 2. "RFO_IM,Receive FIFO Overflow Interrupt Mask" "0: RFO interrupt enabled,1: RFO interrupt masked (default)"
|
|
newline
|
|
bitfld.long 0x00 1. "TC_IM,Transmit Complete Interrupt Mask" "0: TCF interrupt enabled,1: TCF interrupt masked (default)"
|
|
bitfld.long 0x00 0. "RDT_IM,Receive Data Threshold Interrupt Mask" "0: RDTF interrupt enabled,1: RDTF interrupt masked (default)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX_THD,Receiver Threshold Register"
|
|
bitfld.long 0x00 8.--11. "RNCK_THD,Receiver NACK Threshold Value" "0: Zero Threshold,?..."
|
|
bitfld.long 0x00 0.--3. "RDT,Receiver Data Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TX_THD,Transmitter Threshold Register"
|
|
bitfld.long 0x00 8.--11. "TNCK_THD,Transmitter NACK Threshold Value" "0: TNTE will never be set retransmission after..,1: TNTE will be set after 1 nack is received 0..,2: TNTE will be set after 2 nacks are received..,3: TNTE will be set after 3 nacks are received..,?,?,?,?,?,?,?,?,?,?,?,15: TNTE will be set after 15 nacks are received.."
|
|
bitfld.long 0x00 0.--3. "TDT,Transmitter Data Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RX_STATUS,Receive Status Register"
|
|
rbitfld.long 0x00 22.--24. "RX_CNT,Receive FIFO Byte Count" "0: FIFO is emtpy,?..."
|
|
rbitfld.long 0x00 16.--17. "RX_WPTR,Receive FIFO Write Pointer Value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "FEF,Frame Error Flag" "0: No frame error detected,1: Frame error detected"
|
|
bitfld.long 0x00 12. "PEF,Parity Error Flag" "0: No parity error detected,1: Parity error detected"
|
|
newline
|
|
bitfld.long 0x00 11. "BGT_ERR,Block Guard Time Error Flag" "0: Block guard time was sufficient,1: Block guard time was too small"
|
|
bitfld.long 0x00 10. "BWT_ERR,Block Wait Time Error Flag" "0: Block wait time not exceeded,1: Block wait time was exceeded"
|
|
newline
|
|
bitfld.long 0x00 9. "RTE,Received NACK Threshold Error Flag" "0: Number of NACKs generated by the receiver is..,1: Number of NACKs generated by the receiver is.."
|
|
bitfld.long 0x00 8. "CWT_ERR,Character Wait Time Error Flag" "0: No CWT violation has occurred (default),1: Time between two consecutive characters has.."
|
|
newline
|
|
rbitfld.long 0x00 7. "CRC_OK,CRC Check OK Flag" "0: Current CRC value does not match remainder,1: Current calculated CRC value matches the.."
|
|
rbitfld.long 0x00 6. "LRC_OK,LRC Check OK Flag" "0: Current LRC value does not match remainder,1: Current calculated LRC value matches the.."
|
|
newline
|
|
rbitfld.long 0x00 5. "RDTF,Receive Data Threshold Interrupt Flag" "0: Number of unread bytes in receive FIFO less..,1: Number of unread bytes in receive FIFO.."
|
|
bitfld.long 0x00 4. "RX_DATA,Receive Data Interrupt Flag" "0: No new byte is received,1: New byte is received ans stored in Receive FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. "RFO,Receive FIFO Overflow Flag" "0: No overrun error has occurred (default),1: A byte was received when the received FIFO.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RX_STATUS,Receive Status Register"
|
|
rbitfld.long 0x00 24.--27. "RX_CNT,Receive FIFO Byte Count" "0: FIFO is emtpy,?..."
|
|
rbitfld.long 0x00 16.--19. "RX_WPTR,Receive FIFO Write Pointer Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
eventfld.long 0x00 13. "FEF,Frame Error Flag" "0: No frame error detected,1: Frame error detected"
|
|
eventfld.long 0x00 12. "PEF,Parity Error Flag" "0: No parity error detected,1: Parity error detected"
|
|
newline
|
|
eventfld.long 0x00 11. "BGT_ERR,Block Guard Time Error Flag" "0: Block guard time was sufficient,1: Block guard time was too small"
|
|
eventfld.long 0x00 10. "BWT_ERR,Block Wait Time Error Flag" "0: Block wait time not exceeded,1: Block wait time was exceeded"
|
|
newline
|
|
eventfld.long 0x00 9. "RTE,Received NACK Threshold Error Flag" "0: Number of NACKs generated by the receiver is..,1: Number of NACKs generated by the receiver is.."
|
|
eventfld.long 0x00 8. "CWT_ERR,Character Wait Time Error Flag" "0: No CWT violation has occurred (default),1: Time between two consecutive characters has.."
|
|
newline
|
|
rbitfld.long 0x00 7. "CRC_OK,CRC Check OK Flag" "0: Current CRC value does not match remainder,1: Current calculated CRC value matches the.."
|
|
rbitfld.long 0x00 6. "LRC_OK,LRC Check OK Flag" "0: Current LRC value does not match remainder,1: Current calculated LRC value matches the.."
|
|
newline
|
|
rbitfld.long 0x00 5. "RDTF,Receive Data Threshold Interrupt Flag" "0: Number of unread bytes in receive FIFO less..,1: Number of unread bytes in receive FIFO.."
|
|
eventfld.long 0x00 4. "RX_DATA,Receive Data Interrupt Flag" "0: No new byte is received,1: New byte is received ans stored in Receive FIFO"
|
|
newline
|
|
eventfld.long 0x00 0. "RFO,Receive FIFO Overflow Flag" "0: No overrun error has occurred (default),1: A byte was received when the received FIFO.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TX_STATUS,Transmitter Status Register"
|
|
rbitfld.long 0x00 22.--24. "TX_CNT,Transmit FIFO Byte Count" "0: FIFO is emtpy,?..."
|
|
rbitfld.long 0x00 16.--17. "TX_RPTR,Transmit FIFO Read Pointer" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "GPCNT1_TO,General Purpose Counter 1 Timeout Flag" "0: GPCNT1_VAL time not reached or bit has been..,1: General Purpose counter has reached the.."
|
|
bitfld.long 0x00 8. "GPCNT0_TO,General Purpose Counter 0 Timeout Flag" "0: GPCNT0_VAL time not reached or bit has been..,1: General Purpose counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x00 7. "TDTF,Transmit Data Threshold Flag" "0: Number of bytes in FIFO is greater than..,1: Number of bytes in FIFO is less than or equal.."
|
|
bitfld.long 0x00 6. "TFF,Transmit FIFO Full Flag" "0: Transmit FIFO Full condition has not occurred..,1: A Transmit FIFO Full condition has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "TCF,Transmit Complete Flag" "0: Transmit pending or in progress,1: Transmit complete (default)"
|
|
bitfld.long 0x00 4. "ETCF,Early Transmit Complete Flag" "0: Transmit pending or in progress,1: Transmit complete (default)"
|
|
newline
|
|
bitfld.long 0x00 3. "TFE,Transmit FIFO Empty Flag" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty (default)"
|
|
bitfld.long 0x00 0. "TNTE,Transmit NACK Threshold Error Flag" "0: Transmit NACK threshold has not been reached..,1: Transmit NACK threshold reached transmitter.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TX_STATUS,Transmitter Status Register"
|
|
rbitfld.long 0x00 24.--27. "TX_CNT,Transmit FIFO Byte Count" "0: FIFO is emtpy,?..."
|
|
rbitfld.long 0x00 16.--19. "TX_RPTR,Transmit FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
eventfld.long 0x00 9. "GPCNT1_TO,General Purpose Counter 1 Timeout Flag" "0: GPCNT1_VAL time not reached or bit has been..,1: General Purpose counter has reached the.."
|
|
eventfld.long 0x00 8. "GPCNT0_TO,General Purpose Counter 0 Timeout Flag" "0: GPCNT0_VAL time not reached or bit has been..,1: General Purpose counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x00 7. "TDTF,Transmit Data Threshold Flag" "0: Number of bytes in FIFO is greater than..,1: Number of bytes in FIFO is less than or equal.."
|
|
eventfld.long 0x00 6. "TFF,Transmit FIFO Full Flag" "0: Transmit FIFO Full condition has not occurred..,1: A Transmit FIFO Full condition has occurred"
|
|
newline
|
|
eventfld.long 0x00 5. "TCF,Transmit Complete Flag" "0: Transmit pending or in progress,1: Transmit complete (default)"
|
|
eventfld.long 0x00 4. "ETCF,Early Transmit Complete Flag" "0: Transmit pending or in progress,1: Transmit complete (default)"
|
|
newline
|
|
eventfld.long 0x00 3. "TFE,Transmit FIFO Empty Flag" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty (default)"
|
|
eventfld.long 0x00 0. "TNTE,Transmit NACK Threshold Error Flag" "0: Transmit NACK threshold has not been reached..,1: Transmit NACK threshold reached transmitter.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCSR,Port Control and Status Register"
|
|
bitfld.long 0x00 27. "SPDES,SIM Presence Detect Edge Select" "0: Falling edge on the pin (default),1: Rising edge on the pin"
|
|
rbitfld.long 0x00 26. "SPDP,Smart Card Presence Detect Pin Status" "0: SIM Presence Detect pin is logic low,1: SIM Presence Detectpin is logic high"
|
|
newline
|
|
bitfld.long 0x00 25. "SPDIF,Smart Card Presence Detect Interrupt Flag" "0: No insertion or removal of Smart Card..,1: Insertion or removal of Smart Card detected.."
|
|
bitfld.long 0x00 24. "SPDIM,Smart Card Presence Detect Interrupt Mask" "0: SIM presence detect interrupt is enabled,1: SIM presence detect interrupt is masked.."
|
|
newline
|
|
bitfld.long 0x00 7. "SPD,Auto Power Down Control" "0: No effect (default),1: Start Auto Powerdown or Power Down is in.."
|
|
bitfld.long 0x00 5. "SCSP,Smart Card Clock Stop Polarity" "0: Clock is logic 0 when stopped by SCEN,1: Clock is logic 1 when stopped by SCEN"
|
|
newline
|
|
bitfld.long 0x00 4. "SCEN,Clock Enable for Smart Card" "0: Smart Card Clock Disabled,1: Smart Card Clock Enabled"
|
|
bitfld.long 0x00 3. "SRST,Reset to Smart Card" "0: Smart Card Reset is asserted (default),1: Smart Card Reset is de-asserted"
|
|
newline
|
|
bitfld.long 0x00 2. "VCCENP,VCC Enable Polarity Control" "0: VCC_EN is active high,1: VCC_EN is active low"
|
|
bitfld.long 0x00 1. "SVCC_EN,Vcc Enable for Smart Card" "0: Smart Card Voltage disabled (default),1: Smart Card Voltage enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SAPD,Auto Power Down Enable" "0: Auto power down disabled (default),1: Auto power down enabled"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCSR,Port Control and Status Register"
|
|
bitfld.long 0x00 27. "SPDES,SIM Presence Detect Edge Select" "0: Falling edge on the pin (default),1: Rising edge on the pin"
|
|
rbitfld.long 0x00 26. "SPDP,Smart Card Presence Detect Pin Status" "0: SIM Presence Detect pin is logic low,1: SIM Presence Detectpin is logic high"
|
|
newline
|
|
eventfld.long 0x00 25. "SPDIF,Smart Card Presence Detect Interrupt Flag" "0: No insertion or removal of Smart Card..,1: Insertion or removal of Smart Card detected.."
|
|
bitfld.long 0x00 24. "SPDIM,Smart Card Presence Detect Interrupt Mask" "0: SIM presence detect interrupt is enabled,1: SIM presence detect interrupt is masked.."
|
|
newline
|
|
bitfld.long 0x00 7. "SPD,Auto Power Down Control" "0: No effect (default),1: Start Auto Powerdown or Power Down is in.."
|
|
bitfld.long 0x00 5. "SCSP,Smart Card Clock Stop Polarity" "0: Clock is logic 0 when stopped by SCEN,1: Clock is logic 1 when stopped by SCEN"
|
|
newline
|
|
bitfld.long 0x00 4. "SCEN,Clock Enable for Smart Card" "0: Smart Card Clock Disabled,1: Smart Card Clock Enabled"
|
|
bitfld.long 0x00 3. "SRST,Reset to Smart Card" "0: Smart Card Reset is asserted (default),1: Smart Card Reset is de-asserted"
|
|
newline
|
|
bitfld.long 0x00 2. "VCCENP,VCC Enable Polarity Control" "0: VCC_EN is active high,1: VCC_EN is active low"
|
|
bitfld.long 0x00 1. "SVCC_EN,Vcc Enable for Smart Card" "0: Smart Card Voltage disabled (default),1: Smart Card Voltage enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SAPD,Auto Power Down Enable" "0: Auto power down disabled (default),1: Auto power down enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RX_BUF,Receive Data Read Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_BYTE,Receive Data Byte"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TX_BUF,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_BYTE,Transmit Data Byte"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TX_GETU,Transmitter Guard ETU Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "GETU,Transmitter Guard Time Value in ETU"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CWT_VAL,Character Wait Time Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CWT,Character Wait Time Value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BWT_VAL,Block Wait Time Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "BWT,Block Wait Time Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BGT_VAL,Block Guard Time Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "BGT,Block Guard Time Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPCNT0_VAL,General Purpose Counter 0 Timeout Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPCNT0,General Purpose Counter 0 Timeout Value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPCNT1_VAL,General Purpose Counter 1 Timeout Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPCNT1,General Purpose Counter 1 Timeout Value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "ETM (Embedded Trace Macrocell Registers)"
|
|
base ad:0xE0041000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Main Control Register"
|
|
bitfld.long 0x00 28. "TE,When set this bit enables timestamping" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "PS3,This bit is implemented but has no function" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PM,These bits are implemented but have no function" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "PM2,This bit is implemented but has no function" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ETMPS,ETM port selection" "0: ETMEN is LOW,1: ETMEN is HIGH"
|
|
newline
|
|
bitfld.long 0x00 10. "ETMP,ETM programming" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "DRC,Debug request control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BO,Branch output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SP,Stall processor" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PS,Port size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "ETMPD,ETM power down" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CCR,Configuration Code Register"
|
|
bitfld.long 0x00 31. "ETMIDRP,The value of this bit is 1 indicating that the ETMIDR register 0x79 is present and defines the ETM architecture version in use" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CMA,Coprocessor and memory access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TSSBP,Trace start/stop block present" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "NCIDC,Number of Context ID comparators" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 23. "FFLP,FIFOFULL logic present" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "NEO,Number of external outputs" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "NEI,Number of external inputs" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "SP,Sequencer present" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "NC,Number of counters" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "NMMD,Number of memory map decoders" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "NDVC,Number of data value comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "NumberOfAddressComparatorPairs,Number of address comparator pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TRIGGER,Trigger Event Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. "TriggerEvent,Trigger event"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,ETM Status Register"
|
|
bitfld.long 0x00 3. "Trigger,Trigger bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "Status,Holds the current status of the trace start/stop resource" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "Progbit,ETM programming bit value (Progbit)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "UOF,Untraced overflow flag" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SCR,System Configuration Register"
|
|
bitfld.long 0x00 17. "NoFetchComparisons,No Fetch comparisons" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "N,These bits give the number of supported processors minus 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "PortModeSupported,Port mode supported" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PortSizeSupported,Port size supported" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "MaximumPortSize3,Maximum ETM port size bit [3]" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FIFOFULLsupported,FIFOFULL supported" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "MaximumPortSize,Maximum ETM port size bits [2:0]" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EEVR,Trace Enable Event Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. "TraceEnableEvent,Trace Enable event"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TECR1,Trace Enable Control 1 Register"
|
|
bitfld.long 0x00 25. "TraceControlEnable,Trace start/stop enable" "0: Tracing is unaffected by the trace start/stop..,1: Tracing is controlled by the trace on and off.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FFLR,FIFOFULL Level Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FIFOFullLevel,FIFO full level"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CNTRLDVR1,Free-running counter reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntitialCount,Initial count"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "SYNCFR,Synchronization Frequency Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "SyncFrequency,Synchronization frequency"
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "IDR,ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ImplementorCode,Implementor code"
|
|
newline
|
|
bitfld.long 0x00 20. "BranchPacketEncoding,Branch packet encoding" "0: The ETM implements the original branch packet..,1: The ETM implements the alternative branch.."
|
|
newline
|
|
bitfld.long 0x00 19. "SecurityExtensionSupport,Security Extensions support" "0: The ETM behaves as if the processor is in..,1: The ARM architecture Security Extensions are.."
|
|
newline
|
|
bitfld.long 0x00 18. "ThumbInstructionTracing,32-bit Thumb instruction tracing" "0: A 32-bit Thumb instruction is traced as two..,1: A 32-bit Thimb instruction is traced as a.."
|
|
newline
|
|
bitfld.long 0x00 16. "LoadPCfirst,Load PC first" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ProcessorFamily,Processor family" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MajorETMarchitectureVersion,Major ETM architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MinorETMarchitectureVersion,Minor ETM architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ImplementationRevision,Implementation revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "CCER,Configuration Code Extension Register"
|
|
bitfld.long 0x00 29. "TimestampSize,Timestamp size" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "TimestampEncoding,Timestamp encoding" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ReducedFunctionCounter,Reduced function counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TimestampingImplemented,Timestamping implemented" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "EmbeddedICEbehaviorControlImplemented,EmbeddedICE behavior control implemented" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "TraceStartStopBlockUsesEmbeddedICEwatchpointInputs,Trace Start/Stop block uses EmbeddedICE watchpoint inputs" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "EmbeddedICEwatchpointInputs,EmbeddedICE watchpoint inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "InstrumentationResources,Instrumentation resources" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12. "DataAddressComparisons,Data address comparisons" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ReadableRegisters,Readable registers" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 3.--10. 1. "ExtendedExternalInputBus,Extended external input bus"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "ExtendedExternalInputSelectors,Extended external input selectors" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "TESSEICR,TraceEnable Start/Stop EmbeddedICE Control Register"
|
|
bitfld.long 0x00 16.--19. "StopResourceSelection,Stop resource selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "StartResourceSelection,Start resource selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "TSEVR,Timestamp Event Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "TimestampEvent,Timestamp event"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TRACEIDR,CoreSight Trace ID Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TraceID,Trace ID to output onto the trace bus"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "IDR2,ETM ID Register 2"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "PDSR,Device Power-Down Status Register"
|
|
bitfld.long 0x00 0. "ETMpoweredup,The value of this bit indicates whether you can access the ETM Trace Registers" "0,1"
|
|
rgroup.long 0xEE0++0x03
|
|
line.long 0x00 "_ITMISCIN,Integration Test Miscelaneous Inputs Register"
|
|
bitfld.long 0x00 4. "COREHALT,A read of this bit returns the value of the COREHALT input pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "EXTIN,A read of these bits returns the value of the EXTIN[1:0] input pins" "0,1,2,3"
|
|
group.long 0xEE8++0x03
|
|
line.long 0x00 "_ITTRIGOUT,Integration Test Trigger Out Register"
|
|
bitfld.long 0x00 0. "TRIGGER,A write to this bit sets the TRIGGER output" "0,1"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "_ITATBCTR2,ETM Integration Test ATB Control 2 Register"
|
|
bitfld.long 0x00 0. "ATREADY,A read of this bit returns the value of the ETM ATREADY input" "0,1"
|
|
group.long 0xEF8++0x03
|
|
line.long 0x00 "_ITATBCTR0,ETM Integration Test ATB Control 0 Register"
|
|
bitfld.long 0x00 0. "ATVALID,A write to this bit sets the value of the ETM ATVALID output" "0,1"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0. "Mode,Enable integration mode" "0,1"
|
|
group.long 0xFA0++0x03
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x00 0.--3. "CLAIMSET,A bit programmable register bank which sets the Claim Tag Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xFA4++0x03
|
|
line.long 0x00 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x00 0.--3. "CLAIMCLR,A bit programmable register bank that is zero at reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "WriteAccessCode,Write Access Code"
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
bitfld.long 0x00 2. "s8BIT,Access Lock Register size" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "STATUS,Lock Status" "0: Access permitted,1: Write access to the component is blocked"
|
|
newline
|
|
bitfld.long 0x00 0. "IMP,Lock mechanism is implemented" "0,1"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x00 6.--7. "SNID,Permission for Secure non-invasive debug" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "SID,Reads as b00 Secure invasive debug not supported by the ETM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "NSNID,Permission for Non-secure non-invasive debug" "?,?,2: Non-secure non-invasive debug disabled,3: Non-secure non-invasive debug enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "NSID,Reads as b00 Non-secure invasive debug not supported by the ETM" "0,1,2,3"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVTYPE,CoreSight Device Type Register"
|
|
bitfld.long 0x00 4.--7. "SubType,Sub Type" "?,1: Processor trace,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "MajorType,Major Type and Class" "?,?,?,3: Trace source,?..."
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PIDR4,Peripheral Identification Register 4"
|
|
bitfld.long 0x00 4.--7. "c4KB,4KB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "JEP106,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "5" "6" "7" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Peripheral Identification Register $1"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber,Part Number [7:0]"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PIDR1,Peripheral Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "JEP106_identity_code,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PartNumber,Part Number [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PIDR2,Peripheral Identification Register 2"
|
|
bitfld.long 0x00 4.--7. "Revision,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PIDR3,Peripheral Identification Register 3"
|
|
bitfld.long 0x00 4.--7. "RevAnd,RevAnd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CustomerModified,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Component Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "ComponentClass,Component class" "?,1: ComponentClass_1,?,?,?,?,?,?,?,9: CoreSight component,?,?,?,?,?,15: PrimeCell of system component with no.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "Preamble,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "CIDR$1,Component Identification Register $1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "EWM"
|
|
base ad:0x40022000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CTRL,Control Register"
|
|
bitfld.byte 0x00 3. "INTEN,Interrupt Enable" "0,1"
|
|
bitfld.byte 0x00 2. "INEN,Input Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ASSIN,EWM_in's Assertion State Select" "0,1"
|
|
bitfld.byte 0x00 0. "EWMEN,EWM enable" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SERV,Service Register"
|
|
hexmask.byte 0x00 0.--7. 1. "SERVICE,SERVICE"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "CMPL,Compare Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "COMPAREL,COMPAREL"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "CMPH,Compare High Register"
|
|
hexmask.byte 0x00 0.--7. 1. "COMPAREH,COMPAREH"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register"
|
|
hexmask.byte 0x00 0.--7. 1. "CLK_DIV,CLK_DIV"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")
|
|
tree "FGPIO (General Purpose Input/Output)"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "FGPIOA"
|
|
base ad:0xF8000000
|
|
sif cpuis("K32L2B11*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
endif
|
|
tree.end
|
|
tree "FGPIOB"
|
|
base ad:0xF8000040
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
tree "FGPIOC"
|
|
base ad:0xF8000080
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
tree "FGPIOD"
|
|
base ad:0xF80000C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
tree "FGPIOE"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0xF8000100
|
|
elif cpuis("K32L3A*-CM0+")
|
|
base ad:0xF8000000
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "FGPIOA (General Purpose Input/Output)"
|
|
base ad:0xF8000000
|
|
sif cpuis("K32L2B11*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "FLEXBUS (FB)"
|
|
base ad:0x4000C000
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register"
|
|
bitfld.long 0x00 28.--31. "GROUP1,FlexBus Signal Group 1 Multiplex control" "0: GROUP1_0,1: GROUP1_1,2: GROUP1_2,?..."
|
|
bitfld.long 0x00 24.--27. "GROUP2,FlexBus Signal Group 2 Multiplex control" "0: GROUP2_0,1: GROUP2_1,2: FB_BE_31_24_B,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "GROUP3,FlexBus Signal Group 3 Multiplex control" "0: GROUP3_0,1: GROUP3_1,2: FB_BE_23_16_B,?..."
|
|
bitfld.long 0x00 16.--19. "GROUP4,FlexBus Signal Group 4 Multiplex control" "0: FB_TBST_B,1: GROUP4_1,2: FB_BE_15_8_B,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "GROUP5,FlexBus Signal Group 5 Multiplex control" "0: GROUP5_0,1: FB_CS3_B,2: FB_BE_7_0_B,?..."
|
|
endif
|
|
repeat 6. (increment 0 1)(increment 0 0xC)
|
|
tree "CS[$1]"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CSAR,Chip Select Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "BA,Base Address"
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "CSMR,Chip Select Mask Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "BAM,Base Address Mask"
|
|
bitfld.long 0x00 8. "WP,Write Protect" "0: Write accesses are allowed,1: Write accesses are not allowed"
|
|
newline
|
|
bitfld.long 0x00 0. "V,Valid" "0: Chip-select is invalid,1: Chip-select is valid"
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "CSCR,Chip Select Control Register"
|
|
bitfld.long 0x00 26.--31. "SWS,Secondary Wait States" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "SWSEN,Secondary Wait State Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "EXTS,EXTS" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 20.--21. "ASET,Address Setup" "0: Assert FB_CSn_B on the first rising clock..,1: Assert FB_CSn_B on the second rising clock..,2: Assert FB_CSn_B on the third rising clock..,3: Assert FB_CSn_B on the fourth rising clock.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "RDAH,Read Address Hold or Deselect" "0: When AA is 1b 1 cycle,1: When AA is 1b 2 cycles,2: When AA is 1b 3 cycles,3: When AA is 1b 4 cycles"
|
|
bitfld.long 0x00 16.--17. "WRAH,Write Address Hold or Deselect" "0: 1 cycle (default for all but FB_CS0_B),1: 2 cycles,2: 3 cycles,3: 4 cycles (default for FB_CS0_B)"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "WS,Wait States" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 9. "BLS,Byte-Lane Shift" "0: Not shifted,1: Shifted"
|
|
newline
|
|
bitfld.long 0x00 8. "AA,Auto-Acknowledge Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 6.--7. "PS,Port Size" "0: 32-bit port size,1: 8-bit port size,2: 16-bit port size,3: 16-bit port size"
|
|
newline
|
|
bitfld.long 0x00 5. "BEM,Byte-Enable Mode" "0: FB_BE_B is asserted for data write only,1: FB_BE_B is asserted for data read and write.."
|
|
bitfld.long 0x00 4. "BSTR,Burst-Read Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "BSTW,Burst-Write Enable" "0: Disabled,1: Enabled"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.)"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "FLEXIO"
|
|
base ad:0x4005F000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRIGGER,Trigger Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIN,Pin Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TIMER,Timer Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SHIFTER,Shifter Number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,FlexIO Control Register"
|
|
bitfld.long 0x00 31. "DOZEN,Doze Enable" "0: FlexIO enabled in Doze modes,1: FlexIO disabled in Doze modes"
|
|
bitfld.long 0x00 30. "DBGE,Debug Enable" "0: FlexIO is disabled in debug modes,1: FlexIO is enabled in debug modes"
|
|
newline
|
|
bitfld.long 0x00 2. "FASTACC,Fast Access" "0: Configures for normal register accesses to..,1: Configures for fast register accesses to FlexIO"
|
|
bitfld.long 0x00 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled all FlexIO.."
|
|
newline
|
|
bitfld.long 0x00 0. "FLEXEN,FlexIO Enable" "0: FlexIO module is disabled,1: FlexIO module is enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
bitfld.long 0x00 0.--3. "SSF,Shifter Status Flag" "0: Status flag is clear,1: Status flag is set,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SHIFTERR,Shifter Error Register"
|
|
bitfld.long 0x00 0.--3. "SEF,Shifter Error Flags" "0: Shifter Error Flag is clear,1: Shifter Error Flag is set,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMSTAT,Timer Status Register"
|
|
bitfld.long 0x00 0.--3. "TSF,Timer Status Flags" "0: Timer Status Flag is clear,1: Timer Status Flag is set,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
|
|
bitfld.long 0x00 0.--3. "SSIE,Shifter Status Interrupt Enable" "0: Shifter Status Flag interrupt disabled,1: Shifter Status Flag interrupt enabled,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SHIFTEIEN,Shifter Error Interrupt Enable"
|
|
bitfld.long 0x00 0.--3. "SEIE,Shifter Error Interrupt Enable" "0: Shifter Error Flag interrupt disabled,1: Shifter Error Flag interrupt enabled,?..."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TIMIEN,Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 0.--3. "TEIE,Timer Status Interrupt Enable" "0: Timer Status Flag interrupt is disabled,1: Timer Status Flag interrupt is enabled,?..."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
|
|
bitfld.long 0x00 0.--3. "SSDE,Shifter Status DMA Enable" "0: Shifter Status Flag DMA request is disabled,1: Shifter Status Flag DMA request is enabled,?..."
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL$1,Shifter Control N Register"
|
|
bitfld.long 0x00 24.--25. "TIMSEL,Timer Select" "0,1,2,3"
|
|
bitfld.long 0x00 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of Shift clock,1: Shift on negedge of Shift clock"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open drain or bidirectional..,2: Shifter pin bidirectional output data,3: Shifter pin output"
|
|
bitfld.long 0x00 8.--10. "PINSEL,Shifter Pin Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
bitfld.long 0x00 0.--2. "SMOD,Shifter Mode" "0: Disabled,1: Receive mode,2: Transmit mode,?,4: Match Store mode,5: Match Continuous mode,?..."
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG$1,Shifter Configuration N Register"
|
|
bitfld.long 0x00 8. "INSRC,Input Source" "0: Pin,1: Shifter N+1 Output"
|
|
bitfld.long 0x00 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for..,1: Reserved for transmitter/receiver/match store,2: Transmitter outputs stop bit value 0 on store..,3: Transmitter outputs stop bit value 1 on store.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SSTART,Shifter Start bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.."
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF$1,Shifter Buffer N Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUF,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS$1,Shifter Buffer N Bit Swapped Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBIS,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS$1,Shifter Buffer N Byte Swapped Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBYS,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS$1,Shifter Buffer N Bit Byte Swapped Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "TIMCTL$1,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud/bit mode,2: Dual 8-bit counters PWM mode,3: Single 16-bit counter mode"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "TIMCFG$1,Timer Configuration N Register"
|
|
bitfld.long 0x00 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and.."
|
|
bitfld.long 0x00 20.--21. "TIMDEC,Timer Decrement" "0: Decrement counter on FlexIO clock Shift clock..,1: Decrement counter on Trigger input (both..,2: Decrement counter on Pin input (both edges)..,3: Decrement counter on Trigger input (both.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,?,2: Timer reset on Timer Pin equal to Timer Output,3: Timer reset on Timer Trigger equal to Timer..,4: Timer reset on Timer Pin rising edge,?,6: Timer reset on Trigger rising edge,7: Timer reset on Trigger rising or falling edge"
|
|
bitfld.long 0x00 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on Timer compare,3: Timer disabled on Timer compare and Trigger Low,4: Timer disabled on Pin rising or falling edge,5: Timer disabled on Pin rising or falling edge..,6: Timer disabled on Trigger falling edge,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger..,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge"
|
|
bitfld.long 0x00 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and.."
|
|
newline
|
|
bitfld.long 0x00 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x500)++0x03
|
|
line.long 0x00 "TIMCMP$1,Timer Compare N Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Timer Compare Value"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "FLEXIO0"
|
|
base ad:0x40039000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRIGGER,Trigger Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIN,Pin Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TIMER,Timer Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SHIFTER,Shifter Number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,FlexIO Control Register"
|
|
bitfld.long 0x00 31. "DOZEN,Doze Enable" "0: FlexIO enabled in Doze modes,1: FlexIO disabled in Doze modes"
|
|
bitfld.long 0x00 30. "DBGE,Debug Enable" "0: FlexIO is disabled in debug modes,1: FlexIO is enabled in debug modes"
|
|
newline
|
|
bitfld.long 0x00 2. "FASTACC,Fast Access" "0: Configures for normal register accesses to..,1: Configures for fast register accesses to FlexIO"
|
|
bitfld.long 0x00 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled all FlexIO.."
|
|
newline
|
|
bitfld.long 0x00 0. "FLEXEN,FlexIO Enable" "0: FlexIO module is disabled,1: FlexIO module is enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PIN,Pin State Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Pin Data Input"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSF,Shifter Status Flag"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SHIFTERR,Shifter Error Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEF,Shifter Error Flags"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMSTAT,Timer Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TSF,Timer Status Flags"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSIE,Shifter Status Interrupt Enable"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SHIFTEIEN,Shifter Error Interrupt Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEIE,Shifter Error Interrupt Enable"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TIMIEN,Timer Interrupt Enable Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEIE,Timer Status Interrupt Enable"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSDE,Shifter Status DMA Enable"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHIFTSTATE,Shifter State Register"
|
|
bitfld.long 0x00 0.--2. "STATE,Current State Pointer" "0,1,2,3,4,5,6,7"
|
|
repeat 8. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL[$1],Shifter Control N Register $1"
|
|
bitfld.long 0x00 24.--26. "TIMSEL,Timer Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of Shift clock,1: Shift on negedge of Shift clock"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open drain or bidirectional..,2: Shifter pin bidirectional output data,3: Shifter pin output"
|
|
bitfld.long 0x00 8.--12. "PINSEL,Shifter Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
bitfld.long 0x00 0.--2. "SMOD,Shifter Mode" "0: Disabled,1: Receive mode,2: Transmit mode,?,4: Match Store mode,5: Match Continuous mode,6: State mode,7: Logic mode"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG[$1],Shifter Configuration N Register $1"
|
|
bitfld.long 0x00 16.--20. "PWIDTH,Parallel Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8. "INSRC,Input Source" "0: INSRC_0,1: Shifter N+1 Output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for..,?,2: Transmitter outputs stop bit value 0 on store..,3: Transmitter outputs stop bit value 1 on store.."
|
|
bitfld.long 0x00 0.--1. "SSTART,Shifter Start bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.."
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF[$1],Shifter Buffer N Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUF,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS[$1],Shifter Buffer N Bit Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBIS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS[$1],Shifter Buffer N Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBYS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS[$1],Shifter Buffer N Bit Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "TIMCTL[$1],Timer Control N Register $1"
|
|
bitfld.long 0x00 24.--29. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "TIMCFG[$1],Timer Configuration N Register $1"
|
|
bitfld.long 0x00 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and.."
|
|
bitfld.long 0x00 20.--21. "TIMDEC,Timer Decrement" "0: Decrement counter on FlexIO clock Shift clock..,1: Decrement counter on Trigger input (both..,2: Decrement counter on Pin input (both edges)..,3: Decrement counter on Trigger input (both.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,?,2: Timer reset on Timer Pin equal to Timer Output,3: Timer reset on Timer Trigger equal to Timer..,4: Timer reset on Timer Pin rising edge,?,6: Timer reset on Trigger rising edge,7: Timer reset on Trigger rising or falling edge"
|
|
bitfld.long 0x00 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on Timer compare (upper 8-bits..,3: Timer disabled on Timer compare (upper 8-bits..,4: Timer disabled on Pin rising or falling edge,5: Timer disabled on Pin rising or falling edge..,6: Timer disabled on Trigger falling edge,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger..,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge"
|
|
bitfld.long 0x00 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and.."
|
|
newline
|
|
bitfld.long 0x00 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x500)++0x03
|
|
line.long 0x00 "TIMCMP[$1],Timer Compare N Register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Timer Compare Value"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS[$1],Shifter Buffer N Nibble Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS[$1],Shifter Buffer N Half Word Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFHWS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS[$1],Shifter Buffer N Nibble Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNIS,Shift Buffer"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "FLEXIO0"
|
|
base ad:0x400CA000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRIGGER,Trigger Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIN,Pin Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TIMER,Timer Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SHIFTER,Shifter Number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,FlexIO Control Register"
|
|
bitfld.long 0x00 31. "DOZEN,Doze Enable" "0: FlexIO enabled in Doze modes,1: FlexIO disabled in Doze modes"
|
|
bitfld.long 0x00 30. "DBGE,Debug Enable" "0: FlexIO is disabled in debug modes,1: FlexIO is enabled in debug modes"
|
|
newline
|
|
bitfld.long 0x00 2. "FASTACC,Fast Access" "0: Configures for normal register accesses to..,1: Configures for fast register accesses to FlexIO"
|
|
bitfld.long 0x00 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled all FlexIO.."
|
|
newline
|
|
bitfld.long 0x00 0. "FLEXEN,FlexIO Enable" "0: FlexIO module is disabled,1: FlexIO module is enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PIN,Pin State Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Pin Data Input"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSF,Shifter Status Flag"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SHIFTERR,Shifter Error Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEF,Shifter Error Flags"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMSTAT,Timer Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TSF,Timer Status Flags"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSIE,Shifter Status Interrupt Enable"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SHIFTEIEN,Shifter Error Interrupt Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEIE,Shifter Error Interrupt Enable"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TIMIEN,Timer Interrupt Enable Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEIE,Timer Status Interrupt Enable"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SSDE,Shifter Status DMA Enable"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHIFTSTATE,Shifter State Register"
|
|
bitfld.long 0x00 0.--2. "STATE,Current State Pointer" "0,1,2,3,4,5,6,7"
|
|
repeat 8. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL[$1],Shifter Control N Register $1"
|
|
bitfld.long 0x00 24.--26. "TIMSEL,Timer Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of Shift clock,1: Shift on negedge of Shift clock"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open drain or bidirectional..,2: Shifter pin bidirectional output data,3: Shifter pin output"
|
|
bitfld.long 0x00 8.--12. "PINSEL,Shifter Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
bitfld.long 0x00 0.--2. "SMOD,Shifter Mode" "0: Disabled,1: Receive mode,2: Transmit mode,?,4: Match Store mode,5: Match Continuous mode,6: State mode,7: Logic mode"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG[$1],Shifter Configuration N Register $1"
|
|
bitfld.long 0x00 16.--20. "PWIDTH,Parallel Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8. "INSRC,Input Source" "0: INSRC_0,1: Shifter N+1 Output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for..,?,2: Transmitter outputs stop bit value 0 on store..,3: Transmitter outputs stop bit value 1 on store.."
|
|
bitfld.long 0x00 0.--1. "SSTART,Shifter Start bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.."
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF[$1],Shifter Buffer N Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUF,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS[$1],Shifter Buffer N Bit Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBIS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS[$1],Shifter Buffer N Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBYS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS[$1],Shifter Buffer N Bit Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "TIMCTL[$1],Timer Control N Register $1"
|
|
bitfld.long 0x00 24.--29. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "TIMCFG[$1],Timer Configuration N Register $1"
|
|
bitfld.long 0x00 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and.."
|
|
bitfld.long 0x00 20.--21. "TIMDEC,Timer Decrement" "0: Decrement counter on FlexIO clock Shift clock..,1: Decrement counter on Trigger input (both..,2: Decrement counter on Pin input (both edges)..,3: Decrement counter on Trigger input (both.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,?,2: Timer reset on Timer Pin equal to Timer Output,3: Timer reset on Timer Trigger equal to Timer..,4: Timer reset on Timer Pin rising edge,?,6: Timer reset on Trigger rising edge,7: Timer reset on Trigger rising or falling edge"
|
|
bitfld.long 0x00 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on Timer compare (upper 8-bits..,3: Timer disabled on Timer compare (upper 8-bits..,4: Timer disabled on Pin rising or falling edge,5: Timer disabled on Pin rising or falling edge..,6: Timer disabled on Trigger falling edge,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger..,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge"
|
|
bitfld.long 0x00 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and.."
|
|
newline
|
|
bitfld.long 0x00 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x500)++0x03
|
|
line.long 0x00 "TIMCMP[$1],Timer Compare N Register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Timer Compare Value"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x680)++0x03
|
|
line.long 0x00 "SHIFTBUFNBS[$1],Shifter Buffer N Nibble Byte Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNBS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x700)++0x03
|
|
line.long 0x00 "SHIFTBUFHWS[$1],Shifter Buffer N Half Word Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFHWS,Shift Buffer"
|
|
repeat.end
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x780)++0x03
|
|
line.long 0x00 "SHIFTBUFNIS[$1],Shifter Buffer N Nibble Swapped Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFNIS,Shift Buffer"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "FPB (Flash Patch and Breakpoint Unit Registers)"
|
|
base ad:0xE0002000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,FlashPatch Control Register"
|
|
rbitfld.long 0x00 12.--14. "NUM_CODE_most,NUM_CODE[6:4]" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--11. "NUM_LIT,NUM_LIT bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "NUM_CODE_least,NUM_CODE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "KEY,KEY bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Enable bit for the FPB" "0: FPB disabled,1: FPB enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "REMAP,FlashPatch Remap Register"
|
|
rbitfld.long 0x00 29. "RMPSPT,RMPSPT bit" "0: Remapping not supported,1: Hard-wired remap to SRAM region"
|
|
hexmask.long.tbyte 0x00 5.--28. 1. "REMAP,REMAP bits"
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "COMP$1,FlashPatch Comparator Register $1"
|
|
bitfld.long 0x00 30.--31. "REPLACE,REPLACE[1:0]" "0: Remap to remap address,1: Breakpoint on lower halfword upper is..,2: Breakpoint on upper halfword lower is..,3: Breakpoint on both lower and upper halfwords"
|
|
hexmask.long 0x00 2.--28. 1. "COMP,COMP bits"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Enable bit for this comparator" "0: Comparator disabled,1: Comparator enabled"
|
|
repeat.end
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
bitfld.long 0x00 4.--7. "c4KB,4KB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "JEP106,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "5" "6" "7" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PID$1,Peripheral Identification Register 5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PID0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber,Part Number [7:0]"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PID1,Peripheral Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "JEP106_identity_code,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PartNumber,Part Number [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PID2,Peripheral Identification Register 2"
|
|
bitfld.long 0x00 4.--7. "Revision,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PID3,Peripheral Identification Register 3"
|
|
bitfld.long 0x00 4.--7. "RevAnd,RevAnd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CustomerModified,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "CID0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CID1,Component Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "ComponentClass,Component class" "?,1: ComponentClass_1,?,?,?,?,?,?,?,9: CoreSight component,?,?,?,?,?,15: PrimeCell of system component with no.."
|
|
bitfld.long 0x00 0.--3. "Preamble,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "CID$1,Component Identification Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "FTFA (Flash Memory Interface)"
|
|
base ad:0x40020000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
bitfld.byte 0x00 7. "CCIF,Command Complete Interrupt Flag" "0: Flash command in progress,1: Flash command has completed"
|
|
bitfld.byte 0x00 6. "RDCOLERR,Flash Read Collision Error Flag" "0: No collision error detected,1: Collision error detected"
|
|
newline
|
|
bitfld.byte 0x00 5. "ACCERR,Flash Access Error Flag" "0: No access error detected,1: Access error detected"
|
|
bitfld.byte 0x00 4. "FPVIOL,Flash Protection Violation Flag" "0: No protection violation detected,1: Protection violation detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "MGSTAT0,Memory Controller Command Completion Status Flag" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. "CCIE,Command Complete Interrupt Enable" "0: Command complete interrupt disabled,1: Command complete interrupt enabled"
|
|
bitfld.byte 0x00 6. "RDCOLLIE,Read Collision Error Interrupt Enable" "0: Read collision error interrupt disabled,1: Read collision error interrupt enabled"
|
|
newline
|
|
rbitfld.byte 0x00 5. "ERSAREQ,Erase All Request" "0: No request or request complete,1: Request to"
|
|
bitfld.byte 0x00 4. "ERSSUSP,Erase Suspend" "0: No suspend requested,1: Suspend the current Erase Flash Sector.."
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. "KEYEN,Backdoor Key Security Enable" "0: Backdoor key access disabled,1: Backdoor key access disabled (preferred KEYEN..,2: Backdoor key access enabled,3: Backdoor key access disabled"
|
|
bitfld.byte 0x00 4.--5. "MEEN,Mass Erase Enable" "0: Mass erase is enabled,1: Mass erase is enabled,2: Mass erase is disabled,3: Mass erase is enabled"
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "FSLACC,Factory Security Level Access Code" "0: NXP factory access granted,1: NXP factory access denied,2: NXP factory access denied,3: NXP factory access granted"
|
|
bitfld.byte 0x00 0.--1. "SEC,Flash Security" "0: MCU security status is secure,1: MCU security status is secure,2: MCU security status is unsecure,3: MCU security status is secure"
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
hexmask.byte 0x00 0.--7. 1. "OPT,Nonvolatile Option"
|
|
repeat 8. (strings "3" "2" "1" "0" "7" "6" "5" "4" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
|
|
group.byte ($2+0x04)++0x00
|
|
line.byte 0x00 "FCCOB$1,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,The FCCOB register provides a command code and relevant parameters to the memory controller"
|
|
repeat.end
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "FCCOBB,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,The FCCOB register provides a command code and relevant parameters to the memory controller"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "FCCOBA,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,The FCCOB register provides a command code and relevant parameters to the memory controller"
|
|
repeat 2. (strings "9" "8" )(list 0x0 0x1 )
|
|
group.byte ($2+0x0E)++0x00
|
|
line.byte 0x00 "FCCOB$1,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,The FCCOB register provides a command code and relevant parameters to the memory controller"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
group.byte ($2+0x10)++0x00
|
|
line.byte 0x00 "FPROT$1,Program Flash Protection Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,Program Flash Region Protect"
|
|
repeat.end
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x18)++0x00
|
|
line.byte 0x00 "XACCH$1,Execute-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "XA,Execute-only access control"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x1C)++0x00
|
|
line.byte 0x00 "XACCL$1,Execute-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "XA,Execute-only access control"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x20)++0x00
|
|
line.byte 0x00 "SACCH$1,Supervisor-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "SA,Supervisor-only access control"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x24)++0x00
|
|
line.byte 0x00 "SACCL$1,Supervisor-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "SA,Supervisor-only access control"
|
|
repeat.end
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "FACSS,Flash Access Segment Size Register"
|
|
hexmask.byte 0x00 0.--7. 1. "SGSIZE,Segment Size"
|
|
rgroup.byte 0x2B++0x00
|
|
line.byte 0x00 "FACSN,Flash Access Segment Number Register"
|
|
hexmask.byte 0x00 0.--7. 1. "NUMSG,Number of Segments Indicator"
|
|
endif
|
|
tree.end
|
|
tree "FTFA_FLASHCONFIG (Flash configuration field)"
|
|
base ad:0x400
|
|
repeat 8. (strings "3" "2" "1" "0" "7" "6" "5" "4" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
|
|
rgroup.byte ($2+0x00)++0x00
|
|
line.byte 0x00 "BACKKEY$1,Backdoor Comparison Key 3"
|
|
hexmask.byte 0x00 0.--7. 1. "KEY,Backdoor Comparison Key"
|
|
repeat.end
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT3,Non-volatile P-Flash Protection"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,P-Flash Region Protect"
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "FPROT2,Non-volatile P-Flash Protection"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,P-Flash Region Protect"
|
|
rgroup.byte 0x0A++0x00
|
|
line.byte 0x00 "FPROT1,Non-volatile P-Flash Protection"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,P-Flash Region Protect"
|
|
rgroup.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT0,Non-volatile P-Flash Protection"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,P-Flash Region Protect"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "FSEC,Non-volatile Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. "KEYEN,Backdoor Key Security Enable" "?,?,2: Backdoor key access enabled,3: Backdoor key access disabled"
|
|
bitfld.byte 0x00 4.--5. "MEEN,no description available" "?,?,2: Mass erase is disabled,3: Mass erase is enabled"
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "FSLACC,Freescale Failure Analysis Access Code" "?,?,2: Freescale factory access denied,3: Freescale factory access granted"
|
|
bitfld.byte 0x00 0.--1. "SEC,Flash Security" "?,?,2: MCU security status is unsecure,3: MCU security status is secure"
|
|
rgroup.byte 0x0D++0x00
|
|
line.byte 0x00 "FOPT,Non-volatile Flash Option Register"
|
|
bitfld.byte 0x00 6.--7. "BOOTSRC_SEL,Boot source selection" "0: Boot from Flash,?,2: Boot from ROM,3: Boot from ROM"
|
|
bitfld.byte 0x00 5. "FAST_INIT,no description available" "0: Slower initialization,1: Fast Initialization"
|
|
newline
|
|
bitfld.byte 0x00 4. "LPBOOT1,no description available" "0: Core and system clock divider (OUTDIV1) is..,1: Core and system clock divider (OUTDIV1) is.."
|
|
bitfld.byte 0x00 3. "RESET_PIN_CFG,no description available" "0: RESET pin is disabled following a POR and..,1: RESET_b pin is dedicated"
|
|
newline
|
|
bitfld.byte 0x00 2. "NMI_DIS,no description available" "0: NMI interrupts are always blocked,1: NMI_b pin/interrupts reset default to enabled"
|
|
bitfld.byte 0x00 1. "BOOTPIN_OPT,no description available" "0: Force Boot from ROM if BOOTCFG0 asserted..,1: Boot source configured by FOPT (BOOTSRC_SEL).."
|
|
newline
|
|
bitfld.byte 0x00 0. "LPBOOT0,no description available" "0: Core and system clock divider (OUTDIV1) is..,1: Core and system clock divider (OUTDIV1) is.."
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "FTFE (Flash)"
|
|
base ad:0x40023000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. "CCIF,Command Complete Interrupt Flag" "0: Flash command in progress,1: Flash command has completed"
|
|
eventfld.byte 0x00 6. "RDCOLERR,Flash Read Collision Error Flag" "0: No collision error detected,1: Collision error detected"
|
|
newline
|
|
eventfld.byte 0x00 5. "ACCERR,Flash Access Error Flag" "0: No access error detected,1: Access error detected"
|
|
eventfld.byte 0x00 4. "FPVIOL,Flash Protection Violation Flag" "0: No protection violation detected,1: Protection violation detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "MGSTAT0,Memory Controller Command Completion Status Flag" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. "CCIE,Command Complete Interrupt Enable" "0: Command complete interrupt disabled,1: Command complete interrupt enabled"
|
|
bitfld.byte 0x00 6. "RDCOLLIE,Read Collision Error Interrupt Enable" "0: Read collision error interrupt disabled,1: Read collision error interrupt enabled"
|
|
newline
|
|
rbitfld.byte 0x00 5. "ERSAREQ,Erase All Request" "0: No request or request complete,1: Request to"
|
|
bitfld.byte 0x00 4. "ERSSUSP,Erase Suspend" "0: No suspend requested,1: Suspend the current Erase Flash Sector.."
|
|
newline
|
|
rbitfld.byte 0x00 3. "SWAP,Swap" "0: Program flash 0 block is located at relative..,1: Program flash 1 block is located at relative.."
|
|
rbitfld.byte 0x00 2. "CRCRDY,CRC Ready" "0: Programming acceleration RAM is not available..,1: Programming acceleration RAM is available for.."
|
|
newline
|
|
rbitfld.byte 0x00 1. "RAMRDY,RAM Ready" "0: Programming acceleration RAM is not available,1: Programming acceleration RAM is available"
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. "KEYEN,Backdoor Key Security Enable" "0: Backdoor key access disabled,1: Backdoor key access disabled (preferred KEYEN..,2: Backdoor key access enabled,3: Backdoor key access disabled"
|
|
bitfld.byte 0x00 4.--5. "MEEN,Mass Erase Enable Bits" "0: Mass erase is enabled,1: Mass erase is enabled,2: Mass erase is disabled,3: Mass erase is enabled"
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "FSLACC,Factory Security Level Access Code" "0: Factory access granted,1: Factory access denied,2: Factory access denied,3: Factory access granted"
|
|
bitfld.byte 0x00 0.--1. "SEC,Flash Security" "0: MCU security status is secure,1: MCU security status is secure,2: MCU security status is unsecure (The standard..,3: MCU security status is secure"
|
|
repeat 8. (strings "3" "2" "1" "0" "7" "6" "5" "4" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
|
|
group.byte ($2+0x04)++0x00
|
|
line.byte 0x00 "FCCOB$1,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
repeat.end
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "FCCOBB,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "FCCOBA,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
repeat 2. (strings "9" "8" )(list 0x0 0x1 )
|
|
group.byte ($2+0x0E)++0x00
|
|
line.byte 0x00 "FCCOB$1,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x10)++0x00
|
|
line.byte 0x00 "FOPT$1,Flash Option Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "OPT,Nonvolatile Option"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
group.byte ($2+0x18)++0x00
|
|
line.byte 0x00 "FPROTH$1,Primary Program Flash Protection Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,Primary Program Flash Region Protect"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
group.byte ($2+0x1C)++0x00
|
|
line.byte 0x00 "FPROTL$1,Primary Program Flash Protection Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,Primary Program Flash Region Protect"
|
|
repeat.end
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "FPROTSL,Secondary Program Flash Protection Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "PROTS,Secondary Program Flash Region Protect"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "FPROTSH,Secondary Program Flash Protection Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "PROTS,Secondary Program Flash Region Protect"
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "FACSS,Primary Flash Access Segment Size Register"
|
|
hexmask.byte 0x00 0.--7. 1. "SGSIZE,Segment Size"
|
|
rgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "FACSN,Primary Flash Access Segment Number Register"
|
|
hexmask.byte 0x00 0.--7. 1. "NUMSG,Number of Segments Indicator"
|
|
rgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "FACSSS,Secondary Flash Access Segment Size Register"
|
|
hexmask.byte 0x00 0.--7. 1. "SGSIZE_S,Segment Size"
|
|
rgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "FACSNS,Secondary Flash Access Segment Number Register"
|
|
hexmask.byte 0x00 0.--7. 1. "NUMSG_S,Number of Segments Indicator"
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x30)++0x00
|
|
line.byte 0x00 "XACCH$1,Primary Execute-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "XA,Execute-only access control"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x34)++0x00
|
|
line.byte 0x00 "XACCL$1,Primary Execute-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "XA,Execute-only access control"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x38)++0x00
|
|
line.byte 0x00 "SACCH$1,Primary Supervisor-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "SA,Primary Supervisor-only access control"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
rgroup.byte ($2+0x3C)++0x00
|
|
line.byte 0x00 "SACCL$1,Primary Supervisor-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "SA,Primary Supervisor-only access control"
|
|
repeat.end
|
|
rgroup.byte 0x44++0x00
|
|
line.byte 0x00 "XACCSL,Secondary Execute-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "XA_S,Execute-only access control"
|
|
rgroup.byte 0x45++0x00
|
|
line.byte 0x00 "XACCSH,Secondary Execute-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "XA_S,Execute-only access control"
|
|
rgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "SACCSL,Secondary Supervisor-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "SA_S,Secondary Supervisor-only access control"
|
|
rgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "SACCSH,Secondary Supervisor-only Access Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "SA_S,Secondary Supervisor-only access control"
|
|
rgroup.byte 0x52++0x00
|
|
line.byte 0x00 "FSTDBYCTL,Flash Standby Control Register"
|
|
bitfld.byte 0x00 0. "STDBYDIS,Standy Mode Disable" "0: Standby mode enabled for flash blocks..,1: Standby mode disabled (STDBYx ignored)"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "FSTDBY,Flash Standby Register"
|
|
bitfld.byte 0x00 2. "STDBY2,Standy Mode for Flash Block 2" "0: Standby mode not enabled for flash block 2,1: If STDBYDIS is clear standby mode is enabled.."
|
|
bitfld.byte 0x00 1. "STDBY1,Standy Mode for Flash Block 1" "0: Standby mode not enabled for flash block 1,1: If STDBYDIS is clear standby mode is enabled.."
|
|
newline
|
|
bitfld.byte 0x00 0. "STDBY0,Standy Mode for Flash Block 0" "0: Standby mode not enabled for flash block 0,1: If STDBYDIS is clear standby mode is enabled.."
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "GPIOA"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4000F000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x400FF000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
bitfld.long 0x00 31. "PDO31,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 30. "PDO30,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDO29,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 28. "PDO28,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDO27,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 26. "PDO26,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 25. "PDO25,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 24. "PDO24,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 23. "PDO23,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 22. "PDO22,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 21. "PDO21,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 20. "PDO20,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 19. "PDO19,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 18. "PDO18,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 17. "PDO17,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 16. "PDO16,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 15. "PDO15,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 14. "PDO14,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 13. "PDO13,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 12. "PDO12,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 11. "PDO11,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 10. "PDO10,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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newline
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bitfld.long 0x00 9. "PDO9,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 8. "PDO8,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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newline
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bitfld.long 0x00 7. "PDO7,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 6. "PDO6,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 5. "PDO5,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 4. "PDO4,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 3. "PDO3,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 2. "PDO2,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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newline
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bitfld.long 0x00 1. "PDO1,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 0. "PDO0,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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group.long 0x04++0x03
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line.long 0x00 "PSOR,Port Set Output Register"
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bitfld.long 0x00 31. "PTSO31,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 30. "PTSO30,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 29. "PTSO29,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 28. "PTSO28,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 27. "PTSO27,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 26. "PTSO26,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 25. "PTSO25,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 24. "PTSO24,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 23. "PTSO23,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 22. "PTSO22,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 21. "PTSO21,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 20. "PTSO20,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 19. "PTSO19,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 18. "PTSO18,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 17. "PTSO17,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 16. "PTSO16,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 15. "PTSO15,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 14. "PTSO14,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 13. "PTSO13,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 12. "PTSO12,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 11. "PTSO11,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 10. "PTSO10,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 9. "PTSO9,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 8. "PTSO8,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 7. "PTSO7,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 6. "PTSO6,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 5. "PTSO5,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 4. "PTSO4,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 3. "PTSO3,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 2. "PTSO2,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 1. "PTSO1,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 0. "PTSO0,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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group.long 0x08++0x03
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line.long 0x00 "PCOR,Port Clear Output Register"
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bitfld.long 0x00 31. "PTCO31,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 30. "PTCO30,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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newline
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bitfld.long 0x00 29. "PTCO29,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 28. "PTCO28,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 27. "PTCO27,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 26. "PTCO26,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 25. "PTCO25,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 24. "PTCO24,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 23. "PTCO23,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 22. "PTCO22,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 21. "PTCO21,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 20. "PTCO20,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 19. "PTCO19,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 18. "PTCO18,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 17. "PTCO17,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 16. "PTCO16,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 15. "PTCO15,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 14. "PTCO14,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 13. "PTCO13,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 12. "PTCO12,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 11. "PTCO11,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 10. "PTCO10,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 9. "PTCO9,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 8. "PTCO8,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 7. "PTCO7,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 6. "PTCO6,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 5. "PTCO5,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 4. "PTCO4,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 3. "PTCO3,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 2. "PTCO2,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 1. "PTCO1,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 0. "PTCO0,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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group.long 0x0C++0x03
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line.long 0x00 "PTOR,Port Toggle Output Register"
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bitfld.long 0x00 31. "PTTO31,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 30. "PTTO30,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 29. "PTTO29,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 28. "PTTO28,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 27. "PTTO27,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 26. "PTTO26,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 25. "PTTO25,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 24. "PTTO24,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 23. "PTTO23,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 22. "PTTO22,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 21. "PTTO21,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 20. "PTTO20,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 19. "PTTO19,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 18. "PTTO18,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 17. "PTTO17,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 16. "PTTO16,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 15. "PTTO15,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 14. "PTTO14,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 13. "PTTO13,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 12. "PTTO12,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 11. "PTTO11,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 10. "PTTO10,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 9. "PTTO9,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 8. "PTTO8,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 7. "PTTO7,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 6. "PTTO6,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 5. "PTTO5,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 4. "PTTO4,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 3. "PTTO3,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 2. "PTTO2,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 1. "PTTO1,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 0. "PTTO0,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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rgroup.long 0x10++0x03
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line.long 0x00 "PDIR,Port Data Input Register"
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bitfld.long 0x00 31. "PDI31,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 30. "PDI30,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 29. "PDI29,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 28. "PDI28,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 27. "PDI27,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 26. "PDI26,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 25. "PDI25,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 24. "PDI24,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 23. "PDI23,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 22. "PDI22,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 21. "PDI21,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 20. "PDI20,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 19. "PDI19,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 18. "PDI18,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 17. "PDI17,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 16. "PDI16,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 15. "PDI15,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 14. "PDI14,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 13. "PDI13,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 12. "PDI12,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 11. "PDI11,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 10. "PDI10,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 9. "PDI9,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 8. "PDI8,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 7. "PDI7,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 6. "PDI6,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 5. "PDI5,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 4. "PDI4,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 3. "PDI3,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 2. "PDI2,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 1. "PDI1,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 0. "PDI0,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. "PDD31,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 30. "PDD30,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDD29,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 28. "PDD28,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDD27,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 26. "PDD26,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDD25,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 24. "PDD24,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDD23,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 22. "PDD22,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDD21,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 20. "PDD20,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDD19,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 18. "PDD18,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDD17,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 16. "PDD16,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDD15,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 14. "PDD14,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDD13,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 12. "PDD12,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDD11,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 10. "PDD10,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDD9,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 8. "PDD8,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDD7,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 6. "PDD6,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDD5,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 4. "PDD4,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDD3,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 2. "PDD2,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 1. "PDD1,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 0. "PDD0,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "GPIOA"
|
|
base ad:0x48020000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
bitfld.long 0x00 31. "PDO31,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 30. "PDO30,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDO29,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 28. "PDO28,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDO27,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 26. "PDO26,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDO25,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 24. "PDO24,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDO23,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 22. "PDO22,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDO21,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 20. "PDO20,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDO19,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 18. "PDO18,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDO17,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 16. "PDO16,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDO15,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 14. "PDO14,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDO13,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 12. "PDO12,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDO11,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 10. "PDO10,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDO9,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 8. "PDO8,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDO7,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 6. "PDO6,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDO5,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 4. "PDO4,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDO3,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 2. "PDO2,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 1. "PDO1,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 0. "PDO0,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
bitfld.long 0x00 31. "PTSO31,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 30. "PTSO30,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 29. "PTSO29,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 28. "PTSO28,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 27. "PTSO27,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 26. "PTSO26,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 25. "PTSO25,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 24. "PTSO24,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 23. "PTSO23,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 22. "PTSO22,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 21. "PTSO21,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 20. "PTSO20,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 19. "PTSO19,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 18. "PTSO18,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 17. "PTSO17,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 16. "PTSO16,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 15. "PTSO15,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 14. "PTSO14,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 13. "PTSO13,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 12. "PTSO12,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 11. "PTSO11,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 10. "PTSO10,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 9. "PTSO9,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 8. "PTSO8,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 7. "PTSO7,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 6. "PTSO6,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 5. "PTSO5,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 4. "PTSO4,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 3. "PTSO3,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 2. "PTSO2,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 1. "PTSO1,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 0. "PTSO0,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
bitfld.long 0x00 31. "PTCO31,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 30. "PTCO30,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 29. "PTCO29,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 28. "PTCO28,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PTCO27,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 26. "PTCO26,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PTCO25,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 24. "PTCO24,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 23. "PTCO23,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 22. "PTCO22,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 21. "PTCO21,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 20. "PTCO20,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 19. "PTCO19,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 18. "PTCO18,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 17. "PTCO17,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 16. "PTCO16,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 15. "PTCO15,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 14. "PTCO14,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 13. "PTCO13,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 12. "PTCO12,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 11. "PTCO11,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 10. "PTCO10,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 9. "PTCO9,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 8. "PTCO8,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 7. "PTCO7,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 6. "PTCO6,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 5. "PTCO5,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 4. "PTCO4,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 3. "PTCO3,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 2. "PTCO2,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 1. "PTCO1,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 0. "PTCO0,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. "PTTO31,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 30. "PTTO30,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 29. "PTTO29,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 28. "PTTO28,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 27. "PTTO27,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 26. "PTTO26,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 25. "PTTO25,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 24. "PTTO24,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 23. "PTTO23,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 22. "PTTO22,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 21. "PTTO21,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 20. "PTTO20,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 19. "PTTO19,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 18. "PTTO18,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 17. "PTTO17,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 16. "PTTO16,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 15. "PTTO15,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 14. "PTTO14,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 13. "PTTO13,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 12. "PTTO12,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 11. "PTTO11,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 10. "PTTO10,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 9. "PTTO9,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 8. "PTTO8,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 7. "PTTO7,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 6. "PTTO6,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 5. "PTTO5,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 4. "PTTO4,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 3. "PTTO3,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 2. "PTTO2,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PTTO1,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 0. "PTTO0,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. "PDI31,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 30. "PDI30,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 29. "PDI29,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 28. "PDI28,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 27. "PDI27,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 26. "PDI26,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 25. "PDI25,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 24. "PDI24,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 23. "PDI23,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 22. "PDI22,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 21. "PDI21,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 20. "PDI20,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 19. "PDI19,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 18. "PDI18,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 17. "PDI17,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 16. "PDI16,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 15. "PDI15,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 14. "PDI14,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 13. "PDI13,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 12. "PDI12,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 11. "PDI11,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 10. "PDI10,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 9. "PDI9,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 8. "PDI8,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 7. "PDI7,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 6. "PDI6,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 5. "PDI5,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 4. "PDI4,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 3. "PDI3,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 2. "PDI2,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 1. "PDI1,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 0. "PDI0,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. "PDD31,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 30. "PDD30,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDD29,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 28. "PDD28,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDD27,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 26. "PDD26,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDD25,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 24. "PDD24,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDD23,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 22. "PDD22,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDD21,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 20. "PDD20,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDD19,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 18. "PDD18,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDD17,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 16. "PDD16,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDD15,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 14. "PDD14,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDD13,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 12. "PDD12,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDD11,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 10. "PDD10,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDD9,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 8. "PDD8,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDD7,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 6. "PDD6,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDD5,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 4. "PDD4,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDD3,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 2. "PDD2,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 1. "PDD1,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 0. "PDD0,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "GPIOB"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4000F040
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x400FF040
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
bitfld.long 0x00 31. "PDO31,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 30. "PDO30,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDO29,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 28. "PDO28,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDO27,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 26. "PDO26,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDO25,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 24. "PDO24,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDO23,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 22. "PDO22,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDO21,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 20. "PDO20,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDO19,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 18. "PDO18,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDO17,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 16. "PDO16,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDO15,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 14. "PDO14,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDO13,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 12. "PDO12,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDO11,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 10. "PDO10,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDO9,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 8. "PDO8,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDO7,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 6. "PDO6,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDO5,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 4. "PDO4,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
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bitfld.long 0x00 3. "PDO3,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 2. "PDO2,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 1. "PDO1,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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bitfld.long 0x00 0. "PDO0,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
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group.long 0x04++0x03
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line.long 0x00 "PSOR,Port Set Output Register"
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bitfld.long 0x00 31. "PTSO31,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 30. "PTSO30,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 29. "PTSO29,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 28. "PTSO28,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 27. "PTSO27,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 26. "PTSO26,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 25. "PTSO25,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 24. "PTSO24,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 23. "PTSO23,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 22. "PTSO22,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 21. "PTSO21,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 20. "PTSO20,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 19. "PTSO19,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 18. "PTSO18,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 17. "PTSO17,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 16. "PTSO16,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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newline
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bitfld.long 0x00 15. "PTSO15,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 14. "PTSO14,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 13. "PTSO13,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 12. "PTSO12,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 11. "PTSO11,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 10. "PTSO10,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 9. "PTSO9,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 8. "PTSO8,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 7. "PTSO7,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 6. "PTSO6,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 5. "PTSO5,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 4. "PTSO4,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 3. "PTSO3,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 2. "PTSO2,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 1. "PTSO1,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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bitfld.long 0x00 0. "PTSO0,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
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group.long 0x08++0x03
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line.long 0x00 "PCOR,Port Clear Output Register"
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bitfld.long 0x00 31. "PTCO31,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 30. "PTCO30,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 29. "PTCO29,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 28. "PTCO28,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 27. "PTCO27,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 26. "PTCO26,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 25. "PTCO25,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 24. "PTCO24,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 23. "PTCO23,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 22. "PTCO22,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 21. "PTCO21,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 20. "PTCO20,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 19. "PTCO19,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 18. "PTCO18,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 17. "PTCO17,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 16. "PTCO16,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 15. "PTCO15,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 14. "PTCO14,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 13. "PTCO13,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 12. "PTCO12,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 11. "PTCO11,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 10. "PTCO10,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 9. "PTCO9,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 8. "PTCO8,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 7. "PTCO7,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 6. "PTCO6,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 5. "PTCO5,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 4. "PTCO4,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 3. "PTCO3,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 2. "PTCO2,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 1. "PTCO1,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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bitfld.long 0x00 0. "PTCO0,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
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group.long 0x0C++0x03
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line.long 0x00 "PTOR,Port Toggle Output Register"
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bitfld.long 0x00 31. "PTTO31,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 30. "PTTO30,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 29. "PTTO29,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 28. "PTTO28,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 27. "PTTO27,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 26. "PTTO26,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 25. "PTTO25,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 24. "PTTO24,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 23. "PTTO23,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 22. "PTTO22,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 21. "PTTO21,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 20. "PTTO20,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 19. "PTTO19,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 18. "PTTO18,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 17. "PTTO17,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 16. "PTTO16,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 15. "PTTO15,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 14. "PTTO14,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 13. "PTTO13,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 12. "PTTO12,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 11. "PTTO11,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 10. "PTTO10,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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newline
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bitfld.long 0x00 9. "PTTO9,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 8. "PTTO8,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 7. "PTTO7,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 6. "PTTO6,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 5. "PTTO5,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 4. "PTTO4,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 3. "PTTO3,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 2. "PTTO2,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 1. "PTTO1,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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bitfld.long 0x00 0. "PTTO0,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
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rgroup.long 0x10++0x03
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line.long 0x00 "PDIR,Port Data Input Register"
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bitfld.long 0x00 31. "PDI31,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 30. "PDI30,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 29. "PDI29,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 28. "PDI28,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 27. "PDI27,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 26. "PDI26,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 25. "PDI25,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 24. "PDI24,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 23. "PDI23,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 22. "PDI22,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 21. "PDI21,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 20. "PDI20,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 19. "PDI19,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 18. "PDI18,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 17. "PDI17,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 16. "PDI16,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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newline
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bitfld.long 0x00 15. "PDI15,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 14. "PDI14,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 13. "PDI13,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 12. "PDI12,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 11. "PDI11,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 10. "PDI10,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 9. "PDI9,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 8. "PDI8,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 7. "PDI7,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 6. "PDI6,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 5. "PDI5,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 4. "PDI4,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 3. "PDI3,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 2. "PDI2,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 1. "PDI1,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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bitfld.long 0x00 0. "PDI0,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
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group.long 0x14++0x03
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line.long 0x00 "PDDR,Port Data Direction Register"
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bitfld.long 0x00 31. "PDD31,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
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bitfld.long 0x00 30. "PDD30,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
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bitfld.long 0x00 29. "PDD29,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 28. "PDD28,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDD27,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 26. "PDD26,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDD25,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 24. "PDD24,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDD23,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 22. "PDD22,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDD21,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 20. "PDD20,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDD19,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 18. "PDD18,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDD17,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 16. "PDD16,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDD15,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 14. "PDD14,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDD13,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 12. "PDD12,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDD11,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 10. "PDD10,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDD9,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 8. "PDD8,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDD7,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 6. "PDD6,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDD5,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 4. "PDD4,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDD3,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 2. "PDD2,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 1. "PDD1,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 0. "PDD0,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "GPIOB"
|
|
base ad:0x48020040
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
bitfld.long 0x00 31. "PDO31,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 30. "PDO30,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDO29,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 28. "PDO28,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDO27,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 26. "PDO26,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDO25,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 24. "PDO24,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDO23,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 22. "PDO22,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDO21,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 20. "PDO20,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDO19,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 18. "PDO18,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDO17,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 16. "PDO16,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDO15,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 14. "PDO14,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDO13,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 12. "PDO12,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDO11,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 10. "PDO10,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDO9,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 8. "PDO8,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDO7,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 6. "PDO6,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDO5,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 4. "PDO4,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDO3,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 2. "PDO2,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
newline
|
|
bitfld.long 0x00 1. "PDO1,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
bitfld.long 0x00 0. "PDO0,Port Data Output" "0: Logic level 0 is driven on pin provided pin..,1: Logic level 1 is driven on pin provided pin.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
bitfld.long 0x00 31. "PTSO31,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 30. "PTSO30,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 29. "PTSO29,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 28. "PTSO28,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 27. "PTSO27,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 26. "PTSO26,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 25. "PTSO25,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 24. "PTSO24,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 23. "PTSO23,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 22. "PTSO22,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 21. "PTSO21,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 20. "PTSO20,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 19. "PTSO19,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 18. "PTSO18,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 17. "PTSO17,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 16. "PTSO16,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 15. "PTSO15,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 14. "PTSO14,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 13. "PTSO13,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 12. "PTSO12,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 11. "PTSO11,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 10. "PTSO10,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 9. "PTSO9,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 8. "PTSO8,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 7. "PTSO7,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 6. "PTSO6,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 5. "PTSO5,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 4. "PTSO4,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 3. "PTSO3,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 2. "PTSO2,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
newline
|
|
bitfld.long 0x00 1. "PTSO1,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
bitfld.long 0x00 0. "PTSO0,Port Set Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to logic 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
bitfld.long 0x00 31. "PTCO31,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 30. "PTCO30,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 29. "PTCO29,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 28. "PTCO28,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PTCO27,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 26. "PTCO26,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PTCO25,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 24. "PTCO24,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 23. "PTCO23,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 22. "PTCO22,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 21. "PTCO21,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 20. "PTCO20,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 19. "PTCO19,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 18. "PTCO18,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 17. "PTCO17,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 16. "PTCO16,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 15. "PTCO15,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 14. "PTCO14,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 13. "PTCO13,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 12. "PTCO12,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 11. "PTCO11,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 10. "PTCO10,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 9. "PTCO9,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 8. "PTCO8,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 7. "PTCO7,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 6. "PTCO6,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 5. "PTCO5,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 4. "PTCO4,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 3. "PTCO3,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 2. "PTCO2,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
newline
|
|
bitfld.long 0x00 1. "PTCO1,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
bitfld.long 0x00 0. "PTCO0,Port Clear Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is cleared to.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
bitfld.long 0x00 31. "PTTO31,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 30. "PTTO30,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 29. "PTTO29,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 28. "PTTO28,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 27. "PTTO27,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 26. "PTTO26,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 25. "PTTO25,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 24. "PTTO24,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 23. "PTTO23,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 22. "PTTO22,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 21. "PTTO21,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 20. "PTTO20,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 19. "PTTO19,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 18. "PTTO18,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 17. "PTTO17,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 16. "PTTO16,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 15. "PTTO15,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 14. "PTTO14,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 13. "PTTO13,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 12. "PTTO12,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 11. "PTTO11,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 10. "PTTO10,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 9. "PTTO9,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 8. "PTTO8,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 7. "PTTO7,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 6. "PTTO6,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 5. "PTTO5,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 4. "PTTO4,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 3. "PTTO3,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 2. "PTTO2,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PTTO1,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
bitfld.long 0x00 0. "PTTO0,Port Toggle Output" "0: Corresponding bit in PDORn does not change,1: Corresponding bit in PDORn is set to the.."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
bitfld.long 0x00 31. "PDI31,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 30. "PDI30,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 29. "PDI29,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 28. "PDI28,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 27. "PDI27,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 26. "PDI26,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 25. "PDI25,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 24. "PDI24,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 23. "PDI23,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 22. "PDI22,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 21. "PDI21,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 20. "PDI20,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 19. "PDI19,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 18. "PDI18,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 17. "PDI17,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 16. "PDI16,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 15. "PDI15,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 14. "PDI14,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 13. "PDI13,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 12. "PDI12,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 11. "PDI11,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 10. "PDI10,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 9. "PDI9,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 8. "PDI8,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 7. "PDI7,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 6. "PDI6,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 5. "PDI5,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 4. "PDI4,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 3. "PDI3,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 2. "PDI2,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
newline
|
|
bitfld.long 0x00 1. "PDI1,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
bitfld.long 0x00 0. "PDI0,Port Data Input" "0: Pin logic level is logic 0 or is not..,1: Pin logic level is logic 1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
bitfld.long 0x00 31. "PDD31,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 30. "PDD30,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 29. "PDD29,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 28. "PDD28,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 27. "PDD27,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 26. "PDD26,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 25. "PDD25,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 24. "PDD24,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 23. "PDD23,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 22. "PDD22,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 21. "PDD21,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 20. "PDD20,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 19. "PDD19,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 18. "PDD18,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 17. "PDD17,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 16. "PDD16,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 15. "PDD15,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 14. "PDD14,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 13. "PDD13,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 12. "PDD12,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 11. "PDD11,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 10. "PDD10,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 9. "PDD9,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 8. "PDD8,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 7. "PDD7,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 6. "PDD6,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 5. "PDD5,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 4. "PDD4,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDD3,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 2. "PDD2,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
newline
|
|
bitfld.long 0x00 1. "PDD1,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
bitfld.long 0x00 0. "PDD0,Port Data Direction" "0: Pin is configured as general-purpose input..,1: Pin is configured as general-purpose output.."
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x48020080
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "GPIOC"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4000F080
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x400FF080
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "GPIOD"
|
|
base ad:0x480200C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "GPIOD"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4000F0C0
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x400FF0C0
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "GPIOE"
|
|
base ad:0x4100F000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "GPIOE"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4000F100
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x400FF100
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40066000 ad:0x40067000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "A1,I2C Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 1. "AD,Address"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "F,I2C Frequency Divider register"
|
|
bitfld.byte 0x00 6.--7. "MULT,Multiplier Factor" "0: mul = 1,1: mul = 2,2: mul = 4,?..."
|
|
bitfld.byte 0x00 0.--5. "ICR,ClockRate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. "IICEN,I2C Enable" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x00 6. "IICIE,I2C Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. "MST,Master Mode Select" "0: Slave mode,1: Master mode"
|
|
bitfld.byte 0x00 4. "TX,Transmit Mode Select" "0: Receive,1: Transmit"
|
|
newline
|
|
bitfld.byte 0x00 3. "TXAK,Transmit Acknowledge Enable" "0: An acknowledge signal is sent to the bus on..,1: No acknowledge signal is sent to the bus on.."
|
|
bitfld.byte 0x00 2. "RSTA,Repeat START" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "WUEN,Wakeup Enable" "0: Normal operation,1: Enables the wakeup function in low power mode"
|
|
bitfld.byte 0x00 0. "DMAEN,DMA Enable" "0: All DMA signalling disabled,1: DMA transfer is enabled"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "S,I2C Status register"
|
|
rbitfld.byte 0x00 7. "TCF,Transfer Complete Flag" "0: Transfer in progress,1: Transfer complete"
|
|
bitfld.byte 0x00 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave"
|
|
newline
|
|
rbitfld.byte 0x00 5. "BUSY,Bus Busy" "0: Bus is idle,1: Bus is busy"
|
|
bitfld.byte 0x00 4. "ARBL,Arbitration Lost" "0: Standard bus operation,1: Loss of arbitration"
|
|
newline
|
|
bitfld.byte 0x00 3. "RAM,Range Address Match" "0: Not addressed,1: Addressed as a slave"
|
|
rbitfld.byte 0x00 2. "SRW,Slave Read/" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave"
|
|
newline
|
|
bitfld.byte 0x00 1. "IICIF,Interrupt Flag" "0: No interrupt pending,1: Interrupt pending"
|
|
rbitfld.byte 0x00 0. "RXAK,Receive Acknowledge" "0: Acknowledge signal was received after the..,1: No acknowledge signal detected"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "D,I2C Data I/O register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATA,Data"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. "GCAEN,General Call Address Enable" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x00 6. "ADEXT,Address Extension" "0: 7-bit address scheme,1: 10-bit address scheme"
|
|
newline
|
|
bitfld.byte 0x00 5. "HDRS,High Drive Select" "0: Normal drive mode,1: High drive mode"
|
|
bitfld.byte 0x00 4. "SBRC,Slave Baud Rate Control" "0: The slave baud rate follows the master baud..,1: Slave baud rate is independent of the master.."
|
|
newline
|
|
bitfld.byte 0x00 3. "RMEN,Range Address Matching Enable" "0: Range mode disabled,1: Range mode enabled"
|
|
bitfld.byte 0x00 0.--2. "AD,Slave Address" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "FLT,I2C Programmable Input Glitch Filter Register"
|
|
bitfld.byte 0x00 7. "SHEN,Stop Hold Enable" "0: Stop holdoff is disabled,1: Stop holdoff is enabled"
|
|
bitfld.byte 0x00 6. "STOPF,I2C Bus Stop Detect Flag" "0: No stop happens on I2C bus,1: Stop detected on I2C bus"
|
|
newline
|
|
bitfld.byte 0x00 5. "SSIE,I2C Bus Stop or Start Interrupt Enable" "0: Stop or start detection interrupt is disabled,1: Stop or start detection interrupt is enabled"
|
|
bitfld.byte 0x00 4. "STARTF,I2C Bus Start Detect Flag" "0: No start happens on I2C bus,1: Start detected on I2C bus"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "FLT,I2C Programmable Filter Factor" "0: No filter/bypass,?..."
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "RA,I2C Range Address register"
|
|
hexmask.byte 0x00 1.--7. 1. "RAD,Range Slave Address"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SMB,I2C SMBus Control and Status register"
|
|
bitfld.byte 0x00 7. "FACK,Fast NACK/ACK Enable" "0: An ACK or NACK is sent on the following..,1: Writing 0 to TXAK after receiving a data byte.."
|
|
bitfld.byte 0x00 6. "ALERTEN,SMBus Alert Response Address Enable" "0: SMBus alert response address matching is..,1: SMBus alert response address matching is.."
|
|
newline
|
|
bitfld.byte 0x00 5. "SIICAEN,Second I2C Address Enable" "0: I2C address register 2 matching is disabled,1: I2C address register 2 matching is enabled"
|
|
bitfld.byte 0x00 4. "TCKSEL,Timeout Counter Clock Select" "0: Timeout counter counts at the frequency of..,1: Timeout counter counts at the frequency of.."
|
|
newline
|
|
bitfld.byte 0x00 3. "SLTF,SCL Low Timeout Flag" "0: No low timeout occurs,1: Low timeout occurs"
|
|
rbitfld.byte 0x00 2. "SHTF1,SCL High Timeout Flag 1" "0: No SCL high and SDA high timeout occurs,1: SCL high and SDA high timeout occurs"
|
|
newline
|
|
bitfld.byte 0x00 1. "SHTF2,SCL High Timeout Flag 2" "0: No SCL high and SDA low timeout occurs,1: SCL high and SDA low timeout occurs"
|
|
bitfld.byte 0x00 0. "SHTF2IE,SHTF2 Interrupt Enable" "0: SHTF2 interrupt is disabled,1: SHTF2 interrupt is enabled"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "A2,I2C Address Register 2"
|
|
hexmask.byte 0x00 1.--7. 1. "SAD,SMBus Address"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SLTH,I2C SCL Low Timeout Register High"
|
|
hexmask.byte 0x00 0.--7. 1. "SSLT,SSLT[15:8]"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SLTL,I2C SCL Low Timeout Register Low"
|
|
hexmask.byte 0x00 0.--7. 1. "SSLT,SSLT[7:0]"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "S2,I2C Status register 2"
|
|
bitfld.byte 0x00 1. "ERROR,Error flag" "0: The buffer is not full and all write/read..,1: There are 3 or more write/read errors during.."
|
|
rbitfld.byte 0x00 0. "EMPTY,Empty flag" "0: Tx or Rx buffer is not empty and cannot be..,1: Tx or Rx buffer is empty and can be written.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "I2S (Inter-Integrated Sound Bus Controller)"
|
|
base ad:0x4003D000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 16.--19. "FRAME,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "FIFO,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DATALINE,Number of Datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. "TE,Transmitter Enable" "0: Transmitter is disabled,1: Transmitter is enabled or transmitter has.."
|
|
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Transmitter disabled in Stop mode,1: Transmitter enabled in Stop mode"
|
|
newline
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode"
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled,1: Transmit bit clock is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
newline
|
|
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
newline
|
|
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected,1: Transmit underrun detected"
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty,1: Enabled transmit FIFO is empty"
|
|
newline
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached,1: Transmit FIFO watermark has been reached"
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. "TFW,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver,2: Synchronous with another SAI transmitter,3: Synchronous with another SAI receiver"
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs..,1: Bit clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. "CFR,Channel FIFO Reset" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "TCE,Transmit Channel Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO reads (from..,2: FIFO combine mode enabled on FIFO writes (by..,3: FIFO combine mode enabled on FIFO reads (from.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
bitfld.long 0x00 16.--20. "FRSZ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. "CHMOD,Channel Mode" "0: TDM mode transmit data pins are tri-stated..,1: Output mode transmit data pins are never.."
|
|
newline
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is transmitted first,1: MSB is transmitted first"
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
newline
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
newline
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave..,1: Frame sync is generated internally in Master.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TDR[$1],SAI Transmit Data Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "TDR,Transmit Data Register"
|
|
repeat.end
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "TFR[$1],SAI Transmit FIFO Register $1"
|
|
bitfld.long 0x00 31. "WCP,Write Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO writes and.."
|
|
bitfld.long 0x00 16.--19. "WFP,Write FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RFP,Read FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TMR,SAI Transmit Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "TWM,Transmit Word Mask"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled or receiver has been.."
|
|
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Receiver disabled in Stop mode,1: Receiver enabled in Stop mode"
|
|
newline
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode"
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled,1: Receive bit clock is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
newline
|
|
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
newline
|
|
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected,1: Receive overflow detected"
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full,1: Enabled receive FIFO is full"
|
|
newline
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached,1: Receive FIFO watermark has been reached"
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RCR1,SAI Receive Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. "RFW,Receive FIFO Watermark" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter,2: Synchronous with another SAI receiver,3: Synchronous with another SAI transmitter"
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit Clock is active high with drive outputs..,1: Bit Clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RCR3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x00 24.--25. "CFR,Channel FIFO Reset" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "RCE,Receive Channel Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RCR4,SAI Receive Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO writes..,2: FIFO combine mode enabled on FIFO reads (by..,3: FIFO combine mode enabled on FIFO writes.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
bitfld.long 0x00 16.--20. "FRSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is received first,1: MSB is received first"
|
|
newline
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
newline
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave..,1: Frame Sync is generated internally in Master.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0xA0)++0x03
|
|
line.long 0x00 "RDR[$1],SAI Receive Data Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "RDR,Receive Data Register"
|
|
repeat.end
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "RFR[$1],SAI Receive FIFO Register $1"
|
|
bitfld.long 0x00 16.--19. "WFP,Write FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "RCP,Receive Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO reads and.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RFP,Read FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RMR,SAI Receive Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "RWM,Receive Word Mask"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "INTMUX (Interrupt Multiplexer)"
|
|
tree "INTMUX0"
|
|
base ad:0x40024000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH3_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CH0_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CH1_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "CH2_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CH3_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH2_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CH3_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CH0_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CH1_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "CH2_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "CH3_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "INTMUX1"
|
|
base ad:0x41022000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CH0_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CH0_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CH1_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CH1_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "CH2_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH2_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "CH2_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH3_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CH3_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CH3_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "CH3_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CH4_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CH4_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CH4_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CH4_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CH5_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "CH5_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CH5_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CH5_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CH6_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "CH6_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CH6_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "CH6_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CH7_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "CH7_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CH7_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "CH7_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "ITM (Instrumentation Trace Macrocell Registers)"
|
|
base ad:0xE0000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "STIM0_READ,Stimulus Port Register 0 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "STIM0_WRITE,Stimulus Port Register 0 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "STIM1_READ,Stimulus Port Register 1 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "STIM1_WRITE,Stimulus Port Register 1 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STIM2_READ,Stimulus Port Register 2 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STIM2_WRITE,Stimulus Port Register 2 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STIM3_READ,Stimulus Port Register 3 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STIM3_WRITE,Stimulus Port Register 3 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STIM4_READ,Stimulus Port Register 4 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STIM4_WRITE,Stimulus Port Register 4 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STIM5_READ,Stimulus Port Register 5 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STIM5_WRITE,Stimulus Port Register 5 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STIM6_READ,Stimulus Port Register 6 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STIM6_WRITE,Stimulus Port Register 6 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STIM7_READ,Stimulus Port Register 7 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STIM7_WRITE,Stimulus Port Register 7 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "STIM8_READ,Stimulus Port Register 8 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "STIM8_WRITE,Stimulus Port Register 8 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "STIM9_READ,Stimulus Port Register 9 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "STIM9_WRITE,Stimulus Port Register 9 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "STIM10_READ,Stimulus Port Register 10 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "STIM10_WRITE,Stimulus Port Register 10 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "STIM11_READ,Stimulus Port Register 11 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "STIM11_WRITE,Stimulus Port Register 11 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "STIM12_READ,Stimulus Port Register 12 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "STIM12_WRITE,Stimulus Port Register 12 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "STIM13_READ,Stimulus Port Register 13 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "STIM13_WRITE,Stimulus Port Register 13 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "STIM14_READ,Stimulus Port Register 14 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "STIM14_WRITE,Stimulus Port Register 14 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "STIM15_READ,Stimulus Port Register 15 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "STIM15_WRITE,Stimulus Port Register 15 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "STIM16_READ,Stimulus Port Register 16 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "STIM16_WRITE,Stimulus Port Register 16 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "STIM17_READ,Stimulus Port Register 17 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "STIM17_WRITE,Stimulus Port Register 17 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "STIM18_READ,Stimulus Port Register 18 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "STIM18_WRITE,Stimulus Port Register 18 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "STIM19_READ,Stimulus Port Register 19 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "STIM19_WRITE,Stimulus Port Register 19 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "STIM20_READ,Stimulus Port Register 20 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "STIM20_WRITE,Stimulus Port Register 20 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STIM21_READ,Stimulus Port Register 21 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STIM21_WRITE,Stimulus Port Register 21 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "STIM22_READ,Stimulus Port Register 22 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "STIM22_WRITE,Stimulus Port Register 22 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "STIM23_READ,Stimulus Port Register 23 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "STIM23_WRITE,Stimulus Port Register 23 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "STIM24_READ,Stimulus Port Register 24 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "STIM24_WRITE,Stimulus Port Register 24 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "STIM25_READ,Stimulus Port Register 25 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "STIM25_WRITE,Stimulus Port Register 25 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "STIM26_READ,Stimulus Port Register 26 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "STIM26_WRITE,Stimulus Port Register 26 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "STIM27_READ,Stimulus Port Register 27 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "STIM27_WRITE,Stimulus Port Register 27 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "STIM28_READ,Stimulus Port Register 28 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "STIM28_WRITE,Stimulus Port Register 28 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "STIM29_READ,Stimulus Port Register 29 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "STIM29_WRITE,Stimulus Port Register 29 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "STIM30_READ,Stimulus Port Register 30 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "STIM30_WRITE,Stimulus Port Register 30 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "STIM31_READ,Stimulus Port Register 31 (for reading)"
|
|
bitfld.long 0x00 0. "FIFOREADY,no description available" "0,1"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "STIM31_WRITE,Stimulus Port Register 31 (for writing)"
|
|
hexmask.long 0x00 0.--31. 1. "STIMULUS,Data write to the stimulus port FIFO for forwarding as a software event packet"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "TER,Trace Enable Register"
|
|
abitfld.long 0x00 0.--31. "STIMENA,For bit STIMENA[n] in register ITM_TERx" "0x00000000=0: Stimulus port (32x + n) disabled,0x00000001=1: Stimulus port (32x + n) enabled"
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "TPR,Trace Privilege Register"
|
|
bitfld.long 0x00 0.--3. "PRIVMASK,Bit mask to enable tracing on ITM stimulus ports: Bit [0] = stimulus port [7:0] Bit [1] = stimulus port [15:8] Bit [2] = stimulus port [23:16] Bit [3] = stimulus port [31:24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "TCR,Trace Control Register"
|
|
rbitfld.long 0x00 23. "BUSY,Indicates whether the ITM is currently processing events" "0: ITM is not processing any events,1: ITM events present and beeing drained"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TraceBusID,Identifier for multi-source trace stream formatting"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "GTSFREQ,Global timestamp frequency" "0: Disable generation of global timestamps,1: Generate timestamp request whenever the ITM..,2: Generate timestamp request whenever the ITM..,3: Generate a timestamp after every packet if.."
|
|
bitfld.long 0x00 8.--9. "TSPrescale,Local timestamp prescaler used with the trace packet reference clock" "0: No prescaling,1: TSPrescale_1,2: Divide by 16,3: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 4. "SWOENA,no description available" "0: Timestamp counter uses the processor system..,1: Timestamp counter uses asynchronous clock.."
|
|
bitfld.long 0x00 3. "TXENA,no description available" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SYNCENA,no description available" "0: SYNCENA_0,1: SYNCENA_1"
|
|
bitfld.long 0x00 1. "TSENA,no description available" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ITMENA,no description available" "0: Disabled,1: ITMENA_1"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "WriteAccessCode,Write Access Code"
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
bitfld.long 0x00 2. "s8BIT,Access Lock Register size" "0,1"
|
|
bitfld.long 0x00 1. "STATUS,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMP,Lock mechanism is implemented" "0,1"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
bitfld.long 0x00 4.--7. "c4KB,4KB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "JEP106,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "5" "6" "7" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PID$1,Peripheral Identification Register 5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PID0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber,Part Number [7:0]"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PID1,Peripheral Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "JEP106_identity_code,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PartNumber,Part Number [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PID2,Peripheral Identification Register 2"
|
|
bitfld.long 0x00 4.--7. "Revision,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PID3,Peripheral Identification Register 3"
|
|
bitfld.long 0x00 4.--7. "RevAnd,RevAnd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CustomerModified,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "CID0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CID1,Component Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "ComponentClass,Component class" "?,1: ComponentClass_1,?,?,?,?,?,?,?,9: CoreSight component,?,?,?,?,?,15: PrimeCell of system component with no.."
|
|
bitfld.long 0x00 0.--3. "Preamble,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "CID$1,Component Identification Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
tree "LCD (Segment Liquid Crystal Display)"
|
|
base ad:0x40053000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,LCD General Control Register"
|
|
bitfld.long 0x00 31. "RVEN,Regulated Voltage Enable" "0: Regulated voltage disabled,1: Regulated voltage enabled"
|
|
bitfld.long 0x00 24.--27. "RVTRIM,Regulated Voltage Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. "CPSEL,Charge Pump or Resistor Bias Select" "0: LCD charge pump is disabled,1: LCD charge pump is selected"
|
|
bitfld.long 0x00 20.--21. "LADJ,Load Adjust" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "VSUPPLY,Voltage Supply Control" "0: Drive VLL3 internally from VDD,1: Drive VLL3 externally from VDD or drive VLL1.."
|
|
bitfld.long 0x00 15. "PADSAFE,Pad Safe State Enable" "0: LCD frontplane and backplane functions..,1: LCD frontplane and backplane functions disabled"
|
|
newline
|
|
bitfld.long 0x00 14. "FDCIEN,LCD Fault Detection Complete Interrupt Enable" "0: No interrupt request is generated by this event,1: When a fault is detected and FDCF bit is set.."
|
|
bitfld.long 0x00 12.--13. "ALTDIV,LCD Alternate Clock Divider" "0: Divide factor = 1 (No divide),1: Divide factor = 64,2: Divide factor = 256,3: Divide factor = 512"
|
|
newline
|
|
bitfld.long 0x00 11. "ALTSOURCE,Selects the alternate clock source" "0: Select Alternate Clock Source 1 (default),1: Select Alternate Clock Source 2"
|
|
bitfld.long 0x00 10. "FFR,Fast Frame Rate Select" "0: Standard Frame Rate LCD Frame Freq,1: Fast Frame Rate (Standard Frame Rate *2) LCD.."
|
|
newline
|
|
bitfld.long 0x00 9. "LCDDOZE,LCD Doze enable" "0: Allows the LCD driver charge pump resistor..,1: Disables the LCD driver charge pump resistor.."
|
|
bitfld.long 0x00 8. "LCDSTP,LCD Stop" "0: Allows the LCD driver charge pump resistor..,1: Disables the LCD driver charge pump resistor.."
|
|
newline
|
|
bitfld.long 0x00 7. "LCDEN,LCD Driver Enable" "0: All front plane and back plane pins are..,1: LCD controller driver system is enabled and.."
|
|
bitfld.long 0x00 6. "SOURCE,LCD Clock Source Select" "0: Selects the default clock as the LCD clock..,1: Selects output of the alternate clock source.."
|
|
newline
|
|
bitfld.long 0x00 3.--5. "LCLK,LCD Clock Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "DUTY,LCD duty select" "0: Use 1 BP (1/1 duty cycle),1: Use 2 BP (1/2 duty cycle),2: Use 3 BP (1/3 duty cycle),3: Use 4 BP (1/4 duty cycle),?,?,?,7: Use 8 BP (1/8 duty cycle)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AR,LCD Auxiliary Register"
|
|
bitfld.long 0x00 7. "BLINK,Blink command" "0: Disables blinking,1: Starts blinking at blinking frequency.."
|
|
bitfld.long 0x00 6. "ALT,Alternate display mode" "0: Normal display mode,1: Alternate display mode"
|
|
newline
|
|
bitfld.long 0x00 5. "BLANK,Blank display mode" "0: Normal or alternate display mode,1: Blank display mode"
|
|
bitfld.long 0x00 3. "BMODE,Blink mode" "0: Display blank during the blink period,1: Display alternate display during blink period.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "BRATE,Blink-rate configuration" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FDCR,LCD Fault Detect Control Register"
|
|
bitfld.long 0x00 12.--14. "FDPRS,Fault Detect Clock Prescaler" "0: 1/1 bus clock,1: 1/2 bus clock,2: 1/4 bus clock,3: 1/8 bus clock,4: 1/16 bus clock,5: 1/32 bus clock,6: 1/64 bus clock,7: 1/128 bus clock"
|
|
bitfld.long 0x00 9.--11. "FDSWW,Fault Detect Sample Window Width" "0: Sample window width is 4 sample clock cycles,1: Sample window width is 8 sample clock cycles,2: Sample window width is 16 sample clock cycles,3: Sample window width is 32 sample clock cycles,4: Sample window width is 64 sample clock cycles,5: Sample window width is 128 sample clock cycles,6: Sample window width is 256 sample clock cycles,7: Sample window width is 512 sample clock cycles"
|
|
newline
|
|
bitfld.long 0x00 7. "FDEN,Fault Detect Enable" "0: Disable fault detection,1: Enable fault detection"
|
|
bitfld.long 0x00 6. "FDBPEN,Fault Detect Back Plane Enable" "0: Type of the selected pin under fault detect..,1: Type of the selected pin under fault detect.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "FDPINID,Fault Detect Pin ID" "0: Fault detection for LCD_P0 pin,1: Fault detection for LCD_P1 pin,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: Fault detection for LCD_P63 pin"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FDSR,LCD Fault Detect Status Register"
|
|
bitfld.long 0x00 15. "FDCF,Fault Detection Complete Flag" "0: Fault detection is not completed,1: Fault detection is completed"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FDCNT,Fault Detect Counter"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PENL,LCD Pin Enable register"
|
|
hexmask.long 0x00 0.--31. 1. "PEN,LCD Pin Enable"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PENH,LCD Pin Enable register"
|
|
hexmask.long 0x00 0.--31. 1. "PEN,LCD Pin Enable"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BPENL,LCD Back Plane Enable register"
|
|
hexmask.long 0x00 0.--31. 1. "BPEN,Back Plane Enable"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BPENH,LCD Back Plane Enable register"
|
|
hexmask.long 0x00 0.--31. 1. "BPEN,Back Plane Enable"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "WF3TO0,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF3,Segment-on front plane operation - Each bit turns on or off the segments associated with LCD_P3 in the following pattern: HGFEDCBA (most significant bit controls segment H and least significant bit controls segment A)"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF2,Controls segments or phases connected to LCD_P2 as described above for WF3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF1,Controls segments or phases connected to LCD_P1 as described above for WF3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF0,Controls segments or phases connected to LCD_P0 as described above for WF3"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "WF0,LCD Waveform Register 0"
|
|
bitfld.byte 0x00 7. "BPHLCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD0,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "WF1,LCD Waveform Register 1"
|
|
bitfld.byte 0x00 7. "BPHLCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD1,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "WF2,LCD Waveform Register 2"
|
|
bitfld.byte 0x00 7. "BPHLCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD2,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "WF3,LCD Waveform Register 3"
|
|
bitfld.byte 0x00 7. "BPHLCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD3,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "WF7TO4,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF7,Controls segments or phases connected to LCD_P7 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF6,Controls segments or phases connected to LCD_P6 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF5,Controls segments or phases connected to LCD_P5 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF4,Controls segments or phases connected to LCD_P4 as described above for WF3TO0[WF3]"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "WF4,LCD Waveform Register 4"
|
|
bitfld.byte 0x00 7. "BPHLCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD4,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "WF5,LCD Waveform Register 5"
|
|
bitfld.byte 0x00 7. "BPHLCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD5,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "WF6,LCD Waveform Register 6"
|
|
bitfld.byte 0x00 7. "BPHLCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD6,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "WF7,LCD Waveform Register 7"
|
|
bitfld.byte 0x00 7. "BPHLCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD7,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "WF11TO8,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF11,Controls segments or phases connected to LCD_P11 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF10,Controls segments or phases connected to LCD_P10 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF9,Controls segments or phases connected to LCD_P9 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF8,Controls segments or phases connected to LCD_P8 as described above for WF3TO0[WF3]"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "WF8,LCD Waveform Register 8"
|
|
bitfld.byte 0x00 7. "BPHLCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD8,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "WF9,LCD Waveform Register 9"
|
|
bitfld.byte 0x00 7. "BPHLCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD9,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "WF10,LCD Waveform Register 10"
|
|
bitfld.byte 0x00 7. "BPHLCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD10,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "WF11,LCD Waveform Register 11"
|
|
bitfld.byte 0x00 7. "BPHLCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD11,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WF15TO12,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF15,Controls segments or phases connected to LCD_P15 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF14,Controls segments or phases connected to LCD_P14 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF13,Controls segments or phases connected to LCD_P13 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF12,Controls segments or phases connected to LCD_P12 as described above for WF3TO0[WF3]"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "WF12,LCD Waveform Register 12"
|
|
bitfld.byte 0x00 7. "BPHLCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD12,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "WF13,LCD Waveform Register 13"
|
|
bitfld.byte 0x00 7. "BPHLCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD13,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "WF14,LCD Waveform Register 14"
|
|
bitfld.byte 0x00 7. "BPHLCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD14,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "WF15,LCD Waveform Register 15"
|
|
bitfld.byte 0x00 7. "BPHLCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD15,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "WF19TO16,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF19,Controls segments or phases connected to LCD_P19 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF18,Controls segments or phases connected to LCD_P18 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF17,Controls segments or phases connected to LCD_P17 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF16,Controls segments or phases connected to LCD_P16 as described above for WF3TO0[WF3]"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "WF16,LCD Waveform Register 16"
|
|
bitfld.byte 0x00 7. "BPHLCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD16,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "WF17,LCD Waveform Register 17"
|
|
bitfld.byte 0x00 7. "BPHLCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD17,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "WF18,LCD Waveform Register 18"
|
|
bitfld.byte 0x00 7. "BPHLCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD18,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "WF19,LCD Waveform Register 19"
|
|
bitfld.byte 0x00 7. "BPHLCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD19,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "WF23TO20,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF23,Controls segments or phases connected to LCD_P23 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF22,Controls segments or phases connected to LCD_P22 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF21,Controls segments or phases connected to LCD_P21 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF20,Controls segments or phases connected to LCD_P20 as described above for WF3TO0[WF3]"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "WF20,LCD Waveform Register 20"
|
|
bitfld.byte 0x00 7. "BPHLCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD20,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "WF21,LCD Waveform Register 21"
|
|
bitfld.byte 0x00 7. "BPHLCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD21,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "WF22,LCD Waveform Register 22"
|
|
bitfld.byte 0x00 7. "BPHLCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD22,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "WF23,LCD Waveform Register 23"
|
|
bitfld.byte 0x00 7. "BPHLCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD23,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "WF27TO24,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF27,Controls segments or phases connected to LCD_P27 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF26,Controls segments or phases connected to LCD_P26 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF25,Controls segments or phases connected to LCD_P25 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF24,Controls segments or phases connected to LCD_P24 as described above for WF3TO0[WF3]"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "WF24,LCD Waveform Register 24"
|
|
bitfld.byte 0x00 7. "BPHLCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD24,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "WF25,LCD Waveform Register 25"
|
|
bitfld.byte 0x00 7. "BPHLCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD25,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "WF26,LCD Waveform Register 26"
|
|
bitfld.byte 0x00 7. "BPHLCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD26,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "WF27,LCD Waveform Register 27"
|
|
bitfld.byte 0x00 7. "BPHLCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD27,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "WF31TO28,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF31,Controls segments or phases connected to LCD_P31 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF30,Controls segments or phases connected to LCD_P30 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF29,Controls segments or phases connected to LCD_P29 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF28,Controls segments or phases connected to LCD_P28 as described above for WF3TO0[WF3]"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "WF28,LCD Waveform Register 28"
|
|
bitfld.byte 0x00 7. "BPHLCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD28,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "WF29,LCD Waveform Register 29"
|
|
bitfld.byte 0x00 7. "BPHLCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD29,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "WF30,LCD Waveform Register 30"
|
|
bitfld.byte 0x00 7. "BPHLCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD30,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "WF31,LCD Waveform Register 31"
|
|
bitfld.byte 0x00 7. "BPHLCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD31,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "WF35TO32,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF35,Controls segments or phases connected to LCD_P35 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF34,Controls segments or phases connected to LCD_P34 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF33,Controls segments or phases connected to LCD_P33 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF32,Controls segments or phases connected to LCD_P32 as described above for WF3TO0[WF3]"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "WF32,LCD Waveform Register 32"
|
|
bitfld.byte 0x00 7. "BPHLCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD32,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "WF33,LCD Waveform Register 33"
|
|
bitfld.byte 0x00 7. "BPHLCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD33,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "WF34,LCD Waveform Register 34"
|
|
bitfld.byte 0x00 7. "BPHLCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD34,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "WF35,LCD Waveform Register 35"
|
|
bitfld.byte 0x00 7. "BPHLCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD35,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "WF39TO36,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF39,Controls segments or phases connected to LCD_P39 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF38,Controls segments or phases connected to LCD_P38 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF37,Controls segments or phases connected to LCD_P37 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF36,Controls segments or phases connected to LCD_P36 as described above for WF3TO0[WF3]"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "WF36,LCD Waveform Register 36"
|
|
bitfld.byte 0x00 7. "BPHLCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD36,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "WF37,LCD Waveform Register 37"
|
|
bitfld.byte 0x00 7. "BPHLCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD37,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x46++0x00
|
|
line.byte 0x00 "WF38,LCD Waveform Register 38"
|
|
bitfld.byte 0x00 7. "BPHLCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD38,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "WF39,LCD Waveform Register 39"
|
|
bitfld.byte 0x00 7. "BPHLCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD39,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "WF43TO40,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF43,Controls segments or phases connected to LCD_P43 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF42,Controls segments or phases connected to LCD_P42 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF41,Controls segments or phases connected to LCD_P41 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF40,Controls segments or phases connected to LCD_P40 as described above for WF3TO0[WF3]"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "WF40,LCD Waveform Register 40"
|
|
bitfld.byte 0x00 7. "BPHLCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD40,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "WF41,LCD Waveform Register 41"
|
|
bitfld.byte 0x00 7. "BPHLCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD41,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "WF42,LCD Waveform Register 42"
|
|
bitfld.byte 0x00 7. "BPHLCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD42,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "WF43,LCD Waveform Register 43"
|
|
bitfld.byte 0x00 7. "BPHLCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD43,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "WF47TO44,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF47,Controls segments or phases connected to LCD_P47 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF46,Controls segments or phases connected to LCD_P46 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF45,Controls segments or phases connected to LCD_P45 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF44,Controls segments or phases connected to LCD_P44 as described above for WF3TO0[WF3]"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "WF44,LCD Waveform Register 44"
|
|
bitfld.byte 0x00 7. "BPHLCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD44,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "WF45,LCD Waveform Register 45"
|
|
bitfld.byte 0x00 7. "BPHLCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD45,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "WF46,LCD Waveform Register 46"
|
|
bitfld.byte 0x00 7. "BPHLCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD46,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "WF47,LCD Waveform Register 47"
|
|
bitfld.byte 0x00 7. "BPHLCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD47,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "WF51TO48,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF51,Controls segments or phases connected to LCD_P51 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF50,Controls segments or phases connected to LCD_P50 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF49,Controls segments or phases connected to LCD_P49 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF48,Controls segments or phases connected to LCD_P48 as described above for WF3TO0[WF3]"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "WF48,LCD Waveform Register 48"
|
|
bitfld.byte 0x00 7. "BPHLCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD48,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "WF49,LCD Waveform Register 49"
|
|
bitfld.byte 0x00 7. "BPHLCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD49,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "WF50,LCD Waveform Register 50"
|
|
bitfld.byte 0x00 7. "BPHLCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD50,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "WF51,LCD Waveform Register 51"
|
|
bitfld.byte 0x00 7. "BPHLCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD51,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "WF55TO52,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF55,Controls segments or phases connected to LCD_P55 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF54,Controls segments or phases connected to LCD_P54 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF53,Controls segments or phases connected to LCD_P53 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF52,Controls segments or phases connected to LCD_P52 as described above for WF3TO0[WF3]"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "WF52,LCD Waveform Register 52"
|
|
bitfld.byte 0x00 7. "BPHLCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD52,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "WF53,LCD Waveform Register 53"
|
|
bitfld.byte 0x00 7. "BPHLCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD53,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x56++0x00
|
|
line.byte 0x00 "WF54,LCD Waveform Register 54"
|
|
bitfld.byte 0x00 7. "BPHLCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD54,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "WF55,LCD Waveform Register 55"
|
|
bitfld.byte 0x00 7. "BPHLCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD55,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "WF59TO56,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF59,Controls segments or phases connected to LCD_P59 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF58,Controls segments or phases connected to LCD_P58 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF57,Controls segments or phases connected to LCD_P57 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF56,Controls segments or phases connected to LCD_P56 as described above for WF3TO0[WF3]"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "WF56,LCD Waveform Register 56"
|
|
bitfld.byte 0x00 7. "BPHLCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD56,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "WF57,LCD Waveform Register 57"
|
|
bitfld.byte 0x00 7. "BPHLCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD57,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "WF58,LCD Waveform Register 58"
|
|
bitfld.byte 0x00 7. "BPHLCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD58,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "WF59,LCD Waveform Register 59"
|
|
bitfld.byte 0x00 7. "BPHLCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD59,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "WF63TO60,LCD Waveform register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WF63,Controls segments or phases connected to LCD_P63 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WF62,Controls segments or phases connected to LCD_P62 as described above for WF3TO0[WF3]"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "WF61,Controls segments or phases connected to LCD_P61 as described above for WF3TO0[WF3]"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WF60,Controls segments or phases connected to LCD_P60 as described above for WF3TO0[WF3]"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "WF60,LCD Waveform Register 60"
|
|
bitfld.byte 0x00 7. "BPHLCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD60,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x5D++0x00
|
|
line.byte 0x00 "WF61,LCD Waveform Register 61"
|
|
bitfld.byte 0x00 7. "BPHLCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD61,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x5E++0x00
|
|
line.byte 0x00 "WF62,LCD Waveform Register 62"
|
|
bitfld.byte 0x00 7. "BPHLCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD62,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
group.byte 0x5F++0x00
|
|
line.byte 0x00 "WF63,LCD Waveform Register 63"
|
|
bitfld.byte 0x00 7. "BPHLCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 6. "BPGLCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BPFLCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 4. "BPELCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BPDLCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 2. "BPCLCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
newline
|
|
bitfld.byte 0x00 1. "BPBLCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
bitfld.byte 0x00 0. "BPALCD63,no description available" "0: LCD segment off or LCD backplane inactive for..,1: LCD segment on or LCD backplane active for.."
|
|
tree.end
|
|
endif
|
|
tree "LLWU (Low leakage wakeup unit)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "LLWU"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40061000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4007C000
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "PE1,LLWU Pin Enable 1 register"
|
|
bitfld.byte 0x00 6.--7. "WUPE3,Wakeup Pin Enable For LLWU_P3" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 4.--5. "WUPE2,Wakeup Pin Enable For LLWU_P2" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "WUPE1,Wakeup Pin Enable For LLWU_P1" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 0.--1. "WUPE0,Wakeup Pin Enable For LLWU_P0" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "PE2,LLWU Pin Enable 2 register"
|
|
bitfld.byte 0x00 6.--7. "WUPE7,Wakeup Pin Enable For LLWU_P7" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 4.--5. "WUPE6,Wakeup Pin Enable For LLWU_P6" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "WUPE5,Wakeup Pin Enable For LLWU_P5" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 0.--1. "WUPE4,Wakeup Pin Enable For LLWU_P4" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "PE3,LLWU Pin Enable 3 register"
|
|
bitfld.byte 0x00 6.--7. "WUPE11,Wakeup Pin Enable For LLWU_P11" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 4.--5. "WUPE10,Wakeup Pin Enable For LLWU_P10" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "WUPE9,Wakeup Pin Enable For LLWU_P9" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 0.--1. "WUPE8,Wakeup Pin Enable For LLWU_P8" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "PE4,LLWU Pin Enable 4 register"
|
|
bitfld.byte 0x00 6.--7. "WUPE15,Wakeup Pin Enable For LLWU_P15" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 4.--5. "WUPE14,Wakeup Pin Enable For LLWU_P14" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "WUPE13,Wakeup Pin Enable For LLWU_P13" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.byte 0x00 0.--1. "WUPE12,Wakeup Pin Enable For LLWU_P12" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PINS,Pin Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MODULES,Module Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DMAS,DMA Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FILTERS,Filter Number"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ME,LLWU Module Enable register"
|
|
bitfld.byte 0x00 7. "WUME7,Wakeup Module Enable For Module 7" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.byte 0x00 6. "WUME6,Wakeup Module Enable For Module 6" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 5. "WUME5,Wakeup Module Enable For Module 5" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.byte 0x00 4. "WUME4,Wakeup Module Enable For Module 4" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 3. "WUME3,Wakeup Module Enable For Module 3" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.byte 0x00 2. "WUME2,Wakeup Module Enable For Module 2" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 1. "WUME1,Wakeup Module Enable for Module 1" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.byte 0x00 0. "WUME0,Wakeup Module Enable For Module 0" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "F1,LLWU Flag 1 register"
|
|
bitfld.byte 0x00 7. "WUF7,Wakeup Flag For LLWU_P7" "0: LLWU_P7 input was not a wakeup source,1: LLWU_P7 input was a wakeup source"
|
|
bitfld.byte 0x00 6. "WUF6,Wakeup Flag For LLWU_P6" "0: LLWU_P6 input was not a wakeup source,1: LLWU_P6 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 5. "WUF5,Wakeup Flag For LLWU_P5" "0: LLWU_P5 input was not a wakeup source,1: LLWU_P5 input was a wakeup source"
|
|
bitfld.byte 0x00 4. "WUF4,Wakeup Flag For LLWU_P4" "0: LLWU_P4 input was not a wakeup source,1: LLWU_P4 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 3. "WUF3,Wakeup Flag For LLWU_P3" "0: LLWU_P3 input was not a wake-up source,1: LLWU_P3 input was a wake-up source"
|
|
bitfld.byte 0x00 2. "WUF2,Wakeup Flag For LLWU_P2" "0: LLWU_P2 input was not a wakeup source,1: LLWU_P2 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 1. "WUF1,Wakeup Flag For LLWU_P1" "0: LLWU_P1 input was not a wakeup source,1: LLWU_P1 input was a wakeup source"
|
|
bitfld.byte 0x00 0. "WUF0,Wakeup Flag For LLWU_P0" "0: LLWU_P0 input was not a wakeup source,1: LLWU_P0 input was a wakeup source"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "F2,LLWU Flag 2 register"
|
|
bitfld.byte 0x00 7. "WUF15,Wakeup Flag For LLWU_P15" "0: LLWU_P15 input was not a wakeup source,1: LLWU_P15 input was a wakeup source"
|
|
bitfld.byte 0x00 6. "WUF14,Wakeup Flag For LLWU_P14" "0: LLWU_P14 input was not a wakeup source,1: LLWU_P14 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 5. "WUF13,Wakeup Flag For LLWU_P13" "0: LLWU_P13 input was not a wakeup source,1: LLWU_P13 input was a wakeup source"
|
|
bitfld.byte 0x00 4. "WUF12,Wakeup Flag For LLWU_P12" "0: LLWU_P12 input was not a wakeup source,1: LLWU_P12 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 3. "WUF11,Wakeup Flag For LLWU_P11" "0: LLWU_P11 input was not a wakeup source,1: LLWU_P11 input was a wakeup source"
|
|
bitfld.byte 0x00 2. "WUF10,Wakeup Flag For LLWU_P10" "0: LLWU_P10 input was not a wakeup source,1: LLWU_P10 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 1. "WUF9,Wakeup Flag For LLWU_P9" "0: LLWU_P9 input was not a wakeup source,1: LLWU_P9 input was a wakeup source"
|
|
bitfld.byte 0x00 0. "WUF8,Wakeup Flag For LLWU_P8" "0: LLWU_P8 input was not a wakeup source,1: LLWU_P8 input was a wakeup source"
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "F3,LLWU Flag 3 register"
|
|
bitfld.byte 0x00 7. "MWUF7,Wakeup flag For module 7" "0: Module 7 input was not a wakeup source,1: Module 7 input was a wakeup source"
|
|
bitfld.byte 0x00 6. "MWUF6,Wakeup flag For module 6" "0: Module 6 input was not a wakeup source,1: Module 6 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 5. "MWUF5,Wakeup flag For module 5" "0: Module 5 input was not a wakeup source,1: Module 5 input was a wakeup source"
|
|
bitfld.byte 0x00 4. "MWUF4,Wakeup flag For module 4" "0: Module 4 input was not a wakeup source,1: Module 4 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 3. "MWUF3,Wakeup flag For module 3" "0: Module 3 input was not a wakeup source,1: Module 3 input was a wakeup source"
|
|
bitfld.byte 0x00 2. "MWUF2,Wakeup flag For module 2" "0: Module 2 input was not a wakeup source,1: Module 2 input was a wakeup source"
|
|
newline
|
|
bitfld.byte 0x00 1. "MWUF1,Wakeup flag For module 1" "0: Module 1 input was not a wakeup source,1: Module 1 input was a wakeup source"
|
|
bitfld.byte 0x00 0. "MWUF0,Wakeup flag For module 0" "0: Module 0 input was not a wakeup source,1: Module 0 input was a wakeup source"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FILT1,LLWU Pin Filter 1 register"
|
|
bitfld.byte 0x00 7. "FILTF,Filter Detect Flag" "0: Pin Filter 1 was not a wakeup source,1: Pin Filter 1 was a wakeup source"
|
|
bitfld.byte 0x00 5.--6. "FILTE,Digital Filter On External Pin" "0: Filter disabled,1: Filter posedge detect enabled,2: Filter negedge detect enabled,3: Filter any edge detect enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "FILTSEL,Filter Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Select LLWU_P15 for filter"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PE1,LLWU Pin Enable 1 register"
|
|
bitfld.long 0x00 30.--31. "WUPE15,Wakeup Pin Enable For LLWU_P15" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 28.--29. "WUPE14,Wakeup Pin Enable For LLWU_P14" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "WUPE13,Wakeup Pin Enable For LLWU_P13" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 24.--25. "WUPE12,Wakeup Pin Enable For LLWU_P12" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "WUPE11,Wakeup Pin Enable For LLWU_P11" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 20.--21. "WUPE10,Wakeup Pin Enable For LLWU_P10" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "WUPE9,Wakeup Pin Enable For LLWU_P9" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 16.--17. "WUPE8,Wakeup Pin Enable For LLWU_P8" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "WUPE7,Wakeup Pin Enable For LLWU_P7" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 12.--13. "WUPE6,Wakeup Pin Enable For LLWU_P6" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "WUPE5,Wakeup Pin Enable For LLWU_P5" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 8.--9. "WUPE4,Wakeup Pin Enable For LLWU_P4" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "WUPE3,Wakeup Pin Enable For LLWU_P3" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 4.--5. "WUPE2,Wakeup Pin Enable For LLWU_P2" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "WUPE1,Wakeup Pin Enable For LLWU_P1" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 0.--1. "WUPE0,Wakeup Pin Enable For LLWU_P0" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "FILT2,LLWU Pin Filter 2 register"
|
|
bitfld.byte 0x00 7. "FILTF,Filter Detect Flag" "0: Pin Filter 2 was not a wakeup source,1: Pin Filter 2 was a wakeup source"
|
|
bitfld.byte 0x00 5.--6. "FILTE,Digital Filter On External Pin" "0: Filter disabled,1: Filter posedge detect enabled,2: Filter negedge detect enabled,3: Filter any edge detect enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "FILTSEL,Filter Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Select LLWU_P15 for filter"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PE2,LLWU Pin Enable 2 register"
|
|
bitfld.long 0x00 30.--31. "WUPE31,Wakeup Pin Enable For LLWU_P31" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 28.--29. "WUPE30,Wakeup Pin Enable For LLWU_P30" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "WUPE29,Wakeup Pin Enable For LLWU_P29" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 24.--25. "WUPE28,Wakeup Pin Enable For LLWU_P28" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "WUPE27,Wakeup Pin Enable For LLWU_P27" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 20.--21. "WUPE26,Wakeup Pin Enable For LLWU_P26" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "WUPE25,Wakeup Pin Enable For LLWU_P25" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 16.--17. "WUPE24,Wakeup Pin Enable For LLWU_P24" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "WUPE23,Wakeup Pin Enable For LLWU_P23" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 12.--13. "WUPE22,Wakeup Pin Enable For LLWU_P22" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "WUPE21,Wakeup Pin Enable For LLWU_P21" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 8.--9. "WUPE20,Wakeup Pin Enable For LLWU_P20" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "WUPE19,Wakeup Pin Enable For LLWU_P19" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 4.--5. "WUPE18,Wakeup Pin Enable For LLWU_P18" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "WUPE17,Wakeup Pin Enable For LLWU_P17" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 0.--1. "WUPE16,Wakeup Pin Enable For LLWU_P16" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ME,LLWU Module Interrupt Enable register"
|
|
bitfld.long 0x00 7. "WUME7,Wakeup Module Enable For Module 7" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 6. "WUME6,Wakeup Module Enable For Module 6" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.long 0x00 5. "WUME5,Wakeup Module Enable For Module 5" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 4. "WUME4,Wakeup Module Enable For Module 4" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.long 0x00 3. "WUME3,Wakeup Module Enable For Module 3" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 2. "WUME2,Wakeup Module Enable For Module 2" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.long 0x00 1. "WUME1,Wakeup Module Enable for Module 1" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 0. "WUME0,Wakeup Module Enable For Module 0" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DE,LLWU Module DMA Enable register"
|
|
bitfld.long 0x00 7. "WUDE7,DMA Wakeup Enable For Module 7" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
bitfld.long 0x00 6. "WUDE6,DMA Wakeup Enable For Module 6" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
newline
|
|
bitfld.long 0x00 5. "WUDE5,DMA Wakeup Enable For Module 5" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
bitfld.long 0x00 4. "WUDE4,DMA Wakeup Enable For Module 4" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
newline
|
|
bitfld.long 0x00 3. "WUDE3,DMA Wakeup Enable For Module 3" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
bitfld.long 0x00 2. "WUDE2,DMA Wakeup Enable For Module 2" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
newline
|
|
bitfld.long 0x00 1. "WUDE1,DMA Wakeup Enable for Module 1" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
bitfld.long 0x00 0. "WUDE0,DMA Wakeup Enable For Module 0" "0: Internal module request not used as a DMA..,1: Internal module request used as a DMA wakeup.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PF,LLWU Pin Flag register"
|
|
bitfld.long 0x00 31. "WUF31,Wakeup Flag For LLWU_P31" "0: LLWU_P31 input was not a wakeup source,1: LLWU_P31 input was a wakeup source"
|
|
bitfld.long 0x00 30. "WUF30,Wakeup Flag For LLWU_P30" "0: LLWU_P30 input was not a wakeup source,1: LLWU_P30 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 29. "WUF29,Wakeup Flag For LLWU_P29" "0: LLWU_P29 input was not a wakeup source,1: LLWU_P29 input was a wakeup source"
|
|
bitfld.long 0x00 28. "WUF28,Wakeup Flag For LLWU_P28" "0: LLWU_P28 input was not a wakeup source,1: LLWU_P28 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 27. "WUF27,Wakeup Flag For LLWU_P27" "0: LLWU_P27 input was not a wakeup source,1: LLWU_P27 input was a wakeup source"
|
|
bitfld.long 0x00 26. "WUF26,Wakeup Flag For LLWU_P26" "0: LLWU_P26 input was not a wakeup source,1: LLWU_P26 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 25. "WUF25,Wakeup Flag For LLWU_P25" "0: LLWU_P25 input was not a wakeup source,1: LLWU_P25 input was a wakeup source"
|
|
bitfld.long 0x00 24. "WUF24,Wakeup Flag For LLWU_P24" "0: LLWU_P24 input was not a wakeup source,1: LLWU_P24 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 23. "WUF23,Wakeup Flag For LLWU_P23" "0: LLWU_P23 input was not a wakeup source,1: LLWU_P23 input was a wakeup source"
|
|
bitfld.long 0x00 22. "WUF22,Wakeup Flag For LLWU_P22" "0: LLWU_P22 input was not a wakeup source,1: LLWU_P22 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 21. "WUF21,Wakeup Flag For LLWU_P21" "0: LLWU_P21 input was not a wakeup source,1: LLWU_P21 input was a wakeup source"
|
|
bitfld.long 0x00 20. "WUF20,Wakeup Flag For LLWU_P20" "0: LLWU_P20 input was not a wakeup source,1: LLWU_P20 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 19. "WUF19,Wakeup Flag For LLWU_P19" "0: LLWU_P19 input was not a wakeup source,1: LLWU_P19 input was a wakeup source"
|
|
bitfld.long 0x00 18. "WUF18,Wakeup Flag For LLWU_P18" "0: LLWU_P18 input was not a wakeup source,1: LLWU_P18 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 17. "WUF17,Wakeup Flag For LLWU_P17" "0: LLWU_P17 input was not a wakeup source,1: LLWU_P17 input was a wakeup source"
|
|
bitfld.long 0x00 16. "WUF16,Wakeup Flag For LLWU_P16" "0: LLWU_P16 input was not a wakeup source,1: LLWU_P16 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 15. "WUF15,Wakeup Flag For LLWU_P15" "0: LLWU_P15 input was not a wakeup source,1: LLWU_P15 input was a wakeup source"
|
|
bitfld.long 0x00 14. "WUF14,Wakeup Flag For LLWU_P14" "0: LLWU_P14 input was not a wakeup source,1: LLWU_P14 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 13. "WUF13,Wakeup Flag For LLWU_P13" "0: LLWU_P13 input was not a wakeup source,1: LLWU_P13 input was a wakeup source"
|
|
bitfld.long 0x00 12. "WUF12,Wakeup Flag For LLWU_P12" "0: LLWU_P12 input was not a wakeup source,1: LLWU_P12 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 11. "WUF11,Wakeup Flag For LLWU_P11" "0: LLWU_P11 input was not a wakeup source,1: LLWU_P11 input was a wakeup source"
|
|
bitfld.long 0x00 10. "WUF10,Wakeup Flag For LLWU_P10" "0: LLWU_P10 input was not a wakeup source,1: LLWU_P10 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 9. "WUF9,Wakeup Flag For LLWU_P9" "0: LLWU_P9 input was not a wakeup source,1: LLWU_P9 input was a wakeup source"
|
|
bitfld.long 0x00 8. "WUF8,Wakeup Flag For LLWU_P8" "0: LLWU_P8 input was not a wakeup source,1: LLWU_P8 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 7. "WUF7,Wakeup Flag For LLWU_P7" "0: LLWU_P7 input was not a wakeup source,1: LLWU_P7 input was a wakeup source"
|
|
bitfld.long 0x00 6. "WUF6,Wakeup Flag For LLWU_P6" "0: LLWU_P6 input was not a wakeup source,1: LLWU_P6 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 5. "WUF5,Wakeup Flag For LLWU_P5" "0: LLWU_P5 input was not a wakeup source,1: LLWU_P5 input was a wakeup source"
|
|
bitfld.long 0x00 4. "WUF4,Wakeup Flag For LLWU_P4" "0: LLWU_P4 input was not a wakeup source,1: LLWU_P4 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 3. "WUF3,Wakeup Flag For LLWU_P3" "0: LLWU_P3 input was not a wakeup source,1: LLWU_P3 input was a wakeup source"
|
|
bitfld.long 0x00 2. "WUF2,Wakeup Flag For LLWU_P2" "0: LLWU_P2 input was not a wakeup source,1: LLWU_P2 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 1. "WUF1,Wakeup Flag For LLWU_P1" "0: LLWU_P1 input was not a wakeup source,1: LLWU_P1 input was a wakeup source"
|
|
bitfld.long 0x00 0. "WUF0,Wakeup Flag For LLWU_P0" "0: LLWU_P0 input was not a wakeup source,1: LLWU_P0 input was a wakeup source"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "MF,LLWU Module Interrupt Flag register"
|
|
bitfld.long 0x00 7. "MWUF7,Wakeup flag For module 7" "0: Module 7 input was not a wakeup source,1: Module 7 input was a wakeup source"
|
|
bitfld.long 0x00 6. "MWUF6,Wakeup flag For module 6" "0: Module 6 input was not a wakeup source,1: Module 6 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 5. "MWUF5,Wakeup flag For module 5" "0: Module 5 input was not a wakeup source,1: Module 5 input was a wakeup source"
|
|
bitfld.long 0x00 4. "MWUF4,Wakeup flag For module 4" "0: Module 4 input was not a wakeup source,1: Module 4 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 3. "MWUF3,Wakeup flag For module 3" "0: Module 3 input was not a wakeup source,1: Module 3 input was a wakeup source"
|
|
bitfld.long 0x00 2. "MWUF2,Wakeup flag For module 2" "0: Module 2 input was not a wakeup source,1: Module 2 input was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 1. "MWUF1,Wakeup flag For module 1" "0: Module 1 input was not a wakeup source,1: Module 1 input was a wakeup source"
|
|
bitfld.long 0x00 0. "MWUF0,Wakeup flag For module 0" "0: Module 0 input was not a wakeup source,1: Module 0 input was a wakeup source"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FILT,LLWU Pin Filter register"
|
|
bitfld.long 0x00 31. "FILTF4,Filter 4 Flag" "0: Pin Filter 1 was not a wakeup source,1: Pin Filter 1 was a wakeup source"
|
|
bitfld.long 0x00 29.--30. "FILTE4,Filter 4 Enable" "0: Filter disabled,1: Filter posedge detect enabled,2: Filter negedge detect enabled,3: Filter any edge detect enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--28. "FILTSEL4,Filter 4 Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Select LLWU_P31 for filter"
|
|
bitfld.long 0x00 23. "FILTF3,Filter 3 Flag" "0: Pin Filter 1 was not a wakeup source,1: Pin Filter 1 was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "FILTE3,Filter 3 Enable" "0: Filter disabled,1: Filter posedge detect enabled,2: Filter negedge detect enabled,3: Filter any edge detect enabled"
|
|
bitfld.long 0x00 16.--20. "FILTSEL3,Filter 3 Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Select LLWU_P31 for filter"
|
|
newline
|
|
bitfld.long 0x00 15. "FILTF2,Filter 2 Flag" "0: Pin Filter 1 was not a wakeup source,1: Pin Filter 1 was a wakeup source"
|
|
bitfld.long 0x00 13.--14. "FILTE2,Filter 2 Enable" "0: Filter disabled,1: Filter posedge detect enabled,2: Filter negedge detect enabled,3: Filter any edge detect enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FILTSEL2,Filter 2 Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Select LLWU_P31 for filter"
|
|
bitfld.long 0x00 7. "FILTF1,Filter 1 Flag" "0: Pin Filter 1 was not a wakeup source,1: Pin Filter 1 was a wakeup source"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "FILTE1,Filter 1 Enable" "0: Filter disabled,1: Filter posedge detect enabled,2: Filter negedge detect enabled,3: Filter any edge detect enabled"
|
|
bitfld.long 0x00 0.--4. "FILTSEL1,Filter 1 Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Select LLWU_P31 for filter"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (list 0. 1.) (list ad:0x40024000 ad:0x41023000)
|
|
tree "LLWU$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PINS,Pin Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MODULES,Module Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DMAS,DMA Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FILTERS,Filter Number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PE1,Pin Enable 1 register"
|
|
bitfld.long 0x00 30.--31. "WUPE15,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 28.--29. "WUPE14,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "WUPE13,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 24.--25. "WUPE12,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "WUPE11,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 20.--21. "WUPE10,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "WUPE9,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 16.--17. "WUPE8,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "WUPE7,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 12.--13. "WUPE6,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "WUPE5,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 8.--9. "WUPE4,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "WUPE3,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 4.--5. "WUPE2,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "WUPE1,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 0.--1. "WUPE0,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PE2,Pin Enable 2 register"
|
|
bitfld.long 0x00 30.--31. "WUPE31,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 28.--29. "WUPE30,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "WUPE29,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
rbitfld.long 0x00 24.--25. "Reserved28,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "Reserved27,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 20.--21. "WUPE26,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "WUPE25,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 16.--17. "WUPE24,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "WUPE23,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 12.--13. "WUPE22,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "WUPE21,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 8.--9. "WUPE20,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "WUPE19,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 4.--5. "WUPE18,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "WUPE17,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
bitfld.long 0x00 0.--1. "WUPE16,Wakeup pin enable for LLWU_Pn" "0: External input pin disabled as wakeup input,1: External input pin enabled with rising edge..,2: External input pin enabled with falling edge..,3: External input pin enabled with any change.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ME,Module Interrupt Enable register"
|
|
bitfld.long 0x00 7. "WUME7,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 6. "WUME6,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.long 0x00 5. "WUME5,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
rbitfld.long 0x00 4. "Reserved4,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
rbitfld.long 0x00 3. "Reserved3,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 2. "WUME2,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
newline
|
|
bitfld.long 0x00 1. "WUME1,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
bitfld.long 0x00 0. "WUME0,Wakeup module enable for module n" "0: Internal module flag not used as wakeup source,1: Internal module flag used as wakeup source"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DE,Module DMA/Trigger Enable register"
|
|
rbitfld.long 0x00 7. "Reserved7,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
bitfld.long 0x00 6. "WUDE6,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
newline
|
|
bitfld.long 0x00 5. "WUDE5,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
bitfld.long 0x00 4. "WUDE4,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
newline
|
|
rbitfld.long 0x00 3. "Reserved3,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
bitfld.long 0x00 2. "WUDE2,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
newline
|
|
bitfld.long 0x00 1. "WUDE1,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
bitfld.long 0x00 0. "WUDE0,DMA/Trigger wakeup enable for module n" "0: Internal module request not enabled as a..,1: Internal module request enabled as a.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PF,Pin Flag register"
|
|
eventfld.long 0x00 31. "WUF31,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 30. "WUF30,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 29. "WUF29,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
rbitfld.long 0x00 28. "Reserved28,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
rbitfld.long 0x00 27. "Reserved27,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 26. "WUF26,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 25. "WUF25,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 24. "WUF24,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 23. "WUF23,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 22. "WUF22,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 21. "WUF21,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 20. "WUF20,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 19. "WUF19,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 18. "WUF18,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 17. "WUF17,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 16. "WUF16,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 15. "WUF15,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 14. "WUF14,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 13. "WUF13,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 12. "WUF12,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 11. "WUF11,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 10. "WUF10,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
|
eventfld.long 0x00 9. "WUF9,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
eventfld.long 0x00 8. "WUF8,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
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eventfld.long 0x00 7. "WUF7,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
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eventfld.long 0x00 6. "WUF6,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
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|
newline
|
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eventfld.long 0x00 5. "WUF5,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
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|
eventfld.long 0x00 4. "WUF4,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
newline
|
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eventfld.long 0x00 3. "WUF3,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
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eventfld.long 0x00 2. "WUF2,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
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|
newline
|
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eventfld.long 0x00 1. "WUF1,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
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eventfld.long 0x00 0. "WUF0,Wakeup flag for LLWU_Pn" "0: LLWU_Pn input was not a wakeup source,1: LLWU_Pn input was a wakeup source"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FILT,Pin Filter register"
|
|
eventfld.long 0x00 15. "FILTF2,Filter 2 Flag" "0: Pin Filter 2 was not a wakeup source,1: Pin Filter 2 was a wakeup source"
|
|
bitfld.long 0x00 13.--14. "FILTE2,Filter 2 Enable" "0: Filter disabled,1: Filter posedge detect enabled when configured..,2: Filter negedge detect enabled when configured..,3: Filter any edge detect enabled when.."
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|
newline
|
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bitfld.long 0x00 8.--12. "FILTSEL2,Filter 2 Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Select LLWU_P31 for filter"
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eventfld.long 0x00 7. "FILTF1,Filter 1 Flag" "0: Pin Filter 1 was not a wakeup source,1: Pin Filter 1 was a wakeup source"
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newline
|
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bitfld.long 0x00 5.--6. "FILTE1,Filter 1 Enable" "0: Filter disabled,1: Filter posedge detect enabled when configured..,2: Filter negedge detect enabled when configured..,3: Filter any edge detect enabled when.."
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bitfld.long 0x00 0.--4. "FILTSEL1,Filter 1 Pin Select" "0: Select LLWU_P0 for filter,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Select LLWU_P31 for filter"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDC1,Pin DMA/Trigger Configuration 1 register"
|
|
bitfld.long 0x00 30.--31. "WUPDC15,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 28.--29. "WUPDC14,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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newline
|
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bitfld.long 0x00 26.--27. "WUPDC13,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 24.--25. "WUPDC12,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
|
bitfld.long 0x00 22.--23. "WUPDC11,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 20.--21. "WUPDC10,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
newline
|
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bitfld.long 0x00 18.--19. "WUPDC9,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 16.--17. "WUPDC8,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
|
bitfld.long 0x00 14.--15. "WUPDC7,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 12.--13. "WUPDC6,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
|
bitfld.long 0x00 10.--11. "WUPDC5,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
bitfld.long 0x00 8.--9. "WUPDC4,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
|
bitfld.long 0x00 6.--7. "WUPDC3,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 4.--5. "WUPDC2,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
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bitfld.long 0x00 2.--3. "WUPDC1,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
bitfld.long 0x00 0.--1. "WUPDC0,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDC2,Pin DMA/Trigger Configuration 2 register"
|
|
bitfld.long 0x00 30.--31. "WUPDC31,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 28.--29. "WUPDC30,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
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bitfld.long 0x00 26.--27. "WUPDC29,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
rbitfld.long 0x00 24.--25. "Reserved28,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
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rbitfld.long 0x00 22.--23. "Reserved27,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 20.--21. "WUPDC26,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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newline
|
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bitfld.long 0x00 18.--19. "WUPDC25,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 16.--17. "WUPDC24,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
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bitfld.long 0x00 14.--15. "WUPDC23,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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bitfld.long 0x00 12.--13. "WUPDC22,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
newline
|
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bitfld.long 0x00 10.--11. "WUPDC21,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
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|
bitfld.long 0x00 8.--9. "WUPDC20,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "WUPDC19,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
bitfld.long 0x00 4.--5. "WUPDC18,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "WUPDC17,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
bitfld.long 0x00 0.--1. "WUPDC16,Wakeup pin configuration for LLWU_Pn" "0: External input pin configured as interrupt,1: External input pin configured as DMA request,2: External input pin configured as trigger event,?..."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FDC,Pin Filter DMA/Trigger Configuration register"
|
|
bitfld.long 0x00 2.--3. "FILTC2,Filter configuration for FILT2" "0: Filter output configured as interrupt,1: Filter output configured as DMA request,2: Filter output configured as trigger event,?..."
|
|
bitfld.long 0x00 0.--1. "FILTC1,Filter configuration for FILT1" "0: Filter output configured as interrupt,1: Filter output configured as DMA request,2: Filter output configured as trigger event,?..."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PMC,Pin Mode Configuration register"
|
|
bitfld.long 0x00 31. "WUPMC31,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 30. "WUPMC30,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 29. "WUPMC29,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
rbitfld.long 0x00 28. "Reserved28,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
rbitfld.long 0x00 27. "Reserved27,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 26. "WUPMC26,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 25. "WUPMC25,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 24. "WUPMC24,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 23. "WUPMC23,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 22. "WUPMC22,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 21. "WUPMC21,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 20. "WUPMC20,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 19. "WUPMC19,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 18. "WUPMC18,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 17. "WUPMC17,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 16. "WUPMC16,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 15. "WUPMC15,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 14. "WUPMC14,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 13. "WUPMC13,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 12. "WUPMC12,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 11. "WUPMC11,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 10. "WUPMC10,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 9. "WUPMC9,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 8. "WUPMC8,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 7. "WUPMC7,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 6. "WUPMC6,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 5. "WUPMC5,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 4. "WUPMC4,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 3. "WUPMC3,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 2. "WUPMC2,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
newline
|
|
bitfld.long 0x00 1. "WUPMC1,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
bitfld.long 0x00 0. "WUPMC0,Wakeup pin mode for LLWU_Pn" "0: External input pin detection active only..,1: External input pin detection active during.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FMC,Pin Filter Mode Configuration register"
|
|
bitfld.long 0x00 1. "FILTM2,Filter Mode for FILT2" "0: External input pin filter detection active..,1: External input pin filter detection active.."
|
|
bitfld.long 0x00 0. "FILTM1,Filter Mode for FILT1" "0: External input pin filter detection active..,1: External input pin filter detection active.."
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPADC"
|
|
base ad:0x4004A000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
bitfld.long 0x00 10. "CALOFSI,Calibration Offset Function Implemented" "0: Offset calibration and offset trimming not..,1: Offset calibration and offset trimming.."
|
|
bitfld.long 0x00 9. "IADCKI,Internal LPADC Clock implemented" "0: Internal clock source not implemented,1: Internal clock source (and CFG[ADCKEN]).."
|
|
newline
|
|
bitfld.long 0x00 8. "VR1RNGI,Voltage Reference 1 Range Control Bit Implemented" "0: Range control not required,1: Range control required"
|
|
bitfld.long 0x00 4.--6. "CSW,Channel Scale Width" "0: Channel scaling not supported,1: Channel scaling supported,?,?,?,?,6: Channel scaling supported,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "MVI,Multi Vref Implemented" "0: Single voltage reference high (VREFH) input..,1: Multiple voltage reference high (VREFH).."
|
|
bitfld.long 0x00 1. "DIFFEN,Differential Supported" "0: Differential operation not supported,1: Differential operation supported"
|
|
newline
|
|
bitfld.long 0x00 0. "RES,Resolution" "0: Up to 13-bit differential/12-bit single ended..,1: Up to 16-bit differential/15-bit single ended.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CMD_NUM,Command Buffer Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CV_NUM,Compare Value Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "FIFOSIZE,Result FIFO Depth"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIG_NUM,Trigger Number"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL,LPADC Control Register"
|
|
bitfld.long 0x00 8. "RSTFIFO,Reset FIFO" "0: No effect,1: FIFO is reset"
|
|
bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: LPADC is enabled in Doze mode,1: LPADC is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: LPADC logic is not reset,1: LPADC logic is reset"
|
|
bitfld.long 0x00 0. "ADCEN,LPADC Enable" "0: LPADC is disabled,1: LPADC is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPADC Status Register"
|
|
rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..."
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|
rbitfld.long 0x00 16.--17. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) associated with Trigger 3.."
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newline
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eventfld.long 0x00 1. "FOF,Result FIFO Overflow Flag" "0: No result FIFO overflow has occurred since..,1: At least one result FIFO overflow has.."
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rbitfld.long 0x00 0. "RDY,Result FIFO Ready Flag" "0: Result FIFO data level not above watermark..,1: Result FIFO holding data above watermark level"
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group.long 0x18++0x03
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line.long 0x00 "IE,Interrupt Enable Register"
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bitfld.long 0x00 1. "FOFIE,Result FIFO Overflow Interrupt Enable" "0: FIFO overflow interrupts are not enabled,1: FIFO overflow interrupts are enabled"
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bitfld.long 0x00 0. "FWMIE,FIFO Watermark Interrupt Enable" "0: FIFO watermark interrupts are not enabled,1: FIFO watermark interrupts are enabled"
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group.long 0x1C++0x03
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line.long 0x00 "DE,DMA Enable Register"
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bitfld.long 0x00 0. "FWMDE,FIFO Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
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group.long 0x20++0x03
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line.long 0x00 "CFG,LPADC Configuration Register"
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bitfld.long 0x00 31. "ADCKEN,LPADC asynchronous clock enable" "0: LPADC internal clock is disabled,1: LPADC internal clock is enabled"
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bitfld.long 0x00 29. "VREF1RNG,Enable support for low voltage reference on Option 1 Reference" "0: Configuration required when Voltage Reference..,1: Configuration required when Voltage Reference.."
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newline
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bitfld.long 0x00 28. "PWREN,LPADC Analog Pre-Enable" "0: LPADC analog circuits are only enabled while..,1: LPADC analog circuits are pre-enabled and.."
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hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay"
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newline
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bitfld.long 0x00 15. "CALOFS,Configure for offset calibration function" "0: Calibration function disabled,1: Configure for offset calibration function"
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bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..."
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newline
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bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Level 1 (Lowest power setting),1: PWRSEL_1,2: PWRSEL_2,3: Level 4 (Highest power setting)"
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bitfld.long 0x00 0. "TPRICTRL,LPADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received.."
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group.long 0x24++0x03
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line.long 0x00 "PAUSE,LPADC Pause Register"
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bitfld.long 0x00 31. "PAUSEEN,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled"
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hexmask.long.word 0x00 0.--8. 1. "PAUSEDLY,Pause Delay"
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group.long 0x30++0x03
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line.long 0x00 "FCTRL,LPADC FIFO Control Register"
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bitfld.long 0x00 16.--19. "FWMARK,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 0.--4. "FCOUNT,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x34++0x03
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line.long 0x00 "SWTRIG,Software Trigger Register"
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bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated"
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bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated"
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newline
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bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated"
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bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated"
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group.long 0x40++0x03
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line.long 0x00 "OFSTRIM,LPADC Offset Trim Register"
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bitfld.long 0x00 0.--5. "OFSTRIM,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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repeat 4. (increment 0 1) (increment 0 0x4)
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group.long ($2+0xC0)++0x03
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line.long 0x00 "TCTRL[$1],Trigger Control Register $1"
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bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed"
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bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--9. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to lowest priority Level 4"
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bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
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repeat.end
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group.long 0x100++0x03
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line.long 0x00 "CMDL1,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x104++0x03
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line.long 0x00 "CMDH1,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
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group.long 0x108++0x03
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line.long 0x00 "CMDL2,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x10C++0x03
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line.long 0x00 "CMDH2,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
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group.long 0x110++0x03
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line.long 0x00 "CMDL3,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x114++0x03
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line.long 0x00 "CMDH3,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
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group.long 0x118++0x03
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line.long 0x00 "CMDL4,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x11C++0x03
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line.long 0x00 "CMDH4,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
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group.long 0x120++0x03
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line.long 0x00 "CMDL5,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x124++0x03
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line.long 0x00 "CMDH5,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
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group.long 0x128++0x03
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line.long 0x00 "CMDL6,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x12C++0x03
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line.long 0x00 "CMDH6,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
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group.long 0x130++0x03
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line.long 0x00 "CMDL7,LPADC Command Low Buffer Register"
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bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
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group.long 0x134++0x03
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line.long 0x00 "CMDH7,LPADC Command High Buffer Register"
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bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CMDL8,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CMDH8,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
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|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CMDL9,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CMDH9,LPADC Command High Buffer Register"
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|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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|
newline
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
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|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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|
newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CMDL10,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CMDH10,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CMDL11,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CMDH11,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CMDL12,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CMDH12,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
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|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CMDL13,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CMDH13,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CMDL14,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CMDH14,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CMDL15,LPADC Command Low Buffer Register"
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: The associated A-side channel is converted,1: The associated B-side channel is converted"
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B,1: Select CH1A or CH1B,2: Select CH2A or CH2B,3: Select CH3A or CH3B,4: Select corresponding channel CHnA or CHnB,5: Select corresponding channel CHnA or CHnB,6: Select corresponding channel CHnA or CHnB,7: Select corresponding channel CHnA or CHnB,8: Select corresponding channel CHnA or CHnB,9: Select corresponding channel CHnA or CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B,31: Select CH31A or CH31B"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CMDH15,LPADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "CV$1,Compare Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "CVH,Compare Value High"
|
|
hexmask.long.word 0x00 0.--15. 1. "CVL,Compare Value Low"
|
|
repeat.end
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "RESFIFO,LPADC Data Result FIFO Register"
|
|
bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid"
|
|
bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command"
|
|
bitfld.long 0x00 16.--17. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Trigger source 2 initiated this conversion,3: Trigger source 3 initiated this conversion"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "D,Data result"
|
|
tree.end
|
|
tree "LPCMP"
|
|
repeat 2. (list 0. 1.) (list ad:0x4004B000 ad:0x41038000)
|
|
tree "LPCMP$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 0.--3. "DAC_RES,DAC resolution" "0: DAC_RES_0,1: DAC_RES_1,2: DAC_RES_2,3: 10 bit DAC,4: 12 bit DAC,5: 14 bit DAC,6: 16 bit DAC,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CCR0,Comparator Control Register 0"
|
|
bitfld.long 0x00 1. "CMP_STOP_EN,Comparator Module STOP Mode Enable" "0: Comparator is disabled in STOP modes..,1: Comparator is enabled in STOP mode if CMP_EN.."
|
|
bitfld.long 0x00 0. "CMP_EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CCR1,Comparator Control Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FILT_PER,Filter Sample Period"
|
|
bitfld.long 0x00 16.--18. "FILT_CNT,Filter Sample Count" "0: Filter is disabled,1: 1 consecutive sample must agree (comparator..,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
newline
|
|
bitfld.long 0x00 5. "COUT_PEN,Comparator Output Pin Enable" "0: When COUT_PEN is 0 the comparator output..,1: When COUT_PEN is 1 and if the software has.."
|
|
bitfld.long 0x00 4. "COUT_SEL,Comparator Output Select" "0: Set CMPO to equal COUT (filtered comparator..,1: Set CMPO to equal COUTA (unfiltered.."
|
|
newline
|
|
bitfld.long 0x00 3. "COUT_INV,Comparator invert" "0: Does not invert the comparator output,1: Inverts the comparator output"
|
|
bitfld.long 0x00 2. "DMA_EN,DMA Enable" "0: DMA is disabled,1: DMA is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SAMPLE_EN,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
|
|
bitfld.long 0x00 0. "WINDOW_EN,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CCR2,Comparator Control Register 2"
|
|
bitfld.long 0x00 20.--22. "MSEL,Minus Input MUX Control" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Internal DAC output"
|
|
bitfld.long 0x00 16.--18. "PSEL,Plus Input MUX Control" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Internal DAC output"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "HYSTCTR,Comparator hard block hysteresis control" "0: The hard block output has level 0 hysteresis..,1: The hard block output has level 1 hysteresis..,2: The hard block output has level 2 hysteresis..,3: The hard block output has level 3 hysteresis.."
|
|
bitfld.long 0x00 1. "CMP_NPMD,CMP Nano Power Mode Select" "0: Nano Power Comparator is not enabled (mode is..,1: Nano Power Comparator is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "CMP_HPMD,CMP High Power Mode Select" "0: Low speed comparison mode is selected.(when..,1: High speed comparison mode is selected.(when.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DCR,DAC Control Register"
|
|
bitfld.long 0x00 16.--21. "DAC_DATA,DAC Output Voltage Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. "VRSEL,Supply Voltage Reference Source Select" "0: vrefh_int is selected as resistor ladder..,1: vrefh_ext is selected as resistor ladder.."
|
|
newline
|
|
bitfld.long 0x00 1. "DAC_HPMD,DAC High Power Mode Select" "0: DAC high power mode is not enabled,1: DAC high power mode is enabled"
|
|
bitfld.long 0x00 0. "DAC_EN,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "CFF_IE,Comparator Flag Falling Interrupt Enable" "0: CFF interrupt is disabled,1: CFF interrupt is enabled"
|
|
bitfld.long 0x00 0. "CFR_IE,Comparator Flag Rising Interrupt Enable" "0: CFR interrupt is disabled,1: CFR interrupt is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CSR,Comparator Status Register"
|
|
rbitfld.long 0x00 8. "COUT,Analog Comparator Output" "0,1"
|
|
eventfld.long 0x00 1. "CFF,Analog Comparator Flag Falling" "0: A falling edge has not been detected on COUT,1: A falling edge on COUT has occurred"
|
|
newline
|
|
eventfld.long 0x00 0. "CFR,Analog Comparator Flag Rising" "0: A rising edge has not been detected on COUT,1: A rising edge on COUT has occurred"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LPDAC"
|
|
base ad:0x4004C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version Identifier Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor version number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 0.--2. "FIFOSZ,FIFO size" "?,1: FIFO depth is 4,2: FIFO depth is 8,3: FIFO depth is 16,4: FIFO depth is 32,5: FIFO depth is 64,6: FIFO depth is 128,7: FIFO depth is 256"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DATA,DAC Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATA,In FIFO mode or swing back mode this is the FIFO data entry"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GCR,DAC Global Control Register"
|
|
bitfld.long 0x00 5. "TRGSEL,DAC Trigger Select" "0: The DAC hardware trigger is selected,1: The DAC software trigger is selected"
|
|
bitfld.long 0x00 4. "SWMD,Swing Back Mode" "0: Swing back mode disable,1: Swing back mode enable"
|
|
newline
|
|
bitfld.long 0x00 3. "FIFOEN,FIFO Enable" "0: FIFO mode is disabled and buffer mode is..,1: FIFO mode is enabled"
|
|
bitfld.long 0x00 2. "LPEN,Low Power Enable" "0: High-Power mode,1: Low-Power mode"
|
|
newline
|
|
bitfld.long 0x00 1. "DACRFS,DAC Reference Select" "0: The DAC selects VREFH_INT as the reference..,1: The DAC selects VREFH_EXT as the reference.."
|
|
bitfld.long 0x00 0. "DACEN,DAC Enable" "0: The DAC system is disabled,1: The DAC system is enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FCR,DAC FIFO Control Register"
|
|
bitfld.long 0x00 0.--3. "WML,Watermark Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FPR,DAC FIFO Pointer Register"
|
|
bitfld.long 0x00 16.--19. "FIFO_WPT,FIFO Write Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "FIFO_RPT,FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
eventfld.long 0x00 7. "UF,FIFO Underflow Flag" "0: No underflow has occurred since the last time..,1: At least one trigger underflow has occurred.."
|
|
eventfld.long 0x00 6. "OF,FIFO Overflow Flag" "0: No overflow has occurred since the last time..,1: At least one FIFO overflow has occurred since.."
|
|
newline
|
|
eventfld.long 0x00 3. "SWBK,Swing Back One Cycle Complete Flag" "0: No swing back cycle has completed since the..,1: At least one swing back cycle has occurred.."
|
|
rbitfld.long 0x00 2. "WM,FIFO Watermark Status Flag" "0: Data in FIFO is more than watermark level,1: Data in FIFO is less than or equal to.."
|
|
newline
|
|
rbitfld.long 0x00 1. "EMPTY,FIFO Empty Flag" "0: FIFO is not empty,1: FIFO is empty"
|
|
rbitfld.long 0x00 0. "FULL,FIFO Full Flag" "0: FIFO is not full,1: FIFO is full"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IER,DAC Interrupt Enable Register"
|
|
bitfld.long 0x00 7. "UF_IE,FIFO Underflow Interrupt Enable" "0: Underflow interrupt is disabled,1: Underflow interrupt is enabled"
|
|
bitfld.long 0x00 6. "OF_IE,FIFO Overflow Interrupt Enable" "0: Overflow interrupt is disabled,1: Overflow interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "SWBK_IE,Swing back One Cycle Complete Interrupt Enable" "0: Swing back one time complete interrupt is..,1: Swing back one time complete interrupt is.."
|
|
bitfld.long 0x00 2. "WM_IE,FIFO Watermark Interrupt Enable" "0: Watermark interrupt is disabled,1: Watermark interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "EMPTY_IE,FIFO Empty Interrupt Enable" "0: FIFO Empty interrupt is disabled,1: FIFO Empty interrupt is enabled"
|
|
bitfld.long 0x00 0. "FULL_IE,FIFO Full Interrupt Enable" "0: FIFO Full interrupt is disabled,1: FIFO Full interrupt is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DER,DAC DMA Enable Register"
|
|
bitfld.long 0x00 2. "WM_DMAEN,FIFO Watermark DMA Enable" "0: Watermark DMA request is disabled,1: Watermark DMA request is enabled"
|
|
bitfld.long 0x00 1. "EMPTY_DMAEN,FIFO Empty DMA Enable" "0: FIFO Empty DMA request is disabled,1: FIFO Empty DMA request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RCR,DAC Reset Control Register"
|
|
bitfld.long 0x00 1. "FIFORST,FIFO Reset" "0: FIFORST_0,1: FIFO reset"
|
|
bitfld.long 0x00 0. "SWRST,Software Reset" "0: No effect,1: Software reset"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCR,DAC Trigger Control Register"
|
|
bitfld.long 0x00 0. "SWTRG,Software Trigger" "0: The DAC soft trigger is not valid,1: The DAC soft trigger is valid"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPI2C (The LPI2C Memory Map/Register Definition can be found here.)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPI2C0"
|
|
base ad:0x400C0000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPI2C_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,When set the received NACK field is ignored and assumed to be ACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (list 0. 1.) (list ad:0x4003A000 ad:0x4003B000)
|
|
tree "LPI2C$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPI2C_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,When set the received NACK field is ignored and assumed to be ACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPI2C1"
|
|
base ad:0x400C1000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPI2C_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,When set the received NACK field is ignored and assumed to be ACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPI2C2"
|
|
base ad:0x4003C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPI2C_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,When set the received NACK field is ignored and assumed to be ACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPI2C2"
|
|
base ad:0x40042000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPI2C_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,When set the received NACK field is ignored and assumed to be ACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPI2C3"
|
|
base ad:0x4102E000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPI2C_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,When set the received NACK field is ignored and assumed to be ACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPIT"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPIT0"
|
|
base ad:0x40030000
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXT_TRIG,Number of External Trigger Inputs"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL,Number of Timer Channels"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. "DBG_EN,Debug Enable Bit" "0: Stop timer channels in Debug mode,1: Allow timer channels to continue to run in.."
|
|
bitfld.long 0x00 2. "DOZE_EN,DOZE Mode Enable Bit" "0: Stop timer channels in DOZE mode,1: Allow timer channels to continue to run in.."
|
|
newline
|
|
bitfld.long 0x00 1. "SW_RST,Software Reset Bit" "0: Timer channels and registers are not reset,1: Reset timer channels and registers"
|
|
bitfld.long 0x00 0. "M_CEN,Module Clock Enable" "0: Disable peripheral clock to timers,1: Enable peripheral clock to timers"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MSR,Module Status Register"
|
|
eventfld.long 0x00 3. "TIF3,Channel 3 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 2. "TIF2,Channel 2 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
newline
|
|
eventfld.long 0x00 1. "TIF1,Channel 1 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 0. "TIF0,Channel 0 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "TIE3,Channel 3 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "TIE2,Channel 2 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TIE1,Channel 1 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TIE0,Channel 0 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETTEN,Set Timer Enable Register"
|
|
bitfld.long 0x00 3. "SET_T_EN_3,Set Timer 3 Enable" "0: SET_T_EN_3_0,1: Enables Timer Channel 3"
|
|
bitfld.long 0x00 2. "SET_T_EN_2,Set Timer 2 Enable" "0: SET_T_EN_2_0,1: Enables Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "SET_T_EN_1,Set Timer 1 Enable" "0: SET_T_EN_1_0,1: Enables Timer Channel 1"
|
|
bitfld.long 0x00 0. "SET_T_EN_0,Set Timer 0 Enable" "0: SET_T_EN_0_0,1: Enables Timer Channel 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLRTEN,Clear Timer Enable Register"
|
|
bitfld.long 0x00 3. "CLR_T_EN_3,Clear Timer 3 Enable" "0: CLR_T_EN_3_0,1: Clear the Timer Enable bit (TCTRL3[T_EN]) for.."
|
|
bitfld.long 0x00 2. "CLR_T_EN_2,Clear Timer 2 Enable" "0: CLR_T_EN_2_0,1: Clear the Timer Enable bit (TCTRL2[T_EN]) for.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLR_T_EN_1,Clear Timer 1 Enable" "0: CLR_T_EN_1_0,1: Clear the Timer Enable bit (TCTRL1[T_EN]) for.."
|
|
bitfld.long 0x00 0. "CLR_T_EN_0,Clear Timer 0 Enable" "0: CLR_T_EN_0_0,1: Clear the Timer Enable bit (TCTRL0[T_EN]) for.."
|
|
endif
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TVAL,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "CVAL,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "TCTRL,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0: Timer channel 0 - 3 trigger source is selected,1: Timer channel 0 - 3 trigger source is selected,2: Timer channel 0 - 3 trigger source is selected,3: Timer channel 0 - 3 trigger source is selected,?..."
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Selects external triggers,1: Selects internal triggers"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on the selected trigger,1: Timer will reload on the selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when a rising edge.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "LPIT0"
|
|
base ad:0x40030000
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXT_TRIG,Number of External Trigger Inputs"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL,Number of Timer Channels"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. "DBG_EN,Debug Enable Bit" "0: Stop timer channels in Debug mode,1: Allow timer channels to continue to run in.."
|
|
bitfld.long 0x00 2. "DOZE_EN,DOZE Mode Enable Bit" "0: Stop timer channels in DOZE mode,1: Allow timer channels to continue to run in.."
|
|
newline
|
|
bitfld.long 0x00 1. "SW_RST,Software Reset Bit" "0: Timer channels and registers are not reset,1: Reset timer channels and registers"
|
|
bitfld.long 0x00 0. "M_CEN,Module Clock Enable" "0: Disable peripheral clock to timers,1: Enable peripheral clock to timers"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MSR,Module Status Register"
|
|
eventfld.long 0x00 3. "TIF3,Channel 3 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 2. "TIF2,Channel 2 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
newline
|
|
eventfld.long 0x00 1. "TIF1,Channel 1 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 0. "TIF0,Channel 0 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "TIE3,Channel 3 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "TIE2,Channel 2 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TIE1,Channel 1 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TIE0,Channel 0 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETTEN,Set Timer Enable Register"
|
|
bitfld.long 0x00 3. "SET_T_EN_3,Set Timer 3 Enable" "0: SET_T_EN_3_0,1: Enables Timer Channel 3"
|
|
bitfld.long 0x00 2. "SET_T_EN_2,Set Timer 2 Enable" "0: SET_T_EN_2_0,1: Enables Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "SET_T_EN_1,Set Timer 1 Enable" "0: SET_T_EN_1_0,1: Enables Timer Channel 1"
|
|
bitfld.long 0x00 0. "SET_T_EN_0,Set Timer 0 Enable" "0: SET_T_EN_0_0,1: Enables Timer Channel 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLRTEN,Clear Timer Enable Register"
|
|
bitfld.long 0x00 3. "CLR_T_EN_3,Clear Timer 3 Enable" "0: CLR_T_EN_3_0,1: Clear the Timer Enable bit (TCTRL3[T_EN]) for.."
|
|
bitfld.long 0x00 2. "CLR_T_EN_2,Clear Timer 2 Enable" "0: CLR_T_EN_2_0,1: Clear the Timer Enable bit (TCTRL2[T_EN]) for.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLR_T_EN_1,Clear Timer 1 Enable" "0: CLR_T_EN_1_0,1: Clear the Timer Enable bit (TCTRL1[T_EN]) for.."
|
|
bitfld.long 0x00 0. "CLR_T_EN_0,Clear Timer 0 Enable" "0: CLR_T_EN_0_0,1: Clear the Timer Enable bit (TCTRL0[T_EN]) for.."
|
|
endif
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TVAL,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "CVAL,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "TCTRL,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0: Timer channel 0 - 3 trigger source is selected,1: Timer channel 0 - 3 trigger source is selected,2: Timer channel 0 - 3 trigger source is selected,3: Timer channel 0 - 3 trigger source is selected,?..."
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Selects external triggers,1: Selects internal triggers"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on the selected trigger,1: Timer will reload on the selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when a rising edge.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPIT1"
|
|
base ad:0x4102A000
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXT_TRIG,Number of External Trigger Inputs"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL,Number of Timer Channels"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. "DBG_EN,Debug Enable Bit" "0: Stop timer channels in Debug mode,1: Allow timer channels to continue to run in.."
|
|
bitfld.long 0x00 2. "DOZE_EN,DOZE Mode Enable Bit" "0: Stop timer channels in DOZE mode,1: Allow timer channels to continue to run in.."
|
|
newline
|
|
bitfld.long 0x00 1. "SW_RST,Software Reset Bit" "0: Timer channels and registers are not reset,1: Reset timer channels and registers"
|
|
bitfld.long 0x00 0. "M_CEN,Module Clock Enable" "0: Disable peripheral clock to timers,1: Enable peripheral clock to timers"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MSR,Module Status Register"
|
|
eventfld.long 0x00 3. "TIF3,Channel 3 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 2. "TIF2,Channel 2 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
newline
|
|
eventfld.long 0x00 1. "TIF1,Channel 1 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 0. "TIF0,Channel 0 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "TIE3,Channel 3 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "TIE2,Channel 2 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TIE1,Channel 1 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TIE0,Channel 0 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETTEN,Set Timer Enable Register"
|
|
bitfld.long 0x00 3. "SET_T_EN_3,Set Timer 3 Enable" "0: SET_T_EN_3_0,1: Enables Timer Channel 3"
|
|
bitfld.long 0x00 2. "SET_T_EN_2,Set Timer 2 Enable" "0: SET_T_EN_2_0,1: Enables Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "SET_T_EN_1,Set Timer 1 Enable" "0: SET_T_EN_1_0,1: Enables Timer Channel 1"
|
|
bitfld.long 0x00 0. "SET_T_EN_0,Set Timer 0 Enable" "0: SET_T_EN_0_0,1: Enables Timer Channel 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLRTEN,Clear Timer Enable Register"
|
|
bitfld.long 0x00 3. "CLR_T_EN_3,Clear Timer 3 Enable" "0: CLR_T_EN_3_0,1: Clear the Timer Enable bit (TCTRL3[T_EN]) for.."
|
|
bitfld.long 0x00 2. "CLR_T_EN_2,Clear Timer 2 Enable" "0: CLR_T_EN_2_0,1: Clear the Timer Enable bit (TCTRL2[T_EN]) for.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLR_T_EN_1,Clear Timer 1 Enable" "0: CLR_T_EN_1_0,1: Clear the Timer Enable bit (TCTRL1[T_EN]) for.."
|
|
bitfld.long 0x00 0. "CLR_T_EN_0,Clear Timer 0 Enable" "0: CLR_T_EN_0_0,1: Clear the Timer Enable bit (TCTRL0[T_EN]) for.."
|
|
endif
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TVAL,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "CVAL,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "TCTRL,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0: Timer channel 0 - 3 trigger source is selected,1: Timer channel 0 - 3 trigger source is selected,2: Timer channel 0 - 3 trigger source is selected,3: Timer channel 0 - 3 trigger source is selected,?..."
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Selects external triggers,1: Selects internal triggers"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on the selected trigger,1: Timer will reload on the selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when a rising edge.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPSPI (The LPSPI Memory Map/Register Definition can be found here.)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPSPI0"
|
|
base ad:0x400BC000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (list 0. 1.) (list ad:0x4003F000 ad:0x40040000)
|
|
tree "LPSPI$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPSPI1"
|
|
base ad:0x400BD000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPSPI2"
|
|
base ad:0x40041000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPSPI2"
|
|
base ad:0x4003E000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPSPI3"
|
|
base ad:0x41035000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive FIFO Watermark"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit FIFO Watermark"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "LPTMR (Low Power Timer)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPTMR0"
|
|
base ad:0x40034000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA Request Enable" "0: Timer DMA Request disabled,1: Timer DMA Request enabled"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
newline
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
sif cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
newline
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. "PRESCALE,Prescale Value" "0: Prescaler divides the prescaler clock by 2..,1: Prescaler divides the prescaler clock by 4..,2: Prescaler divides the prescaler clock by 8..,3: Prescaler divides the prescaler clock by 16..,4: Prescaler divides the prescaler clock by 32..,5: Prescaler divides the prescaler clock by 64..,6: Prescaler divides the prescaler clock by 128..,7: Prescaler divides the prescaler clock by 256..,8: Prescaler divides the prescaler clock by 512..,9: Prescaler divides the prescaler clock by 1024..,10: Prescaler divides the prescaler clock by..,11: Prescaler divides the prescaler clock by..,12: Prescaler divides the prescaler clock by..,13: Prescaler divides the prescaler clock by 16..,14: Prescaler divides the prescaler clock by 32..,15: Prescaler divides the prescaler clock by 65.."
|
|
bitfld.long 0x00 2. "PBYP,Prescaler Bypass" "0: Prescaler/glitch filter is enabled,1: Prescaler/glitch filter is bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PCS,Prescaler Clock Select" "0: Prescaler/glitch filter clock 0 selected,1: Prescaler/glitch filter clock 1 selected,2: Prescaler/glitch filter clock 2 selected,3: Prescaler/glitch filter clock 3 selected"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE,Compare Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Counter Value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPTMR0"
|
|
base ad:0x40032000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA Request Enable" "0: Timer DMA Request disabled,1: Timer DMA Request enabled"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
newline
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
sif cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
newline
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. "PRESCALE,Prescale Value" "0: Prescaler divides the prescaler clock by 2..,1: Prescaler divides the prescaler clock by 4..,2: Prescaler divides the prescaler clock by 8..,3: Prescaler divides the prescaler clock by 16..,4: Prescaler divides the prescaler clock by 32..,5: Prescaler divides the prescaler clock by 64..,6: Prescaler divides the prescaler clock by 128..,7: Prescaler divides the prescaler clock by 256..,8: Prescaler divides the prescaler clock by 512..,9: Prescaler divides the prescaler clock by 1024..,10: Prescaler divides the prescaler clock by..,11: Prescaler divides the prescaler clock by..,12: Prescaler divides the prescaler clock by..,13: Prescaler divides the prescaler clock by 16..,14: Prescaler divides the prescaler clock by 32..,15: Prescaler divides the prescaler clock by 65.."
|
|
bitfld.long 0x00 2. "PBYP,Prescaler Bypass" "0: Prescaler/glitch filter is enabled,1: Prescaler/glitch filter is bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PCS,Prescaler Clock Select" "0: Prescaler/glitch filter clock 0 selected,1: Prescaler/glitch filter clock 1 selected,2: Prescaler/glitch filter clock 2 selected,3: Prescaler/glitch filter clock 3 selected"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE,Compare Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Counter Value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "LPTMR0"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA Request Enable" "0: Timer DMA Request disabled,1: Timer DMA Request enabled"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
newline
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
sif cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
newline
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. "PRESCALE,Prescale Value" "0: Prescaler divides the prescaler clock by 2..,1: Prescaler divides the prescaler clock by 4..,2: Prescaler divides the prescaler clock by 8..,3: Prescaler divides the prescaler clock by 16..,4: Prescaler divides the prescaler clock by 32..,5: Prescaler divides the prescaler clock by 64..,6: Prescaler divides the prescaler clock by 128..,7: Prescaler divides the prescaler clock by 256..,8: Prescaler divides the prescaler clock by 512..,9: Prescaler divides the prescaler clock by 1024..,10: Prescaler divides the prescaler clock by..,11: Prescaler divides the prescaler clock by..,12: Prescaler divides the prescaler clock by..,13: Prescaler divides the prescaler clock by 16..,14: Prescaler divides the prescaler clock by 32..,15: Prescaler divides the prescaler clock by 65.."
|
|
bitfld.long 0x00 2. "PBYP,Prescaler Bypass" "0: Prescaler/glitch filter is enabled,1: Prescaler/glitch filter is bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PCS,Prescaler Clock Select" "0: Prescaler/glitch filter clock 0 selected,1: Prescaler/glitch filter clock 1 selected,2: Prescaler/glitch filter clock 2 selected,3: Prescaler/glitch filter clock 3 selected"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE,Compare Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Counter Value"
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPTMR1"
|
|
base ad:0x400B5000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA Request Enable" "0: Timer DMA Request disabled,1: Timer DMA Request enabled"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
newline
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. "PRESCALE,Prescale Value" "0: Prescaler divides the prescaler clock by 2..,1: Prescaler divides the prescaler clock by 4..,2: Prescaler divides the prescaler clock by 8..,3: Prescaler divides the prescaler clock by 16..,4: Prescaler divides the prescaler clock by 32..,5: Prescaler divides the prescaler clock by 64..,6: Prescaler divides the prescaler clock by 128..,7: Prescaler divides the prescaler clock by 256..,8: Prescaler divides the prescaler clock by 512..,9: Prescaler divides the prescaler clock by 1024..,10: Prescaler divides the prescaler clock by..,11: Prescaler divides the prescaler clock by..,12: Prescaler divides the prescaler clock by..,13: Prescaler divides the prescaler clock by 16..,14: Prescaler divides the prescaler clock by 32..,15: Prescaler divides the prescaler clock by 65.."
|
|
bitfld.long 0x00 2. "PBYP,Prescaler Bypass" "0: Prescaler/glitch filter is enabled,1: Prescaler/glitch filter is bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PCS,Prescaler Clock Select" "0: Prescaler/glitch filter clock 0 selected,1: Prescaler/glitch filter clock 1 selected,2: Prescaler/glitch filter clock 2 selected,3: Prescaler/glitch filter clock 3 selected"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE,Compare Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Counter Value"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (list 1. 2.) (list ad:0x40033000 ad:0x4102B000)
|
|
tree "LPTMR$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA Request Enable" "0: Timer DMA Request disabled,1: Timer DMA Request enabled"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
newline
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
sif cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
newline
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. "PRESCALE,Prescale Value" "0: Prescaler divides the prescaler clock by 2..,1: Prescaler divides the prescaler clock by 4..,2: Prescaler divides the prescaler clock by 8..,3: Prescaler divides the prescaler clock by 16..,4: Prescaler divides the prescaler clock by 32..,5: Prescaler divides the prescaler clock by 64..,6: Prescaler divides the prescaler clock by 128..,7: Prescaler divides the prescaler clock by 256..,8: Prescaler divides the prescaler clock by 512..,9: Prescaler divides the prescaler clock by 1024..,10: Prescaler divides the prescaler clock by..,11: Prescaler divides the prescaler clock by..,12: Prescaler divides the prescaler clock by..,13: Prescaler divides the prescaler clock by 16..,14: Prescaler divides the prescaler clock by 32..,15: Prescaler divides the prescaler clock by 65.."
|
|
bitfld.long 0x00 2. "PBYP,Prescaler Bypass" "0: Prescaler/glitch filter is enabled,1: Prescaler/glitch filter is bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PCS,Prescaler Clock Select" "0: Prescaler/glitch filter clock 0 selected,1: Prescaler/glitch filter clock 1 selected,2: Prescaler/glitch filter clock 2 selected,3: Prescaler/glitch filter clock 3 selected"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE,Compare Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Counter Value"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPTPM (TPM)"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x40035000 ad:0x40036000 ad:0x40037000 ad:0x4102D000)
|
|
tree "TPM$1"
|
|
base $2
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WIDTH,Counter Width"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRIG,Trigger Count"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHAN,Channel Count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
bitfld.long 0x00 0. "NOUPDATE,No Update" "0: Internal double buffered registers update as..,1: Internal double buffered registers do not.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC,Status and Control"
|
|
bitfld.long 0x00 8. "DMA,DMA Enable" "0: Disables DMA transfers,1: Enables DMA transfers"
|
|
eventfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: TPM counter operates in up counting mode,1: TPM counter operates in up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CMOD,Clock Mode Selection" "0: TPM counter is disabled,1: TPM counter increments on every TPM counter..,2: TPM counter increments on rising edge of..,3: TPM counter increments on rising edge of the.."
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,Modulo value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STATUS,Capture and Compare Status"
|
|
eventfld.long 0x00 8. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
eventfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. "COMSWAP2,Combine Channels 4 and 5 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels 4 and 5" "0: Channels 4 and 5 are independent,1: Channels 4 and 5 are combined"
|
|
newline
|
|
bitfld.long 0x00 9. "COMSWAP1,Combine Channels 2 and 3 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels 2 and 3" "0: Channels 2 and 3 are independent,1: Channels 2 and 3 are combined"
|
|
newline
|
|
bitfld.long 0x00 1. "COMSWAP0,Combine Channel 0 and 1 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels 0 and 1" "0: Channels 0 and 1 are independent,1: Channels 0 and 1 are combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. "TRIG5,Channel 5 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 4. "TRIG4,Channel 4 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3,Channel 3 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 2. "TRIG2,Channel 2 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1,Channel 1 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 0. "TRIG0,Channel 0 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "POL,Channel Polarity"
|
|
bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. "CH5FVAL,Channel 5 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH4FVAL,Channel 4 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase encoding mode,1: Count and direction encoding mode"
|
|
rbitfld.long 0x00 2. "QUADIR,Counter Direction in Quadrature Decode Mode" "0: Counter direction is decreasing (counter..,1: Counter direction is increasing (counter.."
|
|
newline
|
|
rbitfld.long 0x00 1. "TOFDIR,TOFDIR" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
|
|
bitfld.long 0x00 0. "QUADEN,QUADEN" "0: Quadrature decoder mode is disabled,1: Quadrature decoder mode is enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. "TRGSEL,Trigger Select" "?,1: Channel 0 pin input capture,2: Channel 1 pin input capture,3: Channel 0 or Channel 1 pin input capture"
|
|
bitfld.long 0x00 23. "TRGSRC,Trigger Source" "0: Trigger source selected by TRGSEL is external,1: Trigger source selected by TRGSEL is internal.."
|
|
newline
|
|
bitfld.long 0x00 22. "TRGPOL,Trigger Polarity" "0: Trigger is active high,1: Trigger is active low"
|
|
bitfld.long 0x00 19. "CPOT,Counter Pause On Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CROT,Counter Reload On Trigger" "0: Counter is not reloaded due to a rising edge..,1: Counter is reloaded when a rising edge is.."
|
|
bitfld.long 0x00 17. "CSOO,Counter Stop On Overflow" "0: TPM counter continues incrementing or..,1: TPM counter stops incrementing or.."
|
|
newline
|
|
bitfld.long 0x00 16. "CSOT,Counter Start on Trigger" "0: TPM counter starts to increment immediately..,1: TPM counter only starts to increment when it.."
|
|
bitfld.long 0x00 9. "GTBEEN,Global time base enable" "0: All channels use the internally generated TPM..,1: All channels use an externally generated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GTBSYNC,Global Time Base Synchronization" "0: Global timebase synchronization disabled,1: Global timebase synchronization enabled"
|
|
bitfld.long 0x00 6.--7. "DBGMODE,Debug Mode" "0: TPM counter is paused and does not increment..,?,?,3: TPM counter continues in debug mode"
|
|
newline
|
|
bitfld.long 0x00 5. "DOZEEN,Doze Enable" "0: Internal TPM counter continues in Doze mode,1: Internal TPM counter is paused and does not.."
|
|
endif
|
|
repeat 6. (increment 0 1)(increment 0 0x8)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "CSC,Channel (n) Status and Control"
|
|
eventfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
|
|
newline
|
|
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
|
|
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "CV,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "LPUART"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPUART0"
|
|
base ad:0x40042000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
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|
newline
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bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
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|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
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|
newline
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bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
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bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
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bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
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newline
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rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
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rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
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rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
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|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
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|
newline
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eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
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|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
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|
newline
|
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eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
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eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
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newline
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eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
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|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
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group.long 0x18++0x03
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line.long 0x00 "CTRL,LPUART Control Register"
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bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
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|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
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|
newline
|
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bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
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bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
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|
newline
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bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
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|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
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newline
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bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
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|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
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newline
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bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
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bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
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newline
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bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
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bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
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newline
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bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
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bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
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newline
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bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
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bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
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newline
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bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
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|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
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newline
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bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
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bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
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newline
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bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
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bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
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newline
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bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
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bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
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newline
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bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
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|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
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newline
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bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
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bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
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group.long 0x1C++0x03
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line.long 0x00 "DATA,LPUART Data Register"
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rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
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rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
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newline
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bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
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rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
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newline
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rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
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bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
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newline
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bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
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newline
|
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bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
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|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
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newline
|
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bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
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|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
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newline
|
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bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
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|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
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newline
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bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
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group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
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hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
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hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
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group.long 0x24++0x03
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line.long 0x00 "MODIR,LPUART Modem IrDA Register"
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bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
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bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
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newline
|
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bitfld.long 0x00 8.--10. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
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|
newline
|
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bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
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bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
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bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
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bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
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|
newline
|
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bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
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|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
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newline
|
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bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
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|
newline
|
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rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
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|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--27. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "LPUART0"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x400C4000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40054000
|
|
endif
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
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bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
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|
newline
|
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bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
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bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
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newline
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bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
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|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
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bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
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bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
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|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
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|
newline
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bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
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bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
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|
newline
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bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
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|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
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|
newline
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bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
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bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
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newline
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bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
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newline
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bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
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|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
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newline
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bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
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|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
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newline
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bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
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bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
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newline
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bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
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bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
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newline
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bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
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|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
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|
group.long 0x1C++0x03
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line.long 0x00 "DATA,LPUART Data Register"
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|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
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rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
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newline
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bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
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rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
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newline
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rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
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|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
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newline
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bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
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|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
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newline
|
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bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
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|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
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|
newline
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bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
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|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
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newline
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bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
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|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
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|
newline
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bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
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|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
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|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
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hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
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|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
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newline
|
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bitfld.long 0x00 8.--10. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
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bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
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bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
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bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
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newline
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bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
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line.long 0x00 "FIFO,LPUART FIFO Register"
|
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rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
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bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
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bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
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newline
|
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bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
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bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
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|
newline
|
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rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
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bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
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|
newline
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rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
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group.long 0x2C++0x03
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line.long 0x00 "WATER,LPUART Watermark Register"
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rbitfld.long 0x00 24.--27. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--18. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7"
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|
newline
|
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rbitfld.long 0x00 8.--11. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPUART1"
|
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base ad:0x40043000
|
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rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
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bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
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group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--27. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "LPUART1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x400C5000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40055000
|
|
endif
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--27. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPUART2"
|
|
base ad:0x40044000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--27. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "LPUART2"
|
|
base ad:0x40046000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS pin input,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 8-bit or 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
newline
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
bitfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
bitfld.long 0x00 30. "RXEDGIF,LPUART_RX Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: Break character is detected at length 10 bit..,1: Break character is detected at length of 11.."
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (LPUART_RX input not.."
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
bitfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
bitfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
bitfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
bitfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
bitfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
bitfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,LPUART_TX Pin Direction in Single-Wire Mode" "0: LPUART_TX pin is an input in single-wire mode,1: LPUART_TX pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - LPUART_RX and LPUART_TX..,1: Loop mode or single-wire mode where.."
|
|
newline
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the LPUART_TX.."
|
|
newline
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
newline
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,The current received dataword contained in DATA[R9:R0] was received with noise" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,The current received dataword contained in DATA[R9:R0] was received with a parity error" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,Read receive data buffer 9 or write transmit data buffer 9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,Read receive data buffer 8 or write transmit data buffer 8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,Read receive data buffer 7 or write transmit data buffer 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,Read receive data buffer 6 or write transmit data buffer 6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,Read receive data buffer 5 or write transmit data buffer 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,Read receive data buffer 4 or write transmit data buffer 4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,Read receive data buffer 3 or write transmit data buffer 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,Read receive data buffer 2 or write transmit data buffer 2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,Read receive data buffer 1 or write transmit data buffer 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,Read receive data buffer 0 or write transmit data buffer 0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RTSWATER,Receive RTS Configuration"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the LPUART_CTS pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS assertion is configured by the RTSWATER.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
bitfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "?,1: Transmit FIFO/Buffer depth = 4 datawords,?..."
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "?,1: Receive FIFO/Buffer depth = 4 datawords,?..."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RXCOUNT,Receive Counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RXWATER,Receive Watermark"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TXCOUNT,Transmit Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXWATER,Transmit Watermark"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "LPUART3"
|
|
base ad:0x41036000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
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bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
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bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--27. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "MCG (Multipurpose Clock Generator Lite)"
|
|
base ad:0x40064000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "C1,MCG Control Register 1"
|
|
bitfld.byte 0x00 6.--7. "CLKS,Clock Source Select" "0: Selects HIRC clock as the main clock source,1: Selects LIRC clock as the main clock source,2: Selects external clock as the main clock source,3: Reserved"
|
|
bitfld.byte 0x00 1. "IRCLKEN,Internal Reference Clock Enable" "0: LIRC is disabled,1: LIRC is enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. "IREFSTEN,Internal Reference Stop Enable" "0: LIRC is disabled in Stop mode,1: LIRC is enabled in Stop mode if IRCLKEN is set"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "C2,MCG Control Register 2"
|
|
bitfld.byte 0x00 4.--5. "RANGE0,External Clock Source Frequency Range Select" "0: Low frequency range selected for the crystal..,1: High frequency range selected for the crystal..,2: Very high frequency range selected for the..,3: Very high frequency range selected for the.."
|
|
bitfld.byte 0x00 3. "HGO0,Crystal Oscillator Operation Mode Select" "0: Configure crystal oscillator for low-power..,1: Configure crystal oscillator for high-gain.."
|
|
newline
|
|
bitfld.byte 0x00 2. "EREFS0,External Clock Source Select" "0: External clock requested,1: Oscillator requested"
|
|
bitfld.byte 0x00 0. "IRCS,Low-frequency Internal Reference Clock Select" "0: LIRC is in 2 MHz mode,1: LIRC is in 8 MHz mode"
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "S,MCG Status Register"
|
|
bitfld.byte 0x00 2.--3. "CLKST,Clock Mode Status" "0: HIRC clock is selected as the main clock..,1: LIRC clock is selected as the main clock..,2: External clock is selected as the main clock..,?..."
|
|
bitfld.byte 0x00 1. "OSCINIT0,OSC Initialization Status" "0: OSC is not ready,1: OSC clock is ready"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SC,MCG Status and Control Register"
|
|
bitfld.byte 0x00 1.--3. "FCRDIV,Low-frequency Internal Reference Clock Divider" "0: Division factor is 1,1: Division factor is 2,2: Division factor is 4,3: Division factor is 8,4: Division factor is 16,5: Division factor is 32,6: Division factor is 64,7: Division factor is 128"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MC,MCG Miscellaneous Control Register"
|
|
bitfld.byte 0x00 7. "HIRCEN,High-frequency IRC Enable" "0: HIRC source is not enabled,1: HIRC source is enabled"
|
|
bitfld.byte 0x00 0.--2. "LIRC_DIV2,Second Low-frequency Internal Reference Clock Divider" "0: Division factor is 1,1: Division factor is 2,2: Division factor is 4,3: Division factor is 8,4: Division factor is 16,5: Division factor is 32,6: Division factor is 64,7: Division factor is 128"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "MCM (Core Platform Miscellaneous Control Module)"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "MCM"
|
|
base ad:0xF0003000
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. "ESFC,Enable Stalling Flash Controller" "0: Disable stalling flash controller when flash..,1: Enable stalling flash controller when flash.."
|
|
bitfld.long 0x00 15. "DFCS,Disable Flash Controller Speculation" "0: Enable flash controller speculation,1: Disable flash controller speculation"
|
|
newline
|
|
bitfld.long 0x00 14. "EFDS,Enable Flash Data Speculation" "0: Disable flash data speculation,1: Enable flash data speculation"
|
|
bitfld.long 0x00 13. "DFCC,Disable Flash Controller Cache" "0: Enable flash controller cache,1: Disable flash controller cache"
|
|
newline
|
|
bitfld.long 0x00 12. "DFCIC,Disable Flash Controller Instruction Caching" "0: Enable flash controller instruction caching,1: Disable flash controller instruction caching"
|
|
bitfld.long 0x00 11. "DFCDA,Disable Flash Controller Data Caching" "0: Enable flash controller data caching,1: Disable flash controller data caching"
|
|
newline
|
|
bitfld.long 0x00 10. "CFCC,Clear Flash Controller Cache" "0,1"
|
|
bitfld.long 0x00 9. "ARB,Arbitration select" "0: Fixed-priority arbitration for the crossbar..,1: Round-robin arbitration for the crossbar.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. "CPOWOI,Compute Operation Wake-up on Interrupt" "0: No effect,1: When set the CPOREQ is cleared on any.."
|
|
rbitfld.long 0x00 1. "CPOACK,Compute Operation Acknowledge" "0: Compute operation entry has not completed or..,1: Compute operation entry has completed or.."
|
|
newline
|
|
bitfld.long 0x00 0. "CPOREQ,Compute Operation Request" "0: Request is cleared,1: Request Compute Operation"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "MCM0"
|
|
base ad:0xE0080000
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 9. "CBRR,Crossbar round-robin arbitration enable" "0: Fixed-priority arbitration,1: Round-robin arbitration"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISCR,Interrupt Status and Control Register"
|
|
bitfld.long 0x00 31. "FIDCE,FPU input denormal interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 28. "FIXCE,FPU inexact interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. "FUFCE,FPU underflow interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 26. "FOFCE,FPU overflow interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. "FDZCE,FPU divide-by-zero interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 24. "FIOCE,FPU invalid operation interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
rbitfld.long 0x00 15. "FIDC,FPU input denormal interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 12. "FIXC,FPU inexact interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 11. "FUFC,FPU underflow interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 10. "FOFC,FPU overflow interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 9. "FDZC,FPU divide-by-zero interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 8. "FIOC,FPU invalid operation interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CPCR2,Core Platform Control Register 2"
|
|
bitfld.long 0x00 17. "LCCPWB,Limit code cache peripheral write buffering" "0: Code cache peripheral write buffering is not..,1: Code cache peripheral write buffering is.."
|
|
bitfld.long 0x00 16. "PCCMCTRL,Bypass fixed code cache map" "0: The fixed code cache map is not bypassed,1: The fixed code cache map is bypassed"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "CBCS,Code Bus Cache Size" "0: CBCS_0,1: CBCS_1,2: CBCS_2,3: CBCS_3,4: CBCS_4,5: CBCS_5,6: CBCS_6,?..."
|
|
bitfld.long 0x00 3. "DCBC,Disable code bus cache" "0: Enable code bus cache,1: Disable code bus cache"
|
|
newline
|
|
bitfld.long 0x00 0. "CCBC,Clear code bus cache this field always reads as 0" "0: No effect,1: Clear code bus cache"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. "CPOWOI,Compute Operation wakeup on interrupt" "0: No effect,1: When set the CPOREQ is cleared on any.."
|
|
rbitfld.long 0x00 1. "CPOACK,Compute Operation acknowledge" "0: Compute operation entry has not completed or..,1: Compute operation entry has completed or.."
|
|
newline
|
|
bitfld.long 0x00 0. "CPOREQ,Compute Operation request" "0: Request is cleared,1: Request Compute Operation"
|
|
tree.end
|
|
endif
|
|
tree "MCM0"
|
|
base ad:0xF0003008
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 9. "CBRR,Crossbar round-robin arbitration enable" "0: Fixed-priority arbitration,1: Round-robin arbitration"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISCR,Interrupt Status and Control Register"
|
|
bitfld.long 0x00 31. "FIDCE,FPU input denormal interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 28. "FIXCE,FPU inexact interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. "FUFCE,FPU underflow interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 26. "FOFCE,FPU overflow interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. "FDZCE,FPU divide-by-zero interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 24. "FIOCE,FPU invalid operation interrupt enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
rbitfld.long 0x00 15. "FIDC,FPU input denormal interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 12. "FIXC,FPU inexact interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 11. "FUFC,FPU underflow interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 10. "FOFC,FPU overflow interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 9. "FDZC,FPU divide-by-zero interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 8. "FIOC,FPU invalid operation interrupt status" "0: No interrupt,1: Interrupt occurred"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CPCR2,Core Platform Control Register 2"
|
|
bitfld.long 0x00 17. "LCCPWB,Limit code cache peripheral write buffering" "0: Code cache peripheral write buffering is not..,1: Code cache peripheral write buffering is.."
|
|
bitfld.long 0x00 16. "PCCMCTRL,Bypass fixed code cache map" "0: The fixed code cache map is not bypassed,1: The fixed code cache map is bypassed"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. "CBCS,Code Bus Cache Size" "0: CBCS_0,1: CBCS_1,2: CBCS_2,3: CBCS_3,4: CBCS_4,5: CBCS_5,6: CBCS_6,?..."
|
|
bitfld.long 0x00 3. "DCBC,Disable code bus cache" "0: Enable code bus cache,1: Disable code bus cache"
|
|
newline
|
|
bitfld.long 0x00 0. "CCBC,Clear code bus cache this field always reads as 0" "0: No effect,1: Clear code bus cache"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. "CPOWOI,Compute Operation wakeup on interrupt" "0: No effect,1: When set the CPOREQ is cleared on any.."
|
|
rbitfld.long 0x00 1. "CPOACK,Compute Operation acknowledge" "0: Compute operation entry has not completed or..,1: Compute operation entry has completed or.."
|
|
newline
|
|
bitfld.long 0x00 0. "CPOREQ,Compute Operation request" "0: Request is cleared,1: Request Compute Operation"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "MCM1"
|
|
base ad:0xF0003000
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 9. "ARB,Arbitration select" "0: Fixed-priority arbitration for the crossbar..,1: Round-robin arbitration for the crossbar.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CPCR2,Core Platform Control Register 2"
|
|
rbitfld.long 0x00 4.--7. "CCSIZ,Code cache size" "0: No cache,?,2: CCSIZ_2,3: CCSIZ_3,4: CCSIZ_4,?..."
|
|
bitfld.long 0x00 3. "DCC,Disable the code cache" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCBC,Clear code bus cache" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. "CPOWOI,Compute Operation wakeup on interrupt" "0: No effect,1: When set the CPOREQ is cleared on any.."
|
|
rbitfld.long 0x00 1. "CPOACK,Compute Operation acknowledge" "0: Compute operation entry has not completed or..,1: Compute operation entry has completed or.."
|
|
newline
|
|
bitfld.long 0x00 0. "CPOREQ,Compute Operation request" "0: Request is cleared,1: Request Compute Operation"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "MMDVSQ (Divide and Square Root)"
|
|
tree "MMDVSQ0"
|
|
base ad:0xF0004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DEND,Dividend Register"
|
|
hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DSOR,Divisor Register"
|
|
hexmask.long 0x00 0.--31. 1. "DIVISOR,Divisor"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CSR,Control/Status Register"
|
|
rbitfld.long 0x00 31. "BUSY,BUSY" "0: MMDVSQ is idle,1: MMDVSQ is busy performing a divide or square.."
|
|
rbitfld.long 0x00 30. "DIV,DIVIDE" "0: Current or last MMDVSQ operation was not a..,1: Current or last MMDVSQ operation was a divide"
|
|
newline
|
|
rbitfld.long 0x00 29. "SQRT,SQUARE ROOT" "0: Current or last MMDVSQ operation was not a..,1: Current or last MMDVSQ operation was a square.."
|
|
bitfld.long 0x00 5. "DFS,Disable Fast Start" "0: A divide operation is initiated by a write to..,1: A divide operation is initiated by a write to.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DZ,Divide-by-Zero" "0: The last divide operation had a non-zero..,1: The last divide operation had a zero divisor.."
|
|
bitfld.long 0x00 3. "DZE,Divide-by-Zero-Enable" "0: Reads of the RES register return the register..,1: If CSR[DZ] = 1 an attempted read of RES.."
|
|
newline
|
|
bitfld.long 0x00 2. "REM,REMainder calculation" "0: Return the quotient in the RES for the divide..,1: Return the remainder in the RES for the.."
|
|
bitfld.long 0x00 1. "USGN,Unsigned calculation" "0: Perform a signed divide,1: Perform an unsigned divide"
|
|
newline
|
|
bitfld.long 0x00 0. "SRT,Start" "0: No operation initiated,1: If CSR[DFS] = 1 then initiate a divide.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RES,Result Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESULT,Result"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "RCND,Radicand Register"
|
|
hexmask.long 0x00 0.--31. 1. "RADICAND,Radicand"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "MMDVSQ1"
|
|
base ad:0xF0004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DEND,Dividend Register"
|
|
hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DSOR,Divisor Register"
|
|
hexmask.long 0x00 0.--31. 1. "DIVISOR,Divisor"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CSR,Control/Status Register"
|
|
rbitfld.long 0x00 31. "BUSY,BUSY" "0: MMDVSQ is idle,1: MMDVSQ is busy performing a divide or square.."
|
|
rbitfld.long 0x00 30. "DIV,DIVIDE" "0: Current or last MMDVSQ operation was not a..,1: Current or last MMDVSQ operation was a divide"
|
|
newline
|
|
rbitfld.long 0x00 29. "SQRT,SQUARE ROOT" "0: Current or last MMDVSQ operation was not a..,1: Current or last MMDVSQ operation was a square.."
|
|
bitfld.long 0x00 5. "DFS,Disable Fast Start" "0: A divide operation is initiated by a write to..,1: A divide operation is initiated by a write to.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DZ,Divide-by-Zero" "0: The last divide operation had a non-zero..,1: The last divide operation had a zero divisor.."
|
|
bitfld.long 0x00 3. "DZE,Divide-by-Zero-Enable" "0: Reads of the RES register return the register..,1: If CSR[DZ] = 1 an attempted read of RES.."
|
|
newline
|
|
bitfld.long 0x00 2. "REM,REMainder calculation" "0: Return the quotient in the RES for the divide..,1: Return the remainder in the RES for the.."
|
|
bitfld.long 0x00 1. "USGN,Unsigned calculation" "0: Perform a signed divide,1: Perform an unsigned divide"
|
|
newline
|
|
bitfld.long 0x00 0. "SRT,Start" "0: No operation initiated,1: If CSR[DFS] = 1 then initiate a divide.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RES,Result Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESULT,Result"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "RCND,Radicand Register"
|
|
hexmask.long 0x00 0.--31. 1. "RADICAND,Radicand"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "MSCM"
|
|
base ad:0x40001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPxTYPE,Processor X Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PERSONALITY,Processor x Personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor x Revision"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CPxNUM,Processor X Number Register"
|
|
bitfld.long 0x00 0. "CPN,Processor x Number" "0,1"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CPxMASTER,Processor X Master Register"
|
|
bitfld.long 0x00 0.--5. "PPMN,Processor x Physical Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CPxMASTER,Processor X Master Register"
|
|
bitfld.long 0x00 0.--5. "PPN,Processor x Physical Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CPxCOUNT,Processor X Count Register"
|
|
bitfld.long 0x00 0.--1. "PCNT,Processor Count" "0,1,2,3"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 3. (strings "0" "0" "1" )(list 0x0 0x0 0x4 )
|
|
rgroup.long ($2+0x10)++0x03
|
|
line.long 0x00 "CPxCFG$1,Processor X Configuration Register $1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
endif
|
|
repeat.end
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CPxCFG1,Processor X Configuration Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,Level 2 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "L2WY,Level 2 Instruction Cache Ways"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CPxCFG2,Processor X Configuration Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TMLSZ,Tightly-coupled Memory Lower Size"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TMUSZ,Tightly-coupled Memory Upper Size"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x18)++0x03
|
|
line.long 0x00 "CPxCFG$1,Processor X Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CPxCFG3,Processor X Configuration Register 3"
|
|
bitfld.long 0x00 8.--9. "SBP,System Bus Ports" "0,1,2,3"
|
|
bitfld.long 0x00 6. "BB,Bit Banding" "0: Bit Banding is not supported,1: Bit Banding is supported"
|
|
newline
|
|
bitfld.long 0x00 5. "CMP,Core Memory Protection unit" "0: Core Memory Protection is not included,1: Core Memory Protection is included"
|
|
bitfld.long 0x00 4. "TZ,Trust Zone" "0: Trust Zone support is not included,1: Trust Zone support is included"
|
|
newline
|
|
bitfld.long 0x00 3. "MMU,Memory Management Unit" "0: MMU support is not included,1: MMU support is included"
|
|
bitfld.long 0x00 2. "JAZ,Jazelle support" "0: Jazelle support is not included,1: Jazelle support is included"
|
|
newline
|
|
bitfld.long 0x00 1. "SIMD,SIMD/NEON instruction support" "0: SIMD/NEON support is not included,1: SIMD/NEON support is included"
|
|
bitfld.long 0x00 0. "FPU,Floating Point Unit" "0: FPU support is not included,1: FPU support is included"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CP0TYPE,Processor 0 Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PERSONALITY,Processor x Personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor x Revision"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CP0TYPE,Processor 0 Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PERSONALITY,Processor 0 Personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor 0 Revision"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CP0NUM,Processor 0 Number Register"
|
|
bitfld.long 0x00 0. "CPN,Processor x Number" "0,1"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CP0NUM,Processor 0 Number Register"
|
|
bitfld.long 0x00 0. "CPN,Processor 0 Number" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CP0MASTER,Processor 0 Master Register"
|
|
bitfld.long 0x00 0.--5. "PPMN,Processor 0 Physical Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CP0MASTER,Processor 0 Master Register"
|
|
bitfld.long 0x00 0.--5. "PPN,Processor x Physical Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CP0COUNT,Processor 0 Count Register"
|
|
bitfld.long 0x00 0.--1. "PCNT,Processor Count" "0,1,2,3"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (strings "0" "0" )(list 0x0 0x0 )
|
|
rgroup.long ($2+0x30)++0x03
|
|
line.long 0x00 "CP0CFG$1,Processor 0 Configuration Register $1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
endif
|
|
repeat.end
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CP0CFG1,Processor 0 Configuration Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,Level 2 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "L2WY,Level 2 Instruction Cache Ways"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x34)++0x03
|
|
line.long 0x00 "CP0CFG$1,Processor 0 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CP0CFG2,Processor 0 Configuration Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TMLSZ,Tightly-coupled Memory Lower Size"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TMUSZ,Tightly-coupled Memory Upper Size"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CP0CFG3,Processor 0 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CP0CFG3,Processor 0 Configuration Register 3"
|
|
bitfld.long 0x00 8.--9. "SBP,System Bus Ports" "0,1,2,3"
|
|
bitfld.long 0x00 6. "BB,Bit Banding" "0: Bit Banding is not supported,1: Bit Banding is supported"
|
|
newline
|
|
bitfld.long 0x00 5. "CMP,Core Memory Protection unit" "0: Core Memory Protection is not included,1: Core Memory Protection is included"
|
|
bitfld.long 0x00 4. "TZ,Trust Zone" "0: Trust Zone support is not included,1: Trust Zone support is included"
|
|
newline
|
|
bitfld.long 0x00 3. "MMU,Memory Management Unit" "0: MMU support is not included,1: MMU support is included"
|
|
bitfld.long 0x00 2. "JAZ,Jazelle support" "0: Jazelle support is not included,1: Jazelle support is included"
|
|
newline
|
|
bitfld.long 0x00 1. "SIMD,SIMD/NEON instruction support" "0: SIMD/NEON support is not included,1: SIMD/NEON support is included"
|
|
bitfld.long 0x00 0. "FPU,Floating Point Unit" "0: FPU support is not included,1: FPU support is included"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CP1TYPE,Processor 1 Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PERSONALITY,Processor 1 Personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor 1 Revision"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CP1NUM,Processor 1 Number Register"
|
|
bitfld.long 0x00 0. "CPN,Processor 1 Number" "0,1"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CP1MASTER,Processor 1 Master Register"
|
|
bitfld.long 0x00 0.--5. "PPMN,Processor 1 Physical Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "CP1COUNT,Processor 1 Count Register"
|
|
bitfld.long 0x00 0.--1. "PCNT,Processor Count" "0,1,2,3"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CP1CFG0,Processor 1 Configuration Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "CP1CFG1,Processor 1 Configuration Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,Level 2 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "L2WY,Level 2 Instruction Cache Ways"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "CP1CFG2,Processor 1 Configuration Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TMLSZ,Tightly-coupled Memory Lower Size"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TMUSZ,Tightly-coupled Memory Upper Size"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "CP1CFG3,Processor 1 Configuration Register 3"
|
|
bitfld.long 0x00 8.--9. "SBP,System Bus Ports" "0,1,2,3"
|
|
bitfld.long 0x00 6. "BB,Bit Banding" "0: Bit Banding is not supported,1: Bit Banding is supported"
|
|
newline
|
|
bitfld.long 0x00 5. "CMP,Core Memory Protection unit" "0: Core Memory Protection is not included,1: Core Memory Protection is included"
|
|
bitfld.long 0x00 4. "TZ,Trust Zone" "0: Trust Zone support is not included,1: Trust Zone support is included"
|
|
newline
|
|
bitfld.long 0x00 3. "MMU,Memory Management Unit" "0: MMU support is not included,1: MMU support is included"
|
|
bitfld.long 0x00 2. "JAZ,Jazelle support" "0: Jazelle support is not included,1: Jazelle support is included"
|
|
newline
|
|
bitfld.long 0x00 1. "SIMD,SIMD/NEON instruction support" "0: SIMD/NEON support is not included,1: SIMD/NEON support is included"
|
|
bitfld.long 0x00 0. "FPU,Floating Point Unit" "0: FPU support is not included,1: FPU support is included"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "?,?,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,?,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 4.--5. "OCM1,OCMEM Control Field 1" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x400)++0x03
|
|
line.long 0x00 "OCMDR$1,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. "V,OCMEM Valid bit" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
bitfld.long 0x00 28. "OCMSZH,OCMEM Size Hole" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "OCMSZ,OCMEM Size" "0: no OCMEMn,?,?,?,4: 4KB OCMEMn,5: 8KB OCMEMn,6: 16KB OCMEMn,7: 32KB OCMEMn,?,?,?,?,?,?,?,15: 8192KB OCMEMn"
|
|
bitfld.long 0x00 17.--19. "OCMW,OCMEM datapath Width" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,Read-Only" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
bitfld.long 0x00 13.--15. "OCMT,OCMEM Type" "0: OCMEMn is a system RAM,1: OCMEMn is a graphics RAM,?,3: OCMEMn is a ROM,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "OCMPU,OCMEM Memory Protection Unit" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "?,?,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,?,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 4.--5. "OCM1,OCMEM Control Field 1" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
bitfld.long 0x00 31. "V,OCMEM Valid bit" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
bitfld.long 0x00 28. "OCMSZH,OCMEM Size Hole" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "OCMSZ,OCMEM Size" "0: no OCMEMn,?,?,?,4: 4KB OCMEMn,5: 8KB OCMEMn,6: 16KB OCMEMn,7: 32KB OCMEMn,?,?,?,?,?,?,?,15: 8192KB OCMEMn"
|
|
bitfld.long 0x00 17.--19. "OCMW,OCMEM datapath Width" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,Read-Only" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
bitfld.long 0x00 13.--15. "OCMT,OCMEM Type" "0: OCMEMn is a system RAM,1: OCMEMn is a graphics RAM,?,3: OCMEMn is a ROM,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "OCMPU,OCMEM Memory Protection Unit" "0,1"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
group.long ($2+0x408)++0x03
|
|
line.long 0x00 "OCMDR$1,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "?,?,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,?,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "MSMC (crr_cmc0)"
|
|
tree "SMC0"
|
|
base ad:0x40020000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 0. "PWRD_INDPT,Power Domains Independent" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 7. "AHSRUN,Allow High Speed Run mode" "0: HSRUN is not allowed,1: HSRUN is allowed"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR VLPW and VLPS are not allowed,1: VLPR VLPW and VLPS are allowed"
|
|
newline
|
|
bitfld.long 0x00 3. "ALLS,Allow Low-Leakage Stop Mode" "0: LLS is not allowed,1: LLS is allowed"
|
|
bitfld.long 0x00 0.--1. "AVLLS,Allow Very-Low-Leakage Stop Mode" "0: VLLS mode is not allowed,1: VLLS0/1 mode is allowed,2: VLLS2/3 mode is allowed,3: VLLS0/1/2/3 mode is allowed"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 16.--17. "PSTOPO,Partial Stop Option" "0: STOP - Normal Stop mode,1: PSTOP1 - Partial Stop with system and bus..,2: PSTOP2 - Partial Stop with system clock..,3: PSTOP3 - Partial Stop with system clock.."
|
|
bitfld.long 0x00 8.--9. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),3: High Speed Run mode (HSRUN)"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),3: Low-Leakage Stop (LLS),4: Very-Low-Leakage Stop with SRAM..,?,6: Very-Low-Leakage Stop without SRAM retention..,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOPSTAT,Stop Entry Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SRS,System Reset Status"
|
|
bitfld.long 0x00 28. "JTAG,JTAG System Reset" "0: Reset not generated by JTAG system reset,1: Reset generated by JTAG system reset"
|
|
bitfld.long 0x00 17. "CORE1,Core1 System Reset" "0: Reset not generated from Core1 system reset..,1: Reset generated from Core1 system reset source"
|
|
newline
|
|
bitfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Reset not generated by core lockup or exception,1: Reset generated by core lockup or exception"
|
|
bitfld.long 0x00 14. "SW,Software Reset" "0: Reset not generated by software request from..,1: Reset generated by software request from core"
|
|
newline
|
|
bitfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Reset is not generated from the WatchDog..,1: Reset is generated from the WatchDog timeout"
|
|
bitfld.long 0x00 12. "SCG,SCG Reset" "0: Reset is not generated from an SCG loss of..,1: Reset is generated from an SCG loss of lock.."
|
|
newline
|
|
bitfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Reset not generated by Stop Controller Timeout,1: Reset generated by Stop Controller Timeout"
|
|
bitfld.long 0x00 10. "RSTACK,Reset Timeout" "0: Reset not generated from Reset Controller..,1: Reset generated from Reset Controller Timeout"
|
|
newline
|
|
bitfld.long 0x00 9. "MDM,MDM Reset" "0: Reset was not generated from the MDM reset..,1: Reset was generated from the MDM reset request"
|
|
bitfld.long 0x00 8. "PIN,Pin Reset" "0: Reset was not generated from the assertion of..,1: Reset was generated from the assertion of.."
|
|
newline
|
|
bitfld.long 0x00 7. "CORE,Core Reset" "0: Reset source was not core only reset,1: Reset source was core reset and reset the.."
|
|
bitfld.long 0x00 5. "FATAL,Fatal Reset" "0: Reset was not generated by a fatal reset source,1: Reset was generated by a fatal reset source"
|
|
newline
|
|
bitfld.long 0x00 4. "WARM,Warm Reset" "0: Reset not generated by Warm Reset source,1: Reset generated by Warm Reset source"
|
|
bitfld.long 0x00 3. "HVD,HVD Reset" "0: Reset not generated by HVD,1: Reset generated by HVD"
|
|
newline
|
|
bitfld.long 0x00 2. "LVD,LVD Reset" "0: Reset not generated by LVD,1: Reset generated by LVD"
|
|
bitfld.long 0x00 1. "POR,POR Reset" "0: Reset not generated by POR,1: Reset generated by POR"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKEUP,Wakeup Reset" "0: Reset not generated by wakeup from VLLS mode,1: Reset generated by wakeup from VLLS mode"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RPC,Reset Pin Control"
|
|
bitfld.long 0x00 9. "LPOFEN,LPO Filter Enable" "0: LPO clock reset pin filter disabled,1: LPO clock reset pin filter enabled in all modes"
|
|
bitfld.long 0x00 8. "FILTEN,Filter Enable" "0: Slow clock reset pin filter disabled,1: Slow clock reset pin filter enabled in Run.."
|
|
newline
|
|
bitfld.long 0x00 0.--4. "FILTCFG,Reset Filter Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SSRS,Sticky System Reset Status"
|
|
eventfld.long 0x00 28. "JTAG,JTAG System Reset" "0: Reset not generated by JTAG system reset,1: Reset generated by JTAG system reset"
|
|
eventfld.long 0x00 17. "CORE1,Core1 Reset" "0: Reset not generated from Core1 reset source,1: Reset generated from Core1 reset source"
|
|
newline
|
|
eventfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Reset not generated by core lockup,1: Reset generated by core lockup"
|
|
eventfld.long 0x00 14. "SW,Software Reset" "0: Reset not generated by software request from..,1: Reset generated by software request from core"
|
|
newline
|
|
eventfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Reset is not generated from the WatchDog..,1: Reset is generated from the WatchDog timeout"
|
|
eventfld.long 0x00 12. "SCG,SCG Reset" "0: Reset is not generated from an SCG loss of..,1: Reset is generated from an SCG loss of lock.."
|
|
newline
|
|
eventfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Reset not generated by Stop Controller Timeout,1: Reset generated by Stop Controller Timeout"
|
|
eventfld.long 0x00 10. "RSTACK,Reset Timeout" "0: Reset not generated from Reset Controller..,1: Reset generated from Reset Controller Timeout"
|
|
newline
|
|
eventfld.long 0x00 9. "MDM,MDM Reset" "0: Reset was not generated from the MDM reset..,1: Reset was generated from the MDM reset request"
|
|
eventfld.long 0x00 8. "PIN,Pin Reset" "0: Reset was not generated from the RESET_B pin,1: Reset was generated from the RESET_B pin"
|
|
newline
|
|
eventfld.long 0x00 5. "FATAL,Fatal Reset" "0: Reset was not generated by a fatal reset source,1: Reset was generated by a fatal reset source"
|
|
eventfld.long 0x00 4. "WARM,Warm Reset" "0: Reset not generated by system reset source,1: Reset generated by system reset source"
|
|
newline
|
|
eventfld.long 0x00 3. "HVD,HVD Reset" "0: Reset not generated by HVD,1: Reset generated by HVD"
|
|
eventfld.long 0x00 2. "LVD,LVD Reset" "0: Reset not generated by LVD,1: Reset generated by LVD"
|
|
newline
|
|
eventfld.long 0x00 1. "POR,POR Reset" "0: Reset not generated by POR,1: Reset generated by POR"
|
|
eventfld.long 0x00 0. "WAKEUP,Wakeup Reset" "0: Reset not generated by wakeup from VLLS mode,1: Reset generated by wakeup from VLLS mode"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SRIE,System Reset Interrupt Enable"
|
|
bitfld.long 0x00 17. "CORE1,Core1 Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "SW,Software Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "MDM,MDM Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "PIN,Pin Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SRIF,System Reset Interrupt Flag"
|
|
eventfld.long 0x00 17. "CORE1,Core1 Reset" "0: Reset source not pending,1: Reset source pending"
|
|
eventfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Reset source not pending,1: Reset source pending"
|
|
newline
|
|
eventfld.long 0x00 14. "SW,Software Reset" "0: Reset source not pending,1: Reset source pending"
|
|
eventfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Reset source not pending,1: Reset source pending"
|
|
newline
|
|
eventfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Reset source not pending,1: Reset source pending"
|
|
eventfld.long 0x00 9. "MDM,MDM Reset" "0: Reset source not pending,1: Reset source pending"
|
|
newline
|
|
eventfld.long 0x00 8. "PIN,Pin Reset" "0: Reset source not pending,1: Reset source pending"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
eventfld.long 0x00 0.--1. "BOOTCFG,Boot Configuration" "0: Boot from Flash,1: Boot from ROM due to BOOTCFG0 pin assertion,2: Boot from ROM due to FOPT configuration,3: Boot from ROM due to both BOOTCFG0 pin.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FM,Force Mode Register"
|
|
bitfld.long 0x00 0.--1. "FORCECFG,Boot Configuration" "0: FORCECFG_0,1: Assert corresponding bit in Mode Register on..,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SRAMLPR,SRAM Low Power Register"
|
|
hexmask.long 0x00 0.--31. 1. "LPE,Low Power Enable"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SRAMDSR,SRAM Deep Sleep Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSE,Deep Sleep Enable"
|
|
tree.end
|
|
tree "SMC1"
|
|
base ad:0x41020000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 0. "PWRD_INDPT,Power Domains Independent" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 7. "AHSRUN,Allow High Speed Run mode" "0: HSRUN is not allowed,1: HSRUN is allowed"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR VLPW and VLPS are not allowed,1: VLPR VLPW and VLPS are allowed"
|
|
newline
|
|
bitfld.long 0x00 3. "ALLS,Allow Low-Leakage Stop Mode" "0: LLS is not allowed,1: LLS is allowed"
|
|
bitfld.long 0x00 0.--1. "AVLLS,Allow Very-Low-Leakage Stop Mode" "0: VLLS mode is not allowed,1: VLLS0/1 mode is allowed,2: VLLS2/3 mode is allowed,3: VLLS0/1/2/3 mode is allowed"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 16.--17. "PSTOPO,Partial Stop Option" "0: STOP - Normal Stop mode,1: PSTOP1 - Partial Stop with system and bus..,2: PSTOP2 - Partial Stop with system clock..,3: PSTOP3 - Partial Stop with system clock.."
|
|
bitfld.long 0x00 8.--9. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),3: High Speed Run mode (HSRUN)"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),3: Low-Leakage Stop (LLS),4: Very-Low-Leakage Stop with SRAM..,?,6: Very-Low-Leakage Stop without SRAM retention..,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOPSTAT,Stop Entry Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SRS,System Reset Status"
|
|
bitfld.long 0x00 28. "JTAG,JTAG System Reset" "0: Reset not generated by JTAG system reset,1: Reset generated by JTAG system reset"
|
|
bitfld.long 0x00 16. "CORE0,Core0 System Reset" "0: Reset not generated from Core0 system reset..,1: Reset generated from Core0 system reset source"
|
|
newline
|
|
bitfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Reset not generated by core lockup or exception,1: Reset generated by core lockup or exception"
|
|
bitfld.long 0x00 14. "SW,Software Reset" "0: Reset not generated by software request from..,1: Reset generated by software request from core"
|
|
newline
|
|
bitfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Reset is not generated from the WatchDog..,1: Reset is generated from the WatchDog timeout"
|
|
bitfld.long 0x00 12. "SCG,SCG Reset" "0: Reset is not generated from an SCG loss of..,1: Reset is generated from an SCG loss of lock.."
|
|
newline
|
|
bitfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Reset not generated by Stop Controller Timeout,1: Reset generated by Stop Controller Timeout"
|
|
bitfld.long 0x00 10. "RSTACK,Reset Timeout" "0: Reset not generated from Reset Controller..,1: Reset generated from Reset Controller Timeout"
|
|
newline
|
|
bitfld.long 0x00 9. "MDM,MDM Reset" "0: Reset was not generated from the MDM reset..,1: Reset was generated from the MDM reset request"
|
|
bitfld.long 0x00 8. "PIN,Pin Reset" "0: Reset was not generated from the assertion of..,1: Reset was generated from the assertion of.."
|
|
newline
|
|
bitfld.long 0x00 7. "CORE,Core Reset" "0: Reset source was not core only reset,1: Reset source was core reset and reset the.."
|
|
bitfld.long 0x00 5. "FATAL,Fatal Reset" "0: Reset was not generated by a fatal reset source,1: Reset was generated by a fatal reset source"
|
|
newline
|
|
bitfld.long 0x00 4. "WARM,Warm Reset" "0: Reset not generated by Warm Reset source,1: Reset generated by Warm Reset source"
|
|
bitfld.long 0x00 3. "HVD,HVD Reset" "0: Reset not generated by HVD,1: Reset generated by HVD"
|
|
newline
|
|
bitfld.long 0x00 2. "LVD,LVD Reset" "0: Reset not generated by LVD,1: Reset generated by LVD"
|
|
bitfld.long 0x00 1. "POR,POR Reset" "0: Reset not generated by POR,1: Reset generated by POR"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKEUP,Wakeup Reset" "0: Reset not generated by wakeup from VLLS mode,1: Reset generated by wakeup from VLLS mode"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SSRS,Sticky System Reset Status"
|
|
eventfld.long 0x00 28. "JTAG,JTAG System Reset" "0: Reset not generated by JTAG system reset,1: Reset generated by JTAG system reset"
|
|
eventfld.long 0x00 16. "CORE0,Core0 Reset" "0: Reset not generated from Core0 reset source,1: Reset generated from Core0 reset source"
|
|
newline
|
|
eventfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Reset not generated by core lockup,1: Reset generated by core lockup"
|
|
eventfld.long 0x00 14. "SW,Software Reset" "0: Reset not generated by software request from..,1: Reset generated by software request from core"
|
|
newline
|
|
eventfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Reset is not generated from the WatchDog..,1: Reset is generated from the WatchDog timeout"
|
|
eventfld.long 0x00 12. "SCG,SCG Reset" "0: Reset is not generated from an SCG loss of..,1: Reset is generated from an SCG loss of lock.."
|
|
newline
|
|
eventfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Reset not generated by Stop Controller Timeout,1: Reset generated by Stop Controller Timeout"
|
|
eventfld.long 0x00 10. "RSTACK,Reset Timeout" "0: Reset not generated from Reset Controller..,1: Reset generated from Reset Controller Timeout"
|
|
newline
|
|
eventfld.long 0x00 9. "MDM,MDM Reset" "0: Reset was not generated from the MDM reset..,1: Reset was generated from the MDM reset request"
|
|
eventfld.long 0x00 8. "PIN,Pin Reset" "0: Reset was not generated from the RESET_B pin,1: Reset was generated from the RESET_B pin"
|
|
newline
|
|
eventfld.long 0x00 5. "FATAL,Fatal Reset" "0: Reset was not generated by a fatal reset source,1: Reset was generated by a fatal reset source"
|
|
eventfld.long 0x00 4. "WARM,Warm Reset" "0: Reset not generated by system reset source,1: Reset generated by system reset source"
|
|
newline
|
|
eventfld.long 0x00 3. "HVD,HVD Reset" "0: Reset not generated by HVD,1: Reset generated by HVD"
|
|
eventfld.long 0x00 2. "LVD,LVD Reset" "0: Reset not generated by LVD,1: Reset generated by LVD"
|
|
newline
|
|
eventfld.long 0x00 1. "POR,POR Reset" "0: Reset not generated by POR,1: Reset generated by POR"
|
|
eventfld.long 0x00 0. "WAKEUP,Wakeup Reset" "0: Reset not generated by wakeup from VLLS mode,1: Reset generated by wakeup from VLLS mode"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SRIE,System Reset Interrupt Enable"
|
|
bitfld.long 0x00 16. "CORE0,Core0 Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "SW,Software Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "MDM,MDM Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "PIN,Pin Reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SRIF,System Reset Interrupt Flag"
|
|
eventfld.long 0x00 16. "CORE0,Core0 Reset" "0: Reset source not pending,1: Reset source pending"
|
|
eventfld.long 0x00 15. "LOCKUP,Lockup Reset" "0: Reset source not pending,1: Reset source pending"
|
|
newline
|
|
eventfld.long 0x00 14. "SW,Software Reset" "0: Reset source not pending,1: Reset source pending"
|
|
eventfld.long 0x00 13. "WDOG,Watchdog Reset" "0: Reset source not pending,1: Reset source pending"
|
|
newline
|
|
eventfld.long 0x00 11. "STOPACK,Stop Timeout Reset" "0: Reset source not pending,1: Reset source pending"
|
|
eventfld.long 0x00 9. "MDM,MDM Reset" "0: Reset source not pending,1: Reset source pending"
|
|
newline
|
|
eventfld.long 0x00 8. "PIN,Pin Reset" "0: Reset source not pending,1: Reset source pending"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
eventfld.long 0x00 0.--1. "BOOTCFG,Boot Configuration" "0: Boot from Flash,1: Boot from ROM due to BOOTCFG0 pin assertion,2: Boot from ROM due to FOPT configuration,3: Boot from ROM due to both BOOTCFG0 pin.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FM,Force Mode Register"
|
|
bitfld.long 0x00 0.--1. "FORCECFG,Boot Configuration" "0: FORCECFG_0,1: Assert corresponding bit in Mode Register on..,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SRAMLPR,SRAM Low Power Register"
|
|
hexmask.long 0x00 0.--31. 1. "LPE,Low Power Enable"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SRAMDSR,SRAM Deep Sleep Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSE,Deep Sleep Enable"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "MTB (Micro Trace Buffer)"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "MTB"
|
|
base ad:0xF0000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POSITION,MTB Position Register"
|
|
hexmask.long 0x00 3.--31. 1. "POINTER,Trace Packet Address Pointer[28:0]"
|
|
bitfld.long 0x00 2. "WRAP,WRAP" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MASTER,MTB Master Register"
|
|
bitfld.long 0x00 31. "EN,Main Trace Enable" "0,1"
|
|
bitfld.long 0x00 9. "HALTREQ,Halt Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RAMPRIV,RAM Privilege" "0,1"
|
|
bitfld.long 0x00 7. "SFRWPRIV,Special Function Register Write Privilege" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTOPEN,Trace Stop Input Enable" "0,1"
|
|
bitfld.long 0x00 5. "TSTARTEN,Trace Start Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "MASK,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FLOW,MTB Flow Register"
|
|
hexmask.long 0x00 3.--31. 1. "WATERMARK,WATERMARK[28:0]"
|
|
bitfld.long 0x00 1. "AUTOHALT,AUTOHALT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTOSTOP,AUTOSTOP" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BASE,MTB Base Register"
|
|
hexmask.long 0x00 0.--31. 1. "BASEADDR,BASEADDR"
|
|
rgroup.long 0xF00++0x03
|
|
line.long 0x00 "MODECTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "MODECTRL,MODECTRL"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "TAGSET,Claim TAG Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAGSET,TAGSET"
|
|
rgroup.long 0xFA4++0x03
|
|
line.long 0x00 "TAGCLEAR,Claim TAG Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAGCLEAR,TAGCLEAR"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "LOCKACCESS,Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOCKACCESS,Hardwired to 0x0000_0000"
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "LOCKSTAT,Lock Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOCKSTAT,LOCKSTAT"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "AUTHSTAT,Authentication Status Register"
|
|
bitfld.long 0x00 2. "BIT2,BIT2" "0,1"
|
|
bitfld.long 0x00 0. "BIT0,Connected to DBGEN" "0,1"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVICEARCH,Device Architecture Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICEARCH,DEVICEARCH"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID$1,Component ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "MTB"
|
|
base ad:0xF0000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POSITION,MTB Position Register"
|
|
hexmask.long 0x00 3.--31. 1. "POINTER,Trace Packet Address Pointer[28:0]"
|
|
bitfld.long 0x00 2. "WRAP,WRAP" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MASTER,MTB Master Register"
|
|
bitfld.long 0x00 31. "EN,Main Trace Enable" "0,1"
|
|
bitfld.long 0x00 9. "HALTREQ,Halt Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RAMPRIV,RAM Privilege" "0,1"
|
|
bitfld.long 0x00 7. "SFRWPRIV,Special Function Register Write Privilege" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTOPEN,Trace Stop Input Enable" "0,1"
|
|
bitfld.long 0x00 5. "TSTARTEN,Trace Start Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "MASK,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FLOW,MTB Flow Register"
|
|
hexmask.long 0x00 3.--31. 1. "WATERMARK,WATERMARK[28:0]"
|
|
bitfld.long 0x00 1. "AUTOHALT,AUTOHALT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTOSTOP,AUTOSTOP" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BASE,MTB Base Register"
|
|
hexmask.long 0x00 0.--31. 1. "BASEADDR,BASEADDR"
|
|
rgroup.long 0xF00++0x03
|
|
line.long 0x00 "MODECTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "MODECTRL,MODECTRL"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "TAGSET,Claim TAG Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAGSET,TAGSET"
|
|
rgroup.long 0xFA4++0x03
|
|
line.long 0x00 "TAGCLEAR,Claim TAG Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAGCLEAR,TAGCLEAR"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "LOCKACCESS,Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOCKACCESS,Hardwired to 0x0000_0000"
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "LOCKSTAT,Lock Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOCKSTAT,LOCKSTAT"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "AUTHSTAT,Authentication Status Register"
|
|
bitfld.long 0x00 2. "BIT2,BIT2" "0,1"
|
|
bitfld.long 0x00 0. "BIT0,Connected to DBGEN" "0,1"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVICEARCH,Device Architecture Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICEARCH,DEVICEARCH"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID$1,Component ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "MTB0"
|
|
base ad:0xF0000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POSITION,MTB Position Register"
|
|
hexmask.long 0x00 3.--31. 1. "POINTER,Trace Packet Address Pointer[28:0]"
|
|
bitfld.long 0x00 2. "WRAP,WRAP" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MASTER,MTB Master Register"
|
|
bitfld.long 0x00 31. "EN,Main Trace Enable" "0,1"
|
|
bitfld.long 0x00 9. "HALTREQ,Halt Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RAMPRIV,RAM Privilege" "0,1"
|
|
bitfld.long 0x00 7. "SFRWPRIV,Special Function Register Write Privilege" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTOPEN,Trace Stop Input Enable" "0,1"
|
|
bitfld.long 0x00 5. "TSTARTEN,Trace Start Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "MASK,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FLOW,MTB Flow Register"
|
|
hexmask.long 0x00 3.--31. 1. "WATERMARK,WATERMARK[28:0]"
|
|
bitfld.long 0x00 1. "AUTOHALT,AUTOHALT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTOSTOP,AUTOSTOP" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BASE,MTB Base Register"
|
|
hexmask.long 0x00 0.--31. 1. "BASEADDR,BASEADDR"
|
|
rgroup.long 0xF00++0x03
|
|
line.long 0x00 "MODECTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "MODECTRL,MODECTRL"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "TAGSET,Claim TAG Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAGSET,TAGSET"
|
|
rgroup.long 0xFA4++0x03
|
|
line.long 0x00 "TAGCLEAR,Claim TAG Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAGCLEAR,TAGCLEAR"
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "LOCKACCESS,Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOCKACCESS,Hardwired to 0x0000_0000"
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "LOCKSTAT,Lock Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOCKSTAT,LOCKSTAT"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "AUTHSTAT,Authentication Status Register"
|
|
bitfld.long 0x00 3. "BIT3,BIT3" "0,1"
|
|
bitfld.long 0x00 2. "BIT2,BIT2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BIT1,BIT1" "0,1"
|
|
bitfld.long 0x00 0. "BIT0,Connected to DBGEN" "0,1"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVICEARCH,Device Architecture Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICEARCH,DEVICEARCH"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID$1,Component ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "MTB0_DWT (MTB data watchpoint and trace)"
|
|
base ad:0xF0001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL,MTB DWT Control Register"
|
|
bitfld.long 0x00 28.--31. "NUMCMP,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--27. 1. "DWTCFGCTRL,DWT configuration controls"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x10 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "COMP$1,MTB_DWT Comparator Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Reference value for comparison"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x10 )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "MASK$1,MTB_DWT Comparator Mask Register"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FCT0,MTB_DWT Comparator Function Register 0"
|
|
rbitfld.long 0x00 24. "MATCHED,Comparator match" "0: No match,1: Match occurred"
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,Data Value Address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Data Value Size" "0: Byte,1: Halfword,2: Word,3: Reserved"
|
|
bitfld.long 0x00 8. "DATAVMATCH,Data Value Match" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FUNCTION,Function" "0: Disabled,?,?,?,4: Instruction fetch,5: Data operand read,6: Data operand write,7: Data operand (read + write),?..."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FCT1,MTB_DWT Comparator Function Register 1"
|
|
rbitfld.long 0x00 24. "MATCHED,Comparator match" "0: No match,1: Match occurred"
|
|
bitfld.long 0x00 0.--3. "FUNCTION,Function" "0: Disabled,?,?,?,4: Instruction fetch,5: Data operand read,6: Data operand write,7: Data operand (read + write),?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TBCTRL,MTB_DWT Trace Buffer Control Register"
|
|
rbitfld.long 0x00 28.--31. "NUMCOMP,Number of Comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "ACOMP1,Action based on Comparator 1 match" "0: Trigger TSTOP based on the assertion of..,1: Trigger TSTART based on the assertion of.."
|
|
newline
|
|
bitfld.long 0x00 0. "ACOMP0,Action based on Comparator 0 match" "0: Trigger TSTOP based on the assertion of..,1: Trigger TSTART based on the assertion of.."
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID$1,Component ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
tree.end
|
|
tree "MTB0_ROM (System ROM)"
|
|
base ad:0xF0002000
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "ENTRY$1,Entry"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRY,ENTRY"
|
|
repeat.end
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TABLEMARK,End of Table Marker Register"
|
|
hexmask.long 0x00 0.--31. 1. "MARK,MARK"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "SYSACCESS,System Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "SYSACCESS,SYSACCESS"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID$1,Component ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")
|
|
tree "MTBDWT (DWT)"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
base ad:0xF0001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. "NUMCMP,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--27. 1. "DWTCFGCTRL,DWT configuration controls"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP0,DWT Comparator Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Reference value for comparison"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MASK0,DWT Comparator Mask Register"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FCT0,DWT Comparator Function Register 0"
|
|
rbitfld.long 0x00 24. "MATCHED,Comparator match" "0: MATCHED_0,1: Match occurred"
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,Data Value Address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Data Value Size" "0: DATAVSIZE_0,1: DATAVSIZE_1,2: DATAVSIZE_2,?..."
|
|
bitfld.long 0x00 8. "DATAVMATCH,Data Value Match" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FUNCTION,Function" "0: FUNCTION_0,?,?,?,4: Instruction fetch,5: Data operand read,6: Data operand write,7: Data operand (read + write),?..."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP1,DWT Comparator Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Reference value for comparison"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,DWT Comparator Mask Register"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FCT1,DWT Comparator Function Register 1"
|
|
rbitfld.long 0x00 24. "MATCHED,Comparator match" "0: MATCHED_0,1: Match occurred"
|
|
bitfld.long 0x00 0.--3. "FUNCTION,Function" "0: FUNCTION_0,?,?,?,4: Instruction fetch,5: Data operand read,6: Data operand write,7: Data operand (read + write),?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TBCTRL,DWT Trace Buffer Control Register"
|
|
rbitfld.long 0x00 28.--31. "NUMCOMP,Number of Comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "ACOMP1,Action based on Comparator 1 match" "0: Trigger TSTOP based on the assertion of..,1: Trigger TSTART based on the assertion of.."
|
|
newline
|
|
bitfld.long 0x00 0. "ACOMP0,Action based on Comparator 0 match" "0: Trigger TSTOP based on the assertion of..,1: Trigger TSTART based on the assertion of.."
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID[$1],Component ID Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0xF0001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. "NUMCMP,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--27. 1. "DWTCFGCTRL,DWT configuration controls"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP0,DWT Comparator Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Reference value for comparison"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MASK0,DWT Comparator Mask Register"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FCT0,DWT Comparator Function Register 0"
|
|
rbitfld.long 0x00 24. "MATCHED,Comparator match" "0: MATCHED_0,1: Match occurred"
|
|
bitfld.long 0x00 12.--15. "DATAVADDR0,Data Value Address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Data Value Size" "0: DATAVSIZE_0,1: DATAVSIZE_1,2: DATAVSIZE_2,?..."
|
|
bitfld.long 0x00 8. "DATAVMATCH,Data Value Match" "0: Perform address comparison,1: Perform data value comparison"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FUNCTION,Function" "0: FUNCTION_0,?,?,?,4: Instruction fetch,5: Data operand read,6: Data operand write,7: Data operand (read + write),?..."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP1,DWT Comparator Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Reference value for comparison"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MASK1,DWT Comparator Mask Register"
|
|
bitfld.long 0x00 0.--4. "MASK,MASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FCT1,DWT Comparator Function Register 1"
|
|
rbitfld.long 0x00 24. "MATCHED,Comparator match" "0: MATCHED_0,1: Match occurred"
|
|
bitfld.long 0x00 0.--3. "FUNCTION,Function" "0: FUNCTION_0,?,?,?,4: Instruction fetch,5: Data operand read,6: Data operand write,7: Data operand (read + write),?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TBCTRL,DWT Trace Buffer Control Register"
|
|
rbitfld.long 0x00 28.--31. "NUMCOMP,Number of Comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "ACOMP1,Action based on Comparator 1 match" "0: Trigger TSTOP based on the assertion of..,1: Trigger TSTART based on the assertion of.."
|
|
newline
|
|
bitfld.long 0x00 0. "ACOMP0,Action based on Comparator 0 match" "0: Trigger TSTOP based on the assertion of..,1: Trigger TSTART based on the assertion of.."
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVICECFG,Device Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICECFG,DEVICECFG"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DEVICETYPID,Device Type Identifier Register"
|
|
hexmask.long 0x00 0.--31. 1. "DEVICETYPID,DEVICETYPID"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID[$1],Component ID Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "MUA (Messaging Unit Processor A-side)"
|
|
base ad:0x40025000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VER,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PAR,Parameter Register"
|
|
hexmask.long 0x00 0.--31. 1. "PARAMETER,This bitfield contains the parameter settings of MUA"
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TR[$1],Transmit Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "RR[$1],Receive Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
|
|
repeat.end
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 28.--31. "GIPn,GIPn" "0: MUA general purpose interrupt n is not pending,1: MUA general purpose interrupt n is pending,?..."
|
|
rbitfld.long 0x00 24.--27. "RFn,RFn" "0: MUA RRn register is not full (default),1: MUA RRn register has received data from MUB..,?..."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TEn,TEn" "0: MUA TRn register is not empty,1: MUA TRn register is empty (default),?..."
|
|
rbitfld.long 0x00 12.--14. "PM,PM" "0: The MUB processor is in Run Mode,1: The MUB processor is in COO Mode,2: The MUB processor is in WAIT Mode,3: The MUB processor is in STOP/VLPS Mode,4: The MUB processor is in LLS/VLLS Mode,?..."
|
|
newline
|
|
eventfld.long 0x00 11. "MURIP,MURIP" "0: Processor B did not issue MU reset,1: Processor B issued MU reset"
|
|
eventfld.long 0x00 10. "RAIP,RAIP" "0: Processor B did not enter reset,1: Processor B entered reset"
|
|
newline
|
|
eventfld.long 0x00 9. "RDIP,RDIP" "0: Processor B did not exit reset,1: Processor B exited from reset"
|
|
rbitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the MUA in..,1: MUA initiated flags update processing"
|
|
newline
|
|
eventfld.long 0x00 7. "HRIP,HRIP" "0: MUB didn't issue hardware reset to Processor A,1: MUB had initiated a hardware reset to.."
|
|
rbitfld.long 0x00 4. "EP,EP" "0: The MUA side event is not pending (default),1: The MUA side event is pending"
|
|
newline
|
|
eventfld.long 0x00 3. "NMIC,NMIC" "0: Default,1: Writing 1 clears the NMI bit in the MUB CR.."
|
|
rbitfld.long 0x00 0.--2. "Fn,Fn" "0: Fn bit in the MUB CR register is written 0..,1: Fn bit in the MUB CR register is written 1,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables MUA General Interrupt n,1: Enables MUA General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables MUA Receive Interrupt n,1: Enables MUA Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables MUA Transmit Interrupt n,1: Enables MUA Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: MUA General Interrupt n is not requested to..,1: MUA General Interrupt n is requested to the MUB,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "RAIE,RAIE" "0: Disables Processor A-side General Purpose..,1: Enables Processor A-side General Purpose.."
|
|
bitfld.long 0x00 11. "MURIE,MURIE" "0: Disables Processor A-side General Purpose..,1: Enables Processor A-side General Purpose.."
|
|
newline
|
|
bitfld.long 0x00 7. "HRIE,Processor A hardware reset interrupt enable" "0: Disables Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 6. "RDIE,RDIE" "0: Disables Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the MU reset"
|
|
bitfld.long 0x00 3. "NMI,NMI" "0: Non-maskable interrupt is not issued to the..,1: Non-maskable interrupt is issued to the.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: Clears the Fn bit in the SR register,1: Sets the Fn bit in the SR register,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CCR,Core Control Register"
|
|
bitfld.long 0x00 4.--5. "BOOT,Slave Processor B Boot Config" "0: Boot from Dflash base,?,2: Boot from CM0+ RAM base,?..."
|
|
bitfld.long 0x00 3. "CLKE,MUB clock enable" "0: MUB platform clock gated when MUB-side enters..,1: MUB platform clock kept running after.."
|
|
newline
|
|
bitfld.long 0x00 2. "RSTH,Processor B Reset Hold" "0: Release Processor B from reset,1: Hold Processor B in reset"
|
|
bitfld.long 0x00 1. "HRM,When set HR bit in MUB CCR has no effect" "0: HR bit in MUB CCR is not masked enables the..,1: HR bit in MUB CCR is masked disables the.."
|
|
newline
|
|
bitfld.long 0x00 0. "HR,HR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "MUB (Messaging Unit Processor B-side)"
|
|
base ad:0x41024000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VER,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PAR,Parameter Register"
|
|
hexmask.long 0x00 0.--31. 1. "PARAMETER,This bitfield contains the parameter settings of MUB"
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TR[$1],Transmit Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "RR[$1],Receive Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
|
|
repeat.end
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 28.--31. "GIPn,GIPn" "0: MUB general purpose interrupt n is not pending,1: MUB general purpose interrupt n is pending,?..."
|
|
rbitfld.long 0x00 24.--27. "RFn,RFn" "0: MUB RRn register is not full (default),1: MUB RRn register has received data from MUA..,?..."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TEn,TEn" "0: MUB TRn register is not empty,1: MUB TRn register is empty (default),?..."
|
|
rbitfld.long 0x00 12.--14. "PM,PM" "0: The MUA processor is in Run Mode,1: The MUA processor is in COO Mode,2: The MUA processor is in WAIT Mode,3: The MUA processor is in STOP/VLPS Mode,4: The MUA processor is in LLS/VLLS Mode,?..."
|
|
newline
|
|
eventfld.long 0x00 11. "MURIP,MURIP" "0: Processor A did not issue MU reset,1: Processor A issued MU reset"
|
|
eventfld.long 0x00 10. "RAIP,RAIP" "0: Processor A did not enter reset,1: Processor A entered reset"
|
|
newline
|
|
eventfld.long 0x00 9. "RDIP,RDIP" "0: Processor A did not exit reset,1: Processor A exited from reset"
|
|
rbitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the MUB in..,1: MUB initiated flags update processing"
|
|
newline
|
|
eventfld.long 0x00 7. "HRIP,HRIP" "0: MUA didn't issue hardware reset to Processor B,1: MUA had initiated a hardware reset to.."
|
|
rbitfld.long 0x00 4. "EP,EP" "0: The MUB side event is not pending (default),1: The MUB side event is pending"
|
|
newline
|
|
eventfld.long 0x00 3. "NMIC,NMIC" "0: Default,1: Writing 1 clears the NMI bit in the MUA CR.."
|
|
rbitfld.long 0x00 0.--2. "Fn,Fn" "0: Fn bit in the MUA CR register is written 0..,1: Fn bit in the MUA CR register is written 1,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables MUB General Interrupt n,1: Enables MUB General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables MUB Receive Interrupt n,1: Enables MUB Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables MUB Transmit Interrupt n,1: Enables MUB Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: MUB General Interrupt n is not requested to..,1: MUB General Interrupt n is requested to the MUA,?..."
|
|
newline
|
|
bitfld.long 0x00 12. "RAIE,RAIE" "0: Disables Processor B-side General Purpose..,1: Enables Processor B-side General Purpose.."
|
|
bitfld.long 0x00 11. "MURIE,MURIE" "0: Disables Processor B-side General Purpose..,1: Enables Processor B-side General Purpose.."
|
|
newline
|
|
bitfld.long 0x00 7. "HRIE,Processor B hardware reset interrupt enable" "0: Disables Processor B General Purpose..,1: Enables Processor B General Purpose Interrupt.."
|
|
bitfld.long 0x00 6. "RDIE,RDIE" "0: Disables Processor B General Purpose..,1: Enables Processor B General Purpose Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the MU reset"
|
|
bitfld.long 0x00 3. "NMI,NMI" "0: Non-maskable interrupt is not issued to the..,1: Non-maskable interrupt is issued to the.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: Clears the Fn bit in the SR register,1: Sets the Fn bit in the SR register,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CCR,Core Control Register"
|
|
bitfld.long 0x00 4.--5. "BOOT,Slave Processor A Boot Config" "0: Boot from Pflash base,?,2: Boot from CM4 RAM base,?..."
|
|
bitfld.long 0x00 3. "CLKE,MUA clock enable" "0: MUA platform clock gated when MUA-side enters..,1: MUA platform clock kept running after.."
|
|
newline
|
|
bitfld.long 0x00 2. "RSTH,Processor A Reset Hold" "0: Release Processor A from reset,1: Hold Processor A in reset"
|
|
bitfld.long 0x00 1. "HRM,When set HR bit in MUA CCR has no effect" "0: HR bit in MUA CCR is not masked enables the..,1: HR bit in MUA CCR is masked disables the.."
|
|
newline
|
|
bitfld.long 0x00 0. "HR,HR" "0: De-assert Hardware reset to the Processor A,1: Assert Hardware reset to the Processor A"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "NVIC"
|
|
base ad:0xE000E100
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC_ISER,Interrupt Set Enable Register"
|
|
bitfld.long 0x00 31. "SETENA31,PORTC and PORTD Pin detect interrupt set-enable bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: enable PORTC and PORTD Pin detect.."
|
|
bitfld.long 0x00 30. "SETENA30,PORTA Pin detect interrupt set-enable bit" "0: write: no effect read: PORTA Pin detect..,1: write: enable PORTA Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "SETENA29,LCD interrupt set-enable bit" "0: write: no effect read: LCD interrupt disabled,1: write: enable LCD interrupt read: LCD.."
|
|
bitfld.long 0x00 28. "SETENA28,Low-Power Timer interrupt set-enable bit" "0: write: no effect read: Low-Power Timer..,1: write: enable Low-Power Timer interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 27. "SETENA27,Reserved iv 43 interrupt set-enable bit" "0: write: no effect read: Reserved iv 43..,1: write: enable Reserved iv 43 interrupt read:.."
|
|
bitfld.long 0x00 26. "SETENA26,Reserved iv 42 interrupt set-enable bit" "0: write: no effect read: Reserved iv 42..,1: write: enable Reserved iv 42 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 25. "SETENA25,Digital to Analog Converter interrupt set-enable bit" "0: write: no effect read: Digital to Analog..,1: write: enable Digital to Analog Converter.."
|
|
bitfld.long 0x00 24. "SETENA24,Universal Serial Bus interrupt set-enable bit" "0: write: no effect read: Universal Serial Bus..,1: write: enable Universal Serial Bus interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "SETENA23,Reserved iv 39 interrupt set-enable bit" "0: write: no effect read: Reserved iv 39..,1: write: enable Reserved iv 39 interrupt read:.."
|
|
bitfld.long 0x00 22. "SETENA22,Periodic Interrupt Timer interrupt set-enable bit" "0: write: no effect read: Periodic Interrupt..,1: write: enable Periodic Interrupt Timer.."
|
|
newline
|
|
bitfld.long 0x00 21. "SETENA21,RTC seconds interrupt set-enable bit" "0: write: no effect read: RTC seconds interrupt..,1: write: enable RTC seconds interrupt read: RTC.."
|
|
bitfld.long 0x00 20. "SETENA20,Real-time counter interrupt set-enable bit" "0: write: no effect read: Real-time counter..,1: write: enable Real-time counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "SETENA19,Timer/PWM module 2 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 2..,1: write: enable Timer/PWM module 2 interrupt.."
|
|
bitfld.long 0x00 18. "SETENA18,Timer/PWM module 1 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 1..,1: write: enable Timer/PWM module 1 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "SETENA17,Timer/PWM module 0 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 0..,1: write: enable Timer/PWM module 0 interrupt.."
|
|
bitfld.long 0x00 16. "SETENA16,Comparator 0 interrupt set-enable bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: enable Comparator 0 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 15. "SETENA15,Analog-to-Digital Converter 0 interrupt set-enable bit" "0: write: no effect read: Analog-to-Digital..,1: write: enable Analog-to-Digital Converter 0.."
|
|
bitfld.long 0x00 14. "SETENA14,UART2 or FLEXIO interrupt set-enable bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: enable UART2 or FLEXIO interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 13. "SETENA13,LPUART1 status and error interrupt set-enable bit" "0: write: no effect read: LPUART1 status and..,1: write: enable LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "SETENA12,LPUART0 status and error interrupt set-enable bit" "0: write: no effect read: LPUART0 status and..,1: write: enable LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "SETENA11,Serial Peripheral Interface 1 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 1.."
|
|
bitfld.long 0x00 10. "SETENA10,Serial Peripheral Interface 0 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 0.."
|
|
newline
|
|
bitfld.long 0x00 9. "SETENA9,Inter-Integrated Circuit 1 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 1.."
|
|
bitfld.long 0x00 8. "SETENA8,Inter-Integrated Circuit 0 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 7. "SETENA7,Low Leakage Wakeup interrupt set-enable bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: enable Low Leakage Wakeup interrupt.."
|
|
bitfld.long 0x00 6. "SETENA6,Low-voltage detect low-voltage warning interrupt set-enable bit" "0: write: no effect read: Low-voltage detect..,1: write: enable Low-voltage detect low-voltage.."
|
|
newline
|
|
bitfld.long 0x00 5. "SETENA5,Command complete and read collision interrupt set-enable bit" "0: write: no effect read: Command complete and..,1: write: enable Command complete and read.."
|
|
bitfld.long 0x00 4. "SETENA4,Reserved iv 20 interrupt set-enable bit" "0: write: no effect read: Reserved iv 20..,1: write: enable Reserved iv 20 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 3. "SETENA3,DMA channel 3 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: enable DMA channel 3 transfer complete.."
|
|
bitfld.long 0x00 2. "SETENA2,DMA channel 2 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: enable DMA channel 2 transfer complete.."
|
|
newline
|
|
bitfld.long 0x00 1. "SETENA1,DMA channel 1 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: enable DMA channel 1 transfer complete.."
|
|
bitfld.long 0x00 0. "SETENA0,DMA channel 0 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: enable DMA channel 0 transfer complete.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC_ISER,Interrupt Set Enable Register"
|
|
bitfld.long 0x00 31. "SETENA31,PORTC and PORTD Pin detect interrupt set-enable bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: enable PORTC and PORTD Pin detect.."
|
|
bitfld.long 0x00 30. "SETENA30,PORTA Pin detect interrupt set-enable bit" "0: write: no effect read: PORTA Pin detect..,1: write: enable PORTA Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "SETENA29,Reserved iv 45 interrupt set-enable bit" "0: write: no effect read: Reserved iv 45..,1: write: enable Reserved iv 45 interrupt read:.."
|
|
bitfld.long 0x00 28. "SETENA28,Low-Power Timer interrupt set-enable bit" "0: write: no effect read: Low-Power Timer..,1: write: enable Low-Power Timer interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 27. "SETENA27,Reserved iv 43 interrupt set-enable bit" "0: write: no effect read: Reserved iv 43..,1: write: enable Reserved iv 43 interrupt read:.."
|
|
bitfld.long 0x00 26. "SETENA26,Reserved iv 42 interrupt set-enable bit" "0: write: no effect read: Reserved iv 42..,1: write: enable Reserved iv 42 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 25. "SETENA25,Digital to Analog Converter interrupt set-enable bit" "0: write: no effect read: Digital to Analog..,1: write: enable Digital to Analog Converter.."
|
|
bitfld.long 0x00 24. "SETENA24,Universal Serial Bus interrupt set-enable bit" "0: write: no effect read: Universal Serial Bus..,1: write: enable Universal Serial Bus interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "SETENA23,Reserved iv 39 interrupt set-enable bit" "0: write: no effect read: Reserved iv 39..,1: write: enable Reserved iv 39 interrupt read:.."
|
|
bitfld.long 0x00 22. "SETENA22,Periodic Interrupt Timer interrupt set-enable bit" "0: write: no effect read: Periodic Interrupt..,1: write: enable Periodic Interrupt Timer.."
|
|
newline
|
|
bitfld.long 0x00 21. "SETENA21,RTC seconds interrupt set-enable bit" "0: write: no effect read: RTC seconds interrupt..,1: write: enable RTC seconds interrupt read: RTC.."
|
|
bitfld.long 0x00 20. "SETENA20,Real-time counter interrupt set-enable bit" "0: write: no effect read: Real-time counter..,1: write: enable Real-time counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "SETENA19,Timer/PWM module 2 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 2..,1: write: enable Timer/PWM module 2 interrupt.."
|
|
bitfld.long 0x00 18. "SETENA18,Timer/PWM module 1 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 1..,1: write: enable Timer/PWM module 1 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "SETENA17,Timer/PWM module 0 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 0..,1: write: enable Timer/PWM module 0 interrupt.."
|
|
bitfld.long 0x00 16. "SETENA16,Comparator 0 interrupt set-enable bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: enable Comparator 0 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 15. "SETENA15,Analog-to-Digital Converter 0 interrupt set-enable bit" "0: write: no effect read: Analog-to-Digital..,1: write: enable Analog-to-Digital Converter 0.."
|
|
bitfld.long 0x00 14. "SETENA14,UART2 or FLEXIO interrupt set-enable bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: enable UART2 or FLEXIO interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 13. "SETENA13,LPUART1 status and error interrupt set-enable bit" "0: write: no effect read: LPUART1 status and..,1: write: enable LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "SETENA12,LPUART0 status and error interrupt set-enable bit" "0: write: no effect read: LPUART0 status and..,1: write: enable LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "SETENA11,Serial Peripheral Interface 1 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 1.."
|
|
bitfld.long 0x00 10. "SETENA10,Serial Peripheral Interface 0 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 0.."
|
|
newline
|
|
bitfld.long 0x00 9. "SETENA9,Inter-Integrated Circuit 1 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 1.."
|
|
bitfld.long 0x00 8. "SETENA8,Inter-Integrated Circuit 0 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 7. "SETENA7,Low Leakage Wakeup interrupt set-enable bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: enable Low Leakage Wakeup interrupt.."
|
|
bitfld.long 0x00 6. "SETENA6,Low-voltage detect low-voltage warning interrupt set-enable bit" "0: write: no effect read: Low-voltage detect..,1: write: enable Low-voltage detect low-voltage.."
|
|
newline
|
|
bitfld.long 0x00 5. "SETENA5,Command complete and read collision interrupt set-enable bit" "0: write: no effect read: Command complete and..,1: write: enable Command complete and read.."
|
|
bitfld.long 0x00 4. "SETENA4,Reserved iv 20 interrupt set-enable bit" "0: write: no effect read: Reserved iv 20..,1: write: enable Reserved iv 20 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 3. "SETENA3,DMA channel 3 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: enable DMA channel 3 transfer complete.."
|
|
bitfld.long 0x00 2. "SETENA2,DMA channel 2 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: enable DMA channel 2 transfer complete.."
|
|
newline
|
|
bitfld.long 0x00 1. "SETENA1,DMA channel 1 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: enable DMA channel 1 transfer complete.."
|
|
bitfld.long 0x00 0. "SETENA0,DMA channel 0 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: enable DMA channel 0 transfer complete.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC_ISER,Interrupt Set Enable Register"
|
|
eventfld.long 0x00 31. "SETENA31,INTMUX1 channel7 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel7..,1: write: enable INTMUX1 channel7 interrupt.."
|
|
eventfld.long 0x00 30. "SETENA30,INTMUX1 channel6 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel6..,1: write: enable INTMUX1 channel6 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 29. "SETENA29,INTMUX1 channel5 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel5..,1: write: enable INTMUX1 channel5 interrupt.."
|
|
eventfld.long 0x00 28. "SETENA28,INTMUX1 channel4 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel4..,1: write: enable INTMUX1 channel4 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 27. "SETENA27,INTMUX1 channel3 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel3..,1: write: enable INTMUX1 channel3 interrupt.."
|
|
eventfld.long 0x00 26. "SETENA26,INTMUX1 channel2 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel2..,1: write: enable INTMUX1 channel2 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 25. "SETENA25,INTMUX1 channel1 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel1..,1: write: enable INTMUX1 channel1 interrupt.."
|
|
eventfld.long 0x00 24. "SETENA24,INTMUX1 channel0 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX1 channel0..,1: write: enable INTMUX1 channel0 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 23. "SETENA23,RTC Alarm interrupt set-enable bit" "0: write: no effect read: RTC Alarm interrupt..,1: write: enable RTC Alarm interrupt read: RTC.."
|
|
eventfld.long 0x00 22. "SETENA22,LPCMP1 interrupt set-enable bit" "0: write: no effect read: LPCMP1 interrupt..,1: write: enable LPCMP1 interrupt read: LPCMP1.."
|
|
newline
|
|
eventfld.long 0x00 21. "SETENA21,PORTE Pin detect interrupt set-enable bit" "0: write: no effect read: PORTE Pin detect..,1: write: enable PORTE Pin detect interrupt.."
|
|
eventfld.long 0x00 20. "SETENA20,LPUART3 status and error interrupt set-enable bit" "0: write: no effect read: LPUART3 status and..,1: write: enable LPUART3 status and error.."
|
|
newline
|
|
eventfld.long 0x00 19. "SETENA19,Serial Peripheral Interface 3 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 3.."
|
|
eventfld.long 0x00 18. "SETENA18,Reserved iv 34 interrupt set-enable bit" "0: write: no effect read: Reserved iv 34..,1: write: enable Reserved iv 34 interrupt read:.."
|
|
newline
|
|
eventfld.long 0x00 17. "SETENA17,Reserved iv 33 interrupt set-enable bit" "0: write: no effect read: Reserved iv 33..,1: write: enable Reserved iv 33 interrupt read:.."
|
|
eventfld.long 0x00 16. "SETENA16,Inter-Integrated Circuit 3 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 3.."
|
|
newline
|
|
eventfld.long 0x00 15. "SETENA15,Timer/PWM module 3 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 3..,1: write: enable Timer/PWM module 3 interrupt.."
|
|
eventfld.long 0x00 14. "SETENA14,Low-Power Timer 2 interrupt set-enable bit" "0: write: no effect read: Low-Power Timer 2..,1: write: enable Low-Power Timer 2 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 13. "SETENA13,Low Power Periodic Interrupt Timer 1 interrupt set-enable bit" "0: write: no effect read: Low Power Periodic..,1: write: enable Low Power Periodic Interrupt.."
|
|
eventfld.long 0x00 12. "SETENA12,TRNG interrupt set-enable bit" "0: write: no effect read: TRNG interrupt disabled,1: write: enable TRNG interrupt read: TRNG.."
|
|
newline
|
|
eventfld.long 0x00 11. "SETENA11,Cryptographic Acceleration Unit version 3 Security Violation interrupt set-enable bit" "0: write: no effect read: Cryptographic..,1: write: enable Cryptographic Acceleration Unit.."
|
|
eventfld.long 0x00 10. "SETENA10,Cryptographic Acceleration Unit version 3 Task Complete interrupt set-enable bit" "0: write: no effect read: Cryptographic..,1: write: enable Cryptographic Acceleration Unit.."
|
|
newline
|
|
eventfld.long 0x00 9. "SETENA9,WDOG1 interrupt set-enable bit" "0: write: no effect read: WDOG1 interrupt disabled,1: write: enable WDOG1 interrupt read: WDOG1.."
|
|
eventfld.long 0x00 8. "SETENA8,Message Unit Side B interrupt set-enable bit" "0: write: no effect read: Message Unit Side B..,1: write: enable Message Unit Side B interrupt.."
|
|
newline
|
|
eventfld.long 0x00 7. "SETENA7,Low leakage wakeup 1 interrupt set-enable bit" "0: write: no effect read: Low leakage wakeup 1..,1: write: enable Low leakage wakeup 1 interrupt.."
|
|
eventfld.long 0x00 6. "SETENA6,MSMC (SMC1) interrupt interrupt set-enable bit" "0: write: no effect read: MSMC (SMC1) interrupt..,1: write: enable MSMC (SMC1) interrupt interrupt.."
|
|
newline
|
|
eventfld.long 0x00 5. "SETENA5,DMA1 channel 0-7 error interrupt interrupt set-enable bit" "0: write: no effect read: DMA1 channel 0-7 error..,1: write: enable DMA1 channel 0-7 error.."
|
|
eventfld.long 0x00 4. "SETENA4,DMA1 channel 3/7 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA1 channel 3/7..,1: write: enable DMA1 channel 3/7 transfer.."
|
|
newline
|
|
eventfld.long 0x00 3. "SETENA3,DMA1 channel 2/6 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA1 channel 2/6..,1: write: enable DMA1 channel 2/6 transfer.."
|
|
eventfld.long 0x00 2. "SETENA2,DMA1 channel 1/5 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA1 channel 1/5..,1: write: enable DMA1 channel 1/5 transfer.."
|
|
newline
|
|
eventfld.long 0x00 1. "SETENA1,DMA1 channel 0/4 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA1 channel 0/4..,1: write: enable DMA1 channel 0/4 transfer.."
|
|
eventfld.long 0x00 0. "SETENA0,Cross Trigger Interface 1 interrupt set-enable bit" "0: write: no effect read: Cross Trigger..,1: write: enable Cross Trigger Interface 1.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "NVICISER$1,Interrupt Set Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt set enable bits"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC_ICER,Interrupt Clear Enable Register"
|
|
bitfld.long 0x00 31. "CLRENA31,PORTC and PORTD Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: disable PORTC and PORTD Pin detect.."
|
|
bitfld.long 0x00 30. "CLRENA30,PORTA Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTA Pin detect..,1: write: disable PORTA Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "CLRENA29,Reserved iv 45 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 45..,1: write: disable Reserved iv 45 interrupt read:.."
|
|
bitfld.long 0x00 28. "CLRENA28,Low-Power Timer interrupt clear-enable bit" "0: write: no effect read: Low-Power Timer..,1: write: disable Low-Power Timer interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "CLRENA27,Reserved iv 43 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 43..,1: write: disable Reserved iv 43 interrupt read:.."
|
|
bitfld.long 0x00 26. "CLRENA26,Reserved iv 42 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 42..,1: write: disable Reserved iv 42 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 25. "CLRENA25,Digital to Analog Converter interrupt clear-enable bit" "0: write: no effect read: Digital to Analog..,1: write: disable Digital to Analog Converter.."
|
|
bitfld.long 0x00 24. "CLRENA24,Universal Serial Bus interrupt clear-enable bit" "0: write: no effect read: Universal Serial Bus..,1: write: disable Universal Serial Bus interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "CLRENA23,Reserved iv 39 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 39..,1: write: disable Reserved iv 39 interrupt read:.."
|
|
bitfld.long 0x00 22. "CLRENA22,Periodic Interrupt Timer interrupt clear-enable bit" "0: write: no effect read: Periodic Interrupt..,1: write: disable Periodic Interrupt Timer.."
|
|
newline
|
|
bitfld.long 0x00 21. "CLRENA21,RTC seconds interrupt clear-enable bit" "0: write: no effect read: RTC seconds interrupt..,1: write: disable RTC seconds interrupt read:.."
|
|
bitfld.long 0x00 20. "CLRENA20,Real-time counter interrupt clear-enable bit" "0: write: no effect read: Real-time counter..,1: write: disable Real-time counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "CLRENA19,Timer/PWM module 2 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 2..,1: write: disable Timer/PWM module 2 interrupt.."
|
|
bitfld.long 0x00 18. "CLRENA18,Timer/PWM module 1 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 1..,1: write: disable Timer/PWM module 1 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "CLRENA17,Timer/PWM module 0 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 0..,1: write: disable Timer/PWM module 0 interrupt.."
|
|
bitfld.long 0x00 16. "CLRENA16,Comparator 0 interrupt clear-enable bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: disable Comparator 0 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 15. "CLRENA15,Analog-to-Digital Converter 0 interrupt clear-enable bit" "0: write: no effect read: Analog-to-Digital..,1: write: disable Analog-to-Digital Converter 0.."
|
|
bitfld.long 0x00 14. "CLRENA14,UART2 or FLEXIO interrupt clear-enable bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: disable UART2 or FLEXIO interrupt.."
|
|
newline
|
|
bitfld.long 0x00 13. "CLRENA13,LPUART1 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART1 status and..,1: write: disable LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "CLRENA12,LPUART0 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART0 status and..,1: write: disable LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "CLRENA11,Serial Peripheral Interface 1 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 1.."
|
|
bitfld.long 0x00 10. "CLRENA10,Serial Peripheral Interface 0 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 0.."
|
|
newline
|
|
bitfld.long 0x00 9. "CLRENA9,Inter-Integrated Circuit 1 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 1.."
|
|
bitfld.long 0x00 8. "CLRENA8,Inter-Integrated Circuit 0 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 7. "CLRENA7,Low Leakage Wakeup interrupt clear-enable bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: disable Low Leakage Wakeup interrupt.."
|
|
bitfld.long 0x00 6. "CLRENA6,Low-voltage detect low-voltage warning interrupt clear-enable bit" "0: write: no effect read: Low-voltage detect..,1: write: disable Low-voltage detect low-voltage.."
|
|
newline
|
|
bitfld.long 0x00 5. "CLRENA5,Command complete and read collision interrupt clear-enable bit" "0: write: no effect read: Command complete and..,1: write: disable Command complete and read.."
|
|
bitfld.long 0x00 4. "CLRENA4,Reserved iv 20 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 20..,1: write: disable Reserved iv 20 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 3. "CLRENA3,DMA channel 3 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: disable DMA channel 3 transfer.."
|
|
bitfld.long 0x00 2. "CLRENA2,DMA channel 2 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: disable DMA channel 2 transfer.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLRENA1,DMA channel 1 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: disable DMA channel 1 transfer.."
|
|
bitfld.long 0x00 0. "CLRENA0,DMA channel 0 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: disable DMA channel 0 transfer.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC_ICER,Interrupt Clear Enable Register"
|
|
bitfld.long 0x00 31. "CLRENA31,PORTC and PORTD Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: disable PORTC and PORTD Pin detect.."
|
|
bitfld.long 0x00 30. "CLRENA30,PORTA Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTA Pin detect..,1: write: disable PORTA Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "CLRENA29,LCD interrupt clear-enable bit" "0: write: no effect read: LCD interrupt disabled,1: write: disable LCD interrupt read: LCD.."
|
|
bitfld.long 0x00 28. "CLRENA28,Low-Power Timer interrupt clear-enable bit" "0: write: no effect read: Low-Power Timer..,1: write: disable Low-Power Timer interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "CLRENA27,Reserved iv 43 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 43..,1: write: disable Reserved iv 43 interrupt read:.."
|
|
bitfld.long 0x00 26. "CLRENA26,Reserved iv 42 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 42..,1: write: disable Reserved iv 42 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 25. "CLRENA25,Digital to Analog Converter interrupt clear-enable bit" "0: write: no effect read: Digital to Analog..,1: write: disable Digital to Analog Converter.."
|
|
bitfld.long 0x00 24. "CLRENA24,Universal Serial Bus interrupt clear-enable bit" "0: write: no effect read: Universal Serial Bus..,1: write: disable Universal Serial Bus interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "CLRENA23,Reserved iv 39 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 39..,1: write: disable Reserved iv 39 interrupt read:.."
|
|
bitfld.long 0x00 22. "CLRENA22,Periodic Interrupt Timer interrupt clear-enable bit" "0: write: no effect read: Periodic Interrupt..,1: write: disable Periodic Interrupt Timer.."
|
|
newline
|
|
bitfld.long 0x00 21. "CLRENA21,RTC seconds interrupt clear-enable bit" "0: write: no effect read: RTC seconds interrupt..,1: write: disable RTC seconds interrupt read:.."
|
|
bitfld.long 0x00 20. "CLRENA20,Real-time counter interrupt clear-enable bit" "0: write: no effect read: Real-time counter..,1: write: disable Real-time counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "CLRENA19,Timer/PWM module 2 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 2..,1: write: disable Timer/PWM module 2 interrupt.."
|
|
bitfld.long 0x00 18. "CLRENA18,Timer/PWM module 1 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 1..,1: write: disable Timer/PWM module 1 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "CLRENA17,Timer/PWM module 0 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 0..,1: write: disable Timer/PWM module 0 interrupt.."
|
|
bitfld.long 0x00 16. "CLRENA16,Comparator 0 interrupt clear-enable bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: disable Comparator 0 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 15. "CLRENA15,Analog-to-Digital Converter 0 interrupt clear-enable bit" "0: write: no effect read: Analog-to-Digital..,1: write: disable Analog-to-Digital Converter 0.."
|
|
bitfld.long 0x00 14. "CLRENA14,UART2 or FLEXIO interrupt clear-enable bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: disable UART2 or FLEXIO interrupt.."
|
|
newline
|
|
bitfld.long 0x00 13. "CLRENA13,LPUART1 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART1 status and..,1: write: disable LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "CLRENA12,LPUART0 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART0 status and..,1: write: disable LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "CLRENA11,Serial Peripheral Interface 1 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 1.."
|
|
bitfld.long 0x00 10. "CLRENA10,Serial Peripheral Interface 0 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 0.."
|
|
newline
|
|
bitfld.long 0x00 9. "CLRENA9,Inter-Integrated Circuit 1 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 1.."
|
|
bitfld.long 0x00 8. "CLRENA8,Inter-Integrated Circuit 0 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 7. "CLRENA7,Low Leakage Wakeup interrupt clear-enable bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: disable Low Leakage Wakeup interrupt.."
|
|
bitfld.long 0x00 6. "CLRENA6,Low-voltage detect low-voltage warning interrupt clear-enable bit" "0: write: no effect read: Low-voltage detect..,1: write: disable Low-voltage detect low-voltage.."
|
|
newline
|
|
bitfld.long 0x00 5. "CLRENA5,Command complete and read collision interrupt clear-enable bit" "0: write: no effect read: Command complete and..,1: write: disable Command complete and read.."
|
|
bitfld.long 0x00 4. "CLRENA4,Reserved iv 20 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 20..,1: write: disable Reserved iv 20 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 3. "CLRENA3,DMA channel 3 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: disable DMA channel 3 transfer.."
|
|
bitfld.long 0x00 2. "CLRENA2,DMA channel 2 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: disable DMA channel 2 transfer.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLRENA1,DMA channel 1 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: disable DMA channel 1 transfer.."
|
|
bitfld.long 0x00 0. "CLRENA0,DMA channel 0 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: disable DMA channel 0 transfer.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVICICER0,Interrupt Clear Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC_ICER,Interrupt Clear Enable Register"
|
|
eventfld.long 0x00 31. "CLRENA31,INTMUX1 channel7 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel7..,1: write: disable INTMUX1 channel7 interrupt.."
|
|
eventfld.long 0x00 30. "CLRENA30,INTMUX1 channel6 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel6..,1: write: disable INTMUX1 channel6 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 29. "CLRENA29,INTMUX1 channel5 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel5..,1: write: disable INTMUX1 channel5 interrupt.."
|
|
eventfld.long 0x00 28. "CLRENA28,INTMUX1 channel4 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel4..,1: write: disable INTMUX1 channel4 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 27. "CLRENA27,INTMUX1 channel3 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel3..,1: write: disable INTMUX1 channel3 interrupt.."
|
|
eventfld.long 0x00 26. "CLRENA26,INTMUX1 channel2 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel2..,1: write: disable INTMUX1 channel2 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 25. "CLRENA25,INTMUX1 channel1 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel1..,1: write: disable INTMUX1 channel1 interrupt.."
|
|
eventfld.long 0x00 24. "CLRENA24,INTMUX1 channel0 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX1 channel0..,1: write: disable INTMUX1 channel0 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 23. "CLRENA23,RTC Alarm interrupt clear-enable bit" "0: write: no effect read: RTC Alarm interrupt..,1: write: disable RTC Alarm interrupt read: RTC.."
|
|
eventfld.long 0x00 22. "CLRENA22,LPCMP1 interrupt clear-enable bit" "0: write: no effect read: LPCMP1 interrupt..,1: write: disable LPCMP1 interrupt read: LPCMP1.."
|
|
newline
|
|
eventfld.long 0x00 21. "CLRENA21,PORTE Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTE Pin detect..,1: write: disable PORTE Pin detect interrupt.."
|
|
eventfld.long 0x00 20. "CLRENA20,LPUART3 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART3 status and..,1: write: disable LPUART3 status and error.."
|
|
newline
|
|
eventfld.long 0x00 19. "CLRENA19,Serial Peripheral Interface 3 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 3.."
|
|
eventfld.long 0x00 18. "CLRENA18,Reserved iv 34 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 34..,1: write: disable Reserved iv 34 interrupt read:.."
|
|
newline
|
|
eventfld.long 0x00 17. "CLRENA17,Reserved iv 33 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 33..,1: write: disable Reserved iv 33 interrupt read:.."
|
|
eventfld.long 0x00 16. "CLRENA16,Inter-Integrated Circuit 3 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 3.."
|
|
newline
|
|
eventfld.long 0x00 15. "CLRENA15,Timer/PWM module 3 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 3..,1: write: disable Timer/PWM module 3 interrupt.."
|
|
eventfld.long 0x00 14. "CLRENA14,Low-Power Timer 2 interrupt clear-enable bit" "0: write: no effect read: Low-Power Timer 2..,1: write: disable Low-Power Timer 2 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 13. "CLRENA13,Low Power Periodic Interrupt Timer 1 interrupt clear-enable bit" "0: write: no effect read: Low Power Periodic..,1: write: disable Low Power Periodic Interrupt.."
|
|
eventfld.long 0x00 12. "CLRENA12,TRNG interrupt clear-enable bit" "0: write: no effect read: TRNG interrupt disabled,1: write: disable TRNG interrupt read: TRNG.."
|
|
newline
|
|
eventfld.long 0x00 11. "CLRENA11,Cryptographic Acceleration Unit version 3 Security Violation interrupt clear-enable bit" "0: write: no effect read: Cryptographic..,1: write: disable Cryptographic Acceleration.."
|
|
eventfld.long 0x00 10. "CLRENA10,Cryptographic Acceleration Unit version 3 Task Complete interrupt clear-enable bit" "0: write: no effect read: Cryptographic..,1: write: disable Cryptographic Acceleration.."
|
|
newline
|
|
eventfld.long 0x00 9. "CLRENA9,WDOG1 interrupt clear-enable bit" "0: write: no effect read: WDOG1 interrupt disabled,1: write: disable WDOG1 interrupt read: WDOG1.."
|
|
eventfld.long 0x00 8. "CLRENA8,Message Unit Side B interrupt clear-enable bit" "0: write: no effect read: Message Unit Side B..,1: write: disable Message Unit Side B interrupt.."
|
|
newline
|
|
eventfld.long 0x00 7. "CLRENA7,Low leakage wakeup 1 interrupt clear-enable bit" "0: write: no effect read: Low leakage wakeup 1..,1: write: disable Low leakage wakeup 1 interrupt.."
|
|
eventfld.long 0x00 6. "CLRENA6,MSMC (SMC1) interrupt interrupt clear-enable bit" "0: write: no effect read: MSMC (SMC1) interrupt..,1: write: disable MSMC (SMC1) interrupt.."
|
|
newline
|
|
eventfld.long 0x00 5. "CLRENA5,DMA1 channel 0-7 error interrupt interrupt clear-enable bit" "0: write: no effect read: DMA1 channel 0-7 error..,1: write: disable DMA1 channel 0-7 error.."
|
|
eventfld.long 0x00 4. "CLRENA4,DMA1 channel 3/7 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA1 channel 3/7..,1: write: disable DMA1 channel 3/7 transfer.."
|
|
newline
|
|
eventfld.long 0x00 3. "CLRENA3,DMA1 channel 2/6 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA1 channel 2/6..,1: write: disable DMA1 channel 2/6 transfer.."
|
|
eventfld.long 0x00 2. "CLRENA2,DMA1 channel 1/5 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA1 channel 1/5..,1: write: disable DMA1 channel 1/5 transfer.."
|
|
newline
|
|
eventfld.long 0x00 1. "CLRENA1,DMA1 channel 0/4 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA1 channel 0/4..,1: write: disable DMA1 channel 0/4 transfer.."
|
|
eventfld.long 0x00 0. "CLRENA0,Cross Trigger Interface 1 interrupt clear-enable bit" "0: write: no effect read: Cross Trigger..,1: write: disable Cross Trigger Interface 1.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "NVICICER$1,Interrupt Clear Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISPR,Interrupt Set Pending Register"
|
|
bitfld.long 0x00 31. "SETPEND31,PORTC and PORTD Pin detect interrupt set-pending bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: changes the PORTC and PORTD Pin detect.."
|
|
bitfld.long 0x00 30. "SETPEND30,PORTA Pin detect interrupt set-pending bit" "0: write: no effect read: PORTA Pin detect..,1: write: changes the PORTA Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "SETPEND29,Reserved iv 45 interrupt set-pending bit" "0: write: no effect read: Reserved iv 45..,1: write: changes the Reserved iv 45 interrupt.."
|
|
bitfld.long 0x00 28. "SETPEND28,Low-Power Timer interrupt set-pending bit" "0: write: no effect read: Low-Power Timer..,1: write: changes the Low-Power Timer interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "SETPEND27,Reserved iv 43 interrupt set-pending bit" "0: write: no effect read: Reserved iv 43..,1: write: changes the Reserved iv 43 interrupt.."
|
|
bitfld.long 0x00 26. "SETPEND26,Reserved iv 42 interrupt set-pending bit" "0: write: no effect read: Reserved iv 42..,1: write: changes the Reserved iv 42 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "SETPEND25,Digital to Analog Converter interrupt set-pending bit" "0: write: no effect read: Digital to Analog..,1: write: changes the Digital to Analog.."
|
|
bitfld.long 0x00 24. "SETPEND24,Universal Serial Bus interrupt set-pending bit" "0: write: no effect read: Universal Serial Bus..,1: write: changes the Universal Serial Bus.."
|
|
newline
|
|
bitfld.long 0x00 23. "SETPEND23,Reserved iv 39 interrupt set-pending bit" "0: write: no effect read: Reserved iv 39..,1: write: changes the Reserved iv 39 interrupt.."
|
|
bitfld.long 0x00 22. "SETPEND22,Periodic Interrupt Timer interrupt set-pending bit" "0: write: no effect read: Periodic Interrupt..,1: write: changes the Periodic Interrupt Timer.."
|
|
newline
|
|
bitfld.long 0x00 21. "SETPEND21,RTC seconds interrupt set-pending bit" "0: write: no effect read: RTC seconds interrupt..,1: write: changes the RTC seconds interrupt.."
|
|
bitfld.long 0x00 20. "SETPEND20,Real-time counter interrupt set-pending bit" "0: write: no effect read: Real-time counter..,1: write: changes the Real-time counter.."
|
|
newline
|
|
bitfld.long 0x00 19. "SETPEND19,Timer/PWM module 2 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 2..,1: write: changes the Timer/PWM module 2.."
|
|
bitfld.long 0x00 18. "SETPEND18,Timer/PWM module 1 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 1..,1: write: changes the Timer/PWM module 1.."
|
|
newline
|
|
bitfld.long 0x00 17. "SETPEND17,Timer/PWM module 0 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 0..,1: write: changes the Timer/PWM module 0.."
|
|
bitfld.long 0x00 16. "SETPEND16,Comparator 0 interrupt set-pending bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: changes the Comparator 0 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "SETPEND15,Analog-to-Digital Converter 0 interrupt set-pending bit" "0: write: no effect read: Analog-to-Digital..,1: write: changes the Analog-to-Digital.."
|
|
bitfld.long 0x00 14. "SETPEND14,UART2 or FLEXIO interrupt set-pending bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: changes the UART2 or FLEXIO interrupt.."
|
|
newline
|
|
bitfld.long 0x00 13. "SETPEND13,LPUART1 status and error interrupt set-pending bit" "0: write: no effect read: LPUART1 status and..,1: write: changes the LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "SETPEND12,LPUART0 status and error interrupt set-pending bit" "0: write: no effect read: LPUART0 status and..,1: write: changes the LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "SETPEND11,Serial Peripheral Interface 1 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
|
|
bitfld.long 0x00 10. "SETPEND10,Serial Peripheral Interface 0 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
|
|
newline
|
|
bitfld.long 0x00 9. "SETPEND9,Inter-Integrated Circuit 1 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 1.."
|
|
bitfld.long 0x00 8. "SETPEND8,Inter-Integrated Circuit 0 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 7. "SETPEND7,Low Leakage Wakeup interrupt set-pending bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: changes the Low Leakage Wakeup.."
|
|
bitfld.long 0x00 6. "SETPEND6,Low-voltage detect low-voltage warning interrupt set-pending bit" "0: write: no effect read: Low-voltage detect..,1: write: changes the Low-voltage detect.."
|
|
newline
|
|
bitfld.long 0x00 5. "SETPEND5,Command complete and read collision interrupt set-pending bit" "0: write: no effect read: Command complete and..,1: write: changes the Command complete and read.."
|
|
bitfld.long 0x00 4. "SETPEND4,Reserved iv 20 interrupt set-pending bit" "0: write: no effect read: Reserved iv 20..,1: write: changes the Reserved iv 20 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 3. "SETPEND3,DMA channel 3 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: changes the DMA channel 3 transfer.."
|
|
bitfld.long 0x00 2. "SETPEND2,DMA channel 2 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: changes the DMA channel 2 transfer.."
|
|
newline
|
|
bitfld.long 0x00 1. "SETPEND1,DMA channel 1 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: changes the DMA channel 1 transfer.."
|
|
bitfld.long 0x00 0. "SETPEND0,DMA channel 0 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: changes the DMA channel 0 transfer.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISPR,Interrupt Set Pending Register"
|
|
bitfld.long 0x00 31. "SETPEND31,PORTC and PORTD Pin detect interrupt set-pending bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: changes the PORTC and PORTD Pin detect.."
|
|
bitfld.long 0x00 30. "SETPEND30,PORTA Pin detect interrupt set-pending bit" "0: write: no effect read: PORTA Pin detect..,1: write: changes the PORTA Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "SETPEND29,LCD interrupt set-pending bit" "0: write: no effect read: LCD interrupt is not..,1: write: changes the LCD interrupt state to.."
|
|
bitfld.long 0x00 28. "SETPEND28,Low-Power Timer interrupt set-pending bit" "0: write: no effect read: Low-Power Timer..,1: write: changes the Low-Power Timer interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "SETPEND27,Reserved iv 43 interrupt set-pending bit" "0: write: no effect read: Reserved iv 43..,1: write: changes the Reserved iv 43 interrupt.."
|
|
bitfld.long 0x00 26. "SETPEND26,Reserved iv 42 interrupt set-pending bit" "0: write: no effect read: Reserved iv 42..,1: write: changes the Reserved iv 42 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "SETPEND25,Digital to Analog Converter interrupt set-pending bit" "0: write: no effect read: Digital to Analog..,1: write: changes the Digital to Analog.."
|
|
bitfld.long 0x00 24. "SETPEND24,Universal Serial Bus interrupt set-pending bit" "0: write: no effect read: Universal Serial Bus..,1: write: changes the Universal Serial Bus.."
|
|
newline
|
|
bitfld.long 0x00 23. "SETPEND23,Reserved iv 39 interrupt set-pending bit" "0: write: no effect read: Reserved iv 39..,1: write: changes the Reserved iv 39 interrupt.."
|
|
bitfld.long 0x00 22. "SETPEND22,Periodic Interrupt Timer interrupt set-pending bit" "0: write: no effect read: Periodic Interrupt..,1: write: changes the Periodic Interrupt Timer.."
|
|
newline
|
|
bitfld.long 0x00 21. "SETPEND21,RTC seconds interrupt set-pending bit" "0: write: no effect read: RTC seconds interrupt..,1: write: changes the RTC seconds interrupt.."
|
|
bitfld.long 0x00 20. "SETPEND20,Real-time counter interrupt set-pending bit" "0: write: no effect read: Real-time counter..,1: write: changes the Real-time counter.."
|
|
newline
|
|
bitfld.long 0x00 19. "SETPEND19,Timer/PWM module 2 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 2..,1: write: changes the Timer/PWM module 2.."
|
|
bitfld.long 0x00 18. "SETPEND18,Timer/PWM module 1 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 1..,1: write: changes the Timer/PWM module 1.."
|
|
newline
|
|
bitfld.long 0x00 17. "SETPEND17,Timer/PWM module 0 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 0..,1: write: changes the Timer/PWM module 0.."
|
|
bitfld.long 0x00 16. "SETPEND16,Comparator 0 interrupt set-pending bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: changes the Comparator 0 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "SETPEND15,Analog-to-Digital Converter 0 interrupt set-pending bit" "0: write: no effect read: Analog-to-Digital..,1: write: changes the Analog-to-Digital.."
|
|
bitfld.long 0x00 14. "SETPEND14,UART2 or FLEXIO interrupt set-pending bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: changes the UART2 or FLEXIO interrupt.."
|
|
newline
|
|
bitfld.long 0x00 13. "SETPEND13,LPUART1 status and error interrupt set-pending bit" "0: write: no effect read: LPUART1 status and..,1: write: changes the LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "SETPEND12,LPUART0 status and error interrupt set-pending bit" "0: write: no effect read: LPUART0 status and..,1: write: changes the LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "SETPEND11,Serial Peripheral Interface 1 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
|
|
bitfld.long 0x00 10. "SETPEND10,Serial Peripheral Interface 0 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
|
|
newline
|
|
bitfld.long 0x00 9. "SETPEND9,Inter-Integrated Circuit 1 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 1.."
|
|
bitfld.long 0x00 8. "SETPEND8,Inter-Integrated Circuit 0 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 7. "SETPEND7,Low Leakage Wakeup interrupt set-pending bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: changes the Low Leakage Wakeup.."
|
|
bitfld.long 0x00 6. "SETPEND6,Low-voltage detect low-voltage warning interrupt set-pending bit" "0: write: no effect read: Low-voltage detect..,1: write: changes the Low-voltage detect.."
|
|
newline
|
|
bitfld.long 0x00 5. "SETPEND5,Command complete and read collision interrupt set-pending bit" "0: write: no effect read: Command complete and..,1: write: changes the Command complete and read.."
|
|
bitfld.long 0x00 4. "SETPEND4,Reserved iv 20 interrupt set-pending bit" "0: write: no effect read: Reserved iv 20..,1: write: changes the Reserved iv 20 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 3. "SETPEND3,DMA channel 3 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: changes the DMA channel 3 transfer.."
|
|
bitfld.long 0x00 2. "SETPEND2,DMA channel 2 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: changes the DMA channel 2 transfer.."
|
|
newline
|
|
bitfld.long 0x00 1. "SETPEND1,DMA channel 1 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: changes the DMA channel 1 transfer.."
|
|
bitfld.long 0x00 0. "SETPEND0,DMA channel 0 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: changes the DMA channel 0 transfer.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISPR,Interrupt Set Pending Register"
|
|
eventfld.long 0x00 31. "SETPEND31,INTMUX1 channel7 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel7..,1: write: changes the INTMUX1 channel7 interrupt.."
|
|
eventfld.long 0x00 30. "SETPEND30,INTMUX1 channel6 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel6..,1: write: changes the INTMUX1 channel6 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 29. "SETPEND29,INTMUX1 channel5 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel5..,1: write: changes the INTMUX1 channel5 interrupt.."
|
|
eventfld.long 0x00 28. "SETPEND28,INTMUX1 channel4 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel4..,1: write: changes the INTMUX1 channel4 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 27. "SETPEND27,INTMUX1 channel3 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel3..,1: write: changes the INTMUX1 channel3 interrupt.."
|
|
eventfld.long 0x00 26. "SETPEND26,INTMUX1 channel2 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel2..,1: write: changes the INTMUX1 channel2 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 25. "SETPEND25,INTMUX1 channel1 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel1..,1: write: changes the INTMUX1 channel1 interrupt.."
|
|
eventfld.long 0x00 24. "SETPEND24,INTMUX1 channel0 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX1 channel0..,1: write: changes the INTMUX1 channel0 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 23. "SETPEND23,RTC Alarm interrupt set-pending bit" "0: write: no effect read: RTC Alarm interrupt is..,1: write: changes the RTC Alarm interrupt state.."
|
|
eventfld.long 0x00 22. "SETPEND22,LPCMP1 interrupt set-pending bit" "0: write: no effect read: LPCMP1 interrupt is..,1: write: changes the LPCMP1 interrupt state to.."
|
|
newline
|
|
eventfld.long 0x00 21. "SETPEND21,PORTE Pin detect interrupt set-pending bit" "0: write: no effect read: PORTE Pin detect..,1: write: changes the PORTE Pin detect interrupt.."
|
|
eventfld.long 0x00 20. "SETPEND20,LPUART3 status and error interrupt set-pending bit" "0: write: no effect read: LPUART3 status and..,1: write: changes the LPUART3 status and error.."
|
|
newline
|
|
eventfld.long 0x00 19. "SETPEND19,Serial Peripheral Interface 3 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
|
|
eventfld.long 0x00 18. "SETPEND18,Reserved iv 34 interrupt set-pending bit" "0: write: no effect read: Reserved iv 34..,1: write: changes the Reserved iv 34 interrupt.."
|
|
newline
|
|
eventfld.long 0x00 17. "SETPEND17,Reserved iv 33 interrupt set-pending bit" "0: write: no effect read: Reserved iv 33..,1: write: changes the Reserved iv 33 interrupt.."
|
|
eventfld.long 0x00 16. "SETPEND16,Inter-Integrated Circuit 3 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 3.."
|
|
newline
|
|
eventfld.long 0x00 15. "SETPEND15,Timer/PWM module 3 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 3..,1: write: changes the Timer/PWM module 3.."
|
|
eventfld.long 0x00 14. "SETPEND14,Low-Power Timer 2 interrupt set-pending bit" "0: write: no effect read: Low-Power Timer 2..,1: write: changes the Low-Power Timer 2.."
|
|
newline
|
|
eventfld.long 0x00 13. "SETPEND13,Low Power Periodic Interrupt Timer 1 interrupt set-pending bit" "0: write: no effect read: Low Power Periodic..,1: write: changes the Low Power Periodic.."
|
|
eventfld.long 0x00 12. "SETPEND12,TRNG interrupt set-pending bit" "0: write: no effect read: TRNG interrupt is not..,1: write: changes the TRNG interrupt state to.."
|
|
newline
|
|
eventfld.long 0x00 11. "SETPEND11,Cryptographic Acceleration Unit version 3 Security Violation interrupt set-pending bit" "0: write: no effect read: Cryptographic..,1: write: changes the Cryptographic Acceleration.."
|
|
eventfld.long 0x00 10. "SETPEND10,Cryptographic Acceleration Unit version 3 Task Complete interrupt set-pending bit" "0: write: no effect read: Cryptographic..,1: write: changes the Cryptographic Acceleration.."
|
|
newline
|
|
eventfld.long 0x00 9. "SETPEND9,WDOG1 interrupt set-pending bit" "0: write: no effect read: WDOG1 interrupt is not..,1: write: changes the WDOG1 interrupt state to.."
|
|
eventfld.long 0x00 8. "SETPEND8,Message Unit Side B interrupt set-pending bit" "0: write: no effect read: Message Unit Side B..,1: write: changes the Message Unit Side B.."
|
|
newline
|
|
eventfld.long 0x00 7. "SETPEND7,Low leakage wakeup 1 interrupt set-pending bit" "0: write: no effect read: Low leakage wakeup 1..,1: write: changes the Low leakage wakeup 1.."
|
|
eventfld.long 0x00 6. "SETPEND6,MSMC (SMC1) interrupt interrupt set-pending bit" "0: write: no effect read: MSMC (SMC1) interrupt..,1: write: changes the MSMC (SMC1) interrupt.."
|
|
newline
|
|
eventfld.long 0x00 5. "SETPEND5,DMA1 channel 0-7 error interrupt interrupt set-pending bit" "0: write: no effect read: DMA1 channel 0-7 error..,1: write: changes the DMA1 channel 0-7 error.."
|
|
eventfld.long 0x00 4. "SETPEND4,DMA1 channel 3/7 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA1 channel 3/7..,1: write: changes the DMA1 channel 3/7 transfer.."
|
|
newline
|
|
eventfld.long 0x00 3. "SETPEND3,DMA1 channel 2/6 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA1 channel 2/6..,1: write: changes the DMA1 channel 2/6 transfer.."
|
|
eventfld.long 0x00 2. "SETPEND2,DMA1 channel 1/5 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA1 channel 1/5..,1: write: changes the DMA1 channel 1/5 transfer.."
|
|
newline
|
|
eventfld.long 0x00 1. "SETPEND1,DMA1 channel 0/4 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA1 channel 0/4..,1: write: changes the DMA1 channel 0/4 transfer.."
|
|
eventfld.long 0x00 0. "SETPEND0,Cross Trigger Interface 1 interrupt set-pending bit" "0: write: no effect read: Cross Trigger..,1: write: changes the Cross Trigger Interface 1.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "NVICISPR$1,Interrupt Set Pending Register n"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt set-pending bits"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICPR,Interrupt Clear Pending Register"
|
|
bitfld.long 0x00 31. "CLRPEND31,PORTC and PORTD Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: removes pending state from the PORTC.."
|
|
bitfld.long 0x00 30. "CLRPEND30,PORTA Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTA Pin detect..,1: write: removes pending state from the PORTA.."
|
|
newline
|
|
bitfld.long 0x00 29. "CLRPEND29,Reserved iv 45 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 45..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 28. "CLRPEND28,Low-Power Timer interrupt clear-pending bit" "0: write: no effect read: Low-Power Timer..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 27. "CLRPEND27,Reserved iv 43 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 43..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 26. "CLRPEND26,Reserved iv 42 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 42..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 25. "CLRPEND25,Digital to Analog Converter interrupt clear-pending bit" "0: write: no effect read: Digital to Analog..,1: write: removes pending state from the Digital.."
|
|
bitfld.long 0x00 24. "CLRPEND24,Universal Serial Bus interrupt clear-pending bit" "0: write: no effect read: Universal Serial Bus..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 23. "CLRPEND23,Reserved iv 39 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 39..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 22. "CLRPEND22,Periodic Interrupt Timer interrupt clear-pending bit" "0: write: no effect read: Periodic Interrupt..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 21. "CLRPEND21,RTC seconds interrupt clear-pending bit" "0: write: no effect read: RTC seconds interrupt..,1: write: removes pending state from the RTC.."
|
|
bitfld.long 0x00 20. "CLRPEND20,Real-time counter interrupt clear-pending bit" "0: write: no effect read: Real-time counter..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 19. "CLRPEND19,Timer/PWM module 2 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 2..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 18. "CLRPEND18,Timer/PWM module 1 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 1..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 17. "CLRPEND17,Timer/PWM module 0 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 0..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 16. "CLRPEND16,Comparator 0 interrupt clear-pending bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 15. "CLRPEND15,Analog-to-Digital Converter 0 interrupt clear-pending bit" "0: write: no effect read: Analog-to-Digital..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 14. "CLRPEND14,UART2 or FLEXIO interrupt clear-pending bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: removes pending state from the UART2.."
|
|
newline
|
|
bitfld.long 0x00 13. "CLRPEND13,LPUART1 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART1 status and..,1: write: removes pending state from the LPUART1.."
|
|
bitfld.long 0x00 12. "CLRPEND12,LPUART0 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART0 status and..,1: write: removes pending state from the LPUART0.."
|
|
newline
|
|
bitfld.long 0x00 11. "CLRPEND11,Serial Peripheral Interface 1 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
|
|
bitfld.long 0x00 10. "CLRPEND10,Serial Peripheral Interface 0 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
|
|
newline
|
|
bitfld.long 0x00 9. "CLRPEND9,Inter-Integrated Circuit 1 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 8. "CLRPEND8,Inter-Integrated Circuit 0 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 7. "CLRPEND7,Low Leakage Wakeup interrupt clear-pending bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: removes pending state from the Low.."
|
|
bitfld.long 0x00 6. "CLRPEND6,Low-voltage detect low-voltage warning interrupt clear-pending bit" "0: write: no effect read: Low-voltage detect..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 5. "CLRPEND5,Command complete and read collision interrupt clear-pending bit" "0: write: no effect read: Command complete and..,1: write: removes pending state from the Command.."
|
|
bitfld.long 0x00 4. "CLRPEND4,Reserved iv 20 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 20..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 3. "CLRPEND3,DMA channel 3 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: removes pending state from the DMA.."
|
|
bitfld.long 0x00 2. "CLRPEND2,DMA channel 2 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: removes pending state from the DMA.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLRPEND1,DMA channel 1 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: removes pending state from the DMA.."
|
|
bitfld.long 0x00 0. "CLRPEND0,DMA channel 0 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: removes pending state from the DMA.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVICICPR0,Interrupt Clear Pending Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICPR,Interrupt Clear Pending Register"
|
|
eventfld.long 0x00 31. "CLRPEND31,INTMUX1 channel7 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel7..,1: write: removes pending state from the INTMUX1.."
|
|
eventfld.long 0x00 30. "CLRPEND30,INTMUX1 channel6 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel6..,1: write: removes pending state from the INTMUX1.."
|
|
newline
|
|
eventfld.long 0x00 29. "CLRPEND29,INTMUX1 channel5 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel5..,1: write: removes pending state from the INTMUX1.."
|
|
eventfld.long 0x00 28. "CLRPEND28,INTMUX1 channel4 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel4..,1: write: removes pending state from the INTMUX1.."
|
|
newline
|
|
eventfld.long 0x00 27. "CLRPEND27,INTMUX1 channel3 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel3..,1: write: removes pending state from the INTMUX1.."
|
|
eventfld.long 0x00 26. "CLRPEND26,INTMUX1 channel2 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel2..,1: write: removes pending state from the INTMUX1.."
|
|
newline
|
|
eventfld.long 0x00 25. "CLRPEND25,INTMUX1 channel1 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel1..,1: write: removes pending state from the INTMUX1.."
|
|
eventfld.long 0x00 24. "CLRPEND24,INTMUX1 channel0 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX1 channel0..,1: write: removes pending state from the INTMUX1.."
|
|
newline
|
|
eventfld.long 0x00 23. "CLRPEND23,RTC Alarm interrupt clear-pending bit" "0: write: no effect read: RTC Alarm interrupt is..,1: write: removes pending state from the RTC.."
|
|
eventfld.long 0x00 22. "CLRPEND22,LPCMP1 interrupt clear-pending bit" "0: write: no effect read: LPCMP1 interrupt is..,1: write: removes pending state from the LPCMP1.."
|
|
newline
|
|
eventfld.long 0x00 21. "CLRPEND21,PORTE Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTE Pin detect..,1: write: removes pending state from the PORTE.."
|
|
eventfld.long 0x00 20. "CLRPEND20,LPUART3 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART3 status and..,1: write: removes pending state from the LPUART3.."
|
|
newline
|
|
eventfld.long 0x00 19. "CLRPEND19,Serial Peripheral Interface 3 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
|
|
eventfld.long 0x00 18. "CLRPEND18,Reserved iv 34 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 34..,1: write: removes pending state from the.."
|
|
newline
|
|
eventfld.long 0x00 17. "CLRPEND17,Reserved iv 33 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 33..,1: write: removes pending state from the.."
|
|
eventfld.long 0x00 16. "CLRPEND16,Inter-Integrated Circuit 3 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
|
|
newline
|
|
eventfld.long 0x00 15. "CLRPEND15,Timer/PWM module 3 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 3..,1: write: removes pending state from the.."
|
|
eventfld.long 0x00 14. "CLRPEND14,Low-Power Timer 2 interrupt clear-pending bit" "0: write: no effect read: Low-Power Timer 2..,1: write: removes pending state from the.."
|
|
newline
|
|
eventfld.long 0x00 13. "CLRPEND13,Low Power Periodic Interrupt Timer 1 interrupt clear-pending bit" "0: write: no effect read: Low Power Periodic..,1: write: removes pending state from the Low.."
|
|
eventfld.long 0x00 12. "CLRPEND12,TRNG interrupt clear-pending bit" "0: write: no effect read: TRNG interrupt is not..,1: write: removes pending state from the TRNG.."
|
|
newline
|
|
eventfld.long 0x00 11. "CLRPEND11,Cryptographic Acceleration Unit version 3 Security Violation interrupt clear-pending bit" "0: write: no effect read: Cryptographic..,1: write: removes pending state from the.."
|
|
eventfld.long 0x00 10. "CLRPEND10,Cryptographic Acceleration Unit version 3 Task Complete interrupt clear-pending bit" "0: write: no effect read: Cryptographic..,1: write: removes pending state from the.."
|
|
newline
|
|
eventfld.long 0x00 9. "CLRPEND9,WDOG1 interrupt clear-pending bit" "0: write: no effect read: WDOG1 interrupt is not..,1: write: removes pending state from the WDOG1.."
|
|
eventfld.long 0x00 8. "CLRPEND8,Message Unit Side B interrupt clear-pending bit" "0: write: no effect read: Message Unit Side B..,1: write: removes pending state from the Message.."
|
|
newline
|
|
eventfld.long 0x00 7. "CLRPEND7,Low leakage wakeup 1 interrupt clear-pending bit" "0: write: no effect read: Low leakage wakeup 1..,1: write: removes pending state from the Low.."
|
|
eventfld.long 0x00 6. "CLRPEND6,MSMC (SMC1) interrupt interrupt clear-pending bit" "0: write: no effect read: MSMC (SMC1) interrupt..,1: write: removes pending state from the MSMC.."
|
|
newline
|
|
eventfld.long 0x00 5. "CLRPEND5,DMA1 channel 0-7 error interrupt interrupt clear-pending bit" "0: write: no effect read: DMA1 channel 0-7 error..,1: write: removes pending state from the DMA1.."
|
|
eventfld.long 0x00 4. "CLRPEND4,DMA1 channel 3/7 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA1 channel 3/7..,1: write: removes pending state from the DMA1.."
|
|
newline
|
|
eventfld.long 0x00 3. "CLRPEND3,DMA1 channel 2/6 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA1 channel 2/6..,1: write: removes pending state from the DMA1.."
|
|
eventfld.long 0x00 2. "CLRPEND2,DMA1 channel 1/5 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA1 channel 1/5..,1: write: removes pending state from the DMA1.."
|
|
newline
|
|
eventfld.long 0x00 1. "CLRPEND1,DMA1 channel 0/4 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA1 channel 0/4..,1: write: removes pending state from the DMA1.."
|
|
eventfld.long 0x00 0. "CLRPEND0,Cross Trigger Interface 1 interrupt clear-pending bit" "0: write: no effect read: Cross Trigger..,1: write: removes pending state from the Cross.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICPR,Interrupt Clear Pending Register"
|
|
bitfld.long 0x00 31. "CLRPEND31,PORTC and PORTD Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTC and PORTD Pin..,1: write: removes pending state from the PORTC.."
|
|
bitfld.long 0x00 30. "CLRPEND30,PORTA Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTA Pin detect..,1: write: removes pending state from the PORTA.."
|
|
newline
|
|
bitfld.long 0x00 29. "CLRPEND29,LCD interrupt clear-pending bit" "0: write: no effect read: LCD interrupt is not..,1: write: removes pending state from the LCD.."
|
|
bitfld.long 0x00 28. "CLRPEND28,Low-Power Timer interrupt clear-pending bit" "0: write: no effect read: Low-Power Timer..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 27. "CLRPEND27,Reserved iv 43 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 43..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 26. "CLRPEND26,Reserved iv 42 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 42..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 25. "CLRPEND25,Digital to Analog Converter interrupt clear-pending bit" "0: write: no effect read: Digital to Analog..,1: write: removes pending state from the Digital.."
|
|
bitfld.long 0x00 24. "CLRPEND24,Universal Serial Bus interrupt clear-pending bit" "0: write: no effect read: Universal Serial Bus..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 23. "CLRPEND23,Reserved iv 39 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 39..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 22. "CLRPEND22,Periodic Interrupt Timer interrupt clear-pending bit" "0: write: no effect read: Periodic Interrupt..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 21. "CLRPEND21,RTC seconds interrupt clear-pending bit" "0: write: no effect read: RTC seconds interrupt..,1: write: removes pending state from the RTC.."
|
|
bitfld.long 0x00 20. "CLRPEND20,Real-time counter interrupt clear-pending bit" "0: write: no effect read: Real-time counter..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 19. "CLRPEND19,Timer/PWM module 2 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 2..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 18. "CLRPEND18,Timer/PWM module 1 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 1..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 17. "CLRPEND17,Timer/PWM module 0 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 0..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 16. "CLRPEND16,Comparator 0 interrupt clear-pending bit" "0: write: no effect read: Comparator 0 interrupt..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 15. "CLRPEND15,Analog-to-Digital Converter 0 interrupt clear-pending bit" "0: write: no effect read: Analog-to-Digital..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 14. "CLRPEND14,UART2 or FLEXIO interrupt clear-pending bit" "0: write: no effect read: UART2 or FLEXIO..,1: write: removes pending state from the UART2.."
|
|
newline
|
|
bitfld.long 0x00 13. "CLRPEND13,LPUART1 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART1 status and..,1: write: removes pending state from the LPUART1.."
|
|
bitfld.long 0x00 12. "CLRPEND12,LPUART0 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART0 status and..,1: write: removes pending state from the LPUART0.."
|
|
newline
|
|
bitfld.long 0x00 11. "CLRPEND11,Serial Peripheral Interface 1 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
|
|
bitfld.long 0x00 10. "CLRPEND10,Serial Peripheral Interface 0 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
|
|
newline
|
|
bitfld.long 0x00 9. "CLRPEND9,Inter-Integrated Circuit 1 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
|
|
bitfld.long 0x00 8. "CLRPEND8,Inter-Integrated Circuit 0 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 7. "CLRPEND7,Low Leakage Wakeup interrupt clear-pending bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: removes pending state from the Low.."
|
|
bitfld.long 0x00 6. "CLRPEND6,Low-voltage detect low-voltage warning interrupt clear-pending bit" "0: write: no effect read: Low-voltage detect..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 5. "CLRPEND5,Command complete and read collision interrupt clear-pending bit" "0: write: no effect read: Command complete and..,1: write: removes pending state from the Command.."
|
|
bitfld.long 0x00 4. "CLRPEND4,Reserved iv 20 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 20..,1: write: removes pending state from the.."
|
|
newline
|
|
bitfld.long 0x00 3. "CLRPEND3,DMA channel 3 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 3 transfer..,1: write: removes pending state from the DMA.."
|
|
bitfld.long 0x00 2. "CLRPEND2,DMA channel 2 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 2 transfer..,1: write: removes pending state from the DMA.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLRPEND1,DMA channel 1 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 1 transfer..,1: write: removes pending state from the DMA.."
|
|
bitfld.long 0x00 0. "CLRPEND0,DMA channel 0 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA channel 0 transfer..,1: write: removes pending state from the DMA.."
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
repeat 3. (strings "1" "2" "3" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x184)++0x03
|
|
line.long 0x00 "NVICICPR$1,Interrupt Clear Pending Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "NVICIABR$1,Interrupt Active bit Register n"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt active flags"
|
|
repeat.end
|
|
group.byte 0x300++0x00
|
|
line.byte 0x00 "NVICIP0,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "NVIC_IPR0,Interrupt Priority Register 0"
|
|
bitfld.long 0x00 30.--31. "PRI_3,Priority of the DMA1 channel 2/6 transfer complete interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_2,Priority of the DMA1 channel 1/5 transfer complete interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_1,Priority of the DMA1 channel 0/4 transfer complete interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_0,Priority of the Cross Trigger Interface 1 interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "NVIC_IPR0,Interrupt Priority Register 0"
|
|
bitfld.long 0x00 30.--31. "PRI_3,Priority of the DMA channel 3 transfer complete interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_2,Priority of the DMA channel 2 transfer complete interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_1,Priority of the DMA channel 1 transfer complete interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_0,Priority of the DMA channel 0 transfer complete interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x301++0x00
|
|
line.byte 0x00 "NVICIP1,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI1,Priority of interrupt 1"
|
|
group.byte 0x302++0x00
|
|
line.byte 0x00 "NVICIP2,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI2,Priority of interrupt 2"
|
|
group.byte 0x303++0x00
|
|
line.byte 0x00 "NVICIP3,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI3,Priority of interrupt 3"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "NVIC_IPR1,Interrupt Priority Register 1"
|
|
bitfld.long 0x00 30.--31. "PRI_7,Priority of the Low Leakage Wakeup interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_6,Priority of the Low-voltage detect low-voltage warning interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_5,Priority of the Command complete and read collision interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4,Priority of the Reserved iv 20 interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x304++0x00
|
|
line.byte 0x00 "NVICIP4,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI4,Priority of interrupt 4"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "NVIC_IPR1,Interrupt Priority Register 1"
|
|
bitfld.long 0x00 30.--31. "PRI_7,Priority of the Low leakage wakeup 1 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_6,Priority of the MSMC (SMC1) interrupt interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_5,Priority of the DMA1 channel 0-7 error interrupt interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4,Priority of the DMA1 channel 3/7 transfer complete interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x305++0x00
|
|
line.byte 0x00 "NVICIP5,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI5,Priority of interrupt 5"
|
|
group.byte 0x306++0x00
|
|
line.byte 0x00 "NVICIP6,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI6,Priority of interrupt 6"
|
|
group.byte 0x307++0x00
|
|
line.byte 0x00 "NVICIP7,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI7,Priority of interrupt 7"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "NVIC_IPR2,Interrupt Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of the Serial Peripheral Interface 1 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_10,Priority of the Serial Peripheral Interface 0 interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_9,Priority of the Inter-Integrated Circuit 1 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_8,Priority of the Inter-Integrated Circuit 0 interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "NVIC_IPR2,Interrupt Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of the Cryptographic Acceleration Unit version 3 Security Violation interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_10,Priority of the Cryptographic Acceleration Unit version 3 Task Complete interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_9,Priority of the WDOG1 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_8,Priority of the Message Unit Side B interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x308++0x00
|
|
line.byte 0x00 "NVICIP8,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI8,Priority of interrupt 8"
|
|
group.byte 0x309++0x00
|
|
line.byte 0x00 "NVICIP9,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI9,Priority of interrupt 9"
|
|
group.byte 0x30A++0x00
|
|
line.byte 0x00 "NVICIP10,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI10,Priority of interrupt 10"
|
|
group.byte 0x30B++0x00
|
|
line.byte 0x00 "NVICIP11,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI11,Priority of interrupt 11"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "NVIC_IPR3,Interrupt Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of the Timer/PWM module 3 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of the Low-Power Timer 2 interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_13,Priority of the Low Power Periodic Interrupt Timer 1 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_12,Priority of the TRNG interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "NVIC_IPR3,Interrupt Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of the Analog-to-Digital Converter 0 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of the UART2 or FLEXIO interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_13,Priority of the LPUART1 status and error interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_12,Priority of the LPUART0 status and error interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x30C++0x00
|
|
line.byte 0x00 "NVICIP12,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI12,Priority of interrupt 12"
|
|
group.byte 0x30D++0x00
|
|
line.byte 0x00 "NVICIP13,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI13,Priority of interrupt 13"
|
|
group.byte 0x30E++0x00
|
|
line.byte 0x00 "NVICIP14,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI14,Priority of interrupt 14"
|
|
group.byte 0x30F++0x00
|
|
line.byte 0x00 "NVICIP15,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI15,Priority of interrupt 15"
|
|
group.byte 0x310++0x00
|
|
line.byte 0x00 "NVICIP16,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI16,Priority of interrupt 16"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "NVIC_IPR4,Interrupt Priority Register 4"
|
|
bitfld.long 0x00 30.--31. "PRI_19,Priority of the Serial Peripheral Interface 3 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_18,Priority of the Reserved iv 34 interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_17,Priority of the Reserved iv 33 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_16,Priority of the Inter-Integrated Circuit 3 interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "NVIC_IPR4,Interrupt Priority Register 4"
|
|
bitfld.long 0x00 30.--31. "PRI_19,Priority of the Timer/PWM module 2 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_18,Priority of the Timer/PWM module 1 interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_17,Priority of the Timer/PWM module 0 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_16,Priority of the Comparator 0 interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x311++0x00
|
|
line.byte 0x00 "NVICIP17,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI17,Priority of interrupt 17"
|
|
group.byte 0x312++0x00
|
|
line.byte 0x00 "NVICIP18,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI18,Priority of interrupt 18"
|
|
group.byte 0x313++0x00
|
|
line.byte 0x00 "NVICIP19,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI19,Priority of interrupt 19"
|
|
group.byte 0x314++0x00
|
|
line.byte 0x00 "NVICIP20,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI20,Priority of interrupt 20"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "NVIC_IPR5,Interrupt Priority Register 5"
|
|
bitfld.long 0x00 30.--31. "PRI_23,Priority of the RTC Alarm interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_22,Priority of the LPCMP1 interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_21,Priority of the PORTE Pin detect interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_20,Priority of the LPUART3 status and error interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "NVIC_IPR5,Interrupt Priority Register 5"
|
|
bitfld.long 0x00 30.--31. "PRI_23,Priority of the Reserved iv 39 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_22,Priority of the Periodic Interrupt Timer interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_21,Priority of the RTC seconds interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_20,Priority of the Real-time counter interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "NVICIP21,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI21,Priority of interrupt 21"
|
|
group.byte 0x316++0x00
|
|
line.byte 0x00 "NVICIP22,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI22,Priority of interrupt 22"
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "NVICIP23,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI23,Priority of interrupt 23"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "NVIC_IPR6,Interrupt Priority Register 6"
|
|
bitfld.long 0x00 30.--31. "PRI_27,Priority of the INTMUX1 channel3 interrupt interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_26,Priority of the INTMUX1 channel2 interrupt interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_25,Priority of the INTMUX1 channel1 interrupt interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_24,Priority of the INTMUX1 channel0 interrupt interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x318++0x00
|
|
line.byte 0x00 "NVICIP24,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI24,Priority of interrupt 24"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "NVIC_IPR6,Interrupt Priority Register 6"
|
|
bitfld.long 0x00 30.--31. "PRI_27,Priority of the Reserved iv 43 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_26,Priority of the Reserved iv 42 interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_25,Priority of the Digital to Analog Converter interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_24,Priority of the Universal Serial Bus interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x319++0x00
|
|
line.byte 0x00 "NVICIP25,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI25,Priority of interrupt 25"
|
|
group.byte 0x31A++0x00
|
|
line.byte 0x00 "NVICIP26,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI26,Priority of interrupt 26"
|
|
group.byte 0x31B++0x00
|
|
line.byte 0x00 "NVICIP27,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI27,Priority of interrupt 27"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "NVIC_IPR7,Interrupt Priority Register 7"
|
|
bitfld.long 0x00 30.--31. "PRI_31,Priority of the INTMUX1 channel7 interrupt interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_30,Priority of the INTMUX1 channel6 interrupt interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_29,Priority of the INTMUX1 channel5 interrupt interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_28,Priority of the INTMUX1 channel4 interrupt interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "NVIC_IPR7,Interrupt Priority Register 7"
|
|
bitfld.long 0x00 30.--31. "PRI_31,Priority of the PORTC and PORTD Pin detect interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_30,Priority of the PORTA Pin detect interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_29,Priority of the Reserved iv 45 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_28,Priority of the Low-Power Timer interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "NVIC_IPR7,Interrupt Priority Register 7"
|
|
bitfld.long 0x00 30.--31. "PRI_31,Priority of the PORTC and PORTD Pin detect interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_30,Priority of the PORTA Pin detect interrupt" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_29,Priority of the LCD interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_28,Priority of the Low-Power Timer interrupt" "0,1,2,3"
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
group.byte 0x31C++0x00
|
|
line.byte 0x00 "NVICIP28,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI28,Priority of interrupt 28"
|
|
group.byte 0x31D++0x00
|
|
line.byte 0x00 "NVICIP29,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI29,Priority of interrupt 29"
|
|
group.byte 0x31E++0x00
|
|
line.byte 0x00 "NVICIP30,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI30,Priority of interrupt 30"
|
|
group.byte 0x31F++0x00
|
|
line.byte 0x00 "NVICIP31,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI31,Priority of interrupt 31"
|
|
group.byte 0x320++0x00
|
|
line.byte 0x00 "NVICIP32,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI32,Priority of interrupt 32"
|
|
group.byte 0x321++0x00
|
|
line.byte 0x00 "NVICIP33,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI33,Priority of interrupt 33"
|
|
group.byte 0x322++0x00
|
|
line.byte 0x00 "NVICIP34,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI34,Priority of interrupt 34"
|
|
group.byte 0x323++0x00
|
|
line.byte 0x00 "NVICIP35,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI35,Priority of interrupt 35"
|
|
group.byte 0x324++0x00
|
|
line.byte 0x00 "NVICIP36,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI36,Priority of interrupt 36"
|
|
group.byte 0x325++0x00
|
|
line.byte 0x00 "NVICIP37,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI37,Priority of interrupt 37"
|
|
group.byte 0x326++0x00
|
|
line.byte 0x00 "NVICIP38,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI38,Priority of interrupt 38"
|
|
group.byte 0x327++0x00
|
|
line.byte 0x00 "NVICIP39,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI39,Priority of interrupt 39"
|
|
group.byte 0x328++0x00
|
|
line.byte 0x00 "NVICIP40,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI40,Priority of interrupt 40"
|
|
group.byte 0x329++0x00
|
|
line.byte 0x00 "NVICIP41,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI41,Priority of interrupt 41"
|
|
group.byte 0x32A++0x00
|
|
line.byte 0x00 "NVICIP42,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI42,Priority of interrupt 42"
|
|
group.byte 0x32B++0x00
|
|
line.byte 0x00 "NVICIP43,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI43,Priority of interrupt 43"
|
|
group.byte 0x32C++0x00
|
|
line.byte 0x00 "NVICIP44,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI44,Priority of interrupt 44"
|
|
group.byte 0x32D++0x00
|
|
line.byte 0x00 "NVICIP45,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI45,Priority of interrupt 45"
|
|
group.byte 0x32E++0x00
|
|
line.byte 0x00 "NVICIP46,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI46,Priority of interrupt 46"
|
|
group.byte 0x32F++0x00
|
|
line.byte 0x00 "NVICIP47,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI47,Priority of interrupt 47"
|
|
group.byte 0x330++0x00
|
|
line.byte 0x00 "NVICIP48,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI48,Priority of interrupt 48"
|
|
group.byte 0x331++0x00
|
|
line.byte 0x00 "NVICIP49,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI49,Priority of interrupt 49"
|
|
group.byte 0x332++0x00
|
|
line.byte 0x00 "NVICIP50,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI50,Priority of interrupt 50"
|
|
group.byte 0x333++0x00
|
|
line.byte 0x00 "NVICIP51,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI51,Priority of interrupt 51"
|
|
group.byte 0x334++0x00
|
|
line.byte 0x00 "NVICIP52,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI52,Priority of interrupt 52"
|
|
group.byte 0x335++0x00
|
|
line.byte 0x00 "NVICIP53,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI53,Priority of interrupt 53"
|
|
group.byte 0x336++0x00
|
|
line.byte 0x00 "NVICIP54,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI54,Priority of interrupt 54"
|
|
group.byte 0x337++0x00
|
|
line.byte 0x00 "NVICIP55,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI55,Priority of interrupt 55"
|
|
group.byte 0x338++0x00
|
|
line.byte 0x00 "NVICIP56,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI56,Priority of interrupt 56"
|
|
group.byte 0x339++0x00
|
|
line.byte 0x00 "NVICIP57,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI57,Priority of interrupt 57"
|
|
group.byte 0x33A++0x00
|
|
line.byte 0x00 "NVICIP58,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI58,Priority of interrupt 58"
|
|
group.byte 0x33B++0x00
|
|
line.byte 0x00 "NVICIP59,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI59,Priority of interrupt 59"
|
|
group.byte 0x33C++0x00
|
|
line.byte 0x00 "NVICIP60,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI60,Priority of interrupt 60"
|
|
group.byte 0x33D++0x00
|
|
line.byte 0x00 "NVICIP61,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI61,Priority of interrupt 61"
|
|
group.byte 0x33E++0x00
|
|
line.byte 0x00 "NVICIP62,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI62,Priority of interrupt 62"
|
|
group.byte 0x33F++0x00
|
|
line.byte 0x00 "NVICIP63,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI63,Priority of interrupt 63"
|
|
group.byte 0x340++0x00
|
|
line.byte 0x00 "NVICIP64,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI64,Priority of interrupt 64"
|
|
group.byte 0x341++0x00
|
|
line.byte 0x00 "NVICIP65,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI65,Priority of interrupt 65"
|
|
group.byte 0x342++0x00
|
|
line.byte 0x00 "NVICIP66,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI66,Priority of interrupt 66"
|
|
group.byte 0x343++0x00
|
|
line.byte 0x00 "NVICIP67,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI67,Priority of interrupt 67"
|
|
group.byte 0x344++0x00
|
|
line.byte 0x00 "NVICIP68,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI68,Priority of interrupt 68"
|
|
group.byte 0x345++0x00
|
|
line.byte 0x00 "NVICIP69,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI69,Priority of interrupt 69"
|
|
group.byte 0x346++0x00
|
|
line.byte 0x00 "NVICIP70,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI70,Priority of interrupt 70"
|
|
group.byte 0x347++0x00
|
|
line.byte 0x00 "NVICIP71,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI71,Priority of interrupt 71"
|
|
group.byte 0x348++0x00
|
|
line.byte 0x00 "NVICIP72,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI72,Priority of interrupt 72"
|
|
group.byte 0x349++0x00
|
|
line.byte 0x00 "NVICIP73,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI73,Priority of interrupt 73"
|
|
group.byte 0x34A++0x00
|
|
line.byte 0x00 "NVICIP74,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI74,Priority of interrupt 74"
|
|
group.byte 0x34B++0x00
|
|
line.byte 0x00 "NVICIP75,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI75,Priority of interrupt 75"
|
|
group.byte 0x34C++0x00
|
|
line.byte 0x00 "NVICIP76,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI76,Priority of interrupt 76"
|
|
group.byte 0x34D++0x00
|
|
line.byte 0x00 "NVICIP77,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI77,Priority of interrupt 77"
|
|
group.byte 0x34E++0x00
|
|
line.byte 0x00 "NVICIP78,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI78,Priority of interrupt 78"
|
|
group.byte 0x34F++0x00
|
|
line.byte 0x00 "NVICIP79,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI79,Priority of interrupt 79"
|
|
group.byte 0x350++0x00
|
|
line.byte 0x00 "NVICIP80,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI80,Priority of interrupt 80"
|
|
group.byte 0x351++0x00
|
|
line.byte 0x00 "NVICIP81,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI81,Priority of interrupt 81"
|
|
group.byte 0x352++0x00
|
|
line.byte 0x00 "NVICIP82,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI82,Priority of interrupt 82"
|
|
group.byte 0x353++0x00
|
|
line.byte 0x00 "NVICIP83,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI83,Priority of interrupt 83"
|
|
group.byte 0x354++0x00
|
|
line.byte 0x00 "NVICIP84,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI84,Priority of interrupt 84"
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "NVICIP85,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI85,Priority of interrupt 85"
|
|
group.byte 0x356++0x00
|
|
line.byte 0x00 "NVICIP86,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI86,Priority of interrupt 86"
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "NVICIP87,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI87,Priority of interrupt 87"
|
|
group.byte 0x358++0x00
|
|
line.byte 0x00 "NVICIP88,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI88,Priority of interrupt 88"
|
|
group.byte 0x359++0x00
|
|
line.byte 0x00 "NVICIP89,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI89,Priority of interrupt 89"
|
|
group.byte 0x35A++0x00
|
|
line.byte 0x00 "NVICIP90,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI90,Priority of interrupt 90"
|
|
group.byte 0x35B++0x00
|
|
line.byte 0x00 "NVICIP91,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI91,Priority of interrupt 91"
|
|
group.byte 0x35C++0x00
|
|
line.byte 0x00 "NVICIP92,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI92,Priority of interrupt 92"
|
|
group.byte 0x35D++0x00
|
|
line.byte 0x00 "NVICIP93,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI93,Priority of interrupt 93"
|
|
group.byte 0x35E++0x00
|
|
line.byte 0x00 "NVICIP94,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI94,Priority of interrupt 94"
|
|
group.byte 0x35F++0x00
|
|
line.byte 0x00 "NVICIP95,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI95,Priority of interrupt 95"
|
|
group.byte 0x360++0x00
|
|
line.byte 0x00 "NVICIP96,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI96,Priority of interrupt 96"
|
|
group.byte 0x361++0x00
|
|
line.byte 0x00 "NVICIP97,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI97,Priority of interrupt 97"
|
|
group.byte 0x362++0x00
|
|
line.byte 0x00 "NVICIP98,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI98,Priority of interrupt 98"
|
|
group.byte 0x363++0x00
|
|
line.byte 0x00 "NVICIP99,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI99,Priority of interrupt 99"
|
|
group.byte 0x364++0x00
|
|
line.byte 0x00 "NVICIP100,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI100,Priority of interrupt 100"
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "NVICIP101,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI101,Priority of interrupt 101"
|
|
group.byte 0x366++0x00
|
|
line.byte 0x00 "NVICIP102,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI102,Priority of interrupt 102"
|
|
group.byte 0x367++0x00
|
|
line.byte 0x00 "NVICIP103,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI103,Priority of interrupt 103"
|
|
group.byte 0x368++0x00
|
|
line.byte 0x00 "NVICIP104,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI104,Priority of interrupt 104"
|
|
group.byte 0x369++0x00
|
|
line.byte 0x00 "NVICIP105,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI105,Priority of interrupt 105"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "NVICSTIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-239"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "NVIC0"
|
|
base ad:0xE000E100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC0_ISER,Interrupt Set Enable Register"
|
|
bitfld.long 0x00 31. "SETENA31,INTMUX0 channel 3 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX0 channel 3..,1: write: enable INTMUX0 channel 3 interrupt.."
|
|
bitfld.long 0x00 30. "SETENA30,INTMUX0 channel 2 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX0 channel 2..,1: write: enable INTMUX0 channel 2 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "SETENA29,INTMUX0 channel 1 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX0 channel 1..,1: write: enable INTMUX0 channel 1 interrupt.."
|
|
bitfld.long 0x00 28. "SETENA28,INTMUX0 channel 0 interrupt interrupt set-enable bit" "0: write: no effect read: INTMUX0 channel 0..,1: write: enable INTMUX0 channel 0 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "SETENA27,RTC seconds interrupt set-enable bit" "0: write: no effect read: RTC seconds interrupt..,1: write: enable RTC seconds interrupt read: RTC.."
|
|
bitfld.long 0x00 26. "SETENA26,Low-Power Timer interrupt set-enable bit" "0: write: no effect read: Low-Power Timer..,1: write: enable Low-Power Timer interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 25. "SETENA25,Analog-to-Digital Converter 0 interrupt set-enable bit" "0: write: no effect read: Analog-to-Digital..,1: write: enable Analog-to-Digital Converter 0.."
|
|
bitfld.long 0x00 24. "SETENA24,Universal Serial Bus interrupt set-enable bit" "0: write: no effect read: Universal Serial Bus..,1: write: enable Universal Serial Bus interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "SETENA23,Reserved iv 39 interrupt set-enable bit" "0: write: no effect read: Reserved iv 39..,1: write: enable Reserved iv 39 interrupt read:.."
|
|
bitfld.long 0x00 22. "SETENA22,Low Leakage Wakeup interrupt set-enable bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: enable Low Leakage Wakeup interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "SETENA21,PORTE Pin detect interrupt set-enable bit" "0: write: no effect read: PORTE Pin detect..,1: write: enable PORTE Pin detect interrupt.."
|
|
bitfld.long 0x00 20. "SETENA20,PORTD Pin detect interrupt set-enable bit" "0: write: no effect read: PORTD Pin detect..,1: write: enable PORTD Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "SETENA19,PORTC Pin detect interrupt set-enable bit" "0: write: no effect read: PORTC Pin detect..,1: write: enable PORTC Pin detect interrupt.."
|
|
bitfld.long 0x00 18. "SETENA18,PORTB Pin detect interrupt set-enable bit" "0: write: no effect read: PORTB Pin detect..,1: write: enable PORTB Pin detect interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "SETENA17,PORTA Pin detect interrupt set-enable bit" "0: write: no effect read: PORTA Pin detect..,1: write: enable PORTA Pin detect interrupt.."
|
|
bitfld.long 0x00 16. "SETENA16,Reserved iv 32 interrupt set-enable bit" "0: write: no effect read: Reserved iv 32..,1: write: enable Reserved iv 32 interrupt read:.."
|
|
newline
|
|
bitfld.long 0x00 15. "SETENA15,Inter-Integrated Circuit 0 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 0.."
|
|
bitfld.long 0x00 14. "SETENA14,Inter-Integrated Circuit 0 interrupt set-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: enable Inter-Integrated Circuit 0.."
|
|
newline
|
|
bitfld.long 0x00 13. "SETENA13,LPUART1 status and error interrupt set-enable bit" "0: write: no effect read: LPUART1 status and..,1: write: enable LPUART1 status and error.."
|
|
bitfld.long 0x00 12. "SETENA12,LPUART0 status and error interrupt set-enable bit" "0: write: no effect read: LPUART0 status and..,1: write: enable LPUART0 status and error.."
|
|
newline
|
|
bitfld.long 0x00 11. "SETENA11,Serial Peripheral Interface 1 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 1.."
|
|
bitfld.long 0x00 10. "SETENA10,Serial Peripheral Interface 0 interrupt set-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: enable Serial Peripheral Interface 0.."
|
|
newline
|
|
bitfld.long 0x00 9. "SETENA9,Low Power Periodic Interrupt Timer interrupt set-enable bit" "0: write: no effect read: Low Power Periodic..,1: write: enable Low Power Periodic Interrupt.."
|
|
bitfld.long 0x00 8. "SETENA8,Timer/PWM module 2 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 2..,1: write: enable Timer/PWM module 2 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 7. "SETENA7,Timer/PWM module 1 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 1..,1: write: enable Timer/PWM module 1 interrupt.."
|
|
bitfld.long 0x00 6. "SETENA6,Timer/PWM module 0 interrupt set-enable bit" "0: write: no effect read: Timer/PWM module 0..,1: write: enable Timer/PWM module 0 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 5. "SETENA5,FLEXIO0 interrupt set-enable bit" "0: write: no effect read: FLEXIO0 interrupt..,1: write: enable FLEXIO0 interrupt read: FLEXIO0.."
|
|
bitfld.long 0x00 4. "SETENA4,CTI0 or DMA0 error interrupt set-enable bit" "0: write: no effect read: CTI0 or DMA0 error..,1: write: enable CTI0 or DMA0 error interrupt.."
|
|
newline
|
|
bitfld.long 0x00 3. "SETENA3,DMA0 channel 3/7 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA0 channel 3/7..,1: write: enable DMA0 channel 3/7 transfer.."
|
|
bitfld.long 0x00 2. "SETENA2,DMA0 channel 2/6 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA0 channel 2/6..,1: write: enable DMA0 channel 2/6 transfer.."
|
|
newline
|
|
bitfld.long 0x00 1. "SETENA1,DMA0 channel 1/5 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA0 channel 1/5..,1: write: enable DMA0 channel 1/5 transfer.."
|
|
bitfld.long 0x00 0. "SETENA0,DMA0 channel 0/4 transfer complete interrupt set-enable bit" "0: write: no effect read: DMA0 channel 0/4..,1: write: enable DMA0 channel 0/4 transfer.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC0_ICER,Interrupt Clear Enable Register"
|
|
bitfld.long 0x00 31. "CLRENA31,INTMUX0 channel 3 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX0 channel 3..,1: write: disable INTMUX0 channel 3 interrupt.."
|
|
bitfld.long 0x00 30. "CLRENA30,INTMUX0 channel 2 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX0 channel 2..,1: write: disable INTMUX0 channel 2 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "CLRENA29,INTMUX0 channel 1 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX0 channel 1..,1: write: disable INTMUX0 channel 1 interrupt.."
|
|
bitfld.long 0x00 28. "CLRENA28,INTMUX0 channel 0 interrupt interrupt clear-enable bit" "0: write: no effect read: INTMUX0 channel 0..,1: write: disable INTMUX0 channel 0 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "CLRENA27,RTC seconds interrupt clear-enable bit" "0: write: no effect read: RTC seconds interrupt..,1: write: disable RTC seconds interrupt read:.."
|
|
bitfld.long 0x00 26. "CLRENA26,Low-Power Timer interrupt clear-enable bit" "0: write: no effect read: Low-Power Timer..,1: write: disable Low-Power Timer interrupt.."
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newline
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bitfld.long 0x00 25. "CLRENA25,Analog-to-Digital Converter 0 interrupt clear-enable bit" "0: write: no effect read: Analog-to-Digital..,1: write: disable Analog-to-Digital Converter 0.."
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bitfld.long 0x00 24. "CLRENA24,Universal Serial Bus interrupt clear-enable bit" "0: write: no effect read: Universal Serial Bus..,1: write: disable Universal Serial Bus interrupt.."
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newline
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bitfld.long 0x00 23. "CLRENA23,Reserved iv 39 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 39..,1: write: disable Reserved iv 39 interrupt read:.."
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bitfld.long 0x00 22. "CLRENA22,Low Leakage Wakeup interrupt clear-enable bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: disable Low Leakage Wakeup interrupt.."
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newline
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bitfld.long 0x00 21. "CLRENA21,PORTE Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTE Pin detect..,1: write: disable PORTE Pin detect interrupt.."
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bitfld.long 0x00 20. "CLRENA20,PORTD Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTD Pin detect..,1: write: disable PORTD Pin detect interrupt.."
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newline
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bitfld.long 0x00 19. "CLRENA19,PORTC Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTC Pin detect..,1: write: disable PORTC Pin detect interrupt.."
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bitfld.long 0x00 18. "CLRENA18,PORTB Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTB Pin detect..,1: write: disable PORTB Pin detect interrupt.."
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|
newline
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bitfld.long 0x00 17. "CLRENA17,PORTA Pin detect interrupt clear-enable bit" "0: write: no effect read: PORTA Pin detect..,1: write: disable PORTA Pin detect interrupt.."
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bitfld.long 0x00 16. "CLRENA16,Reserved iv 32 interrupt clear-enable bit" "0: write: no effect read: Reserved iv 32..,1: write: disable Reserved iv 32 interrupt read:.."
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newline
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bitfld.long 0x00 15. "CLRENA15,Inter-Integrated Circuit 0 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 0.."
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bitfld.long 0x00 14. "CLRENA14,Inter-Integrated Circuit 0 interrupt clear-enable bit" "0: write: no effect read: Inter-Integrated..,1: write: disable Inter-Integrated Circuit 0.."
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newline
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bitfld.long 0x00 13. "CLRENA13,LPUART1 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART1 status and..,1: write: disable LPUART1 status and error.."
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bitfld.long 0x00 12. "CLRENA12,LPUART0 status and error interrupt clear-enable bit" "0: write: no effect read: LPUART0 status and..,1: write: disable LPUART0 status and error.."
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|
newline
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bitfld.long 0x00 11. "CLRENA11,Serial Peripheral Interface 1 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 1.."
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bitfld.long 0x00 10. "CLRENA10,Serial Peripheral Interface 0 interrupt clear-enable bit" "0: write: no effect read: Serial Peripheral..,1: write: disable Serial Peripheral Interface 0.."
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newline
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bitfld.long 0x00 9. "CLRENA9,Low Power Periodic Interrupt Timer interrupt clear-enable bit" "0: write: no effect read: Low Power Periodic..,1: write: disable Low Power Periodic Interrupt.."
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bitfld.long 0x00 8. "CLRENA8,Timer/PWM module 2 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 2..,1: write: disable Timer/PWM module 2 interrupt.."
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newline
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bitfld.long 0x00 7. "CLRENA7,Timer/PWM module 1 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 1..,1: write: disable Timer/PWM module 1 interrupt.."
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bitfld.long 0x00 6. "CLRENA6,Timer/PWM module 0 interrupt clear-enable bit" "0: write: no effect read: Timer/PWM module 0..,1: write: disable Timer/PWM module 0 interrupt.."
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newline
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bitfld.long 0x00 5. "CLRENA5,FLEXIO0 interrupt clear-enable bit" "0: write: no effect read: FLEXIO0 interrupt..,1: write: disable FLEXIO0 interrupt read:.."
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bitfld.long 0x00 4. "CLRENA4,CTI0 or DMA0 error interrupt clear-enable bit" "0: write: no effect read: CTI0 or DMA0 error..,1: write: disable CTI0 or DMA0 error interrupt.."
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newline
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bitfld.long 0x00 3. "CLRENA3,DMA0 channel 3/7 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA0 channel 3/7..,1: write: disable DMA0 channel 3/7 transfer.."
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bitfld.long 0x00 2. "CLRENA2,DMA0 channel 2/6 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA0 channel 2/6..,1: write: disable DMA0 channel 2/6 transfer.."
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newline
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bitfld.long 0x00 1. "CLRENA1,DMA0 channel 1/5 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA0 channel 1/5..,1: write: disable DMA0 channel 1/5 transfer.."
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bitfld.long 0x00 0. "CLRENA0,DMA0 channel 0/4 transfer complete interrupt clear-enable bit" "0: write: no effect read: DMA0 channel 0/4..,1: write: disable DMA0 channel 0/4 transfer.."
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group.long 0x100++0x03
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line.long 0x00 "NVIC0_ISPR,Interrupt Set Pending Register"
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bitfld.long 0x00 31. "SETPEND31,INTMUX0 channel 3 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX0 channel 3..,1: write: changes the INTMUX0 channel 3.."
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bitfld.long 0x00 30. "SETPEND30,INTMUX0 channel 2 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX0 channel 2..,1: write: changes the INTMUX0 channel 2.."
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newline
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bitfld.long 0x00 29. "SETPEND29,INTMUX0 channel 1 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX0 channel 1..,1: write: changes the INTMUX0 channel 1.."
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bitfld.long 0x00 28. "SETPEND28,INTMUX0 channel 0 interrupt interrupt set-pending bit" "0: write: no effect read: INTMUX0 channel 0..,1: write: changes the INTMUX0 channel 0.."
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newline
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bitfld.long 0x00 27. "SETPEND27,RTC seconds interrupt set-pending bit" "0: write: no effect read: RTC seconds interrupt..,1: write: changes the RTC seconds interrupt.."
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bitfld.long 0x00 26. "SETPEND26,Low-Power Timer interrupt set-pending bit" "0: write: no effect read: Low-Power Timer..,1: write: changes the Low-Power Timer interrupt.."
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newline
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bitfld.long 0x00 25. "SETPEND25,Analog-to-Digital Converter 0 interrupt set-pending bit" "0: write: no effect read: Analog-to-Digital..,1: write: changes the Analog-to-Digital.."
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bitfld.long 0x00 24. "SETPEND24,Universal Serial Bus interrupt set-pending bit" "0: write: no effect read: Universal Serial Bus..,1: write: changes the Universal Serial Bus.."
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newline
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bitfld.long 0x00 23. "SETPEND23,Reserved iv 39 interrupt set-pending bit" "0: write: no effect read: Reserved iv 39..,1: write: changes the Reserved iv 39 interrupt.."
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bitfld.long 0x00 22. "SETPEND22,Low Leakage Wakeup interrupt set-pending bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: changes the Low Leakage Wakeup.."
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newline
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bitfld.long 0x00 21. "SETPEND21,PORTE Pin detect interrupt set-pending bit" "0: write: no effect read: PORTE Pin detect..,1: write: changes the PORTE Pin detect interrupt.."
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bitfld.long 0x00 20. "SETPEND20,PORTD Pin detect interrupt set-pending bit" "0: write: no effect read: PORTD Pin detect..,1: write: changes the PORTD Pin detect interrupt.."
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newline
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bitfld.long 0x00 19. "SETPEND19,PORTC Pin detect interrupt set-pending bit" "0: write: no effect read: PORTC Pin detect..,1: write: changes the PORTC Pin detect interrupt.."
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bitfld.long 0x00 18. "SETPEND18,PORTB Pin detect interrupt set-pending bit" "0: write: no effect read: PORTB Pin detect..,1: write: changes the PORTB Pin detect interrupt.."
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newline
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bitfld.long 0x00 17. "SETPEND17,PORTA Pin detect interrupt set-pending bit" "0: write: no effect read: PORTA Pin detect..,1: write: changes the PORTA Pin detect interrupt.."
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bitfld.long 0x00 16. "SETPEND16,Reserved iv 32 interrupt set-pending bit" "0: write: no effect read: Reserved iv 32..,1: write: changes the Reserved iv 32 interrupt.."
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newline
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bitfld.long 0x00 15. "SETPEND15,Inter-Integrated Circuit 0 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 0.."
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bitfld.long 0x00 14. "SETPEND14,Inter-Integrated Circuit 0 interrupt set-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: changes the Inter-Integrated Circuit 0.."
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newline
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bitfld.long 0x00 13. "SETPEND13,LPUART1 status and error interrupt set-pending bit" "0: write: no effect read: LPUART1 status and..,1: write: changes the LPUART1 status and error.."
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bitfld.long 0x00 12. "SETPEND12,LPUART0 status and error interrupt set-pending bit" "0: write: no effect read: LPUART0 status and..,1: write: changes the LPUART0 status and error.."
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newline
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bitfld.long 0x00 11. "SETPEND11,Serial Peripheral Interface 1 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
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bitfld.long 0x00 10. "SETPEND10,Serial Peripheral Interface 0 interrupt set-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: changes the Serial Peripheral.."
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newline
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bitfld.long 0x00 9. "SETPEND9,Low Power Periodic Interrupt Timer interrupt set-pending bit" "0: write: no effect read: Low Power Periodic..,1: write: changes the Low Power Periodic.."
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bitfld.long 0x00 8. "SETPEND8,Timer/PWM module 2 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 2..,1: write: changes the Timer/PWM module 2.."
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newline
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bitfld.long 0x00 7. "SETPEND7,Timer/PWM module 1 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 1..,1: write: changes the Timer/PWM module 1.."
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bitfld.long 0x00 6. "SETPEND6,Timer/PWM module 0 interrupt set-pending bit" "0: write: no effect read: Timer/PWM module 0..,1: write: changes the Timer/PWM module 0.."
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newline
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bitfld.long 0x00 5. "SETPEND5,FLEXIO0 interrupt set-pending bit" "0: write: no effect read: FLEXIO0 interrupt is..,1: write: changes the FLEXIO0 interrupt state to.."
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bitfld.long 0x00 4. "SETPEND4,CTI0 or DMA0 error interrupt set-pending bit" "0: write: no effect read: CTI0 or DMA0 error..,1: write: changes the CTI0 or DMA0 error.."
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newline
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bitfld.long 0x00 3. "SETPEND3,DMA0 channel 3/7 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA0 channel 3/7..,1: write: changes the DMA0 channel 3/7 transfer.."
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bitfld.long 0x00 2. "SETPEND2,DMA0 channel 2/6 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA0 channel 2/6..,1: write: changes the DMA0 channel 2/6 transfer.."
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newline
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bitfld.long 0x00 1. "SETPEND1,DMA0 channel 1/5 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA0 channel 1/5..,1: write: changes the DMA0 channel 1/5 transfer.."
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bitfld.long 0x00 0. "SETPEND0,DMA0 channel 0/4 transfer complete interrupt set-pending bit" "0: write: no effect read: DMA0 channel 0/4..,1: write: changes the DMA0 channel 0/4 transfer.."
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group.long 0x180++0x03
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line.long 0x00 "NVIC0_ICPR,Interrupt Clear Pending Register"
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bitfld.long 0x00 31. "CLRPEND31,INTMUX0 channel 3 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX0 channel 3..,1: write: removes pending state from the INTMUX0.."
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bitfld.long 0x00 30. "CLRPEND30,INTMUX0 channel 2 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX0 channel 2..,1: write: removes pending state from the INTMUX0.."
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newline
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bitfld.long 0x00 29. "CLRPEND29,INTMUX0 channel 1 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX0 channel 1..,1: write: removes pending state from the INTMUX0.."
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bitfld.long 0x00 28. "CLRPEND28,INTMUX0 channel 0 interrupt interrupt clear-pending bit" "0: write: no effect read: INTMUX0 channel 0..,1: write: removes pending state from the INTMUX0.."
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newline
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bitfld.long 0x00 27. "CLRPEND27,RTC seconds interrupt clear-pending bit" "0: write: no effect read: RTC seconds interrupt..,1: write: removes pending state from the RTC.."
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|
bitfld.long 0x00 26. "CLRPEND26,Low-Power Timer interrupt clear-pending bit" "0: write: no effect read: Low-Power Timer..,1: write: removes pending state from the.."
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newline
|
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bitfld.long 0x00 25. "CLRPEND25,Analog-to-Digital Converter 0 interrupt clear-pending bit" "0: write: no effect read: Analog-to-Digital..,1: write: removes pending state from the.."
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bitfld.long 0x00 24. "CLRPEND24,Universal Serial Bus interrupt clear-pending bit" "0: write: no effect read: Universal Serial Bus..,1: write: removes pending state from the.."
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newline
|
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bitfld.long 0x00 23. "CLRPEND23,Reserved iv 39 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 39..,1: write: removes pending state from the.."
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bitfld.long 0x00 22. "CLRPEND22,Low Leakage Wakeup interrupt clear-pending bit" "0: write: no effect read: Low Leakage Wakeup..,1: write: removes pending state from the Low.."
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newline
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bitfld.long 0x00 21. "CLRPEND21,PORTE Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTE Pin detect..,1: write: removes pending state from the PORTE.."
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bitfld.long 0x00 20. "CLRPEND20,PORTD Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTD Pin detect..,1: write: removes pending state from the PORTD.."
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newline
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bitfld.long 0x00 19. "CLRPEND19,PORTC Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTC Pin detect..,1: write: removes pending state from the PORTC.."
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bitfld.long 0x00 18. "CLRPEND18,PORTB Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTB Pin detect..,1: write: removes pending state from the PORTB.."
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newline
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bitfld.long 0x00 17. "CLRPEND17,PORTA Pin detect interrupt clear-pending bit" "0: write: no effect read: PORTA Pin detect..,1: write: removes pending state from the PORTA.."
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bitfld.long 0x00 16. "CLRPEND16,Reserved iv 32 interrupt clear-pending bit" "0: write: no effect read: Reserved iv 32..,1: write: removes pending state from the.."
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newline
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bitfld.long 0x00 15. "CLRPEND15,Inter-Integrated Circuit 0 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
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bitfld.long 0x00 14. "CLRPEND14,Inter-Integrated Circuit 0 interrupt clear-pending bit" "0: write: no effect read: Inter-Integrated..,1: write: removes pending state from the.."
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newline
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bitfld.long 0x00 13. "CLRPEND13,LPUART1 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART1 status and..,1: write: removes pending state from the LPUART1.."
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bitfld.long 0x00 12. "CLRPEND12,LPUART0 status and error interrupt clear-pending bit" "0: write: no effect read: LPUART0 status and..,1: write: removes pending state from the LPUART0.."
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newline
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bitfld.long 0x00 11. "CLRPEND11,Serial Peripheral Interface 1 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
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|
bitfld.long 0x00 10. "CLRPEND10,Serial Peripheral Interface 0 interrupt clear-pending bit" "0: write: no effect read: Serial Peripheral..,1: write: removes pending state from the Serial.."
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newline
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bitfld.long 0x00 9. "CLRPEND9,Low Power Periodic Interrupt Timer interrupt clear-pending bit" "0: write: no effect read: Low Power Periodic..,1: write: removes pending state from the Low.."
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bitfld.long 0x00 8. "CLRPEND8,Timer/PWM module 2 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 2..,1: write: removes pending state from the.."
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newline
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bitfld.long 0x00 7. "CLRPEND7,Timer/PWM module 1 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 1..,1: write: removes pending state from the.."
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bitfld.long 0x00 6. "CLRPEND6,Timer/PWM module 0 interrupt clear-pending bit" "0: write: no effect read: Timer/PWM module 0..,1: write: removes pending state from the.."
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newline
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bitfld.long 0x00 5. "CLRPEND5,FLEXIO0 interrupt clear-pending bit" "0: write: no effect read: FLEXIO0 interrupt is..,1: write: removes pending state from the FLEXIO0.."
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bitfld.long 0x00 4. "CLRPEND4,CTI0 or DMA0 error interrupt clear-pending bit" "0: write: no effect read: CTI0 or DMA0 error..,1: write: removes pending state from the CTI0 or.."
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newline
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bitfld.long 0x00 3. "CLRPEND3,DMA0 channel 3/7 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA0 channel 3/7..,1: write: removes pending state from the DMA0.."
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bitfld.long 0x00 2. "CLRPEND2,DMA0 channel 2/6 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA0 channel 2/6..,1: write: removes pending state from the DMA0.."
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newline
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bitfld.long 0x00 1. "CLRPEND1,DMA0 channel 1/5 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA0 channel 1/5..,1: write: removes pending state from the DMA0.."
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bitfld.long 0x00 0. "CLRPEND0,DMA0 channel 0/4 transfer complete interrupt clear-pending bit" "0: write: no effect read: DMA0 channel 0/4..,1: write: removes pending state from the DMA0.."
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group.long 0x300++0x03
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line.long 0x00 "NVIC0_IPR0,Interrupt Priority Register 0"
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bitfld.long 0x00 30.--31. "PRI_3,Priority of the DMA0 channel 3/7 transfer complete interrupt" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_2,Priority of the DMA0 channel 2/6 transfer complete interrupt" "0,1,2,3"
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newline
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bitfld.long 0x00 14.--15. "PRI_1,Priority of the DMA0 channel 1/5 transfer complete interrupt" "0,1,2,3"
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bitfld.long 0x00 6.--7. "PRI_0,Priority of the DMA0 channel 0/4 transfer complete interrupt" "0,1,2,3"
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group.long 0x304++0x03
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line.long 0x00 "NVIC0_IPR1,Interrupt Priority Register 1"
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bitfld.long 0x00 30.--31. "PRI_7,Priority of the Timer/PWM module 1 interrupt" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_6,Priority of the Timer/PWM module 0 interrupt" "0,1,2,3"
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newline
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bitfld.long 0x00 14.--15. "PRI_5,Priority of the FLEXIO0 interrupt" "0,1,2,3"
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bitfld.long 0x00 6.--7. "PRI_4,Priority of the CTI0 or DMA0 error interrupt" "0,1,2,3"
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group.long 0x308++0x03
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line.long 0x00 "NVIC0_IPR2,Interrupt Priority Register 2"
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bitfld.long 0x00 30.--31. "PRI_11,Priority of the Serial Peripheral Interface 1 interrupt" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_10,Priority of the Serial Peripheral Interface 0 interrupt" "0,1,2,3"
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newline
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bitfld.long 0x00 14.--15. "PRI_9,Priority of the Low Power Periodic Interrupt Timer interrupt" "0,1,2,3"
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bitfld.long 0x00 6.--7. "PRI_8,Priority of the Timer/PWM module 2 interrupt" "0,1,2,3"
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group.long 0x30C++0x03
|
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line.long 0x00 "NVIC0_IPR3,Interrupt Priority Register 3"
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bitfld.long 0x00 30.--31. "PRI_15,Priority of the Inter-Integrated Circuit 0 interrupt" "0,1,2,3"
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|
bitfld.long 0x00 22.--23. "PRI_14,Priority of the Inter-Integrated Circuit 0 interrupt" "0,1,2,3"
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newline
|
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bitfld.long 0x00 14.--15. "PRI_13,Priority of the LPUART1 status and error interrupt" "0,1,2,3"
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|
bitfld.long 0x00 6.--7. "PRI_12,Priority of the LPUART0 status and error interrupt" "0,1,2,3"
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group.long 0x310++0x03
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line.long 0x00 "NVIC0_IPR4,Interrupt Priority Register 4"
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bitfld.long 0x00 30.--31. "PRI_19,Priority of the PORTC Pin detect interrupt" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_18,Priority of the PORTB Pin detect interrupt" "0,1,2,3"
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newline
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bitfld.long 0x00 14.--15. "PRI_17,Priority of the PORTA Pin detect interrupt" "0,1,2,3"
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bitfld.long 0x00 6.--7. "PRI_16,Priority of the Reserved iv 32 interrupt" "0,1,2,3"
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group.long 0x314++0x03
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line.long 0x00 "NVIC0_IPR5,Interrupt Priority Register 5"
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bitfld.long 0x00 30.--31. "PRI_23,Priority of the Reserved iv 39 interrupt" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_22,Priority of the Low Leakage Wakeup interrupt" "0,1,2,3"
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newline
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bitfld.long 0x00 14.--15. "PRI_21,Priority of the PORTE Pin detect interrupt" "0,1,2,3"
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bitfld.long 0x00 6.--7. "PRI_20,Priority of the PORTD Pin detect interrupt" "0,1,2,3"
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group.long 0x318++0x03
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line.long 0x00 "NVIC0_IPR6,Interrupt Priority Register 6"
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bitfld.long 0x00 30.--31. "PRI_27,Priority of the RTC seconds interrupt" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_26,Priority of the Low-Power Timer interrupt" "0,1,2,3"
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|
newline
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bitfld.long 0x00 14.--15. "PRI_25,Priority of the Analog-to-Digital Converter 0 interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_24,Priority of the Universal Serial Bus interrupt" "0,1,2,3"
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|
group.long 0x31C++0x03
|
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line.long 0x00 "NVIC0_IPR7,Interrupt Priority Register 7"
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|
bitfld.long 0x00 30.--31. "PRI_31,Priority of the INTMUX0 channel 3 interrupt interrupt" "0,1,2,3"
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|
bitfld.long 0x00 22.--23. "PRI_30,Priority of the INTMUX0 channel 2 interrupt interrupt" "0,1,2,3"
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newline
|
|
bitfld.long 0x00 14.--15. "PRI_29,Priority of the INTMUX0 channel 1 interrupt interrupt" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_28,Priority of the INTMUX0 channel 0 interrupt interrupt" "0,1,2,3"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "OSC0 (Oscillator)"
|
|
base ad:0x40065000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR,OSC Control Register"
|
|
bitfld.byte 0x00 7. "ERCLKEN,External Reference Enable" "0: External reference clock is inactive,1: External reference clock is enabled"
|
|
bitfld.byte 0x00 5. "EREFSTEN,External Reference Stop Enable" "0: External reference clock is disabled in Stop..,1: External reference clock stays enabled in.."
|
|
newline
|
|
bitfld.byte 0x00 3. "SC2P,Oscillator 2 pF Capacitor Load Configure" "0: Disable the selection,1: Add 2 pF capacitor to the oscillator load"
|
|
bitfld.byte 0x00 2. "SC4P,Oscillator 4 pF Capacitor Load Configure" "0: Disable the selection,1: Add 4 pF capacitor to the oscillator load"
|
|
newline
|
|
bitfld.byte 0x00 1. "SC8P,Oscillator 8 pF Capacitor Load Configure" "0: Disable the selection,1: Add 8 pF capacitor to the oscillator load"
|
|
bitfld.byte 0x00 0. "SC16P,Oscillator 16 pF Capacitor Load Configure" "0: Disable the selection,1: Add 16 pF capacitor to the oscillator load"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "PCC"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "PCC0"
|
|
base ad:0x4002B000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCC_MSCM,PCC MSCM Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCC_AXBS0,PCC AXBS0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCC_DMA0,PCC DMA0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCC_FLEXBUS,PCC FLEXBUS Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCC_XRDC_MGR,PCC XRDC_MGR Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PCC_XRDC_PAC,PCC XRDC_PAC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCC_XRDC_MRC,PCC XRDC_MRC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCC_SEMA42_0,PCC SEMA42_0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PCC_DMAMUX0,PCC DMAMUX0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PCC_EWM,PCC EWM Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PCC_MUA,PCC MUA Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PCC_CRC0,PCC CRC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PCC_LPIT0,PCC LPIT0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PCC_TPM0,PCC TPM0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PCC_TPM1,PCC TPM1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PCC_TPM2,PCC TPM2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PCC_EMVSIM0,PCC EMVSIM0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PCC_FLEXIO0,PCC FLEXIO0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PCC_LPI2C0,PCC LPI2C0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PCC_LPI2C1,PCC LPI2C1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PCC_LPI2C2,PCC LPI2C2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PCC_I2S0,PCC I2S0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PCC_USDHC0,PCC USDHC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PCC_LPSPI0,PCC LPSPI0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCC_LPSPI1,PCC LPSPI1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCC_LPSPI2,PCC LPSPI2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCC_LPUART0,PCC LPUART0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PCC_LPUART1,PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCC_LPUART2,PCC LPUART2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCC_USB0,PCC USB0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCC_PORTA,PCC PORTA Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PCC_PORTB,PCC PORTB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCC_PORTC,PCC PORTC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCC_PORTD,PCC PORTD Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCC_LPADC0,PCC LPADC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
newline
|
|
bitfld.long 0x00 3. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
bitfld.long 0x00 0.--2. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCC_LPDAC0,PCC LPDAC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCC_VREF,PCC VREF Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PCC_TRACE,PCC TRACE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
newline
|
|
bitfld.long 0x00 3. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
bitfld.long 0x00 0.--2. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "PCC0"
|
|
base ad:0x4007A000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCC_MSCM,PCC MSCM Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCC_AXBS0,PCC AXBS0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCC_DMA0,PCC DMA0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCC_FLEXBUS,PCC FLEXBUS Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCC_XRDC_MGR,PCC XRDC_MGR Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PCC_XRDC_PAC,PCC XRDC_PAC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCC_XRDC_MRC,PCC XRDC_MRC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCC_SEMA42_0,PCC SEMA42_0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PCC_DMAMUX0,PCC DMAMUX0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PCC_EWM,PCC EWM Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PCC_MUA,PCC MUA Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PCC_CRC0,PCC CRC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PCC_LPIT0,PCC LPIT0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PCC_TPM0,PCC TPM0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PCC_TPM1,PCC TPM1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PCC_TPM2,PCC TPM2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PCC_EMVSIM0,PCC EMVSIM0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PCC_FLEXIO0,PCC FLEXIO0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PCC_LPI2C0,PCC LPI2C0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PCC_LPI2C1,PCC LPI2C1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PCC_LPI2C2,PCC LPI2C2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PCC_I2S0,PCC I2S0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PCC_USDHC0,PCC USDHC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PCC_LPSPI0,PCC LPSPI0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCC_LPSPI1,PCC LPSPI1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCC_LPSPI2,PCC LPSPI2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCC_LPUART0,PCC LPUART0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PCC_LPUART1,PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCC_LPUART2,PCC LPUART2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCC_USB0,PCC USB0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCC_PORTA,PCC PORTA Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PCC_PORTB,PCC PORTB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCC_PORTC,PCC PORTC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCC_PORTD,PCC PORTD Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCC_LPADC0,PCC LPADC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
newline
|
|
bitfld.long 0x00 3. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
bitfld.long 0x00 0.--2. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCC_LPDAC0,PCC LPDAC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCC_VREF,PCC VREF Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PCC_TRACE,PCC TRACE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
newline
|
|
bitfld.long 0x00 3. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
bitfld.long 0x00 0.--2. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "PCC1"
|
|
base ad:0x41027000
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCC_DMA1,PCC DMA1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCC_GPIOE,PCC GPIOE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PCC_XRDC_PAC,PCC XRDC_PAC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCC_XRDC_MRC,PCC XRDC_MRC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCC_SEMA42_1,PCC SEMA42_1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PCC_DMAMUX1,PCC DMAMUX1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PCC_INTMUX1,PCC INTMUX1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PCC_MUB,PCC MUB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PCC_CAU3,PCC CAU3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PCC_TRNG,PCC TRNG Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PCC_LPIT1,PCC LPIT1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PCC_TPM3,PCC TPM3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PCC_LPI2C3,PCC LPI2C3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PCC_LPSPI3,PCC LPSPI3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PCC_LPUART3,PCC LPUART3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PCC_PORTE,PCC PORTE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PCC_MTB,PCC MTB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PCC_EXT_CLK,PCC EXT_CLK Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "PCC1"
|
|
base ad:0x400FA000
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCC_DMA1,PCC DMA1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCC_GPIOE,PCC GPIOE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PCC_XRDC_PAC,PCC XRDC_PAC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCC_XRDC_MRC,PCC XRDC_MRC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCC_SEMA42_1,PCC SEMA42_1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PCC_DMAMUX1,PCC DMAMUX1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PCC_INTMUX1,PCC INTMUX1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PCC_MUB,PCC MUB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PCC_CAU3,PCC CAU3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PCC_TRNG,PCC TRNG Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PCC_LPIT1,PCC LPIT1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PCC_TPM3,PCC TPM3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PCC_LPI2C3,PCC LPI2C3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "PCC_LPSPI3,PCC LPSPI3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PCC_LPUART3,PCC LPUART3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PCC_PORTE,PCC PORTE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PCC_MTB,PCC MTB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PCC_EXT_CLK,PCC EXT_CLK Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
rbitfld.long 0x00 29. "INUSE,In use flag" "0: Peripheral is not being used,1: Peripheral is being used"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "PIT (Periodic Interrupt Timer)"
|
|
base ad:0x40037000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,PIT Module Control Register"
|
|
bitfld.long 0x00 1. "MDIS,Module Disable - (PIT section)" "0: Clock for standard PIT timers is enabled,1: Clock for standard PIT timers is disabled"
|
|
bitfld.long 0x00 0. "FRZ,Freeze" "0: Timers continue to run in Debug mode,1: Timers are stopped in Debug mode"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register"
|
|
hexmask.long 0x00 0.--31. 1. "LTH,Life Timer value"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "LTMR64L,PIT Lower Lifetime Timer Register"
|
|
hexmask.long 0x00 0.--31. 1. "LTL,Life Timer value"
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "LDVAL$1,Timer Load Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSV,Timer Start Value"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
|
|
rgroup.long ($2+0x104)++0x03
|
|
line.long 0x00 "CVAL$1,Current Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TVL,Current Timer Value"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
|
|
group.long ($2+0x108)++0x03
|
|
line.long 0x00 "TCTRL$1,Timer Control Register"
|
|
bitfld.long 0x00 2. "CHN,Chain Mode" "0: Timer is not chained,1: Timer is chained to previous timer"
|
|
bitfld.long 0x00 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from Timer n are disabled,1: Interrupt will be requested whenever TIF is set"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: Timer n is disabled,1: Timer n is enabled"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
|
|
group.long ($2+0x10C)++0x03
|
|
line.long 0x00 "TFLG$1,Timer Flag Register"
|
|
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag" "0: Timeout has not yet occurred,1: Timeout has occurred"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x4007D000
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 register"
|
|
rbitfld.byte 0x00 7. "LVDF,Low-Voltage Detect Flag" "0: Low-voltage event not detected,1: Low-voltage event detected"
|
|
bitfld.byte 0x00 6. "LVDACK,Low-Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "LVDIE,Low-Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVDF = 1"
|
|
bitfld.byte 0x00 4. "LVDRE,Low-Voltage Detect Reset Enable" "0: LVDF does not generate hardware resets,1: Force an MCU reset when LVDF = 1"
|
|
newline
|
|
bitfld.byte 0x00 0.--1. "LVDV,Low-Voltage Detect Voltage Select" "0: Low trip point selected (V LVD = V LVDL ),1: High trip point selected (V LVD = V LVDH ),?..."
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "LVDSC2,Low Voltage Detect Status And Control 2 register"
|
|
rbitfld.byte 0x00 7. "LVWF,Low-Voltage Warning Flag" "0: Low-voltage warning event not detected,1: Low-voltage warning event detected"
|
|
bitfld.byte 0x00 6. "LVWACK,Low-Voltage Warning Acknowledge" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "LVWIE,Low-Voltage Warning Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVWF = 1"
|
|
bitfld.byte 0x00 0.--1. "LVWV,Low-Voltage Warning Voltage Select" "0: Low trip point selected (VLVW = VLVW1),1: Mid 1 trip point selected (VLVW = VLVW2),2: Mid 2 trip point selected (VLVW = VLVW3),3: High trip point selected (VLVW = VLVW4)"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "REGSC,Regulator Status And Control register"
|
|
bitfld.byte 0x00 4. "BGEN,Bandgap Enable In VLPx Operation" "0: Bandgap voltage reference is disabled in VLPx..,1: Bandgap voltage reference is enabled in VLPx.."
|
|
bitfld.byte 0x00 3. "ACKISO,Acknowledge Isolation" "0: Peripherals and I/O pads are in normal run..,1: Certain peripherals and I/O pads are in an.."
|
|
newline
|
|
rbitfld.byte 0x00 2. "REGONS,Regulator In Run Regulation Status" "0: Regulator is in stop regulation or in..,1: Regulator is in run regulation"
|
|
bitfld.byte 0x00 0. "BGBE,Bandgap Buffer Enable" "0: Bandgap buffer not enabled,1: Bandgap buffer enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter register"
|
|
bitfld.long 0x00 1. "HVDE,HVD Enabled" "0,1"
|
|
bitfld.long 0x00 0. "VLPOE,VLPO Enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 register"
|
|
rbitfld.long 0x00 7. "LVDF,Low-Voltage Detect Flag" "0: Low-voltage event not detected,1: Low-voltage event detected"
|
|
bitfld.long 0x00 6. "LVDACK,Low-Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "LVDIE,Low-Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVDF = 1"
|
|
bitfld.long 0x00 4. "LVDRE,Low-Voltage Detect Reset Enable" "0: LVDF does not generate hardware resets,1: Force an MCU reset when LVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "LVDV,Low-Voltage Detect Voltage Select" "0: Low trip point selected (V LVD = V LVDL ),1: High trip point selected (V LVD = V LVDH ),?..."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LVDSC2,Low Voltage Detect Status And Control 2 register"
|
|
rbitfld.long 0x00 7. "LVWF,Low-Voltage Warning Flag" "0: Low-voltage warning event not detected,1: Low-voltage warning event detected"
|
|
bitfld.long 0x00 6. "LVWACK,Low-Voltage Warning Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "LVWIE,Low-Voltage Warning Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVWF = 1"
|
|
bitfld.long 0x00 0.--1. "LVWV,Low-Voltage Warning Voltage Select" "0: Low trip point selected (VLVW = VLVW1),1: Mid 1 trip point selected (VLVW = VLVW2),2: Mid 2 trip point selected (VLVW = VLVW3),3: High trip point selected (VLVW = VLVW4)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "REGSC,Regulator Status And Control register"
|
|
bitfld.long 0x00 6. "VLPO,VLPx Option" "0: Operating frequencies and SCG clocking modes..,1: If BGEN is also set operating frequencies and.."
|
|
bitfld.long 0x00 4. "BGEN,Bandgap Enable In VLPx Operation" "0: Bandgap voltage reference is disabled in VLPx..,1: Bandgap voltage reference is enabled in VLPx.."
|
|
newline
|
|
bitfld.long 0x00 3. "ACKISO,Acknowledge Isolation" "0: Peripherals and I/O pads are in normal run..,1: Certain peripherals and I/O pads are in an.."
|
|
rbitfld.long 0x00 2. "REGONS,Regulator In Run Regulation Status" "0: Regulator is in stop regulation or in..,1: Regulator is in run regulation"
|
|
newline
|
|
bitfld.long 0x00 0. "BGBE,Bandgap Buffer Enable" "0: Bandgap buffer not enabled,1: Bandgap buffer enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HVDSC1,High Voltage Detect Status And Control 1 register"
|
|
rbitfld.long 0x00 7. "HVDF,High-Voltage Detect Flag" "0: High-voltage event not detected,1: High-voltage event detected"
|
|
bitfld.long 0x00 6. "HVDACK,High-Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HVDIE,High-Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when HVDF = 1"
|
|
bitfld.long 0x00 4. "HVDRE,High-Voltage Detect Reset Enable" "0: HVDF does not generate hardware resets,1: Force an MCU reset when HVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 0. "HVDV,High-Voltage Detect Voltage Select" "0: Low trip point selected (V HVD = V HVDL ),1: High trip point selected (V HVD = V HVDH )"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "PORT (Pin Control and Interrupts)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "PORTA"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4005A000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40049000
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "5" "6" )(list 0x0 0x4 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "6" "7" )(list 0x0 0x4 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCR8,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCR9,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCR11,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "13" "14" )(list 0x0 0x4 )
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "14" "15" )(list 0x0 0x4 )
|
|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "18" "19" )(list 0x0 0x4 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PCR21,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "23" "24" )(list 0x0 0x4 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCR26,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
bitfld.long 0x00 31. "ISF31,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 30. "ISF30,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 29. "ISF29,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 28. "ISF28,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 27. "ISF27,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 26. "ISF26,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 25. "ISF25,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 24. "ISF24,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 23. "ISF23,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 22. "ISF22,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 21. "ISF21,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 20. "ISF20,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 19. "ISF19,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 18. "ISF18,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 17. "ISF17,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16. "ISF16,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 15. "ISF15,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 14. "ISF14,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 13. "ISF13,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 12. "ISF12,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ISF11,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 10. "ISF10,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "ISF9,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 8. "ISF8,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 7. "ISF7,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 6. "ISF6,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "ISF5,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 4. "ISF4,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "ISF3,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 2. "ISF2,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "ISF1,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 0. "ISF0,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "PORTA"
|
|
base ad:0x40046000
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "5" "6" )(list 0x0 0x4 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "6" "7" )(list 0x0 0x4 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCR8,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCR9,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCR11,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "13" "14" )(list 0x0 0x4 )
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "14" "15" )(list 0x0 0x4 )
|
|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "18" "19" )(list 0x0 0x4 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PCR21,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "23" "24" )(list 0x0 0x4 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCR26,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
bitfld.long 0x00 31. "ISF31,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 30. "ISF30,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 29. "ISF29,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 28. "ISF28,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 27. "ISF27,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 26. "ISF26,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 25. "ISF25,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 24. "ISF24,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 23. "ISF23,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 22. "ISF22,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 21. "ISF21,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 20. "ISF20,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 19. "ISF19,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 18. "ISF18,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 17. "ISF17,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16. "ISF16,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 15. "ISF15,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 14. "ISF14,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 13. "ISF13,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 12. "ISF12,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ISF11,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 10. "ISF10,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "ISF9,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 8. "ISF8,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 7. "ISF7,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 6. "ISF6,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "ISF5,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 4. "ISF4,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "ISF3,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 2. "ISF2,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "ISF1,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 0. "ISF0,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "PORTB"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4005B000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4004A000
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCR8,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCR9,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCR11,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCR11,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "12" "13" )(list 0x0 0x4 )
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PCR14,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PCR14,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "16" "17" )(list 0x0 0x4 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "19" "20" )(list 0x0 0x4 )
|
|
group.long ($2+0x4C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "20" "21" )(list 0x0 0x4 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "23" "24" )(list 0x0 0x4 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCR26,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
bitfld.long 0x00 31. "ISF31,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 30. "ISF30,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 29. "ISF29,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 28. "ISF28,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 27. "ISF27,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 26. "ISF26,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 25. "ISF25,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 24. "ISF24,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 23. "ISF23,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 22. "ISF22,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 21. "ISF21,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 20. "ISF20,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 19. "ISF19,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 18. "ISF18,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 17. "ISF17,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16. "ISF16,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 15. "ISF15,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 14. "ISF14,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 13. "ISF13,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 12. "ISF12,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ISF11,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 10. "ISF10,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "ISF9,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 8. "ISF8,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 7. "ISF7,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 6. "ISF6,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "ISF5,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 4. "ISF4,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "ISF3,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 2. "ISF2,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "ISF1,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 0. "ISF0,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "PORTB"
|
|
base ad:0x40047000
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCR8,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCR9,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCR11,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCR11,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "12" "13" )(list 0x0 0x4 )
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PCR14,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PCR14,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "16" "17" )(list 0x0 0x4 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
repeat 2. (strings "19" "20" )(list 0x0 0x4 )
|
|
group.long ($2+0x4C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "20" "21" )(list 0x0 0x4 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "23" "24" )(list 0x0 0x4 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCR26,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
bitfld.long 0x00 31. "ISF31,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 30. "ISF30,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 29. "ISF29,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 28. "ISF28,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 27. "ISF27,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 26. "ISF26,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 25. "ISF25,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 24. "ISF24,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 23. "ISF23,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 22. "ISF22,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 21. "ISF21,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 20. "ISF20,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 19. "ISF19,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 18. "ISF18,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 17. "ISF17,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16. "ISF16,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 15. "ISF15,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 14. "ISF14,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 13. "ISF13,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 12. "ISF12,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ISF11,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 10. "ISF10,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "ISF9,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 8. "ISF8,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 7. "ISF7,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 6. "ISF6,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "ISF5,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 4. "ISF4,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "ISF3,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 2. "ISF2,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "ISF1,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 0. "ISF0,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
tree.end
|
|
tree "PORTC"
|
|
base ad:0x40048000
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 6. (strings "7" "8" "9" "10" "11" "12" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 5. (strings "26" "27" "28" "29" "30" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "PORTC"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4005C000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4004B000
|
|
endif
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 6. (strings "7" "8" "9" "10" "11" "12" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 5. (strings "26" "27" "28" "29" "30" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
tree.end
|
|
tree "PORTD"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4005D000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4004C000
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "4" "5" )(list 0x0 0x4 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "5" "6" )(list 0x0 0x4 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCR8,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCR9,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "11" "12" )(list 0x0 0x4 )
|
|
group.long ($2+0x2C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "13" "14" )(list 0x0 0x4 )
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "14" "15" )(list 0x0 0x4 )
|
|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "18" "19" )(list 0x0 0x4 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "20" "21" )(list 0x0 0x4 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "23" "24" )(list 0x0 0x4 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCR26,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
bitfld.long 0x00 31. "ISF31,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 30. "ISF30,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 29. "ISF29,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 28. "ISF28,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 27. "ISF27,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 26. "ISF26,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 25. "ISF25,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 24. "ISF24,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 23. "ISF23,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 22. "ISF22,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 21. "ISF21,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 20. "ISF20,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 19. "ISF19,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 18. "ISF18,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 17. "ISF17,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16. "ISF16,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 15. "ISF15,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 14. "ISF14,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 13. "ISF13,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 12. "ISF12,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ISF11,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 10. "ISF10,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "ISF9,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 8. "ISF8,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 7. "ISF7,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 6. "ISF6,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "ISF5,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 4. "ISF4,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "ISF3,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 2. "ISF2,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "ISF1,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 0. "ISF0,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "PORTD"
|
|
base ad:0x40049000
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCR0,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCR1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B31*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B21*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "4" "5" )(list 0x0 0x4 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "5" "6" )(list 0x0 0x4 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PCR7,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCR8,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PCR9,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "11" "12" )(list 0x0 0x4 )
|
|
group.long ($2+0x2C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PCR12,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PCR13,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "13" "14" )(list 0x0 0x4 )
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "14" "15" )(list 0x0 0x4 )
|
|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PCR15,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCR16,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PCR17,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PCR18,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "18" "19" )(list 0x0 0x4 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCR19,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "20" "21" )(list 0x0 0x4 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "23" "24" )(list 0x0 0x4 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0x64)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PCR26,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCR27,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PCR28,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PCR29,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PCR30,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PCR31,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
rbitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
rbitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
rbitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
rbitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
rbitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
rbitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
bitfld.long 0x00 31. "GPWE15,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 30. "GPWE14,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 29. "GPWE13,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 28. "GPWE12,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 27. "GPWE11,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 26. "GPWE10,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 25. "GPWE9,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 24. "GPWE8,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 23. "GPWE7,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 22. "GPWE6,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 21. "GPWE5,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 20. "GPWE4,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 19. "GPWE3,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 18. "GPWE2,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 17. "GPWE1,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 16. "GPWE0,Global Pin Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
bitfld.long 0x00 15. "GIWE15,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 14. "GIWE14,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 13. "GIWE13,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 12. "GIWE12,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 11. "GIWE11,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 10. "GIWE10,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 9. "GIWE9,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GIWE8,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 7. "GIWE7,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 6. "GIWE6,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 5. "GIWE5,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 4. "GIWE4,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 3. "GIWE3,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 2. "GIWE2,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
bitfld.long 0x00 1. "GIWE1,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
newline
|
|
bitfld.long 0x00 0. "GIWE0,Global Interrupt Write Enable" "0: Corresponding Pin Control Register is not..,1: Corresponding Pin Control Register is updated.."
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
bitfld.long 0x00 31. "ISF31,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 30. "ISF30,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 29. "ISF29,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 28. "ISF28,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 27. "ISF27,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 26. "ISF26,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 25. "ISF25,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 24. "ISF24,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 23. "ISF23,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 22. "ISF22,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 21. "ISF21,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 20. "ISF20,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 19. "ISF19,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 18. "ISF18,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 17. "ISF17,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16. "ISF16,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 15. "ISF15,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 14. "ISF14,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 13. "ISF13,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 12. "ISF12,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ISF11,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 10. "ISF10,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 9. "ISF9,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 8. "ISF8,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 7. "ISF7,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 6. "ISF6,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "ISF5,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 4. "ISF4,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "ISF3,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 2. "ISF2,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "ISF1,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 0. "ISF0,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
tree.end
|
|
tree "PORTE"
|
|
base ad:0x41037000
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "8" "9" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x20 0x24 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 14. (strings "12" "13" "14" "15" "16" "17" "18" "19" "21" "22" "27" "28" "29" "30" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x24 0x28 0x3C 0x40 0x44 0x48 )
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "PORTE"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4005E000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4004D000
|
|
endif
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "8" "9" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x20 0x24 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 14. (strings "12" "13" "14" "15" "16" "17" "18" "19" "21" "22" "27" "28" "29" "30" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x24 0x28 0x3C 0x40 0x44 0x48 )
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register $1"
|
|
eventfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,5: Flag sets on rising edge,6: Flag sets on falling edge,7: Flag sets on either edge,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,13: Enable active high trigger output flag is..,14: Enable active low trigger output flag is..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register is not locked,1: Pin Control Register is locked and cannot be.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 5. "ODE,Open Drain Enable" "0: Open drain output is disabled on the..,1: Open drain output is enabled on the.."
|
|
bitfld.long 0x00 2. "SRE,Slew Rate Enable" "0: Fast slew rate is configured on the..,1: Slow slew rate is configured on the.."
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pull resistor is not enabled on the..,1: Internal pull resistor is enabled on the.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "RCM (Reset Control Module)"
|
|
base ad:0x4007F000
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "SRS0,System Reset Status Register 0"
|
|
bitfld.byte 0x00 7. "POR,Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
bitfld.byte 0x00 6. "PIN,External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
newline
|
|
bitfld.byte 0x00 5. "WDOG,Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
bitfld.byte 0x00 1. "LVD,Low-Voltage Detect Reset" "0: Reset not caused by LVD trip or POR,1: Reset caused by LVD trip or POR"
|
|
newline
|
|
bitfld.byte 0x00 0. "WAKEUP,Low Leakage Wakeup Reset" "0: Reset not caused by LLWU module wakeup source,1: Reset caused by LLWU module wakeup source"
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "SRS1,System Reset Status Register 1"
|
|
bitfld.byte 0x00 5. "SACKERR,Stop Mode Acknowledge Error Reset" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.byte 0x00 3. "MDM_AP,MDM-AP System Reset Request" "0: Reset not caused by host debugger system..,1: Reset caused by host debugger system setting.."
|
|
newline
|
|
bitfld.byte 0x00 2. "SW,Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.byte 0x00 1. "LOCKUP,Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 16. "ECORE1,Existence of SRS[CORE1] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 15. "ETAMPER,Existence of SRS[TAMPER] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 13. "ESACKERR,Existence of SRS[SACKERR] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 11. "EMDM_AP,Existence of SRS[MDM_AP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 10. "ESW,Existence of SRS[SW] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 9. "ELOCKUP,Existence of SRS[LOCKUP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 8. "EJTAG,Existence of SRS[JTAG] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 7. "EPOR,Existence of SRS[POR] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 6. "EPIN,Existence of SRS[PIN] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 5. "EWDOG,Existence of SRS[WDOG] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 4. "ECMU_LOC,Existence of SRS[CMU_LOC] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 3. "ELOL,Existence of SRS[LOL] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 2. "ELOC,Existence of SRS[LOC] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 1. "ELVD,Existence of SRS[LVD] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 0. "EWAKEUP,Existence of SRS[WAKEUP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "RPFC,Reset Pin Filter Control register"
|
|
bitfld.byte 0x00 2. "RSTFLTSS,Reset Pin Filter Select in Stop Mode" "0: All filtering disabled,1: LPO clock filter enabled"
|
|
bitfld.byte 0x00 0.--1. "RSTFLTSRW,Reset Pin Filter Select in Run and Wait Modes" "0: All filtering disabled,1: Bus clock filter enabled for normal operation,2: LPO clock filter enabled for normal operation,?..."
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "RPFW,Reset Pin Filter Width register"
|
|
bitfld.byte 0x00 0.--4. "RSTFLTSEL,Reset Pin Filter Bus Clock Select" "0: Bus clock filter count is 1,1: Bus clock filter count is 2,2: Bus clock filter count is 3,3: Bus clock filter count is 4,4: Bus clock filter count is 5,5: Bus clock filter count is 6,6: Bus clock filter count is 7,7: Bus clock filter count is 8,8: Bus clock filter count is 9,9: Bus clock filter count is 10,10: Bus clock filter count is 11,11: Bus clock filter count is 12,12: Bus clock filter count is 13,13: Bus clock filter count is 14,14: Bus clock filter count is 15,15: Bus clock filter count is 16,16: Bus clock filter count is 17,17: Bus clock filter count is 18,18: Bus clock filter count is 19,19: Bus clock filter count is 20,20: Bus clock filter count is 21,21: Bus clock filter count is 22,22: Bus clock filter count is 23,23: Bus clock filter count is 24,24: Bus clock filter count is 25,25: Bus clock filter count is 26,26: Bus clock filter count is 27,27: Bus clock filter count is 28,28: Bus clock filter count is 29,29: Bus clock filter count is 30,30: Bus clock filter count is 31,31: Bus clock filter count is 32"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "FM,Force Mode Register"
|
|
bitfld.byte 0x00 1.--2. "FORCEROM,Force ROM Boot" "0: No effect,1: Force boot from ROM with RCM_MR[1] set,2: Force boot from ROM with RCM_MR[2] set,3: Force boot from ROM with RCM_MR[2:1] set"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "MR,Mode Register"
|
|
bitfld.byte 0x00 1.--2. "BOOTROM,Boot ROM Configuration" "0: Boot from Flash,1: Boot from ROM due to BOOTCFG0 pin assertion,2: Boot form ROM due to FOPT[7] configuration,3: Boot from ROM due to both BOOTCFG0 pin.."
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SSRS0,Sticky System Reset Status Register 0"
|
|
bitfld.byte 0x00 7. "SPOR,Sticky Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
bitfld.byte 0x00 6. "SPIN,Sticky External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
newline
|
|
bitfld.byte 0x00 5. "SWDOG,Sticky Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
bitfld.byte 0x00 1. "SLVD,Sticky Low-Voltage Detect Reset" "0: Reset not caused by LVD trip or POR,1: Reset caused by LVD trip or POR"
|
|
newline
|
|
bitfld.byte 0x00 0. "SWAKEUP,Sticky Low Leakage Wakeup Reset" "0: Reset not caused by LLWU module wakeup source,1: Reset caused by LLWU module wakeup source"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SRS,System Reset Status Register"
|
|
bitfld.long 0x00 13. "SACKERR,Stop Acknowledge Error" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 11. "MDM_AP,MDM-AP System Reset Request" "0: Reset was not caused by host debugger system..,1: Reset was caused by host debugger system.."
|
|
newline
|
|
bitfld.long 0x00 10. "SW,Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.long 0x00 9. "LOCKUP,Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
newline
|
|
bitfld.long 0x00 7. "POR,Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
bitfld.long 0x00 6. "PIN,External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
newline
|
|
bitfld.long 0x00 5. "WDOG,Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
bitfld.long 0x00 3. "LOL,Loss-of-Lock Reset" "0: Reset not caused by a loss of lock in the..,1: Reset caused by a loss of lock in the PLL/FLL"
|
|
newline
|
|
bitfld.long 0x00 2. "LOC,Loss-of-Clock Reset" "0: Reset not caused by a loss of external clock,1: Reset caused by a loss of external clock"
|
|
bitfld.long 0x00 1. "LVD,Low-Voltage Detect Reset or High-Voltage Detect Reset" "0: Reset not caused by LVD trip HVD trip or POR,1: Reset caused by LVD trip HVD trip or POR"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKEUP,VLLS Wakeup Reset" "0: Reset not caused by wakeup from VLLS mode,1: Reset caused by wakeup from VLLS mode"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SSRS1,Sticky System Reset Status Register 1"
|
|
bitfld.byte 0x00 5. "SSACKERR,Sticky Stop Mode Acknowledge Error Reset" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.byte 0x00 3. "SMDM_AP,Sticky MDM-AP System Reset Request" "0: Reset not caused by host debugger system..,1: Reset caused by host debugger system setting.."
|
|
newline
|
|
bitfld.byte 0x00 2. "SSW,Sticky Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.byte 0x00 1. "SLOCKUP,Sticky Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RPC,Reset Pin Control register"
|
|
bitfld.long 0x00 8.--12. "RSTFLTSEL,Reset Pin Filter Bus Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 2. "RSTFLTSS,Reset Pin Filter Select in Stop Mode" "0: All filtering disabled,1: LPO clock filter enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RSTFLTSRW,Reset Pin Filter Select in Run and Wait Modes" "0: All filtering disabled,1: Bus clock filter enabled for normal operation,2: LPO clock filter enabled for normal operation,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 1.--2. "BOOTROM,Boot ROM Configuration" "0: Boot from Flash,1: Boot from ROM due to BOOTCFG0 pin assertion /..,2: Boot form ROM due to FOPT[7] configuration,3: Boot from ROM due to both BOOTCFG0 pin.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FM,Force Mode Register"
|
|
bitfld.long 0x00 1.--2. "FORCEROM,Force ROM Boot" "0: No effect,1: Force boot from ROM with RCM_MR[1] set,2: Force boot from ROM with RCM_MR[2] set,3: Force boot from ROM with RCM_MR[2:1] set"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SSRS,Sticky System Reset Status Register"
|
|
bitfld.long 0x00 13. "SSACKERR,Sticky Stop Acknowledge Error" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 11. "SMDM_AP,Sticky MDM-AP System Reset Request" "0: Reset was not caused by host debugger system..,1: Reset was caused by host debugger system.."
|
|
newline
|
|
bitfld.long 0x00 10. "SSW,Sticky Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.long 0x00 9. "SLOCKUP,Sticky Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
newline
|
|
bitfld.long 0x00 7. "SPOR,Sticky Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
bitfld.long 0x00 6. "SPIN,Sticky External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
newline
|
|
bitfld.long 0x00 5. "SWDOG,Sticky Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
bitfld.long 0x00 3. "SLOL,Sticky Loss-of-Lock Reset" "0: Reset not caused by a loss of lock in the..,1: Reset caused by a loss of lock in the PLL/FLL"
|
|
newline
|
|
bitfld.long 0x00 2. "SLOC,Sticky Loss-of-Clock Reset" "0: Reset not caused by a loss of external clock,1: Reset caused by a loss of external clock"
|
|
bitfld.long 0x00 1. "SLVD,Sticky Low-Voltage Detect Reset" "0: Reset not caused by LVD trip or POR,1: Reset caused by LVD trip or POR"
|
|
newline
|
|
bitfld.long 0x00 0. "SWAKEUP,Sticky VLLS Wakeup Reset" "0: Reset not caused by wakeup from VLLS mode,1: Reset caused by wakeup from VLLS mode"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SRIE,System Reset Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "SACKERR,Stop Acknowledge Error Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "MDM_AP,MDM-AP System Reset Request" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "SW,Software Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "LOCKUP,Core Lockup Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "GIE,Global Interrupt Enable" "0: All interrupt sources disabled,1: All interrupt sources enabled"
|
|
bitfld.long 0x00 6. "PIN,External Reset Pin Interrupt" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
newline
|
|
bitfld.long 0x00 5. "WDOG,Watchdog Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 3. "LOL,Loss-of-Lock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "LOC,Loss-of-Clock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0.--1. "DELAY,Reset Delay Time" "0: 10 LPO cycles,1: 34 LPO cycles,2: 130 LPO cycles,3: 514 LPO cycles"
|
|
endif
|
|
tree.end
|
|
tree "RFSYS (System register file)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4007C000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40041000
|
|
endif
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "REG$1,Register file register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HH,High higher byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HL,High lower byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LH,Low higher byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LL,Low lower byte"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")||cpuis("K32L3A*-CM0+")
|
|
tree "ROM"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
base ad:0xF0002000
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "ENTRY[$1],Entry $1"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRY,ENTRY"
|
|
repeat.end
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TABLEMARK,End of Table Marker Register"
|
|
hexmask.long 0x00 0.--31. 1. "MARK,MARK"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "SYSACCESS,System Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "SYSACCESS,SYSACCESS"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID[$1],Component ID Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0xF0002000
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "ENTRY[$1],Entry $1"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRY,ENTRY"
|
|
repeat.end
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TABLEMARK,End of Table Marker Register"
|
|
hexmask.long 0x00 0.--31. 1. "MARK,MARK"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "SYSACCESS,System Access Register"
|
|
hexmask.long 0x00 0.--31. 1. "SYSACCESS,SYSACCESS"
|
|
repeat 8. (strings "4" "5" "6" "7" "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
rgroup.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "PERIPHID$1,Peripheral ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIPHID,PERIPHID"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "COMPID[$1],Component ID Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "COMPID,Component ID"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "RTC (Real-time Counter)"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x40031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSR,Time Seconds Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TPR,Time Prescaler Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAR,Time Alarm Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CIC,Compensation Interval Counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TCV,Time Compensation Value"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIR,Compensation Interval Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TCR,Time Compensation Register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24.--25. "CPE,Clock Pin Enable" "0: The RTC_CLKOUT function is disabled,1: Enable RTC_CLKOUT pin on pin 1,2: Enable RTC_CLKOUT pin on pin 2,3: Enable RTC_CLKOUT pin on pin 3"
|
|
bitfld.long 0x00 16.--17. "PORS,POR Select" "0: POR brownout enabled for 120us every 128ms,1: POR brownout enabled for 120us every 64ms,2: POR brownout enabled for 120us every 32ms,3: POR brownout always enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "OSCM,Oscillator Mode Select" "0: Configures the 32.768kHz crystal oscillator..,1: Configures the 32.768kHz crystal oscillator.."
|
|
bitfld.long 0x00 13. "SC2P,Oscillator 2pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
newline
|
|
bitfld.long 0x00 12. "SC4P,Oscillator 4pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
bitfld.long 0x00 11. "SC8P,Oscillator 8pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
newline
|
|
bitfld.long 0x00 10. "SC16P,Oscillator 16pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
bitfld.long 0x00 9. "CLKO,Clock Output" "0: The 32 kHz clock is output to other peripherals,1: The 32 kHz clock is not output to other.."
|
|
newline
|
|
bitfld.long 0x00 8. "OSCE,Oscillator Enable" "0: 32.768 kHz oscillator is disabled,1: 32.768 kHz oscillator is enabled"
|
|
bitfld.long 0x00 7. "LPOS,LPO Select" "0: RTC prescaler increments using 32.768 kHz clock,1: RTC prescaler increments using 1 kHz LPO bits.."
|
|
newline
|
|
bitfld.long 0x00 5. "CPS,Clock Pin Select" "0: The prescaler output clock (as configured by..,1: The RTC 32.768 kHz clock is output on.."
|
|
bitfld.long 0x00 4. "WPS,Wakeup Pin Select" "0: RTC_WAKEUP pin asserts (active low open..,1: RTC_WAKEUP pin outputs the RTC 32kHz clock.."
|
|
newline
|
|
bitfld.long 0x00 3. "UM,Update Mode" "0: Registers cannot be written when locked,1: Registers can be written when locked under.."
|
|
bitfld.long 0x00 2. "SUP,Supervisor Access" "0: Non-supervisor mode write accesses are not..,1: Non-supervisor mode write accesses are.."
|
|
newline
|
|
bitfld.long 0x00 1. "WPE,Wakeup Pin Enable" "0: RTC_WAKEUP pin is disabled,1: RTC_WAKEUP pin is enabled and asserts if the.."
|
|
bitfld.long 0x00 0. "SWR,Software Reset" "0: No effect,1: Resets all RTC registers except for the SWR.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,RTC Status Register"
|
|
rbitfld.long 0x00 7. "TIDF,Tamper Interrupt Detect Flag" "0: Tamper interrupt has not asserted,1: Tamper interrupt has asserted"
|
|
bitfld.long 0x00 4. "TCE,Time Counter Enable" "0: Time counter is disabled,1: Time counter is enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. "MOF,Monotonic Overflow Flag" "0: Monotonic counter overflow has not occurred,1: Monotonic counter overflow has occurred and.."
|
|
rbitfld.long 0x00 2. "TAF,Time Alarm Flag" "0: Time alarm has not occurred,1: Time alarm has occurred"
|
|
newline
|
|
rbitfld.long 0x00 1. "TOF,Time Overflow Flag" "0: Time overflow has not occurred,1: Time overflow has occurred and time counter.."
|
|
rbitfld.long 0x00 0. "TIF,Time Invalid Flag" "0: Time is valid,1: Time is invalid and time counter is read as.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LR,RTC Lock Register"
|
|
bitfld.long 0x00 16.--19. "PCL,Pin Configuration Lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TIL,Tamper Interrupt Lock" "0: Tamper Interrupt Register is locked and..,1: Tamper Interrupt Register is not locked and.."
|
|
newline
|
|
bitfld.long 0x00 13. "TDL,Tamper Detect Lock" "0: Tamper Detect Register is locked and writes..,1: Tamper Detect Register is not locked and.."
|
|
bitfld.long 0x00 11. "MCHL,Monotonic Counter High Lock" "0: Monotonic Counter High Register is locked and..,1: Monotonic Counter High Register is not locked.."
|
|
newline
|
|
bitfld.long 0x00 10. "MCLL,Monotonic Counter Low Lock" "0: Monotonic Counter Low Register is locked and..,1: Monotonic Counter Low Register is not locked.."
|
|
bitfld.long 0x00 9. "MEL,Monotonic Enable Lock" "0: Monotonic Enable Register is locked and..,1: Monotonic Enable Register is not locked and.."
|
|
newline
|
|
bitfld.long 0x00 8. "TTSL,Tamper Time Seconds Lock" "0: Tamper Time Seconds Register is locked and..,1: Tamper Time Seconds Register is not locked.."
|
|
bitfld.long 0x00 6. "LRL,Lock Register Lock" "0: Lock Register is locked and writes are ignored,1: Lock Register is not locked and writes.."
|
|
newline
|
|
bitfld.long 0x00 5. "SRL,Status Register Lock" "0: Status Register is locked and writes are..,1: Status Register is not locked and writes.."
|
|
bitfld.long 0x00 4. "CRL,Control Register Lock" "0: Control Register is locked and writes are..,1: Control Register is not locked and writes.."
|
|
newline
|
|
bitfld.long 0x00 3. "TCL,Time Compensation Lock" "0: Time Compensation Register is locked and..,1: Time Compensation Register is not locked and.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 16.--18. "TSIC,Timer Seconds Interrupt Configuration" "0: TSIC_0,1: TSIC_1,2: TSIC_2,3: TSIC_3,4: TSIC_4,5: TSIC_5,6: TSIC_6,7: 128 Hz"
|
|
bitfld.long 0x00 7. "WPON,Wakeup Pin On" "0: No effect,1: If the RTC_WAKEUP pin is enabled then the pin.."
|
|
newline
|
|
bitfld.long 0x00 4. "TSIE,Time Seconds Interrupt Enable" "0: Seconds interrupt is disabled,1: Seconds interrupt is enabled"
|
|
bitfld.long 0x00 3. "MOIE,Monotonic Overflow Interrupt Enable" "0: Monotonic overflow flag does not generate an..,1: Monotonic overflow flag does generate an.."
|
|
newline
|
|
bitfld.long 0x00 2. "TAIE,Time Alarm Interrupt Enable" "0: Time alarm flag does not generate an interrupt,1: Time alarm flag does generate an interrupt"
|
|
bitfld.long 0x00 1. "TOIE,Time Overflow Interrupt Enable" "0: Time overflow flag does not generate an..,1: Time overflow flag does generate an interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "TIIE,Time Invalid Interrupt Enable" "0: Time invalid flag does not generate an..,1: Time invalid flag does generate an interrupt"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TTSR,RTC Tamper Time Seconds Register"
|
|
hexmask.long 0x00 0.--31. 1. "TTS,Tamper Time Seconds"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MER,RTC Monotonic Enable Register"
|
|
bitfld.long 0x00 4. "MCE,Monotonic Counter Enable" "0: Writes to the monotonic counter load the..,1: Writes to the monotonic counter increment the.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCLR,RTC Monotonic Counter Low Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCL,Monotonic Counter Low"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCHR,RTC Monotonic Counter High Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCH,Monotonic Counter High"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TDR,RTC Tamper Detect Register"
|
|
eventfld.long 0x00 16.--19. "TPF,Tamper Pin Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x00 7. "TMF,Test Mode Flag" "0: Tamper not detected,1: Test mode tamper detected"
|
|
newline
|
|
eventfld.long 0x00 6. "FSF,Flash Security Flag" "0: Tamper not detected,1: Flash security tamper detected"
|
|
eventfld.long 0x00 5. "STF,Security Tamper Flag" "0: Tamper not detected,1: Security module tamper detected"
|
|
newline
|
|
eventfld.long 0x00 4. "LCTF,Loss of Clock Tamper Flag" "0: Tamper not detected,1: Loss of Clock tamper detected"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIR,RTC Tamper Interrupt Register"
|
|
bitfld.long 0x00 16.--19. "TPIE,Tamper Pin Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "TMIE,Test Mode Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the test mode.."
|
|
newline
|
|
bitfld.long 0x00 6. "FSIE,Flash Security Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the flash.."
|
|
bitfld.long 0x00 5. "SIE,Security Module Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the security.."
|
|
newline
|
|
bitfld.long 0x00 4. "LCIE,Loss of Clock Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the loss of.."
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PCR[$1],RTC Pin Configuration Register $1"
|
|
rbitfld.long 0x00 31. "TPID,Tamper Pin Input Data" "0: Tamper pin input data is logic zero,1: Tamper pin input data is logic one"
|
|
bitfld.long 0x00 27. "TPP,Tamper Pin Polarity" "0: Tamper pin is active high,1: Tamper pin is active low"
|
|
newline
|
|
bitfld.long 0x00 26. "TFE,Tamper Filter Enable" "0: Input filter is disabled on the tamper pin,1: Input filter is enabled on the tamper pin"
|
|
bitfld.long 0x00 25. "TPS,Tamper Pull Select" "0: Tamper pin pull resistor direction will..,1: Tamper pin pull resistor direction will.."
|
|
newline
|
|
bitfld.long 0x00 24. "TPE,Tamper Pull Enable" "0: Pull resistor is disabled on tamper pin,1: Pull resistor is enabled on tamper pin"
|
|
repeat.end
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "WAR,RTC Write Access Register"
|
|
bitfld.long 0x00 16.--19. "PCRW,Pin Configuration Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TIRW,Tamper Interrupt Register" "0: Writes to the Tamper Interrupt Register are..,1: Writes to the Tamper Interrupt Register.."
|
|
newline
|
|
bitfld.long 0x00 13. "TDRW,Tamper Detect Register" "0: Writes to the Tamper Detect Register are..,1: Writes to the Tamper Detect Register complete.."
|
|
bitfld.long 0x00 11. "MCHW,Monotonic Counter High" "0: Writes to the Monotonic Counter High Register..,1: Writes to the Monotonic Counter High Register.."
|
|
newline
|
|
bitfld.long 0x00 10. "MCLW,Monotonic Counter Low" "0: Writes to the Monotonic Counter Low Register..,1: Writes to the Monotonic Counter Low Register.."
|
|
bitfld.long 0x00 9. "MERW,Monotonic Enable Register" "0: Writes to the Monotonic Enable Register are..,1: Writes to the Monotonic Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 8. "TTSW,Tamper Time Seconds" "0: Writes to the Tamper Time Seconds Register..,1: Writes to the Tamper Time Seconds Register.."
|
|
bitfld.long 0x00 7. "IERW,Interrupt Enable Register" "0: Writes to the Interupt Enable Register are..,1: Writes to the Interrupt Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 6. "LRW,Lock Register" "0: Writes to the Lock Register are ignored,1: Writes to the Lock Register complete as normal"
|
|
bitfld.long 0x00 5. "SRW,Status Register" "0: Writes to the Status Register are ignored,1: Writes to the Status Register complete as.."
|
|
newline
|
|
bitfld.long 0x00 4. "CRW,Control Register" "0: Writes to the Control Register are ignored,1: Writes to the Control Register complete as.."
|
|
bitfld.long 0x00 3. "TCRW,Time Compensation Register" "0: Writes to the Time Compensation Register are..,1: Writes to the Time Compensation Register.."
|
|
newline
|
|
bitfld.long 0x00 2. "TARW,Time Alarm Register" "0: Writes to the Time Alarm Register are ignored,1: Writes to the Time Alarm Register complete as.."
|
|
bitfld.long 0x00 1. "TPRW,Time Prescaler Register" "0: Writes to the Time Prescaler Register are..,1: Writes to the Time Prescaler Register.."
|
|
newline
|
|
bitfld.long 0x00 0. "TSRW,Time Seconds Register" "0: Writes to the Time Seconds Register are ignored,1: Writes to the Time Seconds Register complete.."
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "RAR,RTC Read Access Register"
|
|
bitfld.long 0x00 16.--19. "PCRR,Pin Configuration Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TIRR,Tamper Interrupt Register" "0: Reads to the Tamper Interrupt Register are..,1: Reads to the Tamper Interrupt Register.."
|
|
newline
|
|
bitfld.long 0x00 13. "TDRR,Tamper Detect Register" "0: Reads to the Tamper Detect Register are ignored,1: Reads to the Tamper Detect Register complete.."
|
|
bitfld.long 0x00 11. "MCHR,Monotonic Counter High" "0: Reads to the Monotonic Counter High Register..,1: Reads to the Monotonic Counter High Register.."
|
|
newline
|
|
bitfld.long 0x00 10. "MCLR,Monotonic Counter Low" "0: Reads to the Monotonic Counter Low Register..,1: Reads to the Monotonic Counter Low Register.."
|
|
bitfld.long 0x00 9. "MERR,Monotonic Enable Register" "0: Reads to the Monotonic Enable Register are..,1: Reads to the Monotonic Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 8. "TTSR,Tamper Time Seconds" "0: Reads to the Tamper Time Seconds Register are..,1: Reads to the Tamper Time Seconds Register.."
|
|
bitfld.long 0x00 7. "IERR,Interrupt Enable Register" "0: Reads to the Interrupt Enable Register are..,1: Reads to the Interrupt Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 6. "LRR,Lock Register" "0: Reads to the Lock Register are ignored,1: Reads to the Lock Register complete as normal"
|
|
bitfld.long 0x00 5. "SRR,Status Register" "0: Reads to the Status Register are ignored,1: Reads to the Status Register complete as normal"
|
|
newline
|
|
bitfld.long 0x00 4. "CRR,Control Register" "0: Reads to the Control Register are ignored,1: Reads to the Control Register complete as.."
|
|
bitfld.long 0x00 3. "TCRR,Time Compensation Register" "0: Reads to the Time Compensation Register are..,1: Reads to the Time Compensation Register.."
|
|
newline
|
|
bitfld.long 0x00 2. "TARR,Time Alarm Register" "0: Reads to the Time Alarm Register are ignored,1: Reads to the Time Alarm Register complete as.."
|
|
bitfld.long 0x00 1. "TPRR,Time Prescaler Register" "0: Reads to the Time Pprescaler Register are..,1: Reads to the Time Prescaler Register complete.."
|
|
newline
|
|
bitfld.long 0x00 0. "TSRR,Time Seconds Register" "0: Reads to the Time Seconds Register are ignored,1: Reads to the Time Seconds Register complete.."
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40038000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x4003D000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSR,Time Seconds Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TPR,Time Prescaler Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAR,Time Alarm Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CIC,Compensation Interval Counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TCV,Time Compensation Value"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIR,Compensation Interval Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TCR,Time Compensation Register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24.--25. "CPE,Clock Pin Enable" "0: The RTC_CLKOUT function is disabled,1: Enable RTC_CLKOUT pin on pin 1,2: Enable RTC_CLKOUT pin on pin 2,3: Enable RTC_CLKOUT pin on pin 3"
|
|
bitfld.long 0x00 16.--17. "PORS,POR Select" "0: POR brownout enabled for 120us every 128ms,1: POR brownout enabled for 120us every 64ms,2: POR brownout enabled for 120us every 32ms,3: POR brownout always enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "OSCM,Oscillator Mode Select" "0: Configures the 32.768kHz crystal oscillator..,1: Configures the 32.768kHz crystal oscillator.."
|
|
bitfld.long 0x00 13. "SC2P,Oscillator 2pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
newline
|
|
bitfld.long 0x00 12. "SC4P,Oscillator 4pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
bitfld.long 0x00 11. "SC8P,Oscillator 8pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
newline
|
|
bitfld.long 0x00 10. "SC16P,Oscillator 16pF Load Configure" "0: Disable the load,1: Enable the additional load"
|
|
bitfld.long 0x00 9. "CLKO,Clock Output" "0: The 32 kHz clock is output to other peripherals,1: The 32 kHz clock is not output to other.."
|
|
newline
|
|
bitfld.long 0x00 8. "OSCE,Oscillator Enable" "0: 32.768 kHz oscillator is disabled,1: 32.768 kHz oscillator is enabled"
|
|
bitfld.long 0x00 7. "LPOS,LPO Select" "0: RTC prescaler increments using 32.768 kHz clock,1: RTC prescaler increments using 1 kHz LPO bits.."
|
|
newline
|
|
bitfld.long 0x00 5. "CPS,Clock Pin Select" "0: The prescaler output clock (as configured by..,1: The RTC 32.768 kHz clock is output on.."
|
|
bitfld.long 0x00 4. "WPS,Wakeup Pin Select" "0: RTC_WAKEUP pin asserts (active low open..,1: RTC_WAKEUP pin outputs the RTC 32kHz clock.."
|
|
newline
|
|
bitfld.long 0x00 3. "UM,Update Mode" "0: Registers cannot be written when locked,1: Registers can be written when locked under.."
|
|
bitfld.long 0x00 2. "SUP,Supervisor Access" "0: Non-supervisor mode write accesses are not..,1: Non-supervisor mode write accesses are.."
|
|
newline
|
|
bitfld.long 0x00 1. "WPE,Wakeup Pin Enable" "0: RTC_WAKEUP pin is disabled,1: RTC_WAKEUP pin is enabled and asserts if the.."
|
|
bitfld.long 0x00 0. "SWR,Software Reset" "0: No effect,1: Resets all RTC registers except for the SWR.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,RTC Status Register"
|
|
rbitfld.long 0x00 7. "TIDF,Tamper Interrupt Detect Flag" "0: Tamper interrupt has not asserted,1: Tamper interrupt has asserted"
|
|
bitfld.long 0x00 4. "TCE,Time Counter Enable" "0: Time counter is disabled,1: Time counter is enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. "MOF,Monotonic Overflow Flag" "0: Monotonic counter overflow has not occurred,1: Monotonic counter overflow has occurred and.."
|
|
rbitfld.long 0x00 2. "TAF,Time Alarm Flag" "0: Time alarm has not occurred,1: Time alarm has occurred"
|
|
newline
|
|
rbitfld.long 0x00 1. "TOF,Time Overflow Flag" "0: Time overflow has not occurred,1: Time overflow has occurred and time counter.."
|
|
rbitfld.long 0x00 0. "TIF,Time Invalid Flag" "0: Time is valid,1: Time is invalid and time counter is read as.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LR,RTC Lock Register"
|
|
bitfld.long 0x00 16.--19. "PCL,Pin Configuration Lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TIL,Tamper Interrupt Lock" "0: Tamper Interrupt Register is locked and..,1: Tamper Interrupt Register is not locked and.."
|
|
newline
|
|
bitfld.long 0x00 13. "TDL,Tamper Detect Lock" "0: Tamper Detect Register is locked and writes..,1: Tamper Detect Register is not locked and.."
|
|
bitfld.long 0x00 11. "MCHL,Monotonic Counter High Lock" "0: Monotonic Counter High Register is locked and..,1: Monotonic Counter High Register is not locked.."
|
|
newline
|
|
bitfld.long 0x00 10. "MCLL,Monotonic Counter Low Lock" "0: Monotonic Counter Low Register is locked and..,1: Monotonic Counter Low Register is not locked.."
|
|
bitfld.long 0x00 9. "MEL,Monotonic Enable Lock" "0: Monotonic Enable Register is locked and..,1: Monotonic Enable Register is not locked and.."
|
|
newline
|
|
bitfld.long 0x00 8. "TTSL,Tamper Time Seconds Lock" "0: Tamper Time Seconds Register is locked and..,1: Tamper Time Seconds Register is not locked.."
|
|
bitfld.long 0x00 6. "LRL,Lock Register Lock" "0: Lock Register is locked and writes are ignored,1: Lock Register is not locked and writes.."
|
|
newline
|
|
bitfld.long 0x00 5. "SRL,Status Register Lock" "0: Status Register is locked and writes are..,1: Status Register is not locked and writes.."
|
|
bitfld.long 0x00 4. "CRL,Control Register Lock" "0: Control Register is locked and writes are..,1: Control Register is not locked and writes.."
|
|
newline
|
|
bitfld.long 0x00 3. "TCL,Time Compensation Lock" "0: Time Compensation Register is locked and..,1: Time Compensation Register is not locked and.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 16.--18. "TSIC,Timer Seconds Interrupt Configuration" "0: TSIC_0,1: TSIC_1,2: TSIC_2,3: TSIC_3,4: TSIC_4,5: TSIC_5,6: TSIC_6,7: 128 Hz"
|
|
bitfld.long 0x00 7. "WPON,Wakeup Pin On" "0: No effect,1: If the RTC_WAKEUP pin is enabled then the pin.."
|
|
newline
|
|
bitfld.long 0x00 4. "TSIE,Time Seconds Interrupt Enable" "0: Seconds interrupt is disabled,1: Seconds interrupt is enabled"
|
|
bitfld.long 0x00 3. "MOIE,Monotonic Overflow Interrupt Enable" "0: Monotonic overflow flag does not generate an..,1: Monotonic overflow flag does generate an.."
|
|
newline
|
|
bitfld.long 0x00 2. "TAIE,Time Alarm Interrupt Enable" "0: Time alarm flag does not generate an interrupt,1: Time alarm flag does generate an interrupt"
|
|
bitfld.long 0x00 1. "TOIE,Time Overflow Interrupt Enable" "0: Time overflow flag does not generate an..,1: Time overflow flag does generate an interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "TIIE,Time Invalid Interrupt Enable" "0: Time invalid flag does not generate an..,1: Time invalid flag does generate an interrupt"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TTSR,RTC Tamper Time Seconds Register"
|
|
hexmask.long 0x00 0.--31. 1. "TTS,Tamper Time Seconds"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MER,RTC Monotonic Enable Register"
|
|
bitfld.long 0x00 4. "MCE,Monotonic Counter Enable" "0: Writes to the monotonic counter load the..,1: Writes to the monotonic counter increment the.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCLR,RTC Monotonic Counter Low Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCL,Monotonic Counter Low"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCHR,RTC Monotonic Counter High Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCH,Monotonic Counter High"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TDR,RTC Tamper Detect Register"
|
|
eventfld.long 0x00 16.--19. "TPF,Tamper Pin Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x00 7. "TMF,Test Mode Flag" "0: Tamper not detected,1: Test mode tamper detected"
|
|
newline
|
|
eventfld.long 0x00 6. "FSF,Flash Security Flag" "0: Tamper not detected,1: Flash security tamper detected"
|
|
eventfld.long 0x00 5. "STF,Security Tamper Flag" "0: Tamper not detected,1: Security module tamper detected"
|
|
newline
|
|
eventfld.long 0x00 4. "LCTF,Loss of Clock Tamper Flag" "0: Tamper not detected,1: Loss of Clock tamper detected"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIR,RTC Tamper Interrupt Register"
|
|
bitfld.long 0x00 16.--19. "TPIE,Tamper Pin Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "TMIE,Test Mode Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the test mode.."
|
|
newline
|
|
bitfld.long 0x00 6. "FSIE,Flash Security Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the flash.."
|
|
bitfld.long 0x00 5. "SIE,Security Module Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the security.."
|
|
newline
|
|
bitfld.long 0x00 4. "LCIE,Loss of Clock Interrupt Enable" "0: Interupt disabled,1: An interrupt is generated when the loss of.."
|
|
repeat 4. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PCR[$1],RTC Pin Configuration Register $1"
|
|
rbitfld.long 0x00 31. "TPID,Tamper Pin Input Data" "0: Tamper pin input data is logic zero,1: Tamper pin input data is logic one"
|
|
bitfld.long 0x00 27. "TPP,Tamper Pin Polarity" "0: Tamper pin is active high,1: Tamper pin is active low"
|
|
newline
|
|
bitfld.long 0x00 26. "TFE,Tamper Filter Enable" "0: Input filter is disabled on the tamper pin,1: Input filter is enabled on the tamper pin"
|
|
bitfld.long 0x00 25. "TPS,Tamper Pull Select" "0: Tamper pin pull resistor direction will..,1: Tamper pin pull resistor direction will.."
|
|
newline
|
|
bitfld.long 0x00 24. "TPE,Tamper Pull Enable" "0: Pull resistor is disabled on tamper pin,1: Pull resistor is enabled on tamper pin"
|
|
repeat.end
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "WAR,RTC Write Access Register"
|
|
bitfld.long 0x00 16.--19. "PCRW,Pin Configuration Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TIRW,Tamper Interrupt Register" "0: Writes to the Tamper Interrupt Register are..,1: Writes to the Tamper Interrupt Register.."
|
|
newline
|
|
bitfld.long 0x00 13. "TDRW,Tamper Detect Register" "0: Writes to the Tamper Detect Register are..,1: Writes to the Tamper Detect Register complete.."
|
|
bitfld.long 0x00 11. "MCHW,Monotonic Counter High" "0: Writes to the Monotonic Counter High Register..,1: Writes to the Monotonic Counter High Register.."
|
|
newline
|
|
bitfld.long 0x00 10. "MCLW,Monotonic Counter Low" "0: Writes to the Monotonic Counter Low Register..,1: Writes to the Monotonic Counter Low Register.."
|
|
bitfld.long 0x00 9. "MERW,Monotonic Enable Register" "0: Writes to the Monotonic Enable Register are..,1: Writes to the Monotonic Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 8. "TTSW,Tamper Time Seconds" "0: Writes to the Tamper Time Seconds Register..,1: Writes to the Tamper Time Seconds Register.."
|
|
bitfld.long 0x00 7. "IERW,Interrupt Enable Register" "0: Writes to the Interupt Enable Register are..,1: Writes to the Interrupt Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 6. "LRW,Lock Register" "0: Writes to the Lock Register are ignored,1: Writes to the Lock Register complete as normal"
|
|
bitfld.long 0x00 5. "SRW,Status Register" "0: Writes to the Status Register are ignored,1: Writes to the Status Register complete as.."
|
|
newline
|
|
bitfld.long 0x00 4. "CRW,Control Register" "0: Writes to the Control Register are ignored,1: Writes to the Control Register complete as.."
|
|
bitfld.long 0x00 3. "TCRW,Time Compensation Register" "0: Writes to the Time Compensation Register are..,1: Writes to the Time Compensation Register.."
|
|
newline
|
|
bitfld.long 0x00 2. "TARW,Time Alarm Register" "0: Writes to the Time Alarm Register are ignored,1: Writes to the Time Alarm Register complete as.."
|
|
bitfld.long 0x00 1. "TPRW,Time Prescaler Register" "0: Writes to the Time Prescaler Register are..,1: Writes to the Time Prescaler Register.."
|
|
newline
|
|
bitfld.long 0x00 0. "TSRW,Time Seconds Register" "0: Writes to the Time Seconds Register are ignored,1: Writes to the Time Seconds Register complete.."
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "RAR,RTC Read Access Register"
|
|
bitfld.long 0x00 16.--19. "PCRR,Pin Configuration Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TIRR,Tamper Interrupt Register" "0: Reads to the Tamper Interrupt Register are..,1: Reads to the Tamper Interrupt Register.."
|
|
newline
|
|
bitfld.long 0x00 13. "TDRR,Tamper Detect Register" "0: Reads to the Tamper Detect Register are ignored,1: Reads to the Tamper Detect Register complete.."
|
|
bitfld.long 0x00 11. "MCHR,Monotonic Counter High" "0: Reads to the Monotonic Counter High Register..,1: Reads to the Monotonic Counter High Register.."
|
|
newline
|
|
bitfld.long 0x00 10. "MCLR,Monotonic Counter Low" "0: Reads to the Monotonic Counter Low Register..,1: Reads to the Monotonic Counter Low Register.."
|
|
bitfld.long 0x00 9. "MERR,Monotonic Enable Register" "0: Reads to the Monotonic Enable Register are..,1: Reads to the Monotonic Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 8. "TTSR,Tamper Time Seconds" "0: Reads to the Tamper Time Seconds Register are..,1: Reads to the Tamper Time Seconds Register.."
|
|
bitfld.long 0x00 7. "IERR,Interrupt Enable Register" "0: Reads to the Interrupt Enable Register are..,1: Reads to the Interrupt Enable Register.."
|
|
newline
|
|
bitfld.long 0x00 6. "LRR,Lock Register" "0: Reads to the Lock Register are ignored,1: Reads to the Lock Register complete as normal"
|
|
bitfld.long 0x00 5. "SRR,Status Register" "0: Reads to the Status Register are ignored,1: Reads to the Status Register complete as normal"
|
|
newline
|
|
bitfld.long 0x00 4. "CRR,Control Register" "0: Reads to the Control Register are ignored,1: Reads to the Control Register complete as.."
|
|
bitfld.long 0x00 3. "TCRR,Time Compensation Register" "0: Reads to the Time Compensation Register are..,1: Reads to the Time Compensation Register.."
|
|
newline
|
|
bitfld.long 0x00 2. "TARR,Time Alarm Register" "0: Reads to the Time Alarm Register are ignored,1: Reads to the Time Alarm Register complete as.."
|
|
bitfld.long 0x00 1. "TPRR,Time Prescaler Register" "0: Reads to the Time Pprescaler Register are..,1: Reads to the Time Prescaler Register complete.."
|
|
newline
|
|
bitfld.long 0x00 0. "TSRR,Time Seconds Register" "0: Reads to the Time Seconds Register are ignored,1: Reads to the Time Seconds Register complete.."
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "SCB (System Control Block)"
|
|
base ad:0xE000E000
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code"
|
|
bitfld.long 0x00 20.--23. "VARIANT,Major revision number n in the npm revision status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "ARCHITECTURE,Indicates the architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Indicates part number"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "REVISION,Minor revision number m in the rnpm revision status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
eventfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit" "0: write: no effect read: NMI exception is not..,1: write: changes NMI exception state to pending.."
|
|
eventfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit" "0: write: no effect read: PendSV exception is..,1: write: changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit" "0: PENDSVCLR_0,1: removes the pending state from the PendSV.."
|
|
eventfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit" "0: write: no effect read: SysTick exception is..,1: write: changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit" "0: PENDSTCLR_0,1: removes the pending state from the SysTick.."
|
|
rbitfld.long 0x00 12.--17. "VECTPENDING,Exception number of the highest priority pending enabled exception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 1. "TBLOFF,Vector table base offset"
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key"
|
|
rbitfld.long 0x00 15. "ENDIANNESS,Data endianness bit" "0: Little-endian,1: ENDIANNESS_1"
|
|
newline
|
|
bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0: no system reset request,1: asserts a signal to the outer system that.."
|
|
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit" "0: only enabled interrupts or events can wakeup..,1: enabled events and all interrupts including.."
|
|
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode" "0: SLEEPDEEP_0,1: SLEEPDEEP_1"
|
|
newline
|
|
bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode" "0: do not sleep when returning to Thread mode,1: enter sleep or deep sleep on return from an ISR"
|
|
rgroup.long 0xD14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. "STKALIGN,Indicates stack alignment on exception entry" "0,1"
|
|
bitfld.long 0x00 3. "UNALIGN_TRP,Always reads as one indicates that all unaligned accesses generate a HardFault" "0,1"
|
|
group.long 0xD1C++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of system handler 11 SVCall" "0,1,2,3"
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of system handler 15 SysTick exception" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of system handler 14 PendSV" "0,1,2,3"
|
|
group.long 0xD24++0x03
|
|
line.long 0x00 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x00 15. "SVCALLPENDED,no description available" "0: exception is not pending,1: exception is pending"
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x00 4. "EXTERNAL,no description available" "0: No EDBGRQ debug event,1: EDBGRQ debug event"
|
|
bitfld.long 0x00 3. "VCATCH,no description available" "0: No Vector catch triggered,1: Vector catch triggered"
|
|
newline
|
|
bitfld.long 0x00 2. "DWTTRAP,no description available" "0: No current debug events generated by the DWT,1: At least one current debug event generated by.."
|
|
bitfld.long 0x00 1. "BKPT,no description available" "0: No current breakpoint debug event,1: At least one current breakpoint debug event"
|
|
newline
|
|
bitfld.long 0x00 0. "HALTED,no description available" "0: No active halt request debug event,1: Halt request debug event active"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "SCG"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x4002C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "VERSION,SCG Version Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 27.--31. "DIVPRES,Divider Present" "?,1: System DIVSLOW is present,?,3: System DIVSLOW is present,?,5: System DIVSLOW is present,?,7: System DIVSLOW is present,?,9: System DIVSLOW is present,?,11: System DIVSLOW is present,?,13: System DIVSLOW is present,?,15: System DIVSLOW is present,?,17: System DIVSLOW is present,?,19: System DIVSLOW is present,?,21: System DIVSLOW is present,?,23: System DIVSLOW is present,?,25: System DIVSLOW is present,?,27: System DIVSLOW is present,?,29: System DIVSLOW is present,?,31: System DIVSLOW is present"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKPRES,Clock Present"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
bitfld.long 0x00 24.--26. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "VCCR,VLPR Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),?,4: RTC OSC (ROSC_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HCCR,HSRUN Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
bitfld.long 0x00 24.--27. "CLKOUTSEL,SCG Clkout Select" "0: SCG EXTERNAL Clock,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. "SIRCSEL,Slow IRC Selected" "0: Slow IRC is not the system clock source,1: Slow IRC is the system clock source"
|
|
rbitfld.long 0x00 24. "SIRCVLD,Slow IRC Valid" "0: Slow IRC is not enabled or clock is not valid,1: Slow IRC is enabled and output clock is valid"
|
|
newline
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
bitfld.long 0x00 2. "SIRCLPEN,Slow IRC Low Power Enable" "0: Slow IRC is disabled in VLP modes,1: Slow IRC is enabled in VLP modes"
|
|
newline
|
|
bitfld.long 0x00 1. "SIRCSTEN,Slow IRC Stop Enable" "0: Slow IRC is disabled in Stop modes,1: Slow IRC is enabled in Stop modes"
|
|
bitfld.long 0x00 0. "SIRCEN,Slow IRC Enable" "0: Slow IRC is disabled,1: Slow IRC is enabled"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
bitfld.long 0x00 16.--18. "SIRCDIV3,Slow IRC Clock Divider 3" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 8.--10. "SIRCDIV2,Slow IRC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SIRCDIV1,Slow IRC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SIRCCFG,Slow IRC Configuration Register"
|
|
bitfld.long 0x00 0. "RANGE,Frequency Range" "0: Slow IRC low range clock (2 MHz),1: Slow IRC high range clock (8 MHz )"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
eventfld.long 0x00 26. "FIRCERR,Fast IRC Clock Error" "0: Error not detected with the Fast IRC trimming,1: Error detected with the Fast IRC trimming"
|
|
rbitfld.long 0x00 25. "FIRCSEL,Fast IRC Selected status" "0: Fast IRC is not the system clock source,1: Fast IRC is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "FIRCVLD,Fast IRC Valid status" "0: Fast IRC is not enabled or clock is not valid,1: Fast IRC is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 9. "FIRCTRUP,Fast IRC Trim Update" "0: Disable Fast IRC trimming updates,1: Enable Fast IRC trimming updates"
|
|
bitfld.long 0x00 8. "FIRCTREN,Fast IRC Trim Enable" "0: Disable trimming Fast IRC to an external..,1: Enable trimming Fast IRC to an external clock.."
|
|
newline
|
|
bitfld.long 0x00 3. "FIRCREGOFF,Fast IRC Regulator Enable" "0: Fast IRC Regulator is enabled,1: Fast IRC Regulator is disabled"
|
|
bitfld.long 0x00 2. "FIRCLPEN,Fast IRC Low Power Enable" "0: Fast IRC is disabled in VLP modes,1: Fast IRC is enabled in VLP modes"
|
|
newline
|
|
bitfld.long 0x00 1. "FIRCSTEN,Fast IRC Stop Enable" "0: Fast IRC is disabled in Stop modes,1: Fast IRC is enabled in Stop modes"
|
|
bitfld.long 0x00 0. "FIRCEN,Fast IRC Enable" "0: Fast IRC is disabled,1: Fast IRC is enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
bitfld.long 0x00 16.--18. "FIRCDIV3,Fast IRC Clock Divider 3" "0: Clock disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 8.--10. "FIRCDIV2,Fast IRC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FIRCDIV1,Fast IRC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "FIRCCFG,Fast IRC Configuration Register"
|
|
bitfld.long 0x00 0.--1. "RANGE,Frequency Range" "0: Fast IRC is trimmed to 48 MHz,1: Fast IRC is trimmed to 52 MHz,2: Fast IRC is trimmed to 56 MHz,3: Fast IRC is trimmed to 60 MHz"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRIMSRC,Trim Source" "?,?,?,3: RTC OSC (32.768 kHz)"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
bitfld.long 0x00 8.--13. "TRIMCOAR,Trim Coarse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TRIMFINE,Trim Fine"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "ROSCCSR,RTC OSC Control Status Register"
|
|
eventfld.long 0x00 26. "ROSCERR,RTC OSC Clock Error" "0: RTC OSC Clock Monitor is disabled or has not..,1: RTC OSC Clock Monitor is enabled and detected.."
|
|
rbitfld.long 0x00 25. "ROSCSEL,RTC OSC Selected" "0: RTC OSC is not the system clock source,1: RTC OSC is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "ROSCVLD,RTC OSC Valid" "0: RTC OSC is not enabled or clock is not valid,1: RTC OSC is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 17. "ROSCCMRE,RTC OSC Clock Monitor Reset Enable" "0: Clock Monitor generates interrupt when error..,1: Clock Monitor generates reset when error.."
|
|
bitfld.long 0x00 16. "ROSCCM,RTC OSC Clock Monitor" "0: RTC OSC Clock Monitor is disabled,1: RTC OSC Clock Monitor is enabled"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "LPFLLCSR,Low Power FLL Control Status Register"
|
|
eventfld.long 0x00 26. "LPFLLERR,LPFLL Clock Error" "0: Error not detected with the LPFLL trimming,1: Error detected with the LPFLL trimming"
|
|
rbitfld.long 0x00 25. "LPFLLSEL,LPFLL Selected" "0: LPFLL is not the system clock source,1: LPFLL is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "LPFLLVLD,LPFLL Valid" "0: LPFLL is not enabled or clock is not valid,1: LPFLL is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 17. "LPFLLCMRE,LPFLL Clock Monitor Reset Enable" "0: Clock Monitor generates interrupt when error..,1: Clock Monitor generates reset when error.."
|
|
bitfld.long 0x00 16. "LPFLLCM,LPFLL Clock Monitor" "0: LPFLL Clock Monitor is disabled,1: LPFLL Clock Monitor is enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. "LPFLLTRMLOCK,LPFLL Trim LOCK" "0: LPFLL not locked,1: LPFLL trimmed and locked"
|
|
bitfld.long 0x00 9. "LPFLLTRUP,LPFLL Trim Update" "0: Disable LPFLL trimming updates,1: Enable LPFLL trimming updates"
|
|
newline
|
|
bitfld.long 0x00 8. "LPFLLTREN,LPFLL Trim Enable" "0: Disable trimming LPFLL to an reference clock..,1: Enable trimming LPFLL to an reference clock.."
|
|
bitfld.long 0x00 1. "LPFLLSTEN,LPFLL Stop Enable" "0: LPFLL is disabled in Stop modes,1: LPFLL is enabled in Stop modes"
|
|
newline
|
|
bitfld.long 0x00 0. "LPFLLEN,LPFLL Enable" "0: LPFLL is disabled,1: LPFLL is enabled"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "LPFLLDIV,Low Power FLL Divide Register"
|
|
bitfld.long 0x00 16.--18. "LPFLLDIV3,LPFLL Clock Divide 3" "0: Clock disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 8.--10. "LPFLLDIV2,LPFLL Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "LPFLLDIV1,LPFLL Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "LPFLLCFG,Low Power FLL Configuration Register"
|
|
bitfld.long 0x00 0.--1. "FSEL,Frequency Select" "0: LPFLL is trimmed to 48 MHz,1: LPFLL is trimmed to 72 MHz,?..."
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "LPFLLTCFG,Low Power FLL Trim Configuration Register"
|
|
bitfld.long 0x00 16. "LOCKW2LSB,Lock LPFLL with 2 LSBS" "0: LPFLL locks within 1LSB (0.4%),1: LPFLL locks within 2LSB (0.8%)"
|
|
bitfld.long 0x00 8.--12. "TRIMDIV,LPFLL Trim Predivide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRIMSRC,Trim Source" "0: SIRC,1: FIRC,?,3: RTC OSC"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AUTOTRIM,Auto Tune Trim Status"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x4007B000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "VERSION,SCG Version Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 27.--31. "DIVPRES,Divider Present" "?,1: System DIVSLOW is present,?,3: System DIVSLOW is present,?,5: System DIVSLOW is present,?,7: System DIVSLOW is present,?,9: System DIVSLOW is present,?,11: System DIVSLOW is present,?,13: System DIVSLOW is present,?,15: System DIVSLOW is present,?,17: System DIVSLOW is present,?,19: System DIVSLOW is present,?,21: System DIVSLOW is present,?,23: System DIVSLOW is present,?,25: System DIVSLOW is present,?,27: System DIVSLOW is present,?,29: System DIVSLOW is present,?,31: System DIVSLOW is present"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKPRES,Clock Present"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
bitfld.long 0x00 24.--26. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "VCCR,VLPR Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),?,4: RTC OSC (ROSC_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HCCR,HSRUN Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DIVEXT,External Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "?,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
bitfld.long 0x00 24.--27. "CLKOUTSEL,SCG Clkout Select" "0: SCG EXTERNAL Clock,?,2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),4: RTC OSC (ROSC_CLK),5: Low Power FLL (LPFLL_CLK),?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. "SIRCSEL,Slow IRC Selected" "0: Slow IRC is not the system clock source,1: Slow IRC is the system clock source"
|
|
rbitfld.long 0x00 24. "SIRCVLD,Slow IRC Valid" "0: Slow IRC is not enabled or clock is not valid,1: Slow IRC is enabled and output clock is valid"
|
|
newline
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
bitfld.long 0x00 2. "SIRCLPEN,Slow IRC Low Power Enable" "0: Slow IRC is disabled in VLP modes,1: Slow IRC is enabled in VLP modes"
|
|
newline
|
|
bitfld.long 0x00 1. "SIRCSTEN,Slow IRC Stop Enable" "0: Slow IRC is disabled in Stop modes,1: Slow IRC is enabled in Stop modes"
|
|
bitfld.long 0x00 0. "SIRCEN,Slow IRC Enable" "0: Slow IRC is disabled,1: Slow IRC is enabled"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
bitfld.long 0x00 16.--18. "SIRCDIV3,Slow IRC Clock Divider 3" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 8.--10. "SIRCDIV2,Slow IRC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SIRCDIV1,Slow IRC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SIRCCFG,Slow IRC Configuration Register"
|
|
bitfld.long 0x00 0. "RANGE,Frequency Range" "0: Slow IRC low range clock (2 MHz),1: Slow IRC high range clock (8 MHz )"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
eventfld.long 0x00 26. "FIRCERR,Fast IRC Clock Error" "0: Error not detected with the Fast IRC trimming,1: Error detected with the Fast IRC trimming"
|
|
rbitfld.long 0x00 25. "FIRCSEL,Fast IRC Selected status" "0: Fast IRC is not the system clock source,1: Fast IRC is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "FIRCVLD,Fast IRC Valid status" "0: Fast IRC is not enabled or clock is not valid,1: Fast IRC is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 9. "FIRCTRUP,Fast IRC Trim Update" "0: Disable Fast IRC trimming updates,1: Enable Fast IRC trimming updates"
|
|
bitfld.long 0x00 8. "FIRCTREN,Fast IRC Trim Enable" "0: Disable trimming Fast IRC to an external..,1: Enable trimming Fast IRC to an external clock.."
|
|
newline
|
|
bitfld.long 0x00 3. "FIRCREGOFF,Fast IRC Regulator Enable" "0: Fast IRC Regulator is enabled,1: Fast IRC Regulator is disabled"
|
|
bitfld.long 0x00 2. "FIRCLPEN,Fast IRC Low Power Enable" "0: Fast IRC is disabled in VLP modes,1: Fast IRC is enabled in VLP modes"
|
|
newline
|
|
bitfld.long 0x00 1. "FIRCSTEN,Fast IRC Stop Enable" "0: Fast IRC is disabled in Stop modes,1: Fast IRC is enabled in Stop modes"
|
|
bitfld.long 0x00 0. "FIRCEN,Fast IRC Enable" "0: Fast IRC is disabled,1: Fast IRC is enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
bitfld.long 0x00 16.--18. "FIRCDIV3,Fast IRC Clock Divider 3" "0: Clock disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 8.--10. "FIRCDIV2,Fast IRC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FIRCDIV1,Fast IRC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "FIRCCFG,Fast IRC Configuration Register"
|
|
bitfld.long 0x00 0.--1. "RANGE,Frequency Range" "0: Fast IRC is trimmed to 48 MHz,1: Fast IRC is trimmed to 52 MHz,2: Fast IRC is trimmed to 56 MHz,3: Fast IRC is trimmed to 60 MHz"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "FIRCTCFG,Fast IRC Trim Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRIMSRC,Trim Source" "?,?,?,3: RTC OSC (32.768 kHz)"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "FIRCSTAT,Fast IRC Status Register"
|
|
bitfld.long 0x00 8.--13. "TRIMCOAR,Trim Coarse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TRIMFINE,Trim Fine"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "ROSCCSR,RTC OSC Control Status Register"
|
|
eventfld.long 0x00 26. "ROSCERR,RTC OSC Clock Error" "0: RTC OSC Clock Monitor is disabled or has not..,1: RTC OSC Clock Monitor is enabled and detected.."
|
|
rbitfld.long 0x00 25. "ROSCSEL,RTC OSC Selected" "0: RTC OSC is not the system clock source,1: RTC OSC is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "ROSCVLD,RTC OSC Valid" "0: RTC OSC is not enabled or clock is not valid,1: RTC OSC is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 17. "ROSCCMRE,RTC OSC Clock Monitor Reset Enable" "0: Clock Monitor generates interrupt when error..,1: Clock Monitor generates reset when error.."
|
|
bitfld.long 0x00 16. "ROSCCM,RTC OSC Clock Monitor" "0: RTC OSC Clock Monitor is disabled,1: RTC OSC Clock Monitor is enabled"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "LPFLLCSR,Low Power FLL Control Status Register"
|
|
eventfld.long 0x00 26. "LPFLLERR,LPFLL Clock Error" "0: Error not detected with the LPFLL trimming,1: Error detected with the LPFLL trimming"
|
|
rbitfld.long 0x00 25. "LPFLLSEL,LPFLL Selected" "0: LPFLL is not the system clock source,1: LPFLL is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "LPFLLVLD,LPFLL Valid" "0: LPFLL is not enabled or clock is not valid,1: LPFLL is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 17. "LPFLLCMRE,LPFLL Clock Monitor Reset Enable" "0: Clock Monitor generates interrupt when error..,1: Clock Monitor generates reset when error.."
|
|
bitfld.long 0x00 16. "LPFLLCM,LPFLL Clock Monitor" "0: LPFLL Clock Monitor is disabled,1: LPFLL Clock Monitor is enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. "LPFLLTRMLOCK,LPFLL Trim LOCK" "0: LPFLL not locked,1: LPFLL trimmed and locked"
|
|
bitfld.long 0x00 9. "LPFLLTRUP,LPFLL Trim Update" "0: Disable LPFLL trimming updates,1: Enable LPFLL trimming updates"
|
|
newline
|
|
bitfld.long 0x00 8. "LPFLLTREN,LPFLL Trim Enable" "0: Disable trimming LPFLL to an reference clock..,1: Enable trimming LPFLL to an reference clock.."
|
|
bitfld.long 0x00 1. "LPFLLSTEN,LPFLL Stop Enable" "0: LPFLL is disabled in Stop modes,1: LPFLL is enabled in Stop modes"
|
|
newline
|
|
bitfld.long 0x00 0. "LPFLLEN,LPFLL Enable" "0: LPFLL is disabled,1: LPFLL is enabled"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "LPFLLDIV,Low Power FLL Divide Register"
|
|
bitfld.long 0x00 16.--18. "LPFLLDIV3,LPFLL Clock Divide 3" "0: Clock disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 8.--10. "LPFLLDIV2,LPFLL Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "LPFLLDIV1,LPFLL Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "LPFLLCFG,Low Power FLL Configuration Register"
|
|
bitfld.long 0x00 0.--1. "FSEL,Frequency Select" "0: LPFLL is trimmed to 48 MHz,1: LPFLL is trimmed to 72 MHz,?..."
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "LPFLLTCFG,Low Power FLL Trim Configuration Register"
|
|
bitfld.long 0x00 16. "LOCKW2LSB,Lock LPFLL with 2 LSBS" "0: LPFLL locks within 1LSB (0.4%),1: LPFLL locks within 2LSB (0.8%)"
|
|
bitfld.long 0x00 8.--12. "TRIMDIV,LPFLL Trim Predivide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TRIMSRC,Trim Source" "0: SIRC,1: FIRC,?,3: RTC OSC"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "LPFLLSTAT,Low Power FLL Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AUTOTRIM,Auto Tune Trim Status"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "SEMA42 (sema42_ips)"
|
|
repeat 2. (list 420. 421.) (list ad:0x4001B000 ad:0x4101B000)
|
|
tree "SEMA$1"
|
|
base $2
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x00)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,GTFSM" "0: The gate is unlocked (free),1: The gate has been locked by processor 0,2: The gate has been locked by processor 1,3: The gate has been locked by processor 2,4: The gate has been locked by processor 3,5: The gate has been locked by processor 4,6: The gate has been locked by processor 5,7: The gate has been locked by processor 6,8: The gate has been locked by processor 7,9: The gate has been locked by processor 8,10: The gate has been locked by processor 9,11: The gate has been locked by processor 10,12: The gate has been locked by processor 11,13: The gate has been locked by processor 12,14: The gate has been locked by processor 13,15: The gate has been locked by processor 14"
|
|
repeat.end
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_R,Reset Gate"
|
|
bitfld.word 0x00 14.--15. "ROZ,ROZ" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. "RSTGSM,RSTGSM" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,3: This state encoding is never used and.."
|
|
newline
|
|
bitfld.word 0x00 8.--11. "RSTGMS,RSTGMS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,RSTGTN"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_W,Reset Gate"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RSTGDP,RSTGDP"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,RSTGTN"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "SIM"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x40026000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHIPCTRL,Chip Control Register"
|
|
bitfld.long 0x00 8.--9. "FBSL,FLEXBUS security level" "0: All off-chip access(instruction and data) via..,1: All off-chip access(instruction and data) via..,2: off-chip instruction access are disallowed..,3: off-chip instruction access and data access.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
bitfld.long 0x00 28.--31. "FAMID,FAMID" "0: FAMID_0,?..."
|
|
bitfld.long 0x00 24.--27. "SUBFAMID,SUBFAMID" "0: SUBFAMID_0,?..."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "SERIESID,SERIESID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. "REVID,REVID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7.--11. "DIEID,DIEID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "PINID,PINID" "?,?,?,?,?,?,?,?,8: PINID_8,?..."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
rbitfld.long 0x00 28.--31. "CORE0_PFSIZE,The flash size for core0 (CM4)" "?,?,?,?,?,?,?,?,?,?,?,?,12: CM4 has 1 MB flash size,?..."
|
|
rbitfld.long 0x00 24.--27. "CORE1_PFSIZE,The flash size for core1 (CM0+)" "?,?,?,?,?,?,?,?,?,?,10: CM0+ has 256 KB flash size,?..."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "CORE0_SRAMSIZE,The SRAM size for core0 (CM4)" "?,?,?,?,?,?,?,?,?,?,10: CM4 has 256 KB SRAM,?..."
|
|
rbitfld.long 0x00 16.--19. "CORE1_SRAMSIZE,The SRAM size for core1 (CM0+)" "?,?,?,?,?,?,?,?,?,9: CM0+ has 128 KB SRAM,?..."
|
|
newline
|
|
hexmask.long.word 0x00 3.--13. 1. "FLSAUTODISWD,The clock counter for time period of flash auto disable"
|
|
bitfld.long 0x00 2. "FLSAUTODISEN,Flash auto disable enabled" "0: Disable flash auto disable function,1: Enable flash auto disable function"
|
|
newline
|
|
bitfld.long 0x00 1. "FLASHDOZE,Flash Doze" "0: Flash remains enabled during Doze mode,1: Flash is disabled for the duration of Doze mode"
|
|
bitfld.long 0x00 0. "FLASHDIS,Flash disable" "0: Flash is enabled,1: Flash is disabled"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FCFG2,Flash Configuration Register 2"
|
|
bitfld.long 0x00 31. "SWAP,SWAP" "0: Logical P-flash Block 0 is located at..,1: Logical P-flash Block 1 is located at.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "MAXADDR01,Max Address lock"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "MAXADDR2,Max Address lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "UIDH,Unique Identification Register High"
|
|
hexmask.long.word 0x00 0.--15. 1. "UID,Unique Identification"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "UIDM,Unique Identification Register Mid Middle"
|
|
hexmask.long 0x00 0.--31. 1. "UID,Unique Identification"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "UIDL,Unique Identification Register Mid Low"
|
|
hexmask.long 0x00 0.--31. 1. "UID,Unique Identification"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MISC2,MISC2 Register"
|
|
bitfld.long 0x00 0. "systick_clk_en,Systick clock enable" "0: Systick clock is disabled,1: Systick clock is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40074000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40047000
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHIPCTRL,Chip Control Register"
|
|
bitfld.long 0x00 8.--9. "FBSL,FLEXBUS security level" "0: All off-chip access(instruction and data) via..,1: All off-chip access(instruction and data) via..,2: off-chip instruction access are disallowed..,3: off-chip instruction access and data access.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
bitfld.long 0x00 28.--31. "FAMID,FAMID" "0: FAMID_0,?..."
|
|
bitfld.long 0x00 24.--27. "SUBFAMID,SUBFAMID" "0: SUBFAMID_0,?..."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "SERIESID,SERIESID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. "REVID,REVID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7.--11. "DIEID,DIEID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "PINID,PINID" "?,?,?,?,?,?,?,?,8: PINID_8,?..."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
rbitfld.long 0x00 28.--31. "CORE0_PFSIZE,The flash size for core0 (CM4)" "?,?,?,?,?,?,?,?,?,?,?,?,12: CM4 has 1 MB flash size,?..."
|
|
rbitfld.long 0x00 24.--27. "CORE1_PFSIZE,The flash size for core1 (CM0+)" "?,?,?,?,?,?,?,?,?,?,10: CM0+ has 256 KB flash size,?..."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "CORE0_SRAMSIZE,The SRAM size for core0 (CM4)" "?,?,?,?,?,?,?,?,?,?,10: CM4 has 256 KB SRAM,?..."
|
|
rbitfld.long 0x00 16.--19. "CORE1_SRAMSIZE,The SRAM size for core1 (CM0+)" "?,?,?,?,?,?,?,?,?,9: CM0+ has 128 KB SRAM,?..."
|
|
newline
|
|
hexmask.long.word 0x00 3.--13. 1. "FLSAUTODISWD,The clock counter for time period of flash auto disable"
|
|
bitfld.long 0x00 2. "FLSAUTODISEN,Flash auto disable enabled" "0: Disable flash auto disable function,1: Enable flash auto disable function"
|
|
newline
|
|
bitfld.long 0x00 1. "FLASHDOZE,Flash Doze" "0: Flash remains enabled during Doze mode,1: Flash is disabled for the duration of Doze mode"
|
|
bitfld.long 0x00 0. "FLASHDIS,Flash disable" "0: Flash is enabled,1: Flash is disabled"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FCFG2,Flash Configuration Register 2"
|
|
bitfld.long 0x00 31. "SWAP,SWAP" "0: Logical P-flash Block 0 is located at..,1: Logical P-flash Block 1 is located at.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "MAXADDR01,Max Address lock"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "MAXADDR2,Max Address lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "UIDH,Unique Identification Register High"
|
|
hexmask.long.word 0x00 0.--15. 1. "UID,Unique Identification"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "UIDM,Unique Identification Register Mid Middle"
|
|
hexmask.long 0x00 0.--31. 1. "UID,Unique Identification"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "UIDL,Unique Identification Register Mid Low"
|
|
hexmask.long 0x00 0.--31. 1. "UID,Unique Identification"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MISC2,MISC2 Register"
|
|
bitfld.long 0x00 0. "systick_clk_en,Systick clock enable" "0: Systick clock is disabled,1: Systick clock is enabled"
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "SMC (System Mode Controller)"
|
|
base ad:0x4007E000
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,SMC Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.byte 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR VLPW and VLPS are not allowed,1: VLPR VLPW and VLPS are allowed"
|
|
bitfld.byte 0x00 3. "ALLS,Allow Low-Leakage Stop Mode" "0: LLS is not allowed,1: LLS is allowed"
|
|
newline
|
|
bitfld.byte 0x00 1. "AVLLS,Allow Very-Low-Leakage Stop Mode" "0: Any VLLSx mode is not allowed,1: Any VLLSx mode is allowed"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.byte 0x00 5.--6. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),?..."
|
|
rbitfld.byte 0x00 3. "STOPA,Stop Aborted" "0: The previous stop mode entry was successful,1: The previous stop mode entry was aborted"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),3: Low-Leakage Stop (LLS),4: Very-Low-Leakage Stop (VLLSx),?,6: Reseved,?..."
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.byte 0x00 6.--7. "PSTOPO,Partial Stop Option" "0: STOP - Normal Stop mode,1: PSTOP1 - Partial Stop with both system and..,2: PSTOP2 - Partial Stop with system clock..,?..."
|
|
bitfld.byte 0x00 5. "PORPO,POR Power Option" "0: POR detect circuit is enabled in VLLS0,1: POR detect circuit is disabled in VLLS0"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "VLLSM,VLLS Mode Control" "0: VLLS0,1: VLLS1,?,3: VLLS3,?..."
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,SMC Parameter Register"
|
|
bitfld.long 0x00 6. "EVLLS0,Existence of VLLS0 feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 5. "ELLS2,Existence of LLS2 feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 3. "ELLS,Existence of LLS feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 0. "EHSRUN,Existence of HSRUN feature" "0: The feature is not available,1: The feature is available"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 7. "AHSRUN,Allow High Speed Run mode" "0: HSRUN is not allowed,1: HSRUN is allowed"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR VLPW and VLPS are not allowed,1: VLPR VLPW and VLPS are allowed"
|
|
newline
|
|
bitfld.long 0x00 3. "ALLS,Allow Low-Leakage Stop Mode" "0: Any LLSx mode is not allowed,1: Any LLSx mode is allowed"
|
|
bitfld.long 0x00 1. "AVLLS,Allow Very-Low-Leakage Stop Mode" "0: Any VLLSx mode is not allowed,1: Any VLLSx mode is allowed"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 5.--6. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),3: High Speed Run mode (HSRUN)"
|
|
rbitfld.long 0x00 3. "STOPA,Stop Aborted" "0: The previous stop mode entry was successful,1: The previous stop mode entry was aborted"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),3: Low-Leakage Stop (LLSx),4: Very-Low-Leakage Stop (VLLSx),?,6: Reseved,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. "PSTOPO,Partial Stop Option" "0: STOP - Normal Stop mode,1: PSTOP1 - Partial Stop with both system and..,2: PSTOP2 - Partial Stop with system clock..,?..."
|
|
bitfld.long 0x00 5. "PORPO,POR Power Option" "0: POR detect circuit is enabled in VLLS0,1: POR detect circuit is disabled in VLLS0"
|
|
newline
|
|
bitfld.long 0x00 3. "LPOPO,LPO Power Option" "0: LPO clock is enabled in LLS/VLLSx,1: LPO clock is disabled in LLS/VLLSx"
|
|
bitfld.long 0x00 0.--2. "LLSM,LLS or VLLS Mode Control" "0: VLLS0 if PMCTRL[STOPM]=VLLSx reserved if..,1: VLLS1 if PMCTRL[STOPM]=VLLSx reserved if..,2: VLLS2 if PMCTRL[STOPM]=VLLSx LLS2 if..,3: VLLS3 if PMCTRL[STOPM]=VLLSx LLS3 if..,?..."
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x40076000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. "SPRF,SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)" "0: No data available in the receive data buffer..,1: Data available in the receive data buffer.."
|
|
bitfld.byte 0x00 6. "SPMF,SPI Match Flag" "0: Value in the receive data buffer does not..,1: Value in the receive data buffer matches the.."
|
|
newline
|
|
rbitfld.byte 0x00 5. "SPTEF,SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)" "0: SPI transmit buffer not empty (when FIFOMODE..,1: SPI transmit buffer empty (when FIFOMODE is.."
|
|
rbitfld.byte 0x00 4. "MODF,Master Mode Fault Flag" "0: No mode fault error,1: Mode fault error detected"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. "SPPR,SPI Baud Rate Prescale Divisor" "0: Baud rate prescaler divisor is 1,1: Baud rate prescaler divisor is 2,2: Baud rate prescaler divisor is 3,3: Baud rate prescaler divisor is 4,4: Baud rate prescaler divisor is 5,5: Baud rate prescaler divisor is 6,6: Baud rate prescaler divisor is 7,7: Baud rate prescaler divisor is 8"
|
|
bitfld.byte 0x00 0.--3. "SPR,SPI Baud Rate Divisor" "0: Baud rate divisor is 2,1: Baud rate divisor is 4,2: Baud rate divisor is 8,3: Baud rate divisor is 16,4: Baud rate divisor is 32,5: Baud rate divisor is 64,6: Baud rate divisor is 128,7: Baud rate divisor is 256,8: Baud rate divisor is 512,?..."
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "C2,SPI Control Register 2"
|
|
bitfld.byte 0x00 7. "SPMIE,SPI Match Interrupt Enable" "0: Interrupts from SPMF inhibited (use polling),1: When SPMF is 1 requests a hardware interrupt"
|
|
bitfld.byte 0x00 6. "SPIMODE,SPI 8-bit or 16-bit mode" "0: 8-bit SPI shift register match register and..,1: 16-bit SPI shift register match register and.."
|
|
newline
|
|
bitfld.byte 0x00 5. "TXDMAE,Transmit DMA enable" "0: DMA request for transmit is disabled and..,1: DMA request for transmit is enabled and.."
|
|
bitfld.byte 0x00 4. "MODFEN,Master Mode-Fault Function Enable" "0: Mode fault function disabled master SS pin..,1: Mode fault function enabled master SS pin.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BIDIROE,Bidirectional Mode Output Enable" "0: Output driver disabled so SPI data I/O pin..,1: SPI I/O pin enabled as an output"
|
|
bitfld.byte 0x00 2. "RXDMAE,Receive DMA enable" "0: DMA request for receive is disabled and..,1: DMA request for receive is enabled and.."
|
|
newline
|
|
bitfld.byte 0x00 1. "SPISWAI,SPI Stop in Wait Mode" "0: SPI clocks continue to operate in Wait mode,1: SPI clocks stop when the MCU enters Wait mode"
|
|
bitfld.byte 0x00 0. "SPC0,SPI Pin Control 0" "0: SPI uses separate pins for data input and..,1: SPI configured for single-wire bidirectional.."
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. "SPIE,SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)" "0: Interrupts from SPRF and MODF are..,1: Request a hardware interrupt when SPRF or.."
|
|
bitfld.byte 0x00 6. "SPE,SPI System Enable" "0: SPI system inactive,1: SPI system enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. "SPTIE,SPI Transmit Interrupt Enable" "0: Interrupts from SPTEF inhibited (use polling),1: When SPTEF is 1 hardware interrupt requested"
|
|
bitfld.byte 0x00 4. "MSTR,Master/Slave Mode Select" "0: SPI module configured as a slave SPI device,1: SPI module configured as a master SPI device"
|
|
newline
|
|
bitfld.byte 0x00 3. "CPOL,Clock Polarity" "0: Active-high SPI clock (idles low),1: Active-low SPI clock (idles high)"
|
|
bitfld.byte 0x00 2. "CPHA,Clock Phase" "0: First edge on SPSCK occurs at the middle of..,1: First edge on SPSCK occurs at the start of.."
|
|
newline
|
|
bitfld.byte 0x00 1. "SSOE,Slave Select Output Enable" "0: When C2[MODFEN] is 0,1: When C2[MODFEN] is 0"
|
|
bitfld.byte 0x00 0. "LSBFE,LSB First (shifter direction)" "0: SPI serial data transfers start with the most..,1: SPI serial data transfers start with the.."
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ML,SPI Match Register low"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Hardware compare value (low byte)"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MH,SPI match register high"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Hardware compare value (high byte)"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "DL,SPI Data Register low"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Data (low byte)"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "DH,SPI data register high"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Data (high byte)"
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40077000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "S,SPI Status Register"
|
|
rbitfld.byte 0x00 7. "SPRF,SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)" "0: No data available in the receive data buffer..,1: Data available in the receive data buffer.."
|
|
bitfld.byte 0x00 6. "SPMF,SPI Match Flag" "0: Value in the receive data buffer does not..,1: Value in the receive data buffer matches the.."
|
|
newline
|
|
rbitfld.byte 0x00 5. "SPTEF,SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)" "0: SPI transmit buffer not empty (when FIFOMODE..,1: SPI transmit buffer empty (when FIFOMODE is.."
|
|
rbitfld.byte 0x00 4. "MODF,Master Mode Fault Flag" "0: No mode fault error,1: Mode fault error detected"
|
|
newline
|
|
rbitfld.byte 0x00 3. "RNFULLF,Receive FIFO nearly full flag" "0: Receive FIFO has received less than 48 bits..,1: Receive FIFO has received data of an amount.."
|
|
rbitfld.byte 0x00 2. "TNEAREF,Transmit FIFO nearly empty flag" "0: Transmit FIFO has more than 16 bits (when..,1: Transmit FIFO has an amount of data equal to.."
|
|
newline
|
|
rbitfld.byte 0x00 1. "TXFULLF,Transmit FIFO full flag" "0: Transmit FIFO has less than 8 bytes,1: Transmit FIFO has 8 bytes of data"
|
|
rbitfld.byte 0x00 0. "RFIFOEF,SPI read FIFO empty flag" "0: Read FIFO has data,1: Read FIFO is empty"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. "SPPR,SPI Baud Rate Prescale Divisor" "0: Baud rate prescaler divisor is 1,1: Baud rate prescaler divisor is 2,2: Baud rate prescaler divisor is 3,3: Baud rate prescaler divisor is 4,4: Baud rate prescaler divisor is 5,5: Baud rate prescaler divisor is 6,6: Baud rate prescaler divisor is 7,7: Baud rate prescaler divisor is 8"
|
|
bitfld.byte 0x00 0.--3. "SPR,SPI Baud Rate Divisor" "0: Baud rate divisor is 2,1: Baud rate divisor is 4,2: Baud rate divisor is 8,3: Baud rate divisor is 16,4: Baud rate divisor is 32,5: Baud rate divisor is 64,6: Baud rate divisor is 128,7: Baud rate divisor is 256,8: Baud rate divisor is 512,?..."
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "C2,SPI Control Register 2"
|
|
bitfld.byte 0x00 7. "SPMIE,SPI Match Interrupt Enable" "0: Interrupts from SPMF inhibited (use polling),1: When SPMF is 1 requests a hardware interrupt"
|
|
bitfld.byte 0x00 6. "SPIMODE,SPI 8-bit or 16-bit mode" "0: 8-bit SPI shift register match register and..,1: 16-bit SPI shift register match register and.."
|
|
newline
|
|
bitfld.byte 0x00 5. "TXDMAE,Transmit DMA enable" "0: DMA request for transmit is disabled and..,1: DMA request for transmit is enabled and.."
|
|
bitfld.byte 0x00 4. "MODFEN,Master Mode-Fault Function Enable" "0: Mode fault function disabled master SS pin..,1: Mode fault function enabled master SS pin.."
|
|
newline
|
|
bitfld.byte 0x00 3. "BIDIROE,Bidirectional Mode Output Enable" "0: Output driver disabled so SPI data I/O pin..,1: SPI I/O pin enabled as an output"
|
|
bitfld.byte 0x00 2. "RXDMAE,Receive DMA enable" "0: DMA request for receive is disabled and..,1: DMA request for receive is enabled and.."
|
|
newline
|
|
bitfld.byte 0x00 1. "SPISWAI,SPI Stop in Wait Mode" "0: SPI clocks continue to operate in Wait mode,1: SPI clocks stop when the MCU enters Wait mode"
|
|
bitfld.byte 0x00 0. "SPC0,SPI Pin Control 0" "0: SPI uses separate pins for data input and..,1: SPI configured for single-wire bidirectional.."
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C1,SPI Control Register 1"
|
|
bitfld.byte 0x00 7. "SPIE,SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)" "0: Interrupts from SPRF and MODF are..,1: Request a hardware interrupt when SPRF or.."
|
|
bitfld.byte 0x00 6. "SPE,SPI System Enable" "0: SPI system inactive,1: SPI system enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. "SPTIE,SPI Transmit Interrupt Enable" "0: Interrupts from SPTEF inhibited (use polling),1: When SPTEF is 1 hardware interrupt requested"
|
|
bitfld.byte 0x00 4. "MSTR,Master/Slave Mode Select" "0: SPI module configured as a slave SPI device,1: SPI module configured as a master SPI device"
|
|
newline
|
|
bitfld.byte 0x00 3. "CPOL,Clock Polarity" "0: Active-high SPI clock (idles low),1: Active-low SPI clock (idles high)"
|
|
bitfld.byte 0x00 2. "CPHA,Clock Phase" "0: First edge on SPSCK occurs at the middle of..,1: First edge on SPSCK occurs at the start of.."
|
|
newline
|
|
bitfld.byte 0x00 1. "SSOE,Slave Select Output Enable" "0: When C2[MODFEN] is 0,1: When C2[MODFEN] is 0"
|
|
bitfld.byte 0x00 0. "LSBFE,LSB First (shifter direction)" "0: SPI serial data transfers start with the most..,1: SPI serial data transfers start with the.."
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ML,SPI Match Register low"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Hardware compare value (low byte)"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "MH,SPI match register high"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Hardware compare value (high byte)"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "DL,SPI Data Register low"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Data (low byte)"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "DH,SPI data register high"
|
|
hexmask.byte 0x00 0.--7. 1. "Bits,Data (high byte)"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "CI,SPI clear interrupt register"
|
|
rbitfld.byte 0x00 7. "TXFERR,Transmit FIFO error flag" "0: No transmit FIFO error occurred,1: A transmit FIFO error occurred"
|
|
rbitfld.byte 0x00 6. "RXFERR,Receive FIFO error flag" "0: No receive FIFO error occurred,1: A receive FIFO error occurred"
|
|
newline
|
|
rbitfld.byte 0x00 5. "TXFOF,Transmit FIFO overflow flag" "0: Transmit FIFO overflow condition has not..,1: Transmit FIFO overflow condition occurred"
|
|
rbitfld.byte 0x00 4. "RXFOF,Receive FIFO overflow flag" "0: Receive FIFO overflow condition has not..,1: Receive FIFO overflow condition occurred"
|
|
newline
|
|
bitfld.byte 0x00 3. "TNEAREFCI,Transmit FIFO nearly empty flag clear interrupt" "0,1"
|
|
bitfld.byte 0x00 2. "RNFULLFCI,Receive FIFO nearly full flag clear interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "SPTEFCI,Transmit FIFO empty flag clear interrupt" "0,1"
|
|
bitfld.byte 0x00 0. "SPRFCI,Receive FIFO full flag clear interrupt" "0,1"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "C3,SPI control register 3"
|
|
bitfld.byte 0x00 5. "TNEAREF_MARK,Transmit FIFO nearly empty watermark" "0: TNEAREF is set when the transmit FIFO has 16..,1: TNEAREF is set when the transmit FIFO has 32.."
|
|
bitfld.byte 0x00 4. "RNFULLF_MARK,Receive FIFO nearly full watermark" "0: RNFULLF is set when the receive FIFO has 48..,1: RNFULLF is set when the receive FIFO has 32.."
|
|
newline
|
|
bitfld.byte 0x00 3. "INTCLR,Interrupt clearing mechanism select" "0: These interrupts are cleared when the..,1: These interrupts are cleared by writing the.."
|
|
bitfld.byte 0x00 2. "TNEARIEN,Transmit FIFO nearly empty interrupt enable" "0: No interrupt upon TNEAREF being set,1: Enable interrupts upon TNEAREF being set"
|
|
newline
|
|
bitfld.byte 0x00 1. "RNFULLIEN,Receive FIFO nearly full interrupt enable" "0: No interrupt upon RNFULLF being set,1: Enable interrupts upon RNFULLF being set"
|
|
bitfld.byte 0x00 0. "FIFOMODE,FIFO mode enable" "0: FIFO mode disabled,1: FIFO mode enabled"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "SPM"
|
|
base ad:0x40028000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RSR,Regulator Status Register"
|
|
bitfld.long 0x00 16.--20. "MCUPMSTAT,MCU Power Mode Status" "?,1: Last Low Power mode is STOP,2: Last Low Power mode is VLPS,?,4: Last Low Power mode is LLS,?,?,?,8: Last Low Power mode is VLLS23,?,?,?,?,?,?,?,16: Last Low Power mode is VLLS01,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "REGSEL,REGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RCTRL,Run Control Register"
|
|
bitfld.long 0x00 0.--2. "REGSEL,REGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "LPCTRL,Low Power Control Register"
|
|
bitfld.long 0x00 0.--2. "REGSEL,REGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CORERCNFG,CORE LDO RUN Configuration Register"
|
|
bitfld.long 0x00 18. "RTCVDDMEN,RTCVDDMEN" "0: RTC voltage monitor disabled in run modes,1: RTC voltage monitor enabled in run modes"
|
|
newline
|
|
bitfld.long 0x00 17. "USBVDDMEN,USBVDDMEN" "0: USB voltage monitor disabled in run modes,1: USB voltage monitor enabled in run modes"
|
|
newline
|
|
bitfld.long 0x00 16. "VDDIOVDDMEN,VDDIOVDDMEN" "0: VDDIO voltage monitor disabled in run modes,1: VDDIO voltage monitor enabled in run modes"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CORELPCNFG,CORE LDO Low Power Configuration register"
|
|
bitfld.long 0x00 18. "RTCVDDMEN,RTCVDDMEN" "0: RTC voltage monitor disabled in lp modes,1: RTC voltage monitor enabled in lp modes"
|
|
newline
|
|
bitfld.long 0x00 17. "USBVDDMEN,USBVDDMEN" "0: USB voltage monitor disabled in lp modes,1: USB voltage monitor enabled in lp modes"
|
|
newline
|
|
bitfld.long 0x00 16. "VDDIOVDDMEN,VDDIOVDDMEN" "0: VDDIO voltage monitor disabled in lp modes,1: VDDIO voltage monitor enabled in lp modes"
|
|
newline
|
|
bitfld.long 0x00 15. "ALLREFEN,All Reference Enable" "0: All references are disabled in VLLS0/1,1: All references are enabled in VLLS0/1"
|
|
newline
|
|
bitfld.long 0x00 14. "LPHIDRIVE,LPHIDRIVE" "0: High Drive disabled,1: High Drive enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "LVDEN,LVD Enabled" "0: LVD/HVD is disabled in low power modes,1: LVD/HVD remains enabled in low power modes"
|
|
newline
|
|
bitfld.long 0x00 8. "POREN,POR Enabled" "0: POR brownout is disabled in VLLS0/1 mode,1: POR brownout remains enabled in VLLS0/1 mode"
|
|
newline
|
|
bitfld.long 0x00 7. "LPOEN,LPO Enabled" "0: LPO is disabled in VLLS0/1 modes,1: LPO remains enabled in VLLS0/1 modes"
|
|
newline
|
|
bitfld.long 0x00 4. "BGBDS,Bandgap Buffer Drive Select" "0: Low Drive,1: High Drive"
|
|
newline
|
|
bitfld.long 0x00 3. "BGBEN,Bandgap Buffer Enable" "0: Bandgap buffer not enabled,1: Bandgap buffer enabled BGEN must be set when.."
|
|
newline
|
|
bitfld.long 0x00 2. "BGEN,Bandgap Enable In Low Power Mode Operation" "0: Bandgap is disabled in STOP/VLP/LLS and VLLS..,1: Bandgap remains enabled in STOP/VLP/LLS and.."
|
|
newline
|
|
bitfld.long 0x00 1. "LPSEL,LPSEL" "0: Core LDO enters low power state in VLP/Stop..,1: Core LDO remains in high power state in.."
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CORESC,Core LDO Status And Control register"
|
|
rbitfld.long 0x00 26. "RTCVDDOK,RTCVDDOK" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 25. "USBVDDOK,USBVDDOK" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24. "VDDIOOK,VDDIOOK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RTCOVRIDE,RTCOVRIDE" "0: RTCVDDOK status set to 1'b0,1: RTCVDDOK status set to 1'b1"
|
|
newline
|
|
bitfld.long 0x00 17. "USBOVRIDE,USBOVRIDE" "0: USBVDDOK status set to 1'b0,1: USBVDDOK status set to 1'b1"
|
|
newline
|
|
bitfld.long 0x00 16. "VDDIOOVRIDE,VDDIOOVRIDE" "0: VDDIOOK status set to 1'b0,1: VDDIOOK status set to 1'b1"
|
|
newline
|
|
rbitfld.long 0x00 8.--13. "TRIM,Core LDO Regulator TRIM value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
eventfld.long 0x00 3. "ACKISO,Acknowledge Isolation" "0: Peripherals and I/O pads are in normal run..,1: Certain peripherals and I/O pads are in a.."
|
|
newline
|
|
rbitfld.long 0x00 2. "REGONS,CORE LDO Regulator in Run Regulation Status" "0: Regulator is in low power state or in..,1: Regulator is in high power state"
|
|
newline
|
|
bitfld.long 0x00 1. "VSEL_OFFSET,Voltage Offset Select" "0: Core LDO offset not applied,1: Core LDO offset is applied"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "LVDSC1,Low Voltage Detect Status and Control 1 register"
|
|
rbitfld.long 0x00 23. "VDD_LVDF,VDD Low-Voltage Detect Flag" "0: Low-voltage event not detected,1: Low-voltage event detected"
|
|
newline
|
|
bitfld.long 0x00 22. "VDD_LVDACK,VDD Low-Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VDD_LVDIE,VDD Low-Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when VDD_LVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 20. "VDD_LVDRE,VDD Low-Voltage Detect Reset Enable" "0: VDD_LVDF does not generate hardware resets,1: Force an MCU reset when VDD_LVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "VDD_LVDV,VDD Low-Voltage Detect Voltage Select" "0: Low trip point selected (V LVD = V LVDL ),1: High trip point selected (V LVD = V LVDH ),?..."
|
|
newline
|
|
rbitfld.long 0x00 7. "COREVDD_LVDF,Low-Voltage Detect Flag" "0: Low-voltage event not detected,1: Low-voltage event detected"
|
|
newline
|
|
bitfld.long 0x00 6. "COREVDD_LVDACK,Low-Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "COREVDD_LVDIE,Low-Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 4. "COREVDD_LVDRE,Core Low-Voltage Detect Reset Enable" "0: COREVDD_LVDF does not generate hardware resets,1: Force an MCU reset when CORE_LVDF = 1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "LVDSC2,Low Voltage Detect Status and Control 2 register"
|
|
rbitfld.long 0x00 23. "VDD_LVWF,VDD Low-Voltage Warning Flag" "0: Low-voltage warning event not detected,1: Low-voltage warning event detected"
|
|
newline
|
|
bitfld.long 0x00 22. "VDD_LVWACK,VDD Low-Voltage Warning Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VDD_LVWIE,VDD Low-Voltage Warning Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when VDD_LVWF = 1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "VDD_LVWV,VDD Low-Voltage Warning Voltage Select" "0: Low trip point selected (V LVW = VLVW1),1: Mid 1 trip point selected (V LVW = VLVW2),2: Mid 2 trip point selected (V LVW = VLVW3),3: High trip point selected (V LVW = VLVW4)"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "HVDSC1,High Voltage Detect Status And Control 1 register"
|
|
rbitfld.long 0x00 23. "VDD_HVDF,VDD High-Voltage Detect Flag" "0: Vdd High-voltage event not detected,1: Vdd High-voltage event detected"
|
|
newline
|
|
bitfld.long 0x00 22. "VDD_HVDACK,VDD High-Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VDD_HVDIE,VDD High-Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when HVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 20. "VDD_HVDRE,VDD High-Voltage Detect Reset Enable" "0: VDD HVDF does not generate hardware resets,1: Force an MCU reset when VDD_HVDF = 1"
|
|
newline
|
|
bitfld.long 0x00 16. "VDD_HVDV,VDD High-Voltage Detect Voltage Select" "0: Low trip point selected (V VDD = V VDD_HVDL ),1: High trip point selected (V VDD = V VDD_HVDH )"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "AUXLDOLPCNFG,AUX LDO Low Power Configuration register"
|
|
bitfld.long 0x00 1. "LPSEL,LPSEL" "0: AUX LDO regulator enters low power state in..,1: AUX LDO regulator remains in high power state.."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "AUXLDOSC,AUX LDO Status And Control register"
|
|
bitfld.long 0x00 16.--18. "IOSSSEL,IO 1.8 Reg Soft Start Select" "0: Soft Start duration set to 110us,1: Soft Start duration set to 95us,2: Soft Start duration set to 60us,3: Soft Start duration set to 48us,4: Soft Start duration set to 38us,5: Soft Start duration set to 30us,6: Soft Start duration set to 24us,7: Soft Start duration set to 17us"
|
|
newline
|
|
rbitfld.long 0x00 8.--12. "AUXTRIM,Auxiliary Regulator TRIM value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 1. "AUXREGVSEL_OFFSET,Auxiliary Regulator Offset Voltage Select" "0: The AUXREG offset is not applied,1: The AUXREG offset is applied"
|
|
newline
|
|
bitfld.long 0x00 0. "AUXREGVSEL,Auxiliary Regulator Voltage Select" "0: Regulate to 1.8V,1: Regulate to 1.5V"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DCDCSC,DCDC Status Control Register"
|
|
rbitfld.long 0x00 31. "DCDC_STS_DC_OK,DCDC_STS_DC_OK" "0,1"
|
|
newline
|
|
eventfld.long 0x00 30. "CLKFLT_FAULT,DCDC CLKFLT Fault Status Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "PWD_CMP_OFFSET,PWD_CMP_OFFSET" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DCDC_LESS_I,DCDC_LESS_I" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DCDC_VBAT_DIV_CTRL,DCDC_VBAT_DIV_CTRL" "0: DCDC_VBAT_DIV_CTRL_0,1: DCDC_VBAT_DIV_CTRL_1,2: DCDC_VBAT_DIV_CTRL_2,3: DCDC_VBAT_DIV_CTRL_3"
|
|
newline
|
|
bitfld.long 0x00 3. "DCDC_PWD_OSC_INT,DCDC_PWD_OSC_INT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDC_SEL_CLK,DCDC_SEL_CLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DCDC_DISABLE_AUTO_CLK_SWITCH,DCDC_DISABLE_AUTO_CLK_SWITCH" "0,1"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DCDCC1,DCDC Control Register 1"
|
|
bitfld.long 0x00 27. "DCDC_LOOPCTRL_EN_DF_HYST,DCDC_LOOPCTRL_EN_DF_HYST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DCDC_LOOPCTRL_EN_CM_HYST,DCDC_LOOPCTRL_EN_CM_HYST" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "POSLIMIT_BUCK_IN,POSLIMIT_BUCK_IN"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DCDCC2,DCDC Control Register 2"
|
|
hexmask.long.word 0x00 16.--25. 1. "DCDC_BATTMONITOR_BATT_VAL,DCDC_BATTMONITOR_BATT_VAL"
|
|
newline
|
|
bitfld.long 0x00 15. "DCDC_BATTMONITOR_EN_BATADJ,DCDC_BATTMONITOR_EN_BATADJ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DCDC_LOOPCTRL_HYST_SIGN,DCDC_LOOPCTRL_HYST_SIGN" "0,1"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DCDCC3,DCDC Control Register 3"
|
|
bitfld.long 0x00 31. "DCDC_VDD1P8CTRL_DISABLE_STEP,DCDC_VDD1P8CTRL_DISABLE_STEP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DCDC_VDD1P2CTRL_DISABLE_STEP,DCDC_VDD1P2CTRL_DISABLE_STEP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "DCDC_MINPWR_HALF_FETS,DCDC_MINPWR_HALF_FETS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DCDC_MINPWR_DOUBLE_FETS,DCDC_MINPWR_DOUBLE_FETS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DCDC_MINPWR_EXTRA_DOUBLE_FETS,DCDC_MINPWR_EXTRA_DOUBLE_FETS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "DCDC_MINPWR_DC_HALFCLK,DCDC_MINPWR_DC_HALFCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DCDC_VDD1P2CTRL_ADJTN,DCDC_VDD1P2CTRL_ADJTN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "DCDC_VBAT_VALUE,DCDC_VBAT_VALUE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "DCDC_BYPASS_ADC_MEAS,DCDC_BYPASS_ADC_MEAS" "0,1"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DCDCC4,DCDC Control Register 4"
|
|
bitfld.long 0x00 20. "PULSE_RUN_SPEEDUP,PULSE RUN SPEEDUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INTEGRATOR_VALUE_SELECT,INTEGRATOR VALUE SELECT" "0: Select the saved value in hardware,1: Select the integrator value in this register"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "INTEGRATOR_VALUE,INTEGRATOR VALUE"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DCDCC6,DCDC Control Register 6"
|
|
bitfld.long 0x00 24.--27. "DCDC_HSVDD_TRIM,DCDC_HSVDD_TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DCDC_VDD1P2CTRL_TRG_BUCK,DCDC_VDD1P2CTRL_TRG_BUCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "DCDC_VDD1P8CTRL_TRG,DCDC_VDD1P8CTRL_TRG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "LPREQPINCNTRL,LP Request Pin Control Register"
|
|
bitfld.long 0x00 1. "POLARITY,Low Power Request Output Pin Polarity Control Register" "0: High true polarity,1: Low true polarity"
|
|
newline
|
|
bitfld.long 0x00 0. "LPREQOE,Low Power Request Output Enable Register" "0: Low Power request output pin not enabled,1: Low Power request output pin enabled"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "SYSTEMCONTROL (System Control Block)"
|
|
base ad:0xE000E000
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code"
|
|
bitfld.long 0x00 20.--23. "VARIANT,Major revision number n in the npm revision status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "ARCHITECTURE,Indicates the architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Indicates part number"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "REVISION,Minor revision number m in the rnpm revision status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
eventfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit" "0: write: no effect read: NMI exception is not..,1: write: changes NMI exception state to pending.."
|
|
eventfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit" "0: write: no effect read: PendSV exception is..,1: write: changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit" "0: PENDSVCLR_0,1: removes the pending state from the PendSV.."
|
|
eventfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit" "0: write: no effect read: SysTick exception is..,1: write: changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit" "0: PENDSTCLR_0,1: removes the pending state from the SysTick.."
|
|
rbitfld.long 0x00 12.--17. "VECTPENDING,Exception number of the highest priority pending enabled exception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 1. "TBLOFF,Vector table base offset"
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key"
|
|
rbitfld.long 0x00 15. "ENDIANNESS,Data endianness bit" "0: Little-endian,1: ENDIANNESS_1"
|
|
newline
|
|
bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0: no system reset request,1: asserts a signal to the outer system that.."
|
|
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit" "0: only enabled interrupts or events can wakeup..,1: enabled events and all interrupts including.."
|
|
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode" "0: SLEEPDEEP_0,1: SLEEPDEEP_1"
|
|
newline
|
|
bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode" "0: do not sleep when returning to Thread mode,1: enter sleep or deep sleep on return from an ISR"
|
|
rgroup.long 0xD14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. "STKALIGN,Indicates stack alignment on exception entry" "0,1"
|
|
bitfld.long 0x00 3. "UNALIGN_TRP,Always reads as one indicates that all unaligned accesses generate a HardFault" "0,1"
|
|
group.long 0xD1C++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of system handler 11 SVCall" "0,1,2,3"
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of system handler 15 SysTick exception" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of system handler 14 PendSV" "0,1,2,3"
|
|
group.long 0xD24++0x03
|
|
line.long 0x00 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x00 15. "SVCALLPENDED,no description available" "0: exception is not pending,1: exception is pending"
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x00 4. "EXTERNAL,no description available" "0: No EDBGRQ debug event,1: EDBGRQ debug event"
|
|
bitfld.long 0x00 3. "VCATCH,no description available" "0: No Vector catch triggered,1: Vector catch triggered"
|
|
newline
|
|
bitfld.long 0x00 2. "DWTTRAP,no description available" "0: No current debug events generated by the DWT,1: At least one current debug event generated by.."
|
|
bitfld.long 0x00 1. "BKPT,no description available" "0: No current breakpoint debug event,1: At least one current breakpoint debug event"
|
|
newline
|
|
bitfld.long 0x00 0. "HALTED,no description available" "0: No active halt request debug event,1: Halt request debug event active"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "SYSTICK (System timer)"
|
|
base ad:0xE000E010
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. "COUNTFLAG,no description available" "0,1"
|
|
bitfld.long 0x00 2. "CLKSOURCE,no description available" "0: external clock,1: processor clock"
|
|
newline
|
|
bitfld.long 0x00 1. "TICKINT,no description available" "0: counting down to 0 does not assert the..,1: counting down to 0 asserts the SysTick.."
|
|
bitfld.long 0x00 0. "ENABLE,no description available" "0: counter disabled,1: counter enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. "NOREF,no description available" "0: The reference clock is provided,1: The reference clock is not provided"
|
|
bitfld.long 0x00 30. "SKEW,no description available" "0: 10ms calibration value is exact,1: 10ms calibration value is inexact because of.."
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value to use for 10ms timing"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "TPIU (Trace Port Interface Unit Registers)"
|
|
base ad:0xE0040000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SSPSR,Supported Parallel Port Size Register"
|
|
abitfld.long 0x00 0.--31. "SWIDTH,SWIDTH[N] represents a trace port width of (N+1)" "0x00000000=0: Width (N+1) not supported,0x00000001=1: Width (N+1) supported"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CSPSR,Current Parallel Port Size Register"
|
|
abitfld.long 0x00 0.--31. "CWIDTH,CWIDTH[N] represents a trace port width of (N+1)" "0x00000000=0: Width (N+1) is not the current..,0x00000001=1: Width (N+1) is the current trace.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACPR,Asynchronous Clock Prescaler Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "PRESCALER,Divisor for TRACECLKIN is Prescaler + 1"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "SPPR,Selected Pin Protocol Register"
|
|
bitfld.long 0x00 0.--1. "TXMODE,Specified the protocol for trace output from the TPIU" "0: Parallel trace port mode,1: Asynchronous SWO using Manchester encoding,2: Asynchronous SWO using NRZ encoding,?..."
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "FFSR,Formatter and Flush Status Register"
|
|
bitfld.long 0x00 3. "FtNonStop,FtNonStop" "0,1"
|
|
bitfld.long 0x00 2. "TCPresent,TCPresent" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FtStopped,FtStopped" "0,1"
|
|
bitfld.long 0x00 0. "F1InProg,F1InProg" "0,1"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "FFCR,Formatter and Flush Control Register"
|
|
bitfld.long 0x00 8. "TrigIn,This bit Reads-As-One (RAO) specifying that triggers are inserted when a trigger pin is asserted" "0,1"
|
|
bitfld.long 0x00 1. "EnFCont,Enable continuous formatting" "0: Continuous formatting disabled,1: Continuous formatting enabled"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "FSCR,Formatter Synchronization Counter Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "CycCount,CycCount[11:0]"
|
|
rgroup.long 0xEE8++0x03
|
|
line.long 0x00 "TRIGGER,Trigger Register"
|
|
bitfld.long 0x00 0. "TRIGGER,TRIGGER input value" "0,1"
|
|
rgroup.long 0xEEC++0x03
|
|
line.long 0x00 "FIFODATA0,FIFODATA0 Register"
|
|
bitfld.long 0x00 29. "ITMATVALID,Returns the value of the ITM ATVALID signal" "0,1"
|
|
bitfld.long 0x00 27.--28. "ITMbytecount,Number of bytes of ITM trace data since last read of Integration ITM Data Register" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26. "ETMATVALID,Returns the value of the ETM ATVALID signal" "0,1"
|
|
bitfld.long 0x00 24.--25. "ETMbytecount,Number of bytes of ETM trace data since last read of Integration ETM Data Register" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETMdata2,ETM trace data"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ETMdata1,ETM trace data"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ETMdata0,ETM trace data"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "ITATBCTR2,Integration Test ATB Control 2 Register"
|
|
bitfld.long 0x00 0. "ATREADY1_ATREADY2,This bit sets the value of both the ETM and ITM ATREADY" "0,1"
|
|
rgroup.long 0xEF8++0x03
|
|
line.long 0x00 "ITATBCTR0,Integration Test ATB Control 0 Register"
|
|
bitfld.long 0x00 0. "ATVALID1_ATVALID2,A read of this bit returns the value of ATVALIDS1 OR-ed with ATVALIDS2" "0,1"
|
|
rgroup.long 0xEFC++0x03
|
|
line.long 0x00 "FIFODATA1,FIFODATA1 Register"
|
|
bitfld.long 0x00 29. "ITMATVALID,Returns the value of the ITM ATVALID signal" "0,1"
|
|
bitfld.long 0x00 27.--28. "ITMbytecount,Number of bytes of ITM trace data since last read of Integration ITM Data Register" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26. "ETMATVALID,Returns the value of the ETM ATVALID signal" "0,1"
|
|
bitfld.long 0x00 24.--25. "ETMbytecount,Number of bytes of ETM trace data since last read of Integration ETM Data Register" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "ITMdata2,ITM trace data"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ITMdata1,ITM trace data"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ITMdata0,ITM trace data"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0.--1. "Mode,Specifies the current mode for the TPIU" "0: normal mode,1: integration test mode,2: integration data test mode,?..."
|
|
group.long 0xFA0++0x03
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x00 0.--3. "CLAIMSET,A bit programmable register bank which sets the Claim Tag Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xFA4++0x03
|
|
line.long 0x00 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x00 0.--3. "CLAIMCLR,A bit programmable register bank that is zero at reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVID,TPIU_DEVID Register"
|
|
bitfld.long 0x00 11. "NRZ,Asynchronous Serial Wire Output (NRZ)" "0,1"
|
|
bitfld.long 0x00 10. "Manchester,Asynchronous Serial Wire Output (Manchester)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TraceAndClockModes,Trace and clock modes" "0: TraceAndClockModes_0,1: TraceAndClockModes_1"
|
|
bitfld.long 0x00 6.--8. "MinimumBufferSize,Minimum buffer size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "TRACECELKIN,Asynchronous TRACECLKIN" "0: b0 = TRACECLKIN must be synchronous to CLK,1: b1 = TRACECLKIN can be asynchronous to CLK"
|
|
bitfld.long 0x00 0.--4. "NumberOfTraceInputs,Number of trace inputs" "0: 1 input,1: 2 inputs If your,?..."
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
bitfld.long 0x00 4.--7. "c4KB,4KB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "JEP106,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "5" "6" "7" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PID$1,Peripheral Identification Register 5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "PID0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PartNumber,Part Number [7:0]"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "PID1,Peripheral Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "JEP106_identity_code,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PartNumber,Part Number [11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "PID2,Peripheral Identification Register 2"
|
|
bitfld.long 0x00 4.--7. "Revision,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "JEP106_identity_code,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "PID3,Peripheral Identification Register 3"
|
|
bitfld.long 0x00 4.--7. "RevAnd,RevAnd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CustomerModified,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "CID0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CID1,Component Identification Register 1"
|
|
bitfld.long 0x00 4.--7. "ComponentClass,Component class" "?,1: ComponentClass_1,?,?,?,?,?,?,?,9: CoreSight component,?,?,?,?,?,15: PrimeCell of system component with no.."
|
|
bitfld.long 0x00 0.--3. "Preamble,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "CID$1,Component Identification Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Preamble,Preamble"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "TPM (Timer/PWM Module)"
|
|
tree "TPM0"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x400AC000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40038000
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WIDTH,Counter Width"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRIG,Trigger Count"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHAN,Channel Count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
bitfld.long 0x00 0. "NOUPDATE,No Update" "0: Internal double buffered registers update as..,1: Internal double buffered registers do not.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC,Status and Control"
|
|
bitfld.long 0x00 8. "DMA,DMA Enable" "0: Disables DMA transfers,1: Enables DMA transfers"
|
|
eventfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: TPM counter operates in up counting mode,1: TPM counter operates in up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CMOD,Clock Mode Selection" "0: TPM counter is disabled,1: TPM counter increments on every TPM counter..,2: TPM counter increments on rising edge of..,3: TPM counter increments on rising edge of the.."
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,Modulo value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STATUS,Capture and Compare Status"
|
|
eventfld.long 0x00 8. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
eventfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. "COMSWAP2,Combine Channels 4 and 5 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels 4 and 5" "0: Channels 4 and 5 are independent,1: Channels 4 and 5 are combined"
|
|
newline
|
|
bitfld.long 0x00 9. "COMSWAP1,Combine Channels 2 and 3 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels 2 and 3" "0: Channels 2 and 3 are independent,1: Channels 2 and 3 are combined"
|
|
newline
|
|
bitfld.long 0x00 1. "COMSWAP0,Combine Channel 0 and 1 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels 0 and 1" "0: Channels 0 and 1 are independent,1: Channels 0 and 1 are combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. "TRIG5,Channel 5 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 4. "TRIG4,Channel 4 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3,Channel 3 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 2. "TRIG2,Channel 2 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1,Channel 1 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 0. "TRIG0,Channel 0 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "POL,Channel Polarity"
|
|
bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. "CH5FVAL,Channel 5 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH4FVAL,Channel 4 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase encoding mode,1: Count and direction encoding mode"
|
|
rbitfld.long 0x00 2. "QUADIR,Counter Direction in Quadrature Decode Mode" "0: Counter direction is decreasing (counter..,1: Counter direction is increasing (counter.."
|
|
newline
|
|
rbitfld.long 0x00 1. "TOFDIR,TOFDIR" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
|
|
bitfld.long 0x00 0. "QUADEN,QUADEN" "0: Quadrature decoder mode is disabled,1: Quadrature decoder mode is enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. "TRGSEL,Trigger Select" "?,1: Channel 0 pin input capture,2: Channel 1 pin input capture,3: Channel 0 or Channel 1 pin input capture"
|
|
bitfld.long 0x00 23. "TRGSRC,Trigger Source" "0: Trigger source selected by TRGSEL is external,1: Trigger source selected by TRGSEL is internal.."
|
|
newline
|
|
bitfld.long 0x00 22. "TRGPOL,Trigger Polarity" "0: Trigger is active high,1: Trigger is active low"
|
|
bitfld.long 0x00 19. "CPOT,Counter Pause On Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CROT,Counter Reload On Trigger" "0: Counter is not reloaded due to a rising edge..,1: Counter is reloaded when a rising edge is.."
|
|
bitfld.long 0x00 17. "CSOO,Counter Stop On Overflow" "0: TPM counter continues incrementing or..,1: TPM counter stops incrementing or.."
|
|
newline
|
|
bitfld.long 0x00 16. "CSOT,Counter Start on Trigger" "0: TPM counter starts to increment immediately..,1: TPM counter only starts to increment when it.."
|
|
bitfld.long 0x00 9. "GTBEEN,Global time base enable" "0: All channels use the internally generated TPM..,1: All channels use an externally generated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GTBSYNC,Global Time Base Synchronization" "0: Global timebase synchronization disabled,1: Global timebase synchronization enabled"
|
|
bitfld.long 0x00 6.--7. "DBGMODE,Debug Mode" "0: TPM counter is paused and does not increment..,?,?,3: TPM counter continues in debug mode"
|
|
newline
|
|
bitfld.long 0x00 5. "DOZEEN,Doze Enable" "0: Internal TPM counter continues in Doze mode,1: Internal TPM counter is paused and does not.."
|
|
endif
|
|
repeat 6. (increment 0 1)(increment 0 0x8)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("K32L3A*-CM0+")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "CSC,Channel (n) Status and Control"
|
|
eventfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
|
|
newline
|
|
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
|
|
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "CV,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat 2. (list 1. 2.) (list ad:0x400AD000 ad:0x4002E000) (list ad:0x40039000 ad:0x4003A000)
|
|
tree "TPM$1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base $2
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base $3
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status and Control"
|
|
bitfld.long 0x00 8. "DMA,DMA Enable" "0: Disables DMA transfers,1: Enables DMA transfers"
|
|
bitfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: TPM counter operates in up counting mode,1: TPM counter operates in up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CMOD,Clock Mode Selection" "0: TPM counter is disabled,1: TPM counter increments on every TPM counter..,2: TPM counter increments on rising edge of..,?..."
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WIDTH,Counter Width"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRIG,Trigger Count"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHAN,Channel Count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC,Status and Control"
|
|
bitfld.long 0x00 8. "DMA,DMA Enable" "0: Disables DMA transfers,1: Enables DMA transfers"
|
|
bitfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: TPM counter operates in up counting mode,1: TPM counter operates in up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CMOD,Clock Mode Selection" "0: TPM counter is disabled,1: TPM counter increments on every TPM counter..,2: TPM counter increments on rising edge of..,3: TPM counter increments on rising edge of the.."
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,Modulo value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STATUS,Capture and Compare Status"
|
|
bitfld.long 0x00 8. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C0SC,Channel (n) Status and Control"
|
|
bitfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
|
|
newline
|
|
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
|
|
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C0V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C1SC,Channel (n) Status and Control"
|
|
bitfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
|
|
newline
|
|
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
|
|
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C1V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. "COMSWAP2,Combine Channels 4 and 5 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels 4 and 5" "0: Channels 4 and 5 are independent,1: Channels 4 and 5 are combined"
|
|
newline
|
|
bitfld.long 0x00 9. "COMSWAP1,Combine Channels 2 and 3 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels 2 and 3" "0: Channels 2 and 3 are independent,1: Channels 2 and 3 are combined"
|
|
newline
|
|
bitfld.long 0x00 1. "COMSWAP0,Combine Channel 0 and 1 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels 0 and 1" "0: Channels 0 and 1 are independent,1: Channels 0 and 1 are combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. "TRIG5,Channel 5 Trigger" "0: No effect,1: The input trigger is used for input capture.."
|
|
bitfld.long 0x00 4. "TRIG4,Channel 4 Trigger" "0: No effect,1: The input trigger is used for input capture.."
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3,Channel 3 Trigger" "0: No effect,1: The input trigger is used for input capture.."
|
|
bitfld.long 0x00 2. "TRIG2,Channel 2 Trigger" "0: No effect,1: The input trigger is used for input capture.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1,Channel 1 Trigger" "0: No effect,1: The input trigger is used for input capture.."
|
|
bitfld.long 0x00 0. "TRIG0,Channel 0 Trigger" "0: No effect,1: The input trigger is used for input capture.."
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "POL,Channel Polarity"
|
|
bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. "CH5FVAL,Channel 5 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH4FVAL,Channel 4 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase encoding mode,1: Count and direction encoding mode"
|
|
rbitfld.long 0x00 2. "QUADIR,Counter Direction in Quadrature Decode Mode" "0: Counter direction is decreasing (counter..,1: Counter direction is increasing (counter.."
|
|
newline
|
|
rbitfld.long 0x00 1. "TOFDIR,Indicates if the TOF bit was set on the top or the bottom of counting" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
|
|
bitfld.long 0x00 0. "QUADEN,Enables the quadrature decoder mode" "0: Quadrature decoder mode is disabled,1: Quadrature decoder mode is enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 24.--25. "TRGSEL,Trigger Select" "0,1,2,3"
|
|
bitfld.long 0x00 23. "TRGSRC,Trigger Source" "0: Trigger source selected by TRGSEL is external,1: Trigger source selected by TRGSEL is internal.."
|
|
newline
|
|
bitfld.long 0x00 22. "TRGPOL,Trigger Polarity" "0: Trigger is active high,1: Trigger is active low"
|
|
bitfld.long 0x00 19. "CPOT,Counter Pause On Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CROT,Counter Reload On Trigger" "0: Counter is not reloaded due to a rising edge..,1: Counter is reloaded when a rising edge is.."
|
|
bitfld.long 0x00 17. "CSOO,Counter Stop On Overflow" "0: TPM counter continues incrementing or..,1: TPM counter stops incrementing or.."
|
|
newline
|
|
bitfld.long 0x00 16. "CSOT,Counter Start on Trigger" "0: TPM counter starts to increment immediately..,1: TPM counter only starts to increment when it.."
|
|
bitfld.long 0x00 9. "GTBEEN,Global time base enable" "0: All channels use the internally generated TPM..,1: All channels use an externally generated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GTBSYNC,Global Time Base Synchronization" "0: Global timebase synchronization disabled,1: Global timebase synchronization enabled"
|
|
bitfld.long 0x00 6.--7. "DBGMODE,Debug Mode" "0: TPM counter is paused and does not increment..,?,?,3: TPM counter continues in debug mode"
|
|
newline
|
|
bitfld.long 0x00 5. "DOZEEN,Doze Enable" "0: Internal TPM counter continues in Doze mode,1: Internal TPM counter is paused and does not.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "?,1: Channel 0 pin input capture,2: Channel 1 pin input capture,3: Channel 0 or Channel 1 pin input capture,4: Channel 2 pin input capture,5: Channel 0 or Channel 2 pin input capture,6: Channel 1 or Channel 2 pin input capture,7: Channel 0 or Channel 1 or Channel 2 pin input..,8: Channel 3 pin input capture,9: Channel 0 or Channel 3 pin input capture,10: Channel 1 or Channel 3 pin input capture,11: Channel 0 or Channel 1 or Channel 3 pin..,12: Channel 2 or Channel 3 pin input capture,13: Channel 0 or Channel 2 or Channel 3 pin..,14: Channel 1 or Channel 2 or Channel 3 pin..,15: Channel 0 or Channel 1 or Channel 2 or.."
|
|
bitfld.long 0x00 23. "TRGSRC,Trigger Source" "0: Trigger source selected by TRGSEL is external,1: Trigger source selected by TRGSEL is internal.."
|
|
newline
|
|
bitfld.long 0x00 22. "TRGPOL,Trigger Polarity" "0: Trigger is active high,1: Trigger is active low"
|
|
bitfld.long 0x00 19. "CPOT,Counter Pause On Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CROT,Counter Reload On Trigger" "0: Counter is not reloaded due to a rising edge..,1: Counter is reloaded when a rising edge is.."
|
|
bitfld.long 0x00 17. "CSOO,Counter Stop On Overflow" "0: TPM counter continues incrementing or..,1: TPM counter stops incrementing or.."
|
|
newline
|
|
bitfld.long 0x00 16. "CSOT,Counter Start on Trigger" "0: TPM counter starts to increment immediately..,1: TPM counter only starts to increment when it.."
|
|
bitfld.long 0x00 9. "GTBEEN,Global time base enable" "0: All channels use the internally generated TPM..,1: All channels use an externally generated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GTBSYNC,Global Time Base Synchronization" "0: Global timebase synchronization disabled,1: Global timebase synchronization enabled"
|
|
bitfld.long 0x00 6.--7. "DBGMODE,Debug Mode" "0: TPM counter is paused and does not increment..,?,?,3: TPM counter continues in debug mode"
|
|
newline
|
|
bitfld.long 0x00 5. "DOZEEN,Doze Enable" "0: Internal TPM counter continues in Doze mode,1: Internal TPM counter is paused and does not.."
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "TRGMUX"
|
|
tree "TRGMUX0"
|
|
base ad:0x40029000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TRGMUX_DMAMUX0,TRGMUX TRGMUX_DMAMUX0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TRGMUX_LPIT0,TRGMUX TRGMUX_LPIT0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TRGMUX_TPM0,TRGMUX TRGMUX_TPM0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRGMUX_TPM1,TRGMUX TRGMUX_TPM1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRGMUX_TPM2,TRGMUX TRGMUX_TPM2 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRGMUX_FLEXIO0,TRGMUX TRGMUX_FLEXIO0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C0,TRGMUX TRGMUX_LPI2C0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C1,TRGMUX TRGMUX_LPI2C1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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group.long 0x20++0x03
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line.long 0x00 "TRGMUX_LPI2C2,TRGMUX TRGMUX_LPI2C2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x24++0x03
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line.long 0x00 "TRGMUX_LPSPI0,TRGMUX TRGMUX_LPSPI0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x28++0x03
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line.long 0x00 "TRGMUX_LPSPI1,TRGMUX TRGMUX_LPSPI1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x2C++0x03
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line.long 0x00 "TRGMUX_LPSPI2,TRGMUX TRGMUX_LPSPI2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x30++0x03
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line.long 0x00 "TRGMUX_LPUART0,TRGMUX TRGMUX_LPUART0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x34++0x03
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line.long 0x00 "TRGMUX_LPUART1,TRGMUX TRGMUX_LPUART1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x38++0x03
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line.long 0x00 "TRGMUX_LPUART2,TRGMUX TRGMUX_LPUART2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x3C++0x03
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line.long 0x00 "TRGMUX_LPADC0,TRGMUX TRGMUX_LPADC0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x40++0x03
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line.long 0x00 "TRGMUX_LPCMP0,TRGMUX TRGMUX_LPCMP0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x44++0x03
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line.long 0x00 "TRGMUX_LPDAC0,TRGMUX TRGMUX_LPDAC0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x48++0x03
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line.long 0x00 "TRGMUX_DMAMUX1,TRGMUX TRGMUX_DMAMUX1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x4C++0x03
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line.long 0x00 "TRGMUX_LPIT1,TRGMUX TRGMUX_LPIT1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x50++0x03
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line.long 0x00 "TRGMUX_TPM3,TRGMUX TRGMUX_TPM3 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x54++0x03
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line.long 0x00 "TRGMUX_LPI2C3,TRGMUX TRGMUX_LPI2C3 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x58++0x03
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line.long 0x00 "TRGMUX_LPSPI3,TRGMUX TRGMUX_LPSPI3 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x5C++0x03
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line.long 0x00 "TRGMUX_LPUART3,TRGMUX TRGMUX_LPUART3 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x60++0x03
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line.long 0x00 "TRGMUX_LPCMP1,TRGMUX TRGMUX_LPCMP1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
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tree "TRGMUX0"
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base ad:0x40027000
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group.long 0x00++0x03
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line.long 0x00 "TRGMUX_DMAMUX0,TRGMUX TRGMUX_DMAMUX0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x04++0x03
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line.long 0x00 "TRGMUX_LPIT0,TRGMUX TRGMUX_LPIT0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x08++0x03
|
|
line.long 0x00 "TRGMUX_TPM0,TRGMUX TRGMUX_TPM0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x0C++0x03
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line.long 0x00 "TRGMUX_TPM1,TRGMUX TRGMUX_TPM1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x10++0x03
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line.long 0x00 "TRGMUX_TPM2,TRGMUX TRGMUX_TPM2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x14++0x03
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line.long 0x00 "TRGMUX_FLEXIO0,TRGMUX TRGMUX_FLEXIO0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x18++0x03
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line.long 0x00 "TRGMUX_LPI2C0,TRGMUX TRGMUX_LPI2C0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x1C++0x03
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line.long 0x00 "TRGMUX_LPI2C1,TRGMUX TRGMUX_LPI2C1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x20++0x03
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line.long 0x00 "TRGMUX_LPI2C2,TRGMUX TRGMUX_LPI2C2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x24++0x03
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line.long 0x00 "TRGMUX_LPSPI0,TRGMUX TRGMUX_LPSPI0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x28++0x03
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line.long 0x00 "TRGMUX_LPSPI1,TRGMUX TRGMUX_LPSPI1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x2C++0x03
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line.long 0x00 "TRGMUX_LPSPI2,TRGMUX TRGMUX_LPSPI2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x30++0x03
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line.long 0x00 "TRGMUX_LPUART0,TRGMUX TRGMUX_LPUART0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x34++0x03
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line.long 0x00 "TRGMUX_LPUART1,TRGMUX TRGMUX_LPUART1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x38++0x03
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line.long 0x00 "TRGMUX_LPUART2,TRGMUX TRGMUX_LPUART2 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x3C++0x03
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line.long 0x00 "TRGMUX_LPADC0,TRGMUX TRGMUX_LPADC0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x40++0x03
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line.long 0x00 "TRGMUX_LPCMP0,TRGMUX TRGMUX_LPCMP0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x44++0x03
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line.long 0x00 "TRGMUX_LPDAC0,TRGMUX TRGMUX_LPDAC0 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x48++0x03
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line.long 0x00 "TRGMUX_DMAMUX1,TRGMUX TRGMUX_DMAMUX1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x4C++0x03
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line.long 0x00 "TRGMUX_LPIT1,TRGMUX TRGMUX_LPIT1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x50++0x03
|
|
line.long 0x00 "TRGMUX_TPM3,TRGMUX TRGMUX_TPM3 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x54++0x03
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line.long 0x00 "TRGMUX_LPI2C3,TRGMUX TRGMUX_LPI2C3 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x58++0x03
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|
line.long 0x00 "TRGMUX_LPSPI3,TRGMUX TRGMUX_LPSPI3 Register"
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|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x5C++0x03
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line.long 0x00 "TRGMUX_LPUART3,TRGMUX TRGMUX_LPUART3 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x60++0x03
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|
line.long 0x00 "TRGMUX_LPCMP1,TRGMUX TRGMUX_LPCMP1 Register"
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bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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tree "TRGMUX1"
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base ad:0x400A7000
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repeat 2. (strings "0" "1" )(list 0x0 0x4 )
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group.long ($2+0x08)++0x03
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line.long 0x00 "TRGMUX_TPM$1,TRGMUX TRGCFG Register"
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bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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newline
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRGMUX_FLEXIO,TRGMUX TRGCFG Register"
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|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
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bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "TRGMUX_LPUART$1,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C$1,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "TRGMUX_LPSPI$1,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "TRGMUX1"
|
|
base ad:0x41025000
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "TRGMUX_TPM$1,TRGMUX TRGCFG Register"
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|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
newline
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|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRGMUX_FLEXIO,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "TRGMUX_LPUART$1,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C$1,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
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|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "TRGMUX_LPSPI$1,TRGMUX TRGCFG Register"
|
|
bitfld.long 0x00 31. "LK,Enable" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0: Trigger function is disabled,1: Port pin trigger input is selected,2: FlexIO Timer 0 input is selected,3: FlexIO Timer 1 input is selected,4: FlexIO Timer 2 input is selected,5: FlexIO Timer 3 input is selected,6: FlexIO Timer 4 input is selected,7: FlexIO Timer 5 input is selected,8: FlexIO Timer 6 input is selected,9: FlexIO Timer 7 input is selected,10: TPM0 Overflow is selected,11: TPM0 Channel 0 is selected,12: TPM0 Channel 1 is selected,13: TPM1 Overflow is selected,14: TPM1 Channel 0 is selected,15: TPM1 Channel 1 is selected,16: LPIT1 Channel 0 is selected,17: LPIT1 Channel 1 is selected,18: LPIT1 Channel 2 is selected,19: LPIT1 Channel 3 is selected,20: LPUART0 RX Data is selected,21: LPUART0 TX Data is selected,22: LPUART0 RX Idle is selected,23: LPUART1 RX Data is selected,24: LPUART1 TX Data is selected,25: LPUART1 RX Idle is selected,26: LPI2C0 Master STOP is selected,27: LPI2C0 Slave STOP is selected,28: LPI2C1 Master STOP is selected,29: LPI2C1 Slave STOP is selected,30: LPSPI0 Frame is selected,31: LPSPI0 RX data is selected,32: LPSPI1 Frame is selected,33: LPSPI1 RX data is selected,34: RTC Seconds Counter is selected,35: RTC Alarm is selected,36: LPTMR0 Trigger is selected,37: LPTMR1 Trigger is selected,38: CMP0 Output is selected,39: CMP1 Output is selected,40: ADC0 Conversion A Complete is selected,41: ADC0 Conversion B Complete is selected,42: Port A Pin Trigger is selected,43: Port B Pin Trigger is selected,44: Port C Pin Trigger is selected,45: Port D Pin Trigger is selected,46: Port E Pin Trigger is selected,47: TPM2 Overflow selected,48: TPM2 Channel 0 is selected,49: TPM2 Channel 1 is selected,50: LPIT0 Channel 0 is selected,51: LPIT0 Channel 1 is selected,52: LPIT0 Channel 2 is selected,53: LPIT0 Channel 3 is selected,54: USB Start-of-Frame is selected,55: LPUART2 RX Data is selected,56: LPUART2 TX Data is selected,57: LPUART2 RX Idle is selected,58: LPI2C2 Master STOP is selected,59: LPI2C2 Slave STOP is selected,60: LPSPI2 Frame is selected,61: LPSPI2 RX Data is selected,?..."
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "TRNG"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x400A5000
|
|
elif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x41029000
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,TRNG Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. "PRGM,Programming Mode Select" "0,1"
|
|
rbitfld.long 0x00 13. "TSTOP_OK,TRNG_OK_TO_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ERR,Read: Error status" "0,1"
|
|
rbitfld.long 0x00 11. "TST_OUT,Read only: Test point inside ring oscillator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "ENT_VAL,Read only: Entropy Valid" "0,1"
|
|
rbitfld.long 0x00 9. "FCT_VAL,Read only: Frequency Count Valid" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "FCT_FAIL,Read only: Frequency Count Fail" "0,1"
|
|
bitfld.long 0x00 7. "FOR_SCLK,Force System Clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RST_DEF,Reset Defaults" "0,1"
|
|
bitfld.long 0x00 5. "TRNG_ACC,TRNG Access Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "UNUSED,This bit is unused but write-able" "0,1"
|
|
bitfld.long 0x00 2.--3. "OSC_DIV,Oscillator Divide" "0: use ring oscillator with no divide,1: use ring oscillator divided-by-2,2: use ring oscillator divided-by-4,3: use ring oscillator divided-by-8"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SAMP_MODE,Sample Mode" "0: use Von Neumann data into both Entropy..,1: use raw data into both Entropy shifter and..,2: use Von Neumann data into Entropy shifter,3: undefined/reserved"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCTL,Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. "PRGM,Programming Mode Select" "0,1"
|
|
rbitfld.long 0x00 13. "TSTOP_OK,TRNG_OK_TO_STOP" "0,1"
|
|
newline
|
|
eventfld.long 0x00 12. "ERR,Read: Error status" "0,1"
|
|
rbitfld.long 0x00 11. "TST_OUT,Read only: Test point inside ring oscillator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "ENT_VAL,Read only: Entropy Valid" "0,1"
|
|
rbitfld.long 0x00 9. "FCT_VAL,Read only: Frequency Count Valid" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "FCT_FAIL,Read only: Frequency Count Fail" "0,1"
|
|
bitfld.long 0x00 7. "FOR_SCLK,Force System Clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RST_DEF,Reset Defaults" "0,1"
|
|
bitfld.long 0x00 5. "TRNG_ACC,TRNG Access Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "UNUSED4,This bit is unused" "0,1"
|
|
bitfld.long 0x00 2.--3. "OSC_DIV,Oscillator Divide" "0: use ring oscillator with no divide,1: use ring oscillator divided-by-2,2: use ring oscillator divided-by-4,3: use ring oscillator divided-by-8"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SAMP_MODE,Sample Mode" "0: use Von Neumann data into both Entropy..,1: use raw data into both Entropy shifter and..,2: use Von Neumann data into Entropy shifter,3: undefined/reserved"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register"
|
|
bitfld.long 0x00 16.--19. "RTY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LRUN_MAX,LONG RUN MAX LIMIT"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SCMISC,Statistical Check Miscellaneous Register"
|
|
bitfld.long 0x00 16.--19. "RTY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LRUN_MAX,LONG RUN MAX LIMIT"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PKRRNG,TRNG Poker Range Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_RNG,Poker Range"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PKRRNG,Poker Range Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_RNG,Poker Range"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKRSQ,TRNG Poker Square Calculation Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_SQ,Poker Square Calculation Result"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PKRMAX,TRNG Poker Maximum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_MAX,Poker Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PKRMAX,Poker Maximum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_MAX,Poker Maximum Limit"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PKRSQ,Poker Square Calculation Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PKR_SQ,Poker Square Calculation Result"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SDCTL,TRNG Seed Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ENT_DLY,Entropy Delay"
|
|
hexmask.long.word 0x00 0.--15. 1. "SAMP_SIZE,Sample Size"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SDCTL,Seed Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ENT_DLY,Entropy Delay"
|
|
hexmask.long.word 0x00 0.--15. 1. "SAMP_SIZE,Sample Size"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TOTSAM,Total Samples Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "TOT_SAM,Total Samples"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SBLIM,Sparse Bit Limit Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SB_LIM,Sparse Bit Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TOTSAM,TRNG Total Samples Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "TOT_SAM,Total Samples"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SBLIM,TRNG Sparse Bit Limit Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SB_LIM,Sparse Bit Limit"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FRQMIN,Frequency Count Minimum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MIN,Frequency Count Minimum Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FRQMIN,TRNG Frequency Count Minimum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MIN,Frequency Count Minimum Limit"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FRQCNT,TRNG Frequency Count Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_CT,Frequency Count"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FRQMAX,TRNG Frequency Count Maximum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MAX,Frequency Counter Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FRQCNT,Frequency Count Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_CT,Frequency Count"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FRQMAX,Frequency Count Maximum Limit Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "FRQ_MAX,Frequency Counter Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCML,TRNG Statistical Check Monobit Limit Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "MONO_RNG,Monobit Range"
|
|
hexmask.long.word 0x00 0.--15. 1. "MONO_MAX,Monobit Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCML,Statistical Check Monobit Limit Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "MONO_RNG,Monobit Range"
|
|
hexmask.long.word 0x00 0.--15. 1. "MONO_MAX,Monobit Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SCMC,TRNG Statistical Check Monobit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MONO_CT,Monobit Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SCMC,Statistical Check Monobit Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MONO_CT,Monobit Count"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCR1L,Statistical Check Run Length 1 Limit Register"
|
|
hexmask.long.word 0x00 16.--30. 1. "RUN1_RNG,Run Length 1 Range"
|
|
hexmask.long.word 0x00 0.--14. 1. "RUN1_MAX,Run Length 1 Maximum Limit"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SCR1C,Statistical Check Run Length 1 Count Register"
|
|
hexmask.long.word 0x00 16.--30. 1. "R1_1_CT,Runs of One Length 1 Count"
|
|
hexmask.long.word 0x00 0.--14. 1. "R1_0_CT,Runs of Zero Length 1 Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SCR1C,TRNG Statistical Check Run Length 1 Count Register"
|
|
hexmask.long.word 0x00 16.--30. 1. "R1_1_CT,Runs of One Length 1 Count"
|
|
hexmask.long.word 0x00 0.--14. 1. "R1_0_CT,Runs of Zero Length 1 Count"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCR1L,TRNG Statistical Check Run Length 1 Limit Register"
|
|
hexmask.long.word 0x00 16.--30. 1. "RUN1_RNG,Run Length 1 Range"
|
|
hexmask.long.word 0x00 0.--14. 1. "RUN1_MAX,Run Length 1 Maximum Limit"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCR2C,TRNG Statistical Check Run Length 2 Count Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "R2_1_CT,Runs of One Length 2 Count"
|
|
hexmask.long.word 0x00 0.--13. 1. "R2_0_CT,Runs of Zero Length 2 Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SCR2L,Statistical Check Run Length 2 Limit Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "RUN2_RNG,Run Length 2 Range"
|
|
hexmask.long.word 0x00 0.--13. 1. "RUN2_MAX,Run Length 2 Maximum Limit"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCR2C,Statistical Check Run Length 2 Count Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "R2_1_CT,Runs of One Length 2 Count"
|
|
hexmask.long.word 0x00 0.--13. 1. "R2_0_CT,Runs of Zero Length 2 Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SCR2L,TRNG Statistical Check Run Length 2 Limit Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "RUN2_RNG,Run Length 2 Range"
|
|
hexmask.long.word 0x00 0.--13. 1. "RUN2_MAX,Run Length 2 Maximum Limit"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCR3L,TRNG Statistical Check Run Length 3 Limit Register"
|
|
hexmask.long.word 0x00 16.--28. 1. "RUN3_RNG,Run Length 3 Range"
|
|
hexmask.long.word 0x00 0.--12. 1. "RUN3_MAX,Run Length 3 Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SCR3C,Statistical Check Run Length 3 Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. "R3_1_CT,Runs of Ones Length 3 Count"
|
|
hexmask.long.word 0x00 0.--12. 1. "R3_0_CT,Runs of Zeroes Length 3 Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SCR3C,TRNG Statistical Check Run Length 3 Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. "R3_1_CT,Runs of Ones Length 3 Count"
|
|
hexmask.long.word 0x00 0.--12. 1. "R3_0_CT,Runs of Zeroes Length 3 Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCR3L,Statistical Check Run Length 3 Limit Register"
|
|
hexmask.long.word 0x00 16.--28. 1. "RUN3_RNG,Run Length 3 Range"
|
|
hexmask.long.word 0x00 0.--12. 1. "RUN3_MAX,Run Length 3 Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SCR4L,TRNG Statistical Check Run Length 4 Limit Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "RUN4_RNG,Run Length 4 Range"
|
|
hexmask.long.word 0x00 0.--11. 1. "RUN4_MAX,Run Length 4 Maximum Limit"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SCR4C,TRNG Statistical Check Run Length 4 Count Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "R4_1_CT,Runs of One Length 4 Count"
|
|
hexmask.long.word 0x00 0.--11. 1. "R4_0_CT,Runs of Zero Length 4 Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SCR4L,Statistical Check Run Length 4 Limit Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "RUN4_RNG,Run Length 4 Range"
|
|
hexmask.long.word 0x00 0.--11. 1. "RUN4_MAX,Run Length 4 Maximum Limit"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SCR4C,Statistical Check Run Length 4 Count Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "R4_1_CT,Runs of One Length 4 Count"
|
|
hexmask.long.word 0x00 0.--11. 1. "R4_0_CT,Runs of Zero Length 4 Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SCR5C,TRNG Statistical Check Run Length 5 Count Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "R5_1_CT,Runs of One Length 5 Count"
|
|
hexmask.long.word 0x00 0.--10. 1. "R5_0_CT,Runs of Zero Length 5 Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SCR5C,Statistical Check Run Length 5 Count Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "R5_1_CT,Runs of One Length 5 Count"
|
|
hexmask.long.word 0x00 0.--10. 1. "R5_0_CT,Runs of Zero Length 5 Count"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SCR5L,Statistical Check Run Length 5 Limit Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "RUN5_RNG,Run Length 5 Range"
|
|
hexmask.long.word 0x00 0.--10. 1. "RUN5_MAX,Run Length 5 Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SCR5L,TRNG Statistical Check Run Length 5 Limit Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "RUN5_RNG,Run Length 5 Range"
|
|
hexmask.long.word 0x00 0.--10. 1. "RUN5_MAX,Run Length 5 Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SCR6PC,Statistical Check Run Length 6+ Count Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "R6P_1_CT,Runs of One Length 6+ Count"
|
|
hexmask.long.word 0x00 0.--10. 1. "R6P_0_CT,Runs of Zero Length 6+ Count"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCR6PL,Statistical Check Run Length 6+ Limit Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "RUN6P_RNG,Run Length 6+ Range"
|
|
hexmask.long.word 0x00 0.--10. 1. "RUN6P_MAX,Run Length 6+ Maximum Limit"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCR6PL,TRNG Statistical Check Run Length 6+ Limit Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "RUN6P_RNG,Run Length 6+ Range"
|
|
hexmask.long.word 0x00 0.--10. 1. "RUN6P_MAX,Run Length 6+ Maximum Limit"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SCR6PC,TRNG Statistical Check Run Length 6+ Count Register"
|
|
hexmask.long.word 0x00 16.--26. 1. "R6P_1_CT,Runs of One Length 6+ Count"
|
|
hexmask.long.word 0x00 0.--10. 1. "R6P_0_CT,Runs of Zero Length 6+ Count"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "STATUS,TRNG Status Register"
|
|
bitfld.long 0x00 16.--19. "RETRY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TFMB,Test Fail Mono Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TFP,Test Fail Poker" "0,1"
|
|
bitfld.long 0x00 13. "TFLR,Test Fail Long Run" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TFSB,Test Fail Sparse Bit" "0,1"
|
|
bitfld.long 0x00 11. "TF6PBR1,Test Fail 6 Plus Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TF6PBR0,Test Fail 6 Plus Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 9. "TF5BR1,Test Fail 5-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TF5BR0,Test Fail 5-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 7. "TF4BR1,Test Fail 4-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TF4BR0,Test Fail 4-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 5. "TF3BR1,Test Fail 3-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TF3BR0,Test Fail 3-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 3. "TF2BR1,Test Fail 2-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TF2BR0,Test Fail 2-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 1. "TF1BR1,Test Fail 1-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TF1BR0,Test Fail 1-Bit Run Sampling 0s" "0,1"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 16.--19. "RETRY_CT,RETRY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "TFMB,Test Fail Mono Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TFP,Test Fail Poker" "0,1"
|
|
bitfld.long 0x00 13. "TFLR,Test Fail Long Run" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TFSB,Test Fail Sparse Bit" "0,1"
|
|
bitfld.long 0x00 11. "TF6PBR1,Test Fail 6 Plus Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TF6PBR0,Test Fail 6 Plus Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 9. "TF5BR1,Test Fail 5-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TF5BR0,Test Fail 5-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 7. "TF4BR1,Test Fail 4-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TF4BR0,Test Fail 4-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 5. "TF3BR1,Test Fail 3-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TF3BR0,Test Fail 3-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 3. "TF2BR1,Test Fail 2-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TF2BR0,Test Fail 2-Bit Run Sampling 0s" "0,1"
|
|
bitfld.long 0x00 1. "TF1BR1,Test Fail 1-Bit Run Sampling 1s" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TF1BR0,Test Fail 1-Bit Run Sampling 0s" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ENT[0],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ENT0,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ENT[1],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ENT1,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ENT[2],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x48)++0x03
|
|
line.long 0x00 "ENT$1,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ENT[3],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ENT4,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ENT[4],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ENT5,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x54)++0x03
|
|
line.long 0x00 "ENT[$1],Entropy Read Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ENT6,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ENT[7],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x5C)++0x03
|
|
line.long 0x00 "ENT$1,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ENT[8],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ENT9,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ENT[9],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ENT10,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ENT[10],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ENT11,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x6C)++0x03
|
|
line.long 0x00 "ENT[$1],Entropy Read Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "12" "13" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x70)++0x03
|
|
line.long 0x00 "ENT$1,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
repeat 2. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x74)++0x03
|
|
line.long 0x00 "ENT[$1],Entropy Read Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "ENT14,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "ENT[15],Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "ENT15,TRNG Entropy Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENT,Entropy Value"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 and 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_1_CT,Poker 1h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_0_CT,Poker 0h Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PKRCNT10,Statistical Check Poker Count 1 and 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_1_CT,Poker 1h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_0_CT,Poker 0h Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 and 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_3_CT,Poker 3h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_2_CT,Poker 2h Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PKRCNT32,Statistical Check Poker Count 3 and 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_3_CT,Poker 3h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_2_CT,Poker 2h Count"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PKRCNT54,Statistical Check Poker Count 5 and 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_5_CT,Poker 5h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_4_CT,Poker 4h Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 and 4 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_5_CT,Poker 5h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_4_CT,Poker 4h Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "PKRCNT76,Statistical Check Poker Count 7 and 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_7_CT,Poker 7h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_6_CT,Poker 6h Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 and 6 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_7_CT,Poker 7h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_6_CT,Poker 6h Count"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 and 8 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_9_CT,Poker 9h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_8_CT,Poker 8h Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "PKRCNT98,Statistical Check Poker Count 9 and 8 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_9_CT,Poker 9h Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_8_CT,Poker 8h Count"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKRCNTBA,Statistical Check Poker Count B and A Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_B_CT,Poker Bh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_A_CT,Poker Ah Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B and A Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_B_CT,Poker Bh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_A_CT,Poker Ah Count"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D and C Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_D_CT,Poker Dh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_C_CT,Poker Ch Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PKRCNTDC,Statistical Check Poker Count D and C Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_D_CT,Poker Dh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_C_CT,Poker Ch Count"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F and E Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_F_CT,Poker Fh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_E_CT,Poker Eh Count"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "PKRCNTFE,Statistical Check Poker Count F and E Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PKR_F_CT,Poker Fh Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "PKR_E_CT,Poker Eh Count"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SEC_CFG,Security Configuration Register"
|
|
bitfld.long 0x00 2. "UNUSED2,This bit is unused" "0,1"
|
|
bitfld.long 0x00 1. "NO_PRGM,If set the TRNG registers cannot be programmed" "0: Programability of registers controlled only..,1: Overides Miscellaneous Control Register.."
|
|
newline
|
|
bitfld.long 0x00 0. "UNUSED0,This bit is unused" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SEC_CFG,TRNG Security Configuration Register"
|
|
bitfld.long 0x00 2. "SK_VAL,Reserved" "0: See DRNG version,1: See DRNG version"
|
|
bitfld.long 0x00 1. "NO_PRGM,If set the TRNG registers cannot be programmed" "0: Programability of registers controlled only..,1: Overides TRNG Miscellaneous Control Register.."
|
|
newline
|
|
bitfld.long 0x00 0. "SH0,Reserved" "0: See DRNG version,1: See DRNG version"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "INT_CTRL,Interrupt Control Register"
|
|
hexmask.long 0x00 3.--31. 1. "UNUSED,Reserved but writeable"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
newline
|
|
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted" "0: Corresponding bit of INT_STATUS register..,1: Corresponding bit of INT_STATUS register active"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "INT_CTRL,TRNG Interrupt Control Register"
|
|
hexmask.long 0x00 3.--31. 1. "UNUSED,Reserved but writeable"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
|
|
newline
|
|
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
|
|
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted" "0: Corresponding bit of INT_STATUS cleared,1: Corresponding bit of INT_STATUS active"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "INT_MASK,Mask Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 of this register" "0: Same behavior as bit 0 of this register,1: Same behavior as bit 0 of this register"
|
|
newline
|
|
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted" "0: Corresponding interrupt of INT_STATUS is masked,1: Corresponding bit of INT_STATUS is active"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "INT_MASK,TRNG Mask Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
|
|
bitfld.long 0x00 1. "ENT_VAL,Same behavior as bit 0 above" "0: Same behavior as bit 0 above,1: Same behavior as bit 0 above"
|
|
newline
|
|
bitfld.long 0x00 0. "HW_ERR,Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted" "0: Corresponding interrupt of INT_STATUS is masked,1: Corresponding bit of INT_STATUS is active"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "INT_STATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Read only: Frequency Count Fail" "0: No hardware nor self test frequency errors,1: The frequency counter has detected a failure"
|
|
bitfld.long 0x00 1. "ENT_VAL,Read only: Entropy Valid" "0: Busy generation entropy,1: TRNG can be stopped and entropy is valid if"
|
|
newline
|
|
bitfld.long 0x00 0. "HW_ERR,Read: Error status" "0: HW_ERR_0,1: error detected"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "INT_STATUS,TRNG Interrupt Status Register"
|
|
bitfld.long 0x00 2. "FRQ_CT_FAIL,Read only: Frequency Count Fail" "0: No hardware nor self test frequency errors,1: The frequency counter has detected a failure"
|
|
rbitfld.long 0x00 1. "ENT_VAL,Read only: Entropy Valid" "0: Busy generation entropy,1: TRNG can be stopped and entropy is valid if"
|
|
newline
|
|
rbitfld.long 0x00 0. "HW_ERR,Read: Error status" "0: no error,1: error detected"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "VID1,Version ID Register (MS)"
|
|
hexmask.long.word 0x00 16.--31. 1. "IP_ID,Shows the IP ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MAJ_REV,Shows the IP's Major revision of the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "MIN_REV,Shows the IP's Minor revision of the TRNG"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "VID1,TRNG Version ID Register (MS)"
|
|
hexmask.long.word 0x00 16.--31. 1. "IP_ID,Shows the Freescale IP ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MAJ_REV,Shows the Freescale IP's Major revision of the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "MIN_REV,Shows the Freescale IP's Minor revision of the TRNG"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "VID2,TRNG Version ID Register (LS)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ERA,Shows the Freescale compile options for the TRNG"
|
|
hexmask.long.byte 0x00 16.--23. 1. "INTG_OPT,Shows the Freescale integration options for the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ECO_REV,Shows the Freescale IP's ECO revision of the TRNG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CONFIG_OPT,Shows the Freescale IP's Configuaration options for the TRNG"
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "VID2,Version ID Register (LS)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ERA,Shows the compile options for the TRNG"
|
|
hexmask.long.byte 0x00 16.--23. 1. "INTG_OPT,Shows the integration options for the TRNG"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ECO_REV,Shows the IP's ECO revision of the TRNG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CONFIG_OPT,Shows the IP's Configuaration options for the TRNG"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "TSI0 (Touch sense input)"
|
|
base ad:0x40062000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GENCS,TSI General Control and Status Register"
|
|
bitfld.long 0x00 31. "OUTRGF,Out of Range Flag" "0,1"
|
|
bitfld.long 0x00 28. "ESOR,End-of-scan or Out-of-Range Interrupt Selection" "0: Out-of-range interrupt is allowed,1: End-of-scan interrupt is allowed"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "MODE,TSI analog modes setup and status" "0: Set TSI in capacitive sensing(non-noise..,?,?,?,4: Set TSI analog to work in single threshold..,?,?,?,8: Set TSI analog to work in single threshold..,?,?,?,12: Set TSI analog to work in automatic noise..,?..."
|
|
bitfld.long 0x00 21.--23. "REFCHRG,REFCHRG" "0: 500 nA,1: 1 uA,2: 2 uA,3: 4 uA,4: 8 uA,5: 16 uA,6: 32 uA,7: 64 uA"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DVOLT,DVOLT" "0: DV = 1.026 V VP = 1.328 V Vm = 0.302 V,1: DV = 0.592 V VP = 1.111 V Vm = 0.519 V,2: DV = 0.342 V VP = 0.986 V Vm = 0.644 V,3: DV = 0.197 V VP = 0.914 V Vm = 0.716 V"
|
|
bitfld.long 0x00 16.--18. "EXTCHRG,EXTCHRG" "0: 500 nA,1: 1 uA,2: 2 uA,3: 4 uA,4: 8 uA,5: 16 uA,6: 32 uA,7: 64 uA"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "PS,PS" "0: Electrode Oscillator Frequency divided by 1,1: Electrode Oscillator Frequency divided by 2,2: Electrode Oscillator Frequency divided by 4,3: Electrode Oscillator Frequency divided by 8,4: Electrode Oscillator Frequency divided by 16,5: Electrode Oscillator Frequency divided by 32,6: Electrode Oscillator Frequency divided by 64,7: Electrode Oscillator Frequency divided by 128"
|
|
bitfld.long 0x00 8.--12. "NSCN,NSCN" "0: Once per electrode,1: Twice per electrode,2: 3 times per electrode,3: 4 times per electrode,4: 5 times per electrode,5: 6 times per electrode,6: 7 times per electrode,7: 8 times per electrode,8: 9 times per electrode,9: 10 times per electrode,10: 11 times per electrode,11: 12 times per electrode,12: 13 times per electrode,13: 14 times per electrode,14: 15 times per electrode,15: 16 times per electrode,16: 17 times per electrode,17: 18 times per electrode,18: 19 times per electrode,19: 20 times per electrode,20: 21 times per electrode,21: 22 times per electrode,22: 23 times per electrode,23: 24 times per electrode,24: 25 times per electrode,25: 26 times per electrode,26: 27 times per electrode,27: 28 times per electrode,28: 29 times per electrode,29: 30 times per electrode,30: 31 times per electrode,31: 32 times per electrode"
|
|
newline
|
|
bitfld.long 0x00 7. "TSIEN,Touch Sensing Input Module Enable" "0: TSI module disabled,1: TSI module enabled"
|
|
bitfld.long 0x00 6. "TSIIEN,Touch Sensing Input Interrupt Enable" "0: TSI interrupt is disabled,1: TSI interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STPE,TSI STOP Enable" "0: TSI is disabled when MCU goes into low power..,1: Allows TSI to continue running in all low.."
|
|
bitfld.long 0x00 4. "STM,Scan Trigger Mode" "0: Software trigger scan,1: Hardware trigger scan"
|
|
newline
|
|
rbitfld.long 0x00 3. "SCNIP,Scan In Progress Status" "0: No scan in progress,1: Scan in progress"
|
|
bitfld.long 0x00 2. "EOSF,End of Scan Flag" "0: Scan not complete,1: Scan complete"
|
|
newline
|
|
bitfld.long 0x00 1. "CURSW,CURSW" "0: The current source pair are not swapped,1: The current source pair are swapped"
|
|
bitfld.long 0x00 0. "EOSDMEO,End-of-Scan DMA Transfer Request Enable Only" "0: Do not enable the End-of-Scan DMA transfer..,1: Only the End-of-Scan event can trigger a DMA.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DATA,TSI DATA Register"
|
|
bitfld.long 0x00 28.--31. "TSICH,TSICH" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3,4: Channel 4,5: Channel 5,6: Channel 6,7: Channel 7,8: Channel 8,9: Channel 9,10: Channel 10,11: Channel 11,12: Channel 12,13: Channel 13,14: Channel 14,15: Channel 15"
|
|
bitfld.long 0x00 23. "DMAEN,DMA Transfer Enabled" "0: Interrupt is selected when the interrupt..,1: DMA transfer request is selected when the.."
|
|
newline
|
|
bitfld.long 0x00 22. "SWTS,Software Trigger Start" "0: No effect,1: Start a scan to determine which channel is.."
|
|
hexmask.long.word 0x00 0.--15. 1. "TSICNT,TSI Conversion Counter Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TSHD,TSI Threshold Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "THRESH,TSI Wakeup Channel High-threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. "THRESL,TSI Wakeup Channel Low-threshold"
|
|
tree.end
|
|
tree "TSTMR0 (Timestamp Timer)"
|
|
base ad:0x400750F0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "L,Time Stamp Timer Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "VALUE,Time Stamp Timer Low"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "H,Time Stamp Timer Register High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Time Stamp Timer High"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM4")
|
|
tree "TSTMRA"
|
|
base ad:0x40034000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "LOW,Time Stamp Timer Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "VALUE,Time Stamp Timer Low"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "HIGH,Time Stamp Timer Register High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Time Stamp Timer High"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")
|
|
tree "TSTMRB"
|
|
base ad:0x4102C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "LOW,Time Stamp Timer Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "VALUE,Time Stamp Timer Low"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "HIGH,Time Stamp Timer Register High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Time Stamp Timer High"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "UART2 (Serial Communication Interface)"
|
|
base ad:0x4006C000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "BDH,UART Baud Rate Registers: High"
|
|
bitfld.byte 0x00 6. "RXEDGIE,RxD Input Active Edge Interrupt Enable" "0: Hardware interrupts from RXEDGIF disabled..,1: RXEDGIF interrupt request enabled"
|
|
bitfld.byte 0x00 0.--4. "SBR,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BDL,UART Baud Rate Registers: Low"
|
|
hexmask.byte 0x00 0.--7. 1. "SBR,UART Baud Rate Bits"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "C1,UART Control Register 1"
|
|
bitfld.byte 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation,1: Loop mode where transmitter output is.."
|
|
bitfld.byte 0x00 5. "RSRC,Receiver Source Select" "0: Selects internal loop back mode,1: Single wire UART mode where the receiver.."
|
|
newline
|
|
bitfld.byte 0x00 4. "M,9-bit or 8-bit Mode Select" "0: Normal-start + 8 data bits (MSB/LSB first as..,1: Use-start + 9 data bits (MSB/LSB first as.."
|
|
bitfld.byte 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Idle line wakeup,1: Address mark wakeup"
|
|
newline
|
|
bitfld.byte 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
bitfld.byte 0x00 1. "PE,Parity Enable" "0: Parity function disabled,1: Parity function enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "C2,UART Control Register 2"
|
|
bitfld.byte 0x00 7. "TIE,Transmitter Interrupt or DMA Transfer Enable" "0: TDRE interrupt and DMA transfer requests..,1: TDRE interrupt or DMA transfer requests enabled"
|
|
bitfld.byte 0x00 6. "TCIE,Transmission Complete Interrupt Enable" "0: TC interrupt requests disabled,1: TC interrupt requests enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. "RIE,Receiver Full Interrupt or DMA Transfer Enable" "0: RDRF interrupt and DMA transfer requests..,1: RDRF interrupt or DMA transfer requests enabled"
|
|
bitfld.byte 0x00 4. "ILIE,Idle Line Interrupt Enable" "0: IDLE interrupt requests disabled,1: IDLE interrupt requests enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. "TE,Transmitter Enable" "0: Transmitter off,1: Transmitter on"
|
|
bitfld.byte 0x00 2. "RE,Receiver Enable" "0: Receiver off,1: Receiver on"
|
|
newline
|
|
bitfld.byte 0x00 1. "RWU,Receiver Wakeup Control" "0: Normal operation,1: RWU enables the wakeup function and inhibits.."
|
|
bitfld.byte 0x00 0. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break characters to be sent"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer is full,1: Transmit data buffer is empty"
|
|
bitfld.byte 0x00 6. "TC,Transmit Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
bitfld.byte 0x00 5. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer is empty,1: Receive data buffer is full"
|
|
bitfld.byte 0x00 4. "IDLE,Idle Line Flag" "0: Receiver input is either active now or has..,1: Receiver input has become idle or the flag.."
|
|
newline
|
|
bitfld.byte 0x00 3. "OR,Receiver Overrun Flag" "0: No overrun has occurred since the last time..,1: Overrun has occurred or the overrun flag has.."
|
|
bitfld.byte 0x00 2. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in D"
|
|
newline
|
|
bitfld.byte 0x00 1. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
bitfld.byte 0x00 0. "PF,Parity Error Flag" "0: No parity error detected,1: Parity error"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "S2,UART Status Register 2"
|
|
bitfld.byte 0x00 6. "RXEDGIF,RxD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
bitfld.byte 0x00 5. "MSBF,Most Significant Bit First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit8 bit7 or bit6) is the first bit that.."
|
|
newline
|
|
bitfld.byte 0x00 4. "RXINV,Receive Data Inversion" "0: Receive data is not inverted,1: Receive data is inverted"
|
|
bitfld.byte 0x00 3. "RWUID,Receive Wakeup Idle Detect" "0: S1[IDLE] is not set upon detection of an idle..,1: S1[IDLE] is set upon detection of an idle.."
|
|
newline
|
|
bitfld.byte 0x00 2. "BRK13,Break Transmit Character Length" "0: Break character is 10 11 or 12 bits long,1: Break character is 13 or 14 bits long"
|
|
rbitfld.byte 0x00 0. "RAF,Receiver Active Flag" "0: UART receiver idle/inactive waiting for a..,1: UART receiver active RxD input not idle"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. "R8,Received Bit 8" "0,1"
|
|
bitfld.byte 0x00 6. "T8,Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "TXDIR,Transmitter Pin Data Direction in Single-Wire mode" "0: TXD pin is an input in single wire mode,1: TXD pin is an output in single wire mode"
|
|
bitfld.byte 0x00 4. "TXINV,Transmit Data Inversion" "0: Transmit data is not inverted,1: Transmit data is inverted"
|
|
newline
|
|
bitfld.byte 0x00 3. "ORIE,Overrun Error Interrupt Enable" "0: OR interrupts are disabled,1: OR interrupt requests are enabled"
|
|
bitfld.byte 0x00 2. "NEIE,Noise Error Interrupt Enable" "0: NF interrupt requests are disabled,1: NF interrupt requests are enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. "FEIE,Framing Error Interrupt Enable" "0: FE interrupt requests are disabled,1: FE interrupt requests are enabled"
|
|
bitfld.byte 0x00 0. "PEIE,Parity Error Interrupt Enable" "0: PF interrupt requests are disabled,1: PF interrupt requests are enabled"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "D,UART Data Register"
|
|
hexmask.byte 0x00 0.--7. 1. "RT,Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x1 )
|
|
group.byte ($2+0x08)++0x00
|
|
line.byte 0x00 "MA$1,UART Match Address Registers $1"
|
|
hexmask.byte 0x00 0.--7. 1. "MA,Match Address"
|
|
repeat.end
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "C4,UART Control Register 4"
|
|
bitfld.byte 0x00 7. "MAEN1,Match Address Mode Enable 1" "0: All data received is transferred to the data..,1: All data received with the most significant.."
|
|
bitfld.byte 0x00 6. "MAEN2,Match Address Mode Enable 2" "0: All data received is transferred to the data..,1: All data received with the most significant.."
|
|
newline
|
|
bitfld.byte 0x00 5. "M10,10-bit Mode select" "0: The parity bit is the ninth bit in the serial..,1: The parity bit is the tenth bit in the serial.."
|
|
bitfld.byte 0x00 0.--4. "BRFA,Baud Rate Fine Adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "C5,UART Control Register 5"
|
|
bitfld.byte 0x00 7. "TDMAS,Transmitter DMA Select" "0: If C2[TIE] is set and the S1[TDRE] flag is..,1: If C2[TIE] is set and the S1[TDRE] flag is.."
|
|
bitfld.byte 0x00 5. "RDMAS,Receiver Full DMA Select" "0: If C2[RIE] and S1[RDRF] are set the RDFR..,1: If C2[RIE] and S1[RDRF] are set the RDRF DMA.."
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "C7816,UART 7816 Control Register"
|
|
bitfld.byte 0x00 4. "ONACK,Generate NACK on Overflow" "0: The received data does not generate a NACK..,1: If the receiver buffer overflows a NACK is.."
|
|
bitfld.byte 0x00 3. "ANACK,Generate NACK on Error" "0: No NACK is automatically generated,1: A NACK is automatically generated if a parity.."
|
|
newline
|
|
bitfld.byte 0x00 2. "INIT,Detect Initial Character" "0: Normal operating mode,1: Receiver searches for initial character"
|
|
bitfld.byte 0x00 1. "TTYPE,Transfer Type" "0: T = 0 per the ISO-7816 specification,1: T = 1 per the ISO-7816 specification"
|
|
newline
|
|
bitfld.byte 0x00 0. "ISO_7816E,ISO-7816 Functionality Enabled" "0: ISO-7816 functionality is turned off/not..,1: ISO-7816 functionality is turned on/enabled"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "IE7816,UART 7816 Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. "WTE,Wait Timer Interrupt Enable" "0: The assertion of IS7816[WT] does not result..,1: The assertion of IS7816[WT] results in the.."
|
|
bitfld.byte 0x00 6. "CWTE,Character Wait Timer Interrupt Enable" "0: The assertion of IS7816[CWT] does not result..,1: The assertion of IS7816[CWT] results in the.."
|
|
newline
|
|
bitfld.byte 0x00 5. "BWTE,Block Wait Timer Interrupt Enable" "0: The assertion of IS7816[BWT] does not result..,1: The assertion of IS7816[BWT] results in the.."
|
|
bitfld.byte 0x00 4. "INITDE,Initial Character Detected Interrupt Enable" "0: The assertion of IS7816[INITD] does not..,1: The assertion of IS7816[INITD] results in the.."
|
|
newline
|
|
bitfld.byte 0x00 3. "ADTE,ATR Duration Timer Interrupt Enable" "0: The assertion of IS7816[ADT] does not result..,1: The assertion of IS7816[ADT] results in the.."
|
|
bitfld.byte 0x00 2. "GTVE,Guard Timer Violated Interrupt Enable" "0: The assertion of IS7816[GTV] does not result..,1: The assertion of IS7816[GTV] results in the.."
|
|
newline
|
|
bitfld.byte 0x00 1. "TXTE,Transmit Threshold Exceeded Interrupt Enable" "0: The assertion of IS7816[TXT] does not result..,1: The assertion of IS7816[TXT] results in the.."
|
|
bitfld.byte 0x00 0. "RXTE,Receive Threshold Exceeded Interrupt Enable" "0: The assertion of IS7816[RXT] does not result..,1: The assertion of IS7816[RXT] results in the.."
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "IS7816,UART 7816 Interrupt Status Register"
|
|
bitfld.byte 0x00 7. "WT,Wait Timer Interrupt" "0: Wait time (WT) has not been violated,1: Wait time (WT) has been violated"
|
|
bitfld.byte 0x00 6. "CWT,Character Wait Timer Interrupt" "0: Character wait time (CWT) has not been violated,1: Character wait time (CWT) has been violated"
|
|
newline
|
|
bitfld.byte 0x00 5. "BWT,Block Wait Timer Interrupt" "0: Block wait time (BWT) has not been violated,1: Block wait time (BWT) has been violated"
|
|
bitfld.byte 0x00 4. "INITD,Initial Character Detected Interrupt" "0: A valid initial character has not been received,1: A valid initial character has been received"
|
|
newline
|
|
bitfld.byte 0x00 3. "ADT,ATR Duration Time Interrupt" "0: ATR Duration time (ADT) has not been violated,1: ATR Duration time (ADT) has been violated"
|
|
bitfld.byte 0x00 2. "GTV,Guard Timer Violated Interrupt" "0: A guard time (GT CGT or BGT) has not been..,1: A guard time (GT CGT or BGT) has been violated"
|
|
newline
|
|
bitfld.byte 0x00 1. "TXT,Transmit Threshold Exceeded Interrupt" "0: The number of retries and corresponding NACKS..,1: The number of retries and corresponding NACKS.."
|
|
bitfld.byte 0x00 0. "RXT,Receive Threshold Exceeded Interrupt" "0: The number of consecutive NACKS generated as..,1: The number of consecutive NACKS generated as.."
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "WP7816,UART 7816 Wait Parameter Register"
|
|
hexmask.byte 0x00 0.--7. 1. "WTX,Wait Time Multiplier (C7816[TTYPE] = 1)"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "WN7816,UART 7816 Wait N Register"
|
|
hexmask.byte 0x00 0.--7. 1. "GTN,Guard Band N"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "WF7816,UART 7816 Wait FD Register"
|
|
hexmask.byte 0x00 0.--7. 1. "GTFD,FD Multiplier"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "ET7816,UART 7816 Error Threshold Register"
|
|
bitfld.byte 0x00 4.--7. "TXTHRESHOLD,Transmit NACK Threshold" "0: TXT asserts on the first NACK that is received,1: TXT asserts on the second NACK that is received,?..."
|
|
bitfld.byte 0x00 0.--3. "RXTHRESHOLD,Receive NACK Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "TL7816,UART 7816 Transmit Length Register"
|
|
hexmask.byte 0x00 0.--7. 1. "TLEN,Transmit Length"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "AP7816A_T0,UART 7816 ATR Duration Timer Register A"
|
|
hexmask.byte 0x00 0.--7. 1. "ADTI_H,ATR Duration Time Integer High (C7816[TTYPE] = 0)"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "AP7816B_T0,UART 7816 ATR Duration Timer Register B"
|
|
hexmask.byte 0x00 0.--7. 1. "ADTI_L,ATR Duration Time Integer Low (C7816[TTYPE] = 0)"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "WP7816A_T0,UART 7816 Wait Parameter Register A"
|
|
hexmask.byte 0x00 0.--7. 1. "WI_H,Wait Time Integer High (C7816[TTYPE] = 0)"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "WP7816A_T1,UART 7816 Wait Parameter Register A"
|
|
hexmask.byte 0x00 0.--7. 1. "BWI_H,Block Wait Time Integer High (C7816[TTYPE] = 1)"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "WP7816B_T0,UART 7816 Wait Parameter Register B"
|
|
hexmask.byte 0x00 0.--7. 1. "WI_L,Wait Time Integer Low (C7816[TTYPE] = 0)"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "WP7816B_T1,UART 7816 Wait Parameter Register B"
|
|
hexmask.byte 0x00 0.--7. 1. "BWI_L,Block Wait Time Integer Low (C7816[TTYPE] = 1)"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "WGP7816_T1,UART 7816 Wait and Guard Parameter Register"
|
|
bitfld.byte 0x00 4.--7. "CWI1,Character Wait Time Integer 1 (C7816[TTYPE] = 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "BGI,Block Guard Time Integer (C7816[TTYPE] = 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "WP7816C_T1,UART 7816 Wait Parameter Register C"
|
|
bitfld.byte 0x00 0.--4. "CWI2,Character Wait Time Integer 2 (C7816[TTYPE] = 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
tree "USB0 (Universal Serial Bus OTG Capable Controller)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40055000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40072000
|
|
endif
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "PERID,Peripheral ID register"
|
|
bitfld.byte 0x00 0.--5. "ID,Peripheral Identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement register"
|
|
bitfld.byte 0x00 0.--5. "NID,Ones' complement of PERID[ID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement register"
|
|
bitfld.byte 0x00 0.--5. "NID,Ones' complement of PERID[ID] bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "REV,Peripheral Revision register"
|
|
hexmask.byte 0x00 0.--7. 1. "REV,Revision"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "ADDINFO,Peripheral Additional Info register"
|
|
bitfld.byte 0x00 0. "IEHOST,This bit is set if host mode is enabled" "0,1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "OTGISTAT,OTG Interrupt Status register"
|
|
bitfld.byte 0x00 6. "ONEMSEC,This bit is set when the 1 millisecond timer expires" "0,1"
|
|
bitfld.byte 0x00 5. "LINE_STATE_CHG,This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond and the value of the line state is different from the last time when the line state was stable" "0,1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "OTGICR,OTG Interrupt Control register"
|
|
bitfld.byte 0x00 6. "ONEMSECEN,One Millisecond Interrupt Enable" "0: Diables the 1ms timer interrupt,1: Enables the 1ms timer interrupt"
|
|
bitfld.byte 0x00 5. "LINESTATEEN,Line State Change Interrupt Enable" "0: Disables the LINE_STAT_CHG interrupt,1: Enables the LINE_STAT_CHG interrupt"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "OTGSTAT,OTG Status register"
|
|
bitfld.byte 0x00 6. "ONEMSECEN,This bit is reserved for the 1ms count but it is not useful to software" "0,1"
|
|
bitfld.byte 0x00 5. "LINESTATESTABLE,Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 ms" "0: The LINE_STAT_CHG bit is not yet stable,1: The LINE_STAT_CHG bit has been debounced and.."
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "OTGCTL,OTG Control register"
|
|
bitfld.byte 0x00 7. "DPHIGH,D+ Data Line pullup resistor enable" "0: D+ pullup resistor is not enabled,1: D+ pullup resistor is enabled"
|
|
bitfld.byte 0x00 5. "DPLOW,D+ Data Line pull-down resistor enable" "0: D+ pulldown resistor is not enabled,1: D+ pulldown resistor is enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. "DMLOW,D- Data Line pull-down resistor enable" "0: D- pulldown resistor is not enabled,1: D- pulldown resistor is enabled"
|
|
bitfld.byte 0x00 2. "OTGEN,On-The-Go pullup/pulldown resistor enable" "0: If USB_EN is 1 and HOST_MODE is 0 in the..,1: The pull-up and pull-down controls in this.."
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status register"
|
|
bitfld.byte 0x00 7. "STALL,Stall Interrupt" "0,1"
|
|
bitfld.byte 0x00 6. "ATTACH,Attach Interrupt" "0: No Attach is detected since the last time the..,1: A peripheral is now present and must be.."
|
|
newline
|
|
bitfld.byte 0x00 5. "RESUME,This bit is set when a K-state is observed on the DP/DM signals for 2" "0,1"
|
|
bitfld.byte 0x00 4. "SLEEP,This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "TOKDNE,This bit is set when the current token being processed has completed" "0,1"
|
|
bitfld.byte 0x00 2. "SOFTOK,This bit is set when the USB Module receives a Start Of Frame (SOF) token" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ERROR,This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur" "0,1"
|
|
bitfld.byte 0x00 0. "USBRST,This bit is set when the USB Module has decoded a valid USB reset" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status register"
|
|
bitfld.byte 0x00 7. "STALL,Stall Interrupt" "0,1"
|
|
bitfld.byte 0x00 5. "RESUME,This bit is set when a K-state is observed on the DP/DM signals for 2" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "SLEEP,This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms" "0,1"
|
|
bitfld.byte 0x00 3. "TOKDNE,This bit is set when the current token being processed has completed" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "SOFTOK,This bit is set when the USB Module receives a Start Of Frame (SOF) token" "0,1"
|
|
bitfld.byte 0x00 1. "ERROR,This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "USBRST,This bit is set when the USB Module has decoded a valid USB reset" "0,1"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "STALLEN,STALL Interrupt Enable" "0: Diasbles the STALL interrupt,1: Enables the STALL interrupt"
|
|
bitfld.byte 0x00 5. "RESUMEEN,RESUME Interrupt Enable" "0: Disables the RESUME interrupt,1: Enables the RESUME interrupt"
|
|
newline
|
|
bitfld.byte 0x00 4. "SLEEPEN,SLEEP Interrupt Enable" "0: Disables the SLEEP interrupt,1: Enables the SLEEP interrupt"
|
|
bitfld.byte 0x00 3. "TOKDNEEN,TOKDNE Interrupt Enable" "0: Disables the TOKDNE interrupt,1: Enables the TOKDNE interrupt"
|
|
newline
|
|
bitfld.byte 0x00 2. "SOFTOKEN,SOFTOK Interrupt Enable" "0: Disbles the SOFTOK interrupt,1: Enables the SOFTOK interrupt"
|
|
bitfld.byte 0x00 1. "ERROREN,ERROR Interrupt Enable" "0: Disables the ERROR interrupt,1: Enables the ERROR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. "USBRSTEN,USBRST Interrupt Enable" "0: Disables the USBRST interrupt,1: Enables the USBRST interrupt"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "STALLEN,STALL Interrupt Enable" "0: Diasbles the STALL interrupt,1: Enables the STALL interrupt"
|
|
bitfld.byte 0x00 6. "ATTACHEN,ATTACH Interrupt Enable" "0: Disables the ATTACH interrupt,1: Enables the ATTACH interrupt"
|
|
newline
|
|
bitfld.byte 0x00 5. "RESUMEEN,RESUME Interrupt Enable" "0: Disables the RESUME interrupt,1: Enables the RESUME interrupt"
|
|
bitfld.byte 0x00 4. "SLEEPEN,SLEEP Interrupt Enable" "0: Disables the SLEEP interrupt,1: Enables the SLEEP interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. "TOKDNEEN,TOKDNE Interrupt Enable" "0: Disables the TOKDNE interrupt,1: Enables the TOKDNE interrupt"
|
|
bitfld.byte 0x00 2. "SOFTOKEN,SOFTOK Interrupt Enable" "0: Disbles the SOFTOK interrupt,1: Enables the SOFTOK interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. "ERROREN,ERROR Interrupt Enable" "0: Disables the ERROR interrupt,1: Enables the ERROR interrupt"
|
|
bitfld.byte 0x00 0. "USBRSTEN,USBRST Interrupt Enable" "0: Disables the USBRST interrupt,1: Enables the USBRST interrupt"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status register"
|
|
bitfld.byte 0x00 7. "BTSERR,This bit is set when a bit stuff error is detected" "0,1"
|
|
bitfld.byte 0x00 5. "DMAERR,This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "BTOERR,This bit is set when a bus turnaround timeout error occurs" "0,1"
|
|
bitfld.byte 0x00 3. "DFN8,This bit is set if the data field received was not 8 bits in length" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "CRC16,This bit is set when a data packet is rejected due to a CRC16 error" "0,1"
|
|
bitfld.byte 0x00 1. "CRC5,This error interrupt has two functions" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "PIDERR,This bit is set when the PID check field fails" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status register"
|
|
bitfld.byte 0x00 7. "BTSERR,This bit is set when a bit stuff error is detected" "0,1"
|
|
bitfld.byte 0x00 6. "OWNERR,This field is valid when the USB Module is operating in peripheral mode (CTL[HOSTMODEEN]=0)" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "DMAERR,This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data" "0,1"
|
|
bitfld.byte 0x00 4. "BTOERR,This bit is set when a bus turnaround timeout error occurs" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "DFN8,This bit is set if the data field received was not 8 bits in length" "0,1"
|
|
bitfld.byte 0x00 2. "CRC16,This bit is set when a data packet is rejected due to a CRC16 error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "CRC5EOF,This error interrupt has two functions" "0,1"
|
|
bitfld.byte 0x00 0. "PIDERR,This bit is set when the PID check field fails" "0,1"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "BTSERREN,BTSERR Interrupt Enable" "0: Disables the BTSERR interrupt,1: Enables the BTSERR interrupt"
|
|
bitfld.byte 0x00 6. "OWNERREN,OWNERR Interrupt Enable" "0: Disables the OWNERR interrupt,1: Enables the OWNERR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 5. "DMAERREN,DMAERR Interrupt Enable" "0: Disables the DMAERR interrupt,1: Enables the DMAERR interrupt"
|
|
bitfld.byte 0x00 4. "BTOERREN,BTOERR Interrupt Enable" "0: Disables the BTOERR interrupt,1: Enables the BTOERR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. "DFN8EN,DFN8 Interrupt Enable" "0: Disables the DFN8 interrupt,1: Enables the DFN8 interrupt"
|
|
bitfld.byte 0x00 2. "CRC16EN,CRC16 Interrupt Enable" "0: Disables the CRC16 interrupt,1: Enables the CRC16 interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. "CRC5EOFEN,CRC5/EOF Interrupt Enable" "0: Disables the CRC5/EOF interrupt,1: Enables the CRC5/EOF interrupt"
|
|
bitfld.byte 0x00 0. "PIDERREN,PIDERR Interrupt Enable" "0: Disables the PIDERR interrupt,1: Enters the PIDERR interrupt"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "BTSERREN,BTSERR Interrupt Enable" "0: Disables the BTSERR interrupt,1: Enables the BTSERR interrupt"
|
|
bitfld.byte 0x00 5. "DMAERREN,DMAERR Interrupt Enable" "0: Disables the DMAERR interrupt,1: Enables the DMAERR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 4. "BTOERREN,BTOERR Interrupt Enable" "0: Disables the BTOERR interrupt,1: Enables the BTOERR interrupt"
|
|
bitfld.byte 0x00 3. "DFN8EN,DFN8 Interrupt Enable" "0: Disables the DFN8 interrupt,1: Enables the DFN8 interrupt"
|
|
newline
|
|
bitfld.byte 0x00 2. "CRC16EN,CRC16 Interrupt Enable" "0: Disables the CRC16 interrupt,1: Enables the CRC16 interrupt"
|
|
bitfld.byte 0x00 1. "CRC5EOFEN,CRC5/EOF Interrupt Enable" "0: Disables the CRC5/EOF interrupt,1: Enables the CRC5/EOF interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. "PIDERREN,PIDERR Interrupt Enable" "0: Disables the PIDERR interrupt,1: Enters the PIDERR interrupt"
|
|
endif
|
|
rgroup.byte 0x90++0x00
|
|
line.byte 0x00 "STAT,Status register"
|
|
bitfld.byte 0x00 4.--7. "ENDP,This four-bit field encodes the endpoint address that received or transmitted the previous token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 3. "TX,Transmit Indicator" "0: The most recent transaction was a receive..,1: The most recent transaction was a transmit.."
|
|
newline
|
|
bitfld.byte 0x00 2. "ODD,This bit is set if the last buffer descriptor updated was in the odd bank of the BDT" "0,1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control register"
|
|
bitfld.byte 0x00 7. "JSTATE,Live USB differential receiver JSTATE signal" "0,1"
|
|
bitfld.byte 0x00 6. "SE0,Live USB Single Ended Zero signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "TXSUSPENDTOKENBUSY,In Host mode TOKEN_BUSY is set when the USB module is busy executing a USB token" "0,1"
|
|
bitfld.byte 0x00 4. "RESET,Setting this bit enables the USB Module to generate USB reset signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "HOSTMODEEN,When set to 1 this bit enables the USB Module to operate in Host mode" "0,1"
|
|
bitfld.byte 0x00 2. "RESUME,When set to 1 this bit enables the USB Module to execute resume signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ODDRST,Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0 which then specifies the EVEN BDT bank" "0,1"
|
|
bitfld.byte 0x00 0. "USBENSOFEN,USB Enable" "0: Disables the USB Module,1: Enables the USB Module"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control register"
|
|
bitfld.byte 0x00 7. "JSTATE,Live USB differential receiver JSTATE signal" "0,1"
|
|
bitfld.byte 0x00 6. "SE0,Live USB Single Ended Zero signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "TXSUSPENDTOKENBUSY,In Device mode TXD_SUSPEND is set when the SIE has disabled packet transmission and reception" "0,1"
|
|
bitfld.byte 0x00 2. "RESUME,When set to 1 this bit enables the USB Module to execute resume signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ODDRST,Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0 which then specifies the EVEN BDT bank" "0,1"
|
|
bitfld.byte 0x00 0. "USBENSOFEN,USB Enable" "0: Disables the USB Module,1: Enables the USB Module"
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address register"
|
|
hexmask.byte 0x00 0.--6. 1. "ADDR,USB Address"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address register"
|
|
bitfld.byte 0x00 7. "LSEN,Low Speed Enable bit" "0,1"
|
|
hexmask.byte 0x00 0.--6. 1. "ADDR,USB Address"
|
|
endif
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "BDTPAGE1,BDT Page register 1"
|
|
hexmask.byte 0x00 1.--7. 1. "BDTBA,Provides address bits 15 through 9 of the BDT base address"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "FRMNUML,Frame Number register Low"
|
|
hexmask.byte 0x00 0.--7. 1. "FRM,This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "FRMNUMH,Frame Number register High"
|
|
bitfld.byte 0x00 0.--2. "FRM,This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "TOKEN,Token register"
|
|
bitfld.byte 0x00 4.--7. "TOKENPID,Contains the token type executed by the USB module" "?,1: OUT Token,?,?,?,?,?,?,?,9: IN Token,?,?,?,13: SETUP Token,?..."
|
|
bitfld.byte 0x00 0.--3. "TOKENENDPT,Holds the Endpoint address for the token command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "SOFTHLD,SOF Threshold register"
|
|
hexmask.byte 0x00 0.--7. 1. "CNT,Represents the SOF count threshold in byte times when SOFDYNTHLD=0 or 8 byte times when SOFDYNTHLD=1"
|
|
endif
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "BDTPAGE2,BDT Page Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. "BDTBA,Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "BDTPAGE3,BDT Page Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. "BDTBA,Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.byte ($2+0xC0)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
group.byte ($2+0xC8)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "6" "7" )(list 0x0 0x4 )
|
|
group.byte ($2+0xD8)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
|
|
group.byte ($2+0xDC)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "9" "10" )(list 0x0 0x4 )
|
|
group.byte ($2+0xE4)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.byte ($2+0xE8)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "12" "13" )(list 0x0 0x4 )
|
|
group.byte ($2+0xF0)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control register"
|
|
bitfld.byte 0x00 7. "SUSP,Places the USB transceiver into the suspend state" "0: USB transceiver is not in suspend state,1: USB transceiver is in suspend state"
|
|
bitfld.byte 0x00 6. "PDE,Enables the weak pulldowns on the USB transceiver" "0: Weak pulldowns are disabled on D+ and D,1: Weak pulldowns are enabled on D+ and D"
|
|
newline
|
|
bitfld.byte 0x00 5. "UARTCHLS,UART Signal Channel Select" "0: USB DP/DM signals used as UART TX/RX,1: USB DP/DM signals used as UART RX/TX"
|
|
bitfld.byte 0x00 4. "UARTSEL,Selects USB signals to be used as UART signals" "0: USB signals not used as UART signals,1: USB signals used as UART signals"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control register"
|
|
bitfld.byte 0x00 7. "SUSP,Places the USB transceiver into the suspend state" "0: USB transceiver is not in suspend state,1: USB transceiver is in suspend state"
|
|
bitfld.byte 0x00 6. "PDE,Enables the weak pulldowns on the USB transceiver" "0: Weak pulldowns are disabled on D+ and D,1: Weak pulldowns are enabled on D+ and D"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe register"
|
|
bitfld.byte 0x00 7. "DPPU,Provides observability of the D+ Pullup enable at the USB transceiver" "0: D+ pullup disabled,1: D+ pullup enabled"
|
|
bitfld.byte 0x00 6. "DPPD,Provides observability of the D+ Pulldown enable at the USB transceiver" "0: D+ pulldown disabled,1: D+ pulldown enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. "DMPD,Provides observability of the D- Pulldown enable at the USB transceiver" "0: D- pulldown disabled,1: D- pulldown enabled"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe register"
|
|
bitfld.byte 0x00 7. "DPPU,Provides observability of the D+ Pullup signal output from USB" "0: D+ pullup disabled,1: D+ pullup enabled"
|
|
bitfld.byte 0x00 6. "DPPD,Provides observability of the D+ Pulldown signal output from USB" "0: D+ pulldown disabled,1: D+ pulldown enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. "DMPD,Provides observability of the D- Pulldown signal output from USB" "0: D- pulldown disabled,1: D- pulldown enabled"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control register"
|
|
bitfld.byte 0x00 4. "DPPULLUPNONOTG,Provides control of the DP Pullup in USB if USB is configured in non-OTG device mode" "0: DP Pullup in non-OTG device mode is not enabled,1: DP Pullup in non-OTG device mode is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control register"
|
|
bitfld.byte 0x00 4. "DPPULLUPNONOTG,Provides control of the DP Pullup in USBOTG if USB is configured in non-OTG device mode" "0: DP Pullup in non-OTG device mode is not enabled,1: DP Pullup in non-OTG device mode is enabled"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control register 0"
|
|
bitfld.byte 0x00 7. "USBRESET,USB Reset" "0: Normal USB module operation,1: Returns the USB module to its reset state"
|
|
bitfld.byte 0x00 5. "USBRESMEN,Asynchronous Resume Interrupt Enable" "0: USB asynchronous wakeup from suspend mode..,1: USB asynchronous wakeup from suspend mode.."
|
|
newline
|
|
rbitfld.byte 0x00 4. "VFEDG_DET,VREGIN Falling Edge Interrupt Detect" "0: VREGIN falling edge interrupt has not been..,1: VREGIN falling edge interrupt has been detected"
|
|
rbitfld.byte 0x00 3. "VREDG_DET,VREGIN Rising Edge Interrupt Detect" "0: VREGIN rising edge interrupt has not been..,1: VREGIN rising edge interrupt has been detected"
|
|
newline
|
|
rbitfld.byte 0x00 2. "USB_CLK_RECOVERY_INT,Combined USB Clock Recovery interrupt status" "0,1"
|
|
rbitfld.byte 0x00 1. "SYNC_DET,Synchronous USB Interrupt Detect" "0: Synchronous interrupt has not been detected,1: Synchronous interrupt has been detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "USB_RESUME_INT,USB Asynchronous Interrupt" "0: No interrupt was generated,1: Interrupt was generated because of the USB.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control register 0"
|
|
bitfld.byte 0x00 7. "USBRESET,USB Reset" "0: Normal USB module operation,1: Returns the USB module to its reset state"
|
|
bitfld.byte 0x00 5. "USBRESMEN,Asynchronous Resume Interrupt Enable" "0: USB asynchronous wakeup from suspend mode..,1: USB asynchronous wakeup from suspend mode.."
|
|
newline
|
|
rbitfld.byte 0x00 2. "USB_CLK_RECOVERY_INT,Combined USB Clock Recovery interrupt status" "0,1"
|
|
rbitfld.byte 0x00 1. "SYNC_DET,Synchronous USB Interrupt Detect" "0: Synchronous interrupt has not been detected,1: Synchronous interrupt has been detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "USB_RESUME_INT,USB Asynchronous Interrupt" "0: No interrupt was generated,1: Interrupt was generated because of the USB.."
|
|
endif
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
hexmask.byte 0x00 0.--7. 1. "ADJ,Frame Adjustment"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control register"
|
|
bitfld.byte 0x00 4. "VFEDG_EN,VREGIN Falling Edge Interrupt Enable" "0: VREGIN falling edge interrupt disabled,1: VREGIN falling edge interrupt enabled"
|
|
bitfld.byte 0x00 3. "VREDG_EN,VREGIN Rising Edge Interrupt Enable" "0: VREGIN rising edge interrupt disabled,1: VREGIN rising edge interrupt enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. "OWNERRISODIS,OWN Error Detect for ISO IN / ISO OUT Disable" "0: OWN error detect for ISO IN / ISO OUT is not..,1: OWN error detect for ISO IN / ISO OUT is.."
|
|
bitfld.byte 0x00 1. "SOFBUSSET,SOF_TOK Interrupt Generation Mode Select" "0: SOF_TOK interrupt is set according to SOF..,1: SOF_TOK interrupt is set when SOF counter.."
|
|
newline
|
|
bitfld.byte 0x00 0. "SOFDYNTHLD,Dynamic SOF Threshold Compare mode" "0: SOF_TOK interrupt is set when byte times SOF..,1: SOF_TOK interrupt is set when 8 byte times.."
|
|
endif
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock recovery control"
|
|
bitfld.byte 0x00 7. "CLOCK_RECOVER_EN,Crystal-less USB enable" "0: Disable clock recovery block (default),1: Enable clock recovery block"
|
|
bitfld.byte 0x00 6. "RESET_RESUME_ROUGH_EN,Reset/resume to rough phase enable" "0: Always works in tracking phase after the..,1: Go back to rough stage whenever bus reset or.."
|
|
newline
|
|
bitfld.byte 0x00 5. "RESTART_IFRTRIM_EN,Restart from IFR trim value" "0: Trim fine adjustment always works based on..,1: Trim fine restarts from the IFR trim value.."
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M oscillator enable register"
|
|
bitfld.byte 0x00 1. "IRC_EN,IRC48M enable" "0: Disable the IRC48M module (default),1: Enable the IRC48M module"
|
|
endif
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_EN,Clock recovery combined interrupt enable"
|
|
bitfld.byte 0x00 4. "OVF_ERROR_EN,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "0: The interrupt will be masked,1: The interrupt will be enabled (default)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock recovery separated interrupt status"
|
|
bitfld.byte 0x00 4. "OVF_ERROR,Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the FIRC output clock is outside the available TRIM_FINE adjustment range for the FIRC module" "0: No interrupt is reported,1: Unmasked interrupt has been generated"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock recovery separated interrupt status"
|
|
bitfld.byte 0x00 4. "OVF_ERROR,Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M module" "0: No interrupt is reported,1: Unmasked interrupt has been generated"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "USBFSOTG (USB)"
|
|
base ad:0x40045000
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "PERID,Peripheral ID register"
|
|
bitfld.byte 0x00 0.--5. "ID,Peripheral Identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement register"
|
|
bitfld.byte 0x00 0.--5. "NID,Ones' complement of PERID[ID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "IDCOMP,Peripheral ID Complement register"
|
|
bitfld.byte 0x00 0.--5. "NID,Ones' complement of PERID[ID] bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "REV,Peripheral Revision register"
|
|
hexmask.byte 0x00 0.--7. 1. "REV,Revision"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "ADDINFO,Peripheral Additional Info register"
|
|
bitfld.byte 0x00 0. "IEHOST,This bit is set if host mode is enabled" "0,1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "OTGISTAT,OTG Interrupt Status register"
|
|
bitfld.byte 0x00 6. "ONEMSEC,This bit is set when the 1 millisecond timer expires" "0,1"
|
|
bitfld.byte 0x00 5. "LINE_STATE_CHG,This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond and the value of the line state is different from the last time when the line state was stable" "0,1"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "OTGICR,OTG Interrupt Control register"
|
|
bitfld.byte 0x00 6. "ONEMSECEN,One Millisecond Interrupt Enable" "0: Diables the 1ms timer interrupt,1: Enables the 1ms timer interrupt"
|
|
bitfld.byte 0x00 5. "LINESTATEEN,Line State Change Interrupt Enable" "0: Disables the LINE_STAT_CHG interrupt,1: Enables the LINE_STAT_CHG interrupt"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "OTGSTAT,OTG Status register"
|
|
bitfld.byte 0x00 6. "ONEMSECEN,This bit is reserved for the 1ms count but it is not useful to software" "0,1"
|
|
bitfld.byte 0x00 5. "LINESTATESTABLE,Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 ms" "0: The LINE_STAT_CHG bit is not yet stable,1: The LINE_STAT_CHG bit has been debounced and.."
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "OTGCTL,OTG Control register"
|
|
bitfld.byte 0x00 7. "DPHIGH,D+ Data Line pullup resistor enable" "0: D+ pullup resistor is not enabled,1: D+ pullup resistor is enabled"
|
|
bitfld.byte 0x00 5. "DPLOW,D+ Data Line pull-down resistor enable" "0: D+ pulldown resistor is not enabled,1: D+ pulldown resistor is enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. "DMLOW,D- Data Line pull-down resistor enable" "0: D- pulldown resistor is not enabled,1: D- pulldown resistor is enabled"
|
|
bitfld.byte 0x00 2. "OTGEN,On-The-Go pullup/pulldown resistor enable" "0: If USB_EN is 1 and HOST_MODE is 0 in the..,1: The pull-up and pull-down controls in this.."
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status register"
|
|
bitfld.byte 0x00 7. "STALL,Stall Interrupt" "0,1"
|
|
bitfld.byte 0x00 6. "ATTACH,Attach Interrupt" "0: No Attach is detected since the last time the..,1: A peripheral is now present and must be.."
|
|
newline
|
|
bitfld.byte 0x00 5. "RESUME,This bit is set when a K-state is observed on the DP/DM signals for 2" "0,1"
|
|
bitfld.byte 0x00 4. "SLEEP,This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "TOKDNE,This bit is set when the current token being processed has completed" "0,1"
|
|
bitfld.byte 0x00 2. "SOFTOK,This bit is set when the USB Module receives a Start Of Frame (SOF) token" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ERROR,This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur" "0,1"
|
|
bitfld.byte 0x00 0. "USBRST,This bit is set when the USB Module has decoded a valid USB reset" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "ISTAT,Interrupt Status register"
|
|
bitfld.byte 0x00 7. "STALL,Stall Interrupt" "0,1"
|
|
bitfld.byte 0x00 5. "RESUME,This bit is set when a K-state is observed on the DP/DM signals for 2" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "SLEEP,This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms" "0,1"
|
|
bitfld.byte 0x00 3. "TOKDNE,This bit is set when the current token being processed has completed" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "SOFTOK,This bit is set when the USB Module receives a Start Of Frame (SOF) token" "0,1"
|
|
bitfld.byte 0x00 1. "ERROR,This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "USBRST,This bit is set when the USB Module has decoded a valid USB reset" "0,1"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "STALLEN,STALL Interrupt Enable" "0: Diasbles the STALL interrupt,1: Enables the STALL interrupt"
|
|
bitfld.byte 0x00 5. "RESUMEEN,RESUME Interrupt Enable" "0: Disables the RESUME interrupt,1: Enables the RESUME interrupt"
|
|
newline
|
|
bitfld.byte 0x00 4. "SLEEPEN,SLEEP Interrupt Enable" "0: Disables the SLEEP interrupt,1: Enables the SLEEP interrupt"
|
|
bitfld.byte 0x00 3. "TOKDNEEN,TOKDNE Interrupt Enable" "0: Disables the TOKDNE interrupt,1: Enables the TOKDNE interrupt"
|
|
newline
|
|
bitfld.byte 0x00 2. "SOFTOKEN,SOFTOK Interrupt Enable" "0: Disbles the SOFTOK interrupt,1: Enables the SOFTOK interrupt"
|
|
bitfld.byte 0x00 1. "ERROREN,ERROR Interrupt Enable" "0: Disables the ERROR interrupt,1: Enables the ERROR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. "USBRSTEN,USBRST Interrupt Enable" "0: Disables the USBRST interrupt,1: Enables the USBRST interrupt"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "INTEN,Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "STALLEN,STALL Interrupt Enable" "0: Diasbles the STALL interrupt,1: Enables the STALL interrupt"
|
|
bitfld.byte 0x00 6. "ATTACHEN,ATTACH Interrupt Enable" "0: Disables the ATTACH interrupt,1: Enables the ATTACH interrupt"
|
|
newline
|
|
bitfld.byte 0x00 5. "RESUMEEN,RESUME Interrupt Enable" "0: Disables the RESUME interrupt,1: Enables the RESUME interrupt"
|
|
bitfld.byte 0x00 4. "SLEEPEN,SLEEP Interrupt Enable" "0: Disables the SLEEP interrupt,1: Enables the SLEEP interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. "TOKDNEEN,TOKDNE Interrupt Enable" "0: Disables the TOKDNE interrupt,1: Enables the TOKDNE interrupt"
|
|
bitfld.byte 0x00 2. "SOFTOKEN,SOFTOK Interrupt Enable" "0: Disbles the SOFTOK interrupt,1: Enables the SOFTOK interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. "ERROREN,ERROR Interrupt Enable" "0: Disables the ERROR interrupt,1: Enables the ERROR interrupt"
|
|
bitfld.byte 0x00 0. "USBRSTEN,USBRST Interrupt Enable" "0: Disables the USBRST interrupt,1: Enables the USBRST interrupt"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status register"
|
|
bitfld.byte 0x00 7. "BTSERR,This bit is set when a bit stuff error is detected" "0,1"
|
|
bitfld.byte 0x00 5. "DMAERR,This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "BTOERR,This bit is set when a bus turnaround timeout error occurs" "0,1"
|
|
bitfld.byte 0x00 3. "DFN8,This bit is set if the data field received was not 8 bits in length" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "CRC16,This bit is set when a data packet is rejected due to a CRC16 error" "0,1"
|
|
bitfld.byte 0x00 1. "CRC5,This error interrupt has two functions" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "PIDERR,This bit is set when the PID check field fails" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "ERRSTAT,Error Interrupt Status register"
|
|
bitfld.byte 0x00 7. "BTSERR,This bit is set when a bit stuff error is detected" "0,1"
|
|
bitfld.byte 0x00 6. "OWNERR,This field is valid when the USB Module is operating in peripheral mode (CTL[HOSTMODEEN]=0)" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "DMAERR,This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data" "0,1"
|
|
bitfld.byte 0x00 4. "BTOERR,This bit is set when a bus turnaround timeout error occurs" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "DFN8,This bit is set if the data field received was not 8 bits in length" "0,1"
|
|
bitfld.byte 0x00 2. "CRC16,This bit is set when a data packet is rejected due to a CRC16 error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "CRC5EOF,This error interrupt has two functions" "0,1"
|
|
bitfld.byte 0x00 0. "PIDERR,This bit is set when the PID check field fails" "0,1"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "BTSERREN,BTSERR Interrupt Enable" "0: Disables the BTSERR interrupt,1: Enables the BTSERR interrupt"
|
|
bitfld.byte 0x00 6. "OWNERREN,OWNERR Interrupt Enable" "0: Disables the OWNERR interrupt,1: Enables the OWNERR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 5. "DMAERREN,DMAERR Interrupt Enable" "0: Disables the DMAERR interrupt,1: Enables the DMAERR interrupt"
|
|
bitfld.byte 0x00 4. "BTOERREN,BTOERR Interrupt Enable" "0: Disables the BTOERR interrupt,1: Enables the BTOERR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 3. "DFN8EN,DFN8 Interrupt Enable" "0: Disables the DFN8 interrupt,1: Enables the DFN8 interrupt"
|
|
bitfld.byte 0x00 2. "CRC16EN,CRC16 Interrupt Enable" "0: Disables the CRC16 interrupt,1: Enables the CRC16 interrupt"
|
|
newline
|
|
bitfld.byte 0x00 1. "CRC5EOFEN,CRC5/EOF Interrupt Enable" "0: Disables the CRC5/EOF interrupt,1: Enables the CRC5/EOF interrupt"
|
|
bitfld.byte 0x00 0. "PIDERREN,PIDERR Interrupt Enable" "0: Disables the PIDERR interrupt,1: Enters the PIDERR interrupt"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "ERREN,Error Interrupt Enable register"
|
|
bitfld.byte 0x00 7. "BTSERREN,BTSERR Interrupt Enable" "0: Disables the BTSERR interrupt,1: Enables the BTSERR interrupt"
|
|
bitfld.byte 0x00 5. "DMAERREN,DMAERR Interrupt Enable" "0: Disables the DMAERR interrupt,1: Enables the DMAERR interrupt"
|
|
newline
|
|
bitfld.byte 0x00 4. "BTOERREN,BTOERR Interrupt Enable" "0: Disables the BTOERR interrupt,1: Enables the BTOERR interrupt"
|
|
bitfld.byte 0x00 3. "DFN8EN,DFN8 Interrupt Enable" "0: Disables the DFN8 interrupt,1: Enables the DFN8 interrupt"
|
|
newline
|
|
bitfld.byte 0x00 2. "CRC16EN,CRC16 Interrupt Enable" "0: Disables the CRC16 interrupt,1: Enables the CRC16 interrupt"
|
|
bitfld.byte 0x00 1. "CRC5EOFEN,CRC5/EOF Interrupt Enable" "0: Disables the CRC5/EOF interrupt,1: Enables the CRC5/EOF interrupt"
|
|
newline
|
|
bitfld.byte 0x00 0. "PIDERREN,PIDERR Interrupt Enable" "0: Disables the PIDERR interrupt,1: Enters the PIDERR interrupt"
|
|
endif
|
|
rgroup.byte 0x90++0x00
|
|
line.byte 0x00 "STAT,Status register"
|
|
bitfld.byte 0x00 4.--7. "ENDP,This four-bit field encodes the endpoint address that received or transmitted the previous token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 3. "TX,Transmit Indicator" "0: The most recent transaction was a receive..,1: The most recent transaction was a transmit.."
|
|
newline
|
|
bitfld.byte 0x00 2. "ODD,This bit is set if the last buffer descriptor updated was in the odd bank of the BDT" "0,1"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control register"
|
|
bitfld.byte 0x00 7. "JSTATE,Live USB differential receiver JSTATE signal" "0,1"
|
|
bitfld.byte 0x00 6. "SE0,Live USB Single Ended Zero signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "TXSUSPENDTOKENBUSY,In Host mode TOKEN_BUSY is set when the USB module is busy executing a USB token" "0,1"
|
|
bitfld.byte 0x00 4. "RESET,Setting this bit enables the USB Module to generate USB reset signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "HOSTMODEEN,When set to 1 this bit enables the USB Module to operate in Host mode" "0,1"
|
|
bitfld.byte 0x00 2. "RESUME,When set to 1 this bit enables the USB Module to execute resume signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ODDRST,Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0 which then specifies the EVEN BDT bank" "0,1"
|
|
bitfld.byte 0x00 0. "USBENSOFEN,USB Enable" "0: Disables the USB Module,1: Enables the USB Module"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "CTL,Control register"
|
|
bitfld.byte 0x00 7. "JSTATE,Live USB differential receiver JSTATE signal" "0,1"
|
|
bitfld.byte 0x00 6. "SE0,Live USB Single Ended Zero signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "TXSUSPENDTOKENBUSY,In Device mode TXD_SUSPEND is set when the SIE has disabled packet transmission and reception" "0,1"
|
|
bitfld.byte 0x00 2. "RESUME,When set to 1 this bit enables the USB Module to execute resume signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ODDRST,Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0 which then specifies the EVEN BDT bank" "0,1"
|
|
bitfld.byte 0x00 0. "USBENSOFEN,USB Enable" "0: Disables the USB Module,1: Enables the USB Module"
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address register"
|
|
hexmask.byte 0x00 0.--6. 1. "ADDR,USB Address"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "ADDR,Address register"
|
|
bitfld.byte 0x00 7. "LSEN,Low Speed Enable bit" "0,1"
|
|
hexmask.byte 0x00 0.--6. 1. "ADDR,USB Address"
|
|
endif
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "BDTPAGE1,BDT Page register 1"
|
|
hexmask.byte 0x00 1.--7. 1. "BDTBA,Provides address bits 15 through 9 of the BDT base address"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "FRMNUML,Frame Number register Low"
|
|
hexmask.byte 0x00 0.--7. 1. "FRM,This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "FRMNUMH,Frame Number register High"
|
|
bitfld.byte 0x00 0.--2. "FRM,This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "TOKEN,Token register"
|
|
bitfld.byte 0x00 4.--7. "TOKENPID,Contains the token type executed by the USB module" "?,1: OUT Token,?,?,?,?,?,?,?,9: IN Token,?,?,?,13: SETUP Token,?..."
|
|
bitfld.byte 0x00 0.--3. "TOKENENDPT,Holds the Endpoint address for the token command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "SOFTHLD,SOF Threshold register"
|
|
hexmask.byte 0x00 0.--7. 1. "CNT,Represents the SOF count threshold in byte times when SOFDYNTHLD=0 or 8 byte times when SOFDYNTHLD=1"
|
|
endif
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "BDTPAGE2,BDT Page Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. "BDTBA,Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "BDTPAGE3,BDT Page Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. "BDTBA,Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory"
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "ENDPT0,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.byte ($2+0xC0)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "ENDPT1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "ENDPT2,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
|
|
group.byte ($2+0xC8)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "ENDPT3,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ENDPT4,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ENDPT5,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ENDPT6,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "6" "7" )(list 0x0 0x4 )
|
|
group.byte ($2+0xD8)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
|
|
group.byte ($2+0xDC)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ENDPT8,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ENDPT9,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "9" "10" )(list 0x0 0x4 )
|
|
group.byte ($2+0xE4)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
repeat 2. (strings "10" "11" )(list 0x0 0x4 )
|
|
group.byte ($2+0xE8)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ENDPT11,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "ENDPT12,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
repeat 2. (strings "12" "13" )(list 0x0 0x4 )
|
|
group.byte ($2+0xF0)++0x00
|
|
line.byte 0x00 "ENDPT$1,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "ENDPT13,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "ENDPT14,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control register"
|
|
bitfld.byte 0x00 7. "HOSTWOHUB,Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only" "0: Low-speed device connected to Host through a..,1: Low-speed device directly connected"
|
|
bitfld.byte 0x00 6. "RETRYDIS,This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "ENDPT15,Endpoint Control register"
|
|
bitfld.byte 0x00 4. "EPCTLDIS,This bit when set disables control (SETUP) transfers" "0,1"
|
|
bitfld.byte 0x00 3. "EPRXEN,This bit when set enables the endpoint for RX transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "EPTXEN,This bit when set enables the endpoint for TX transfers" "0,1"
|
|
bitfld.byte 0x00 1. "EPSTALL,When set this bit indicates that the endpoint is stalled" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EPHSHK,When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint" "0,1"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control register"
|
|
bitfld.byte 0x00 7. "SUSP,Places the USB transceiver into the suspend state" "0: USB transceiver is not in suspend state,1: USB transceiver is in suspend state"
|
|
bitfld.byte 0x00 6. "PDE,Enables the weak pulldowns on the USB transceiver" "0: Weak pulldowns are disabled on D+ and D,1: Weak pulldowns are enabled on D+ and D"
|
|
newline
|
|
bitfld.byte 0x00 5. "UARTCHLS,UART Signal Channel Select" "0: USB DP/DM signals used as UART TX/RX,1: USB DP/DM signals used as UART RX/TX"
|
|
bitfld.byte 0x00 4. "UARTSEL,Selects USB signals to be used as UART signals" "0: USB signals not used as UART signals,1: USB signals used as UART signals"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "USBCTRL,USB Control register"
|
|
bitfld.byte 0x00 7. "SUSP,Places the USB transceiver into the suspend state" "0: USB transceiver is not in suspend state,1: USB transceiver is in suspend state"
|
|
bitfld.byte 0x00 6. "PDE,Enables the weak pulldowns on the USB transceiver" "0: Weak pulldowns are disabled on D+ and D,1: Weak pulldowns are enabled on D+ and D"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe register"
|
|
bitfld.byte 0x00 7. "DPPU,Provides observability of the D+ Pullup enable at the USB transceiver" "0: D+ pullup disabled,1: D+ pullup enabled"
|
|
bitfld.byte 0x00 6. "DPPD,Provides observability of the D+ Pulldown enable at the USB transceiver" "0: D+ pulldown disabled,1: D+ pulldown enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. "DMPD,Provides observability of the D- Pulldown enable at the USB transceiver" "0: D- pulldown disabled,1: D- pulldown enabled"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
rgroup.byte 0x104++0x00
|
|
line.byte 0x00 "OBSERVE,USB OTG Observe register"
|
|
bitfld.byte 0x00 7. "DPPU,Provides observability of the D+ Pullup signal output from USB" "0: D+ pullup disabled,1: D+ pullup enabled"
|
|
bitfld.byte 0x00 6. "DPPD,Provides observability of the D+ Pulldown signal output from USB" "0: D+ pulldown disabled,1: D+ pulldown enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. "DMPD,Provides observability of the D- Pulldown signal output from USB" "0: D- pulldown disabled,1: D- pulldown enabled"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control register"
|
|
bitfld.byte 0x00 4. "DPPULLUPNONOTG,Provides control of the DP Pullup in USB if USB is configured in non-OTG device mode" "0: DP Pullup in non-OTG device mode is not enabled,1: DP Pullup in non-OTG device mode is enabled"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "CONTROL,USB OTG Control register"
|
|
bitfld.byte 0x00 4. "DPPULLUPNONOTG,Provides control of the DP Pullup in USBOTG if USB is configured in non-OTG device mode" "0: DP Pullup in non-OTG device mode is not enabled,1: DP Pullup in non-OTG device mode is enabled"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control register 0"
|
|
bitfld.byte 0x00 7. "USBRESET,USB Reset" "0: Normal USB module operation,1: Returns the USB module to its reset state"
|
|
bitfld.byte 0x00 5. "USBRESMEN,Asynchronous Resume Interrupt Enable" "0: USB asynchronous wakeup from suspend mode..,1: USB asynchronous wakeup from suspend mode.."
|
|
newline
|
|
rbitfld.byte 0x00 4. "VFEDG_DET,VREGIN Falling Edge Interrupt Detect" "0: VREGIN falling edge interrupt has not been..,1: VREGIN falling edge interrupt has been detected"
|
|
rbitfld.byte 0x00 3. "VREDG_DET,VREGIN Rising Edge Interrupt Detect" "0: VREGIN rising edge interrupt has not been..,1: VREGIN rising edge interrupt has been detected"
|
|
newline
|
|
rbitfld.byte 0x00 2. "USB_CLK_RECOVERY_INT,Combined USB Clock Recovery interrupt status" "0,1"
|
|
rbitfld.byte 0x00 1. "SYNC_DET,Synchronous USB Interrupt Detect" "0: Synchronous interrupt has not been detected,1: Synchronous interrupt has been detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "USB_RESUME_INT,USB Asynchronous Interrupt" "0: No interrupt was generated,1: Interrupt was generated because of the USB.."
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "USBTRC0,USB Transceiver Control register 0"
|
|
bitfld.byte 0x00 7. "USBRESET,USB Reset" "0: Normal USB module operation,1: Returns the USB module to its reset state"
|
|
bitfld.byte 0x00 5. "USBRESMEN,Asynchronous Resume Interrupt Enable" "0: USB asynchronous wakeup from suspend mode..,1: USB asynchronous wakeup from suspend mode.."
|
|
newline
|
|
rbitfld.byte 0x00 2. "USB_CLK_RECOVERY_INT,Combined USB Clock Recovery interrupt status" "0,1"
|
|
rbitfld.byte 0x00 1. "SYNC_DET,Synchronous USB Interrupt Detect" "0: Synchronous interrupt has not been detected,1: Synchronous interrupt has been detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "USB_RESUME_INT,USB Asynchronous Interrupt" "0: No interrupt was generated,1: Interrupt was generated because of the USB.."
|
|
endif
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "USBFRMADJUST,Frame Adjust Register"
|
|
hexmask.byte 0x00 0.--7. 1. "ADJ,Frame Adjustment"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "MISCCTRL,Miscellaneous Control register"
|
|
bitfld.byte 0x00 4. "VFEDG_EN,VREGIN Falling Edge Interrupt Enable" "0: VREGIN falling edge interrupt disabled,1: VREGIN falling edge interrupt enabled"
|
|
bitfld.byte 0x00 3. "VREDG_EN,VREGIN Rising Edge Interrupt Enable" "0: VREGIN rising edge interrupt disabled,1: VREGIN rising edge interrupt enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. "OWNERRISODIS,OWN Error Detect for ISO IN / ISO OUT Disable" "0: OWN error detect for ISO IN / ISO OUT is not..,1: OWN error detect for ISO IN / ISO OUT is.."
|
|
bitfld.byte 0x00 1. "SOFBUSSET,SOF_TOK Interrupt Generation Mode Select" "0: SOF_TOK interrupt is set according to SOF..,1: SOF_TOK interrupt is set when SOF counter.."
|
|
newline
|
|
bitfld.byte 0x00 0. "SOFDYNTHLD,Dynamic SOF Threshold Compare mode" "0: SOF_TOK interrupt is set when byte times SOF..,1: SOF_TOK interrupt is set when 8 byte times.."
|
|
endif
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock recovery control"
|
|
bitfld.byte 0x00 7. "CLOCK_RECOVER_EN,Crystal-less USB enable" "0: Disable clock recovery block (default),1: Enable clock recovery block"
|
|
bitfld.byte 0x00 6. "RESET_RESUME_ROUGH_EN,Reset/resume to rough phase enable" "0: Always works in tracking phase after the..,1: Go back to rough stage whenever bus reset or.."
|
|
newline
|
|
bitfld.byte 0x00 5. "RESTART_IFRTRIM_EN,Restart from IFR trim value" "0: Trim fine adjustment always works based on..,1: Trim fine restarts from the IFR trim value.."
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M oscillator enable register"
|
|
bitfld.byte 0x00 1. "IRC_EN,IRC48M enable" "0: Disable the IRC48M module (default),1: Enable the IRC48M module"
|
|
endif
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_EN,Clock recovery combined interrupt enable"
|
|
bitfld.byte 0x00 4. "OVF_ERROR_EN,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "0: The interrupt will be masked,1: The interrupt will be enabled (default)"
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock recovery separated interrupt status"
|
|
bitfld.byte 0x00 4. "OVF_ERROR,Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the FIRC output clock is outside the available TRIM_FINE adjustment range for the FIRC module" "0: No interrupt is reported,1: Unmasked interrupt has been generated"
|
|
endif
|
|
sif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock recovery separated interrupt status"
|
|
bitfld.byte 0x00 4. "OVF_ERROR,Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M module" "0: No interrupt is reported,1: Unmasked interrupt has been generated"
|
|
endif
|
|
tree.end
|
|
tree "USBVREG"
|
|
base ad:0x40027000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,USB VREG Control Register"
|
|
bitfld.long 0x00 31. "EN,USB Voltage Regulator Enable" "0: USB voltage regulator is disabled,1: USB voltage regulator is enabled"
|
|
bitfld.long 0x00 30. "SSTBY,USB Voltage Regulator in Standby Mode during Stop VLPS LLS and VLLS Modes" "0: USB voltage regulator is not in standby..,1: USB voltage regulator is in standby during.."
|
|
newline
|
|
bitfld.long 0x00 29. "VSTBY,USB Voltage Regulator in Standby Mode during VLPR and VLPW modes" "0: USB voltage regulator is not in standby..,1: USB voltage regulator in standby during VLPR.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFGCTRL,USB VREG Configuration Control Register"
|
|
bitfld.long 0x00 26. "USSWE,USB Voltage Rregulator Stop Standby Write Enable" "0: CTRL[SSTBY] field cannot be written,1: CTRL[SSTBY] can be written"
|
|
bitfld.long 0x00 25. "UVSWE,USB Voltage Regulator VLP Standby Write Enable" "0: CTRL[VSTBY] cannot be written,1: CTRL[VSTBY] can be written"
|
|
newline
|
|
bitfld.long 0x00 24. "URWE,USB Voltage Regulator Enable Write Enable" "0: CTRL[EN] can not be written,1: CTRL[EN] can be written"
|
|
tree.end
|
|
tree "USDHC (Ultra Secured Digital Host Controller)"
|
|
base ad:0x4003E000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DS_ADDR,DMA System Address"
|
|
hexmask.long 0x00 0.--31. 1. "DS_ADDR,DS_ADDR"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BLK_ATT,Block Attributes"
|
|
hexmask.long.word 0x00 16.--31. 1. "BLKCNT,Block Count"
|
|
hexmask.long.word 0x00 0.--12. 1. "BLKSIZE,Block Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD_ARG,Command Argument"
|
|
hexmask.long 0x00 0.--31. 1. "CMDARG,Command Argument"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
|
|
bitfld.long 0x00 24.--29. "CMDINX,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. "CMDTYP,Command Type" "0: Normal Other commands,1: Suspend CMD52 for writing Bus Suspend in CCCR,2: Resume CMD52 for writing Function Select in..,3: Abort CMD12 CMD52 for writing I/O Abort in CCCR"
|
|
newline
|
|
bitfld.long 0x00 21. "DPSEL,Data Present Select" "0: No Data Present,1: Data Present"
|
|
bitfld.long 0x00 20. "CICEN,Command Index Check Enable" "0: CICEN_0,1: CICEN_1"
|
|
newline
|
|
bitfld.long 0x00 19. "CCCEN,Command CRC Check Enable" "0: CCCEN_0,1: CCCEN_1"
|
|
bitfld.long 0x00 16.--17. "RSPTYP,Response Type Select" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 check Busy after response"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CMD_RSP0,Command Response0"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP0,Command Response 0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CMD_RSP1,Command Response1"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP1,Command Response 1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CMD_RSP2,Command Response2"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CMD_RSP3,Command Response3"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP3,Command Response 3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
|
|
hexmask.long 0x00 0.--31. 1. "DATCONT,Data Content"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PRES_STATE,Present State"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DLSL,DATA[7:0] Line Signal Level"
|
|
bitfld.long 0x00 23. "CLSL,CMD Line Signal Level" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "WPSPL,Write Protect Switch Pin Level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
|
|
bitfld.long 0x00 18. "CDPL,Card Detect Pin Level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
|
|
newline
|
|
bitfld.long 0x00 16. "CINST,Card Inserted" "0: Power on Reset or No Card,1: Card Inserted"
|
|
bitfld.long 0x00 11. "BREN,Buffer Read Enable" "0: Read disable,1: Read enable"
|
|
newline
|
|
bitfld.long 0x00 10. "BWEN,Buffer Write Enable" "0: Write disable,1: Write enable"
|
|
bitfld.long 0x00 9. "RTA,Read Transfer Active" "0: No valid data,1: Transferring data"
|
|
newline
|
|
bitfld.long 0x00 8. "WTA,Write Transfer Active" "0: No valid data,1: Transferring data"
|
|
bitfld.long 0x00 7. "SDOFF,SD Clock Gated Off Internally" "0: SD Clock is active,1: SD Clock is gated off"
|
|
newline
|
|
bitfld.long 0x00 6. "PEROFF,IPG_PERCLK Gated Off Internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
|
|
bitfld.long 0x00 5. "HCKOFF,HCLK Gated Off Internally" "0: HCLK is active,1: HCLK is gated off"
|
|
newline
|
|
bitfld.long 0x00 4. "IPGOFF,IPG_CLK Gated Off Internally" "0: IPG_CLK is active,1: IPG_CLK is gated off"
|
|
bitfld.long 0x00 3. "SDSTB,SD Clock Stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
|
|
newline
|
|
bitfld.long 0x00 2. "DLA,Data Line Active" "0: DATA Line Inactive,1: DATA Line Active"
|
|
bitfld.long 0x00 1. "CDIHB,Command Inhibit (DATA)" "0: Can issue command which uses the DATA line,1: Cannot issue command which uses the DATA line"
|
|
newline
|
|
bitfld.long 0x00 0. "CIHB,Command Inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PROT_CTRL,Protocol Control"
|
|
bitfld.long 0x00 30. "NON_EXACT_BLK_RD,NON_EXACT_BLK_RD" "0: The block read is exact block,1: The block read is non-exact block"
|
|
bitfld.long 0x00 27.--29. "BURST_LEN_EN,BURST length enable for INCR INCR4 / INCR8 / INCR16 INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" "?,1: Burst length is enabled for INCR,?,3: Burst length is enabled for INCR,?,5: Burst length is enabled for INCR,?,7: Burst length is enabled for INCR"
|
|
newline
|
|
bitfld.long 0x00 26. "WECRM,Wakeup Event Enable On SD Card Removal" "0: WECRM_0,1: WECRM_1"
|
|
bitfld.long 0x00 25. "WECINS,Wakeup Event Enable On SD Card Insertion" "0: WECINS_0,1: WECINS_1"
|
|
newline
|
|
bitfld.long 0x00 24. "WECINT,Wakeup Event Enable On Card Interrupt" "0: WECINT_0,1: WECINT_1"
|
|
bitfld.long 0x00 20. "RD_DONE_NO_8CLK,RD_DONE_NO_8CLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IABG,Interrupt At Block Gap" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 18. "RWCTL,Read Wait Control" "0: Disable Read Wait Control and stop SD Clock..,1: Enable Read Wait Control and assert Read Wait.."
|
|
newline
|
|
bitfld.long 0x00 17. "CREQ,Continue Request" "0: No effect,1: Restart"
|
|
bitfld.long 0x00 16. "SABGREQ,Stop At Block Gap Request" "0: SABGREQ_0,1: SABGREQ_1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "DMASEL,DMA Select" "0: No DMA or Simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,?..."
|
|
bitfld.long 0x00 7. "CDSS,Card Detect Signal Selection" "0: Card Detection Level is selected (for normal..,1: Card Detection Test Level is selected (for.."
|
|
newline
|
|
bitfld.long 0x00 6. "CDTL,Card Detect Test Level" "0: Card Detect Test Level is 0 no card inserted,1: Card Detect Test Level is 1 card inserted"
|
|
bitfld.long 0x00 4.--5. "EMODE,Endian Mode" "0: Big Endian Mode,1: Half Word Big Endian Mode,2: Little Endian Mode,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "D3CD,DATA3 as Card Detection Pin" "0: DATA3 does not monitor Card Insertion,1: DATA3 as Card Detection Pin"
|
|
bitfld.long 0x00 1.--2. "DTW,Data Transfer Width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "LCTL,LED Control" "0: LED off,1: LCTL_1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SYS_CTRL,System Control"
|
|
bitfld.long 0x00 27. "INITA,Initialization Active" "0,1"
|
|
bitfld.long 0x00 26. "RSTD,Software Reset For DATA Line" "0: No Reset,1: RSTD_1"
|
|
newline
|
|
bitfld.long 0x00 25. "RSTC,Software Reset For CMD Line" "0: No Reset,1: RSTC_1"
|
|
bitfld.long 0x00 24. "RSTA,Software Reset For ALL" "0: No Reset,1: RSTA_1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPP_RST_N,IPP_RST_N" "0,1"
|
|
bitfld.long 0x00 16.--19. "DTOCV,Data Timeout Counter Value" "0: SDCLK x 2 14,1: SDCLK x 2 15,?,?,?,?,?,?,?,?,?,?,?,13: SDCLK x 2 27,14: SDCLK x 2 28,15: SDCLK x 2 29"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SDCLKFS,SDCLK Frequency Select"
|
|
bitfld.long 0x00 4.--7. "DVS,Divisor" "0: Divide-by-1,1: Divide-by-2,?,?,?,?,?,?,?,?,?,?,?,?,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INT_STATUS,Interrupt Status"
|
|
eventfld.long 0x00 28. "DMAE,DMA Error" "0: No Error,1: DMAE_1"
|
|
eventfld.long 0x00 24. "AC12E,Auto CMD12 Error" "0: No Error,1: AC12E_1"
|
|
newline
|
|
eventfld.long 0x00 22. "DEBE,Data End Bit Error" "0: No Error,1: DEBE_1"
|
|
eventfld.long 0x00 21. "DCE,Data CRC Error" "0: No Error,1: DCE_1"
|
|
newline
|
|
eventfld.long 0x00 20. "DTOE,Data Timeout Error" "0: No Error,1: Time out"
|
|
eventfld.long 0x00 19. "CIE,Command Index Error" "0: No Error,1: CIE_1"
|
|
newline
|
|
eventfld.long 0x00 18. "CEBE,Command End Bit Error" "0: No Error,1: End Bit Error Generated"
|
|
eventfld.long 0x00 17. "CCE,Command CRC Error" "0: No Error,1: CRC Error Generated"
|
|
newline
|
|
eventfld.long 0x00 16. "CTOE,Command Timeout Error" "0: No Error,1: Time out"
|
|
eventfld.long 0x00 8. "CINT,Card Interrupt" "0: No Card Interrupt,1: Generate Card Interrupt"
|
|
newline
|
|
eventfld.long 0x00 7. "CRM,Card Removal" "0: Card state unstable or inserted,1: Card removed"
|
|
eventfld.long 0x00 6. "CINS,Card Insertion" "0: Card state unstable or removed,1: Card inserted"
|
|
newline
|
|
eventfld.long 0x00 5. "BRR,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
|
|
eventfld.long 0x00 4. "BWR,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer"
|
|
newline
|
|
eventfld.long 0x00 3. "DINT,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
|
|
eventfld.long 0x00 2. "BGE,Block Gap Event" "0: No block gap event,1: Transaction stopped at block gap"
|
|
newline
|
|
eventfld.long 0x00 1. "TC,Transfer Complete" "0: Transfer not complete,1: Transfer complete"
|
|
eventfld.long 0x00 0. "CC,Command Complete" "0: Command not complete,1: Command complete"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
|
|
bitfld.long 0x00 28. "DMAESEN,DMA Error Status Enable" "0: DMAESEN_0,1: DMAESEN_1"
|
|
bitfld.long 0x00 24. "AC12ESEN,Auto CMD12 Error Status Enable" "0: AC12ESEN_0,1: AC12ESEN_1"
|
|
newline
|
|
bitfld.long 0x00 22. "DEBESEN,Data End Bit Error Status Enable" "0: DEBESEN_0,1: DEBESEN_1"
|
|
bitfld.long 0x00 21. "DCESEN,Data CRC Error Status Enable" "0: DCESEN_0,1: DCESEN_1"
|
|
newline
|
|
bitfld.long 0x00 20. "DTOESEN,Data Timeout Error Status Enable" "0: DTOESEN_0,1: DTOESEN_1"
|
|
bitfld.long 0x00 19. "CIESEN,Command Index Error Status Enable" "0: CIESEN_0,1: CIESEN_1"
|
|
newline
|
|
bitfld.long 0x00 18. "CEBESEN,Command End Bit Error Status Enable" "0: CEBESEN_0,1: CEBESEN_1"
|
|
bitfld.long 0x00 17. "CCESEN,Command CRC Error Status Enable" "0: CCESEN_0,1: CCESEN_1"
|
|
newline
|
|
bitfld.long 0x00 16. "CTOESEN,Command Timeout Error Status Enable" "0: CTOESEN_0,1: CTOESEN_1"
|
|
bitfld.long 0x00 8. "CINTSEN,Card Interrupt Status Enable" "0: CINTSEN_0,1: CINTSEN_1"
|
|
newline
|
|
bitfld.long 0x00 7. "CRMSEN,Card Removal Status Enable" "0: CRMSEN_0,1: CRMSEN_1"
|
|
bitfld.long 0x00 6. "CINSSEN,Card Insertion Status Enable" "0: CINSSEN_0,1: CINSSEN_1"
|
|
newline
|
|
bitfld.long 0x00 5. "BRRSEN,Buffer Read Ready Status Enable" "0: BRRSEN_0,1: BRRSEN_1"
|
|
bitfld.long 0x00 4. "BWRSEN,Buffer Write Ready Status Enable" "0: BWRSEN_0,1: BWRSEN_1"
|
|
newline
|
|
bitfld.long 0x00 3. "DINTSEN,DMA Interrupt Status Enable" "0: DINTSEN_0,1: DINTSEN_1"
|
|
bitfld.long 0x00 2. "BGESEN,Block Gap Event Status Enable" "0: BGESEN_0,1: BGESEN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "TCSEN,Transfer Complete Status Enable" "0: TCSEN_0,1: TCSEN_1"
|
|
bitfld.long 0x00 0. "CCSEN,Command Complete Status Enable" "0: CCSEN_0,1: CCSEN_1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
|
|
bitfld.long 0x00 28. "DMAEIEN,DMA Error Interrupt Enable" "0: DMAEIEN_0,1: DMAEIEN_1"
|
|
bitfld.long 0x00 24. "AC12EIEN,Auto CMD12 Error Interrupt Enable" "0: AC12EIEN_0,1: AC12EIEN_1"
|
|
newline
|
|
bitfld.long 0x00 22. "DEBEIEN,Data End Bit Error Interrupt Enable" "0: DEBEIEN_0,1: DEBEIEN_1"
|
|
bitfld.long 0x00 21. "DCEIEN,Data CRC Error Interrupt Enable" "0: DCEIEN_0,1: DCEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 20. "DTOEIEN,Data Timeout Error Interrupt Enable" "0: DTOEIEN_0,1: DTOEIEN_1"
|
|
bitfld.long 0x00 19. "CIEIEN,Command Index Error Interrupt Enable" "0: CIEIEN_0,1: CIEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 18. "CEBEIEN,Command End Bit Error Interrupt Enable" "0: CEBEIEN_0,1: CEBEIEN_1"
|
|
bitfld.long 0x00 17. "CCEIEN,Command CRC Error Interrupt Enable" "0: CCEIEN_0,1: CCEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 16. "CTOEIEN,Command Timeout Error Interrupt Enable" "0: CTOEIEN_0,1: CTOEIEN_1"
|
|
bitfld.long 0x00 8. "CINTIEN,Card Interrupt Interrupt Enable" "0: CINTIEN_0,1: CINTIEN_1"
|
|
newline
|
|
bitfld.long 0x00 7. "CRMIEN,Card Removal Interrupt Enable" "0: CRMIEN_0,1: CRMIEN_1"
|
|
bitfld.long 0x00 6. "CINSIEN,Card Insertion Interrupt Enable" "0: CINSIEN_0,1: CINSIEN_1"
|
|
newline
|
|
bitfld.long 0x00 5. "BRRIEN,Buffer Read Ready Interrupt Enable" "0: BRRIEN_0,1: BRRIEN_1"
|
|
bitfld.long 0x00 4. "BWRIEN,Buffer Write Ready Interrupt Enable" "0: BWRIEN_0,1: BWRIEN_1"
|
|
newline
|
|
bitfld.long 0x00 3. "DINTIEN,DMA Interrupt Enable" "0: DINTIEN_0,1: DINTIEN_1"
|
|
bitfld.long 0x00 2. "BGEIEN,Block Gap Event Interrupt Enable" "0: BGEIEN_0,1: BGEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "TCIEN,Transfer Complete Interrupt Enable" "0: TCIEN_0,1: TCIEN_1"
|
|
bitfld.long 0x00 0. "CCIEN,Command Complete Interrupt Enable" "0: CCIEN_0,1: CCIEN_1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
|
|
bitfld.long 0x00 7. "CNIBAC12E,Command Not Issued By Auto CMD12 Error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
|
|
bitfld.long 0x00 4. "AC12IE,Auto CMD12 / 23 Index Error" "0: AC12IE_0,1: Error the CMD index in response is not CMD12/23"
|
|
newline
|
|
bitfld.long 0x00 3. "AC12CE,Auto CMD12 / 23 CRC Error" "0: No CRC error,1: CRC Error Met in Auto CMD12/23 Response"
|
|
bitfld.long 0x00 2. "AC12EBE,Auto CMD12 / 23 End Bit Error" "0: AC12EBE_0,1: End Bit Error Generated"
|
|
newline
|
|
bitfld.long 0x00 1. "AC12TOE,Auto CMD12 / 23 Timeout Error" "0: AC12TOE_0,1: AC12TOE_1"
|
|
bitfld.long 0x00 0. "AC12NE,Auto CMD12 Not Executed" "0: AC12NE_0,1: Not executed"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. "VS18,Voltage Support 1.8 V" "0: 1.8V not supported,1: 1.8V supported"
|
|
bitfld.long 0x00 25. "VS30,Voltage Support 3.0 V" "0: 3.0V not supported,1: 3.0V supported"
|
|
newline
|
|
bitfld.long 0x00 24. "VS33,Voltage Support 3.3V" "0: 3.3V not supported,1: 3.3V supported"
|
|
bitfld.long 0x00 23. "SRS,Suspend / Resume Support" "0: Not supported,1: Supported"
|
|
newline
|
|
bitfld.long 0x00 22. "DMAS,DMA Support" "0: DMA not supported,1: DMA Supported"
|
|
bitfld.long 0x00 21. "HSS,High Speed Support" "0: High Speed Not Supported,1: High Speed Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "ADMAS,ADMA Support" "0: Advanced DMA Not supported,1: Advanced DMA Supported"
|
|
bitfld.long 0x00 16.--18. "MBL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 support" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "WTMK_LVL,Watermark Level"
|
|
bitfld.long 0x00 24.--28. "WR_BRST_LEN,Write Burst Length Due to system restriction the actual burst length may not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WR_WML,Write Watermark Level"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "RD_BRST_LEN,Read Burst Length Due to system restriction the actual burst length may not exceed 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RD_WML,Read Watermark Level"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MIX_CTRL,Mixer Control"
|
|
bitfld.long 0x00 7. "AC23EN,Auto CMD23 Enable" "0,1"
|
|
bitfld.long 0x00 6. "NIBBLE_POS,NIBBLE_POS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MSBSEL,Multi / Single Block Select" "0: Single Block,1: Multiple Blocks"
|
|
bitfld.long 0x00 4. "DTDSEL,Data Transfer Direction Select" "0: Write (Host to Card),1: Read (Card to Host)"
|
|
newline
|
|
bitfld.long 0x00 3. "DDR_EN,Dual Data Rate mode selection" "0,1"
|
|
bitfld.long 0x00 2. "AC12EN,Auto CMD12 Enable" "0: AC12EN_0,1: AC12EN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "BCEN,Block Count Enable" "0: Disable,1: BCEN_1"
|
|
bitfld.long 0x00 0. "DMAEN,DMA Enable" "0: DMAEN_0,1: DMAEN_1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FORCE_EVENT,Force Event"
|
|
bitfld.long 0x00 31. "FEVTCINT,Force Event Card Interrupt" "0,1"
|
|
bitfld.long 0x00 28. "FEVTDMAE,Force Event DMA Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "FEVTAC12E,Force Event Auto Command 12 Error" "0,1"
|
|
bitfld.long 0x00 22. "FEVTDEBE,Force Event Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "FEVTDCE,Force Event Data CRC Error" "0,1"
|
|
bitfld.long 0x00 20. "FEVTDTOE,Force Event Data Time Out Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "FEVTCIE,Force Event Command Index Error" "0,1"
|
|
bitfld.long 0x00 18. "FEVTCEBE,Force Event Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "FEVTCCE,Force Event Command CRC Error" "0,1"
|
|
bitfld.long 0x00 16. "FEVTCTOE,Force Event Command Time Out Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "FEVTCNIBAC12E,Force Event Command Not Executed By Auto Command 12 Error" "0,1"
|
|
bitfld.long 0x00 4. "FEVTAC12IE,Force Event Auto Command 12 Index Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FEVTAC12EBE,Force Event Auto Command 12 End Bit Error" "0,1"
|
|
bitfld.long 0x00 2. "FEVTAC12CE,Force Event Auto Command 12 CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FEVTAC12TOE,Force Event Auto Command 12 Time Out Error" "0,1"
|
|
bitfld.long 0x00 0. "FEVTAC12NE,Force Event Auto Command 12 Not Executed" "0,1"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. "ADMADCE,ADMA Descriptor Error" "0: ADMADCE_0,1: ADMADCE_1"
|
|
bitfld.long 0x00 2. "ADMALME,ADMA Length Mismatch Error" "0: ADMALME_0,1: ADMALME_1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ADMAES,ADMA Error State (when ADMA Error is occurred)" "0,1,2,3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
|
|
hexmask.long 0x00 2.--31. 1. "ADS_ADDR,ADMA System Address"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
|
|
bitfld.long 0x00 31. "CMD_BYTE_EN,CMD_BYTE_EN" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
|
|
bitfld.long 0x00 15. "CRC_CHK_DIS,CRC Check Disable" "0: Check CRC16 for every read data packet and..,1: Ignore CRC16 check for every read data packet.."
|
|
newline
|
|
bitfld.long 0x00 8. "FRC_SDCLK_ON,FRC_SDCLK_ON" "0: CLK active or inactive is fully controlled by..,1: Force CLK active"
|
|
bitfld.long 0x00 3. "AC12_WR_CHKBUSY_EN,AC12_WR_CHKBUSY_EN" "0: Do not check busy after auto CMD12 for write..,1: Check busy after auto CMD12 for write data.."
|
|
newline
|
|
bitfld.long 0x00 2. "CONFLICT_CHK_EN,Conflict check enable" "0: Conflict check disable,1: Conflict check enable"
|
|
bitfld.long 0x00 1. "VSELECT,Voltage Selection" "0: Change the voltage to high voltage range..,1: Change the voltage to low voltage range.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "MMC_BOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "BOOT_BLK_CNT,BOOT_BLK_CNT"
|
|
bitfld.long 0x00 8. "DISABLE_TIME_OUT,Disable Time Out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
|
|
newline
|
|
bitfld.long 0x00 7. "AUTO_SABG_EN,AUTO_SABG_EN" "0,1"
|
|
bitfld.long 0x00 6. "BOOT_EN,BOOT_EN" "0: Fast boot disable,1: Fast boot enable"
|
|
newline
|
|
bitfld.long 0x00 5. "BOOT_MODE,BOOT_MODE" "0: BOOT_MODE_0,1: Alternative boot"
|
|
bitfld.long 0x00 4. "BOOT_ACK,BOOT_ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTOCV_ACK,DTOCV_ACK" "0: SDCLK x 2^14,1: SDCLK x 2^15,2: SDCLK x 2^16,3: SDCLK x 2^17,4: SDCLK x 2^18,5: SDCLK x 2^19,6: SDCLK x 2^20,7: SDCLK x 2^21,?,?,?,?,?,?,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
|
|
bitfld.long 0x00 14. "AHB_RST,AHB BUS reset" "0,1"
|
|
bitfld.long 0x00 12. "ACMD23_ARGU2_EN,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing.."
|
|
newline
|
|
bitfld.long 0x00 3. "CARD_INT_D3_TEST,Card Interrupt Detection Test" "0: Check the card interrupt only when DATA3 is..,1: Check the card interrupt by ignoring the.."
|
|
tree.end
|
|
endif
|
|
tree "VREF"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
base ad:0x4004D000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TRM,VREF Trim Register"
|
|
bitfld.byte 0x00 6. "CHOPEN,Chop oscillator enable" "0: Chop oscillator is disabled,1: Chop oscillator is enabled"
|
|
bitfld.byte 0x00 0.--5. "TRIM,Trim bits" "0: TRIM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: TRIM_63"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status and Control Register"
|
|
bitfld.byte 0x00 7. "VREFEN,Internal Voltage Reference enable" "0: The module is disabled,1: The module is enabled"
|
|
bitfld.byte 0x00 6. "REGEN,Regulator enable" "0: Internal 1.75 V regulator is disabled,1: Internal 1.75 V regulator is enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. "ICOMPEN,Second order curvature compensation enable" "0: ICOMPEN_0,1: ICOMPEN_1"
|
|
rbitfld.byte 0x00 2. "VREFST,Internal Voltage Reference stable" "0: The module is disabled or not stable,1: The module is stable"
|
|
newline
|
|
bitfld.byte 0x00 0.--1. "MODE_LV,Buffer Mode selection" "0: Bandgap on only for stabilization and startup,1: High power buffer mode enabled,2: Low-power buffer mode enabled,?..."
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "TRM4,VREF Trim 2.1V Register"
|
|
bitfld.byte 0x00 7. "VREF2V1_EN,Internal Voltage Reference (2.1V) Enable" "0: VREF 2.1V is enabled,1: VREF 2.1V is disabled"
|
|
bitfld.byte 0x00 0.--5. "TRIM2V1,VREF 2.1V Trim Bits" "0: TRIM2V1_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: TRIM2V1_63"
|
|
endif
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")||cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
base ad:0x40072000
|
|
elif cpuis("K32L2B11*")||cpuis("K32L2B21*")||cpuis("K32L2B31*")
|
|
base ad:0x40074000
|
|
endif
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TRM,VREF Trim Register"
|
|
bitfld.byte 0x00 6. "CHOPEN,Chop oscillator enable" "0: Chop oscillator is disabled,1: Chop oscillator is enabled"
|
|
bitfld.byte 0x00 0.--5. "TRIM,Trim bits" "0: TRIM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: TRIM_63"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SC,VREF Status and Control Register"
|
|
bitfld.byte 0x00 7. "VREFEN,Internal Voltage Reference enable" "0: The module is disabled,1: The module is enabled"
|
|
bitfld.byte 0x00 6. "REGEN,Regulator enable" "0: Internal 1.75 V regulator is disabled,1: Internal 1.75 V regulator is enabled"
|
|
newline
|
|
bitfld.byte 0x00 5. "ICOMPEN,Second order curvature compensation enable" "0: ICOMPEN_0,1: ICOMPEN_1"
|
|
rbitfld.byte 0x00 2. "VREFST,Internal Voltage Reference stable" "0: The module is disabled or not stable,1: The module is stable"
|
|
newline
|
|
bitfld.byte 0x00 0.--1. "MODE_LV,Buffer Mode selection" "0: Bandgap on only for stabilization and startup,1: High power buffer mode enabled,2: Low-power buffer mode enabled,?..."
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "TRM4,VREF Trim 2.1V Register"
|
|
bitfld.byte 0x00 7. "VREF2V1_EN,Internal Voltage Reference (2.1V) Enable" "0: VREF 2.1V is enabled,1: VREF 2.1V is disabled"
|
|
bitfld.byte 0x00 0.--5. "TRIM2V1,VREF 2.1V Trim Bits" "0: TRIM2V1_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: TRIM2V1_63"
|
|
endif
|
|
tree.end
|
|
sif cpuis("K32L2A31*")||cpuis("K32L2A41*")
|
|
tree "WDOG (Watchdog Timer Unit)"
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "WDOG0"
|
|
base ad:0x4002A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
eventfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0: Bus clock,1: LPO clock,2: INTCLK (internal clock),3: ERCLK (external reference clock)"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
endif
|
|
tree "WDOG0"
|
|
base ad:0x40076000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
eventfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0: Bus clock,1: LPO clock,2: INTCLK (internal clock),3: ERCLK (external reference clock)"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "WDOG1"
|
|
base ad:0x41026000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
eventfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0: Bus clock,1: LPO clock,2: INTCLK (internal clock),3: ERCLK (external reference clock)"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("K32L3A*-CM0+")||cpuis("K32L3A*-CM4")
|
|
tree "XRDC"
|
|
base ad:0x40014000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
bitfld.long 0x00 15. "GVLDC,Global Valid for MRCs" "0: XRDC MRCs are disabled,1: XRDC MRCs are enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "GVLDP,Global Valid for PACs/MSCs" "0: XRDC PACs/MSCs are disabled,1: XRDC PACs/MSCs are enabled"
|
|
rbitfld.long 0x00 8. "VAW,Virtualization aware" "0: Implementation is not virtualization aware,1: Implementation is virtualization aware"
|
|
newline
|
|
rbitfld.long 0x00 1.--4. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "GVLDM,Global Valid MDACs(XRDC global enable/disable)" "0: XRDC MDACs are disabled,1: XRDC MDACs are enabled"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "HWCFG0,Hardware Configuration Register 0"
|
|
bitfld.long 0x00 28.--31. "MID,Module ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "NPAC,Number of PACs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "NMRC,Number of MRCs"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NMSTR,Number of bus masters"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "NDID,Number of domains"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "HWCFG1,Hardware Configuration Register 1"
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "HWCFG2,Hardware Configuration Register 2"
|
|
bitfld.long 0x00 31. "PIDP31,Process identifier" "0: Bus master 31 does not source a process..,1: Bus master 31 sources a process identifier.."
|
|
bitfld.long 0x00 30. "PIDP30,Process identifier" "0: Bus master 30 does not source a process..,1: Bus master 30 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 29. "PIDP29,Process identifier" "0: Bus master 29 does not source a process..,1: Bus master 29 sources a process identifier.."
|
|
bitfld.long 0x00 28. "PIDP28,Process identifier" "0: Bus master 28 does not source a process..,1: Bus master 28 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 27. "PIDP27,Process identifier" "0: Bus master 27 does not source a process..,1: Bus master 27 sources a process identifier.."
|
|
bitfld.long 0x00 26. "PIDP26,Process identifier" "0: Bus master 26 does not source a process..,1: Bus master 26 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 25. "PIDP25,Process identifier" "0: Bus master 25 does not source a process..,1: Bus master 25 sources a process identifier.."
|
|
bitfld.long 0x00 24. "PIDP24,Process identifier" "0: Bus master 24 does not source a process..,1: Bus master 24 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 23. "PIDP23,Process identifier" "0: Bus master 23 does not source a process..,1: Bus master 23 sources a process identifier.."
|
|
bitfld.long 0x00 22. "PIDP22,Process identifier" "0: Bus master 22 does not source a process..,1: Bus master 22 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 21. "PIDP21,Process identifier" "0: Bus master 21 does not source a process..,1: Bus master 21 sources a process identifier.."
|
|
bitfld.long 0x00 20. "PIDP20,Process identifier" "0: Bus master 20 does not source a process..,1: Bus master 20 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 19. "PIDP19,Process identifier" "0: Bus master 19 does not source a process..,1: Bus master 19 sources a process identifier.."
|
|
bitfld.long 0x00 18. "PIDP18,Process identifier" "0: Bus master 18 does not source a process..,1: Bus master 18 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 17. "PIDP17,Process identifier" "0: Bus master 17 does not source a process..,1: Bus master 17 sources a process identifier.."
|
|
bitfld.long 0x00 16. "PIDP16,Process identifier" "0: Bus master 16 does not source a process..,1: Bus master 16 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 15. "PIDP15,Process identifier" "0: Bus master 15 does not source a process..,1: Bus master 15 sources a process identifier.."
|
|
bitfld.long 0x00 14. "PIDP14,Process identifier" "0: Bus master 14 does not source a process..,1: Bus master 14 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 13. "PIDP13,Process identifier" "0: Bus master 13 does not source a process..,1: Bus master 13 sources a process identifier.."
|
|
bitfld.long 0x00 12. "PIDP12,Process identifier" "0: Bus master 12 does not source a process..,1: Bus master 12 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 11. "PIDP11,Process identifier" "0: Bus master 11 does not source a process..,1: Bus master 11 sources a process identifier.."
|
|
bitfld.long 0x00 10. "PIDP10,Process identifier" "0: Bus master 10 does not source a process..,1: Bus master 10 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 9. "PIDP9,Process identifier" "0: Bus master 9 does not source a process..,1: Bus master 9 sources a process identifier.."
|
|
bitfld.long 0x00 8. "PIDP8,Process identifier" "0: Bus master 8 does not source a process..,1: Bus master 8 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 7. "PIDP7,Process identifier" "0: Bus master 7 does not source a process..,1: Bus master 7 sources a process identifier.."
|
|
bitfld.long 0x00 6. "PIDP6,Process identifier" "0: Bus master 6 does not source a process..,1: Bus master 6 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 5. "PIDP5,Process identifier" "0: Bus master 5 does not source a process..,1: Bus master 5 sources a process identifier.."
|
|
bitfld.long 0x00 4. "PIDP4,Process identifier" "0: Bus master 4 does not source a process..,1: Bus master 4 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 3. "PIDP3,Process identifier" "0: Bus master 3 does not source a process..,1: Bus master 3 sources a process identifier.."
|
|
bitfld.long 0x00 2. "PIDP2,Process identifier" "0: Bus master 2 does not source a process..,1: Bus master 2 sources a process identifier.."
|
|
newline
|
|
bitfld.long 0x00 1. "PIDP1,Process identifier" "0: Bus master 1 does not source a process..,1: Bus master 1 sources a process identifier.."
|
|
bitfld.long 0x00 0. "PIDP0,Process identifier" "0: Bus master 0 does not source a process..,1: Bus master 0 sources a process identifier.."
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "HWCFG3,Hardware Configuration Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "PIDPn,Process identifier"
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "32" "33" "34" )(list 0x00 0x01 0x02 0x03 0x04 0x20 0x21 0x22 )
|
|
rgroup.byte ($2+0x100)++0x00
|
|
line.byte 0x00 "MDACFG$1,Master Domain Assignment Configuration Register"
|
|
bitfld.byte 0x00 7. "NCM,Non-CPU Master" "0: Bus master is a processor,1: Bus master is a non-processor"
|
|
bitfld.byte 0x00 0.--3. "NMDAR,Number of master domain assignment registers for bus master m" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x01 )
|
|
rgroup.byte ($2+0x140)++0x00
|
|
line.byte 0x00 "MRCFG$1,Memory Region Configuration Register"
|
|
bitfld.byte 0x00 0.--4. "NMRGD,Number of memory region descriptors for memory region controller n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "FDID,Fault Domain ID"
|
|
bitfld.long 0x00 0.--3. "FDID,Domain ID of Faulted Access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x200)++0x03
|
|
line.long 0x00 "DERRLOC[$1],Domain Error Location Register $1"
|
|
bitfld.long 0x00 16.--19. "PACINST,PAC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "MRCINST,MRC instance"
|
|
repeat.end
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "DERR_W0_0,Domain Error Word0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error address"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "DERR_W1_0,Domain Error Word1 Register"
|
|
bitfld.long 0x00 30.--31. "EST,Error state" "0: No access violation has been detected,1: No access violation has been detected,2: A single access violation has been detected,3: Multiple access violations for this domain.."
|
|
bitfld.long 0x00 24.--26. "EPORT,Error port" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "ERW,Error read/" "0: Read access,1: Write access"
|
|
bitfld.long 0x00 8.--10. "EATR,Error attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EDID,Error domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "DERR_W3_0,Domain Error Word3 Register"
|
|
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0,1,2,3"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "DERR_W0_1,Domain Error Word0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error address"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "DERR_W1_1,Domain Error Word1 Register"
|
|
bitfld.long 0x00 30.--31. "EST,Error state" "0: No access violation has been detected,1: No access violation has been detected,2: A single access violation has been detected,3: Multiple access violations for this domain.."
|
|
bitfld.long 0x00 24.--26. "EPORT,Error port" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "ERW,Error read/" "0: Read access,1: Write access"
|
|
bitfld.long 0x00 8.--10. "EATR,Error attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EDID,Error domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "DERR_W3_1,Domain Error Word3 Register"
|
|
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0,1,2,3"
|
|
rgroup.long 0x500++0x03
|
|
line.long 0x00 "DERR_W0_16,Domain Error Word0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error address"
|
|
rgroup.long 0x504++0x03
|
|
line.long 0x00 "DERR_W1_16,Domain Error Word1 Register"
|
|
bitfld.long 0x00 30.--31. "EST,Error state" "0: No access violation has been detected,1: No access violation has been detected,2: A single access violation has been detected,3: Multiple access violations for this domain.."
|
|
bitfld.long 0x00 24.--26. "EPORT,Error port" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "ERW,Error read/" "0: Read access,1: Write access"
|
|
bitfld.long 0x00 8.--10. "EATR,Error attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EDID,Error domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "DERR_W3_16,Domain Error Word3 Register"
|
|
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0,1,2,3"
|
|
rgroup.long 0x510++0x03
|
|
line.long 0x00 "DERR_W0_17,Domain Error Word0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error address"
|
|
rgroup.long 0x514++0x03
|
|
line.long 0x00 "DERR_W1_17,Domain Error Word1 Register"
|
|
bitfld.long 0x00 30.--31. "EST,Error state" "0: No access violation has been detected,1: No access violation has been detected,2: A single access violation has been detected,3: Multiple access violations for this domain.."
|
|
bitfld.long 0x00 24.--26. "EPORT,Error port" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "ERW,Error read/" "0: Read access,1: Write access"
|
|
bitfld.long 0x00 8.--10. "EATR,Error attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EDID,Error domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "DERR_W3_17,Domain Error Word3 Register"
|
|
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0,1,2,3"
|
|
rgroup.long 0x520++0x03
|
|
line.long 0x00 "DERR_W0_18,Domain Error Word0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error address"
|
|
rgroup.long 0x524++0x03
|
|
line.long 0x00 "DERR_W1_18,Domain Error Word1 Register"
|
|
bitfld.long 0x00 30.--31. "EST,Error state" "0: No access violation has been detected,1: No access violation has been detected,2: A single access violation has been detected,3: Multiple access violations for this domain.."
|
|
bitfld.long 0x00 24.--26. "EPORT,Error port" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "ERW,Error read/" "0: Read access,1: Write access"
|
|
bitfld.long 0x00 8.--10. "EATR,Error attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EDID,Error domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "DERR_W3_18,Domain Error Word3 Register"
|
|
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0,1,2,3"
|
|
repeat 3. (strings "0" "1" "32" )(list 0x00 0x04 0x80 )
|
|
group.long ($2+0x700)++0x03
|
|
line.long 0x00 "PID$1,Process Identifier"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Register can be written by any secure..,1: Register can be written by any secure..,2: Register can only be written by a secure..,3: Register is locked (read-only) until the next.."
|
|
bitfld.long 0x00 28. "TSM,Three-state model" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "SP4SM,Special 4-state model" "0,1"
|
|
bitfld.long 0x00 0.--5. "PID,Process identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "MDA_W0_0_DFMT0,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. "PE,Process identifier enable" "0: No process identifier is included in the..,1: No process identifier is included in the..,2: The process identifier is included in the..,3: The process identifier is included in the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use MDAm[3:0] as the domain identifier,1: Use the input DID as the domain identifier,2: Use MDAm[3:2] concatenated with the low-order..,?..."
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "MDA_W1_0_DFMT0,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. "PE,Process identifier enable" "0: No process identifier is included in the..,1: No process identifier is included in the..,2: The process identifier is included in the..,3: The process identifier is included in the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use MDAm[3:0] as the domain identifier,1: Use the input DID as the domain identifier,2: Use MDAm[3:2] concatenated with the low-order..,?..."
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "MDA_W0_1_DFMT0,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. "PE,Process identifier enable" "0: No process identifier is included in the..,1: No process identifier is included in the..,2: The process identifier is included in the..,3: The process identifier is included in the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use MDAm[3:0] as the domain identifier,1: Use the input DID as the domain identifier,2: Use MDAm[3:2] concatenated with the low-order..,?..."
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "MDA_W1_1_DFMT0,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. "PE,Process identifier enable" "0: No process identifier is included in the..,1: No process identifier is included in the..,2: The process identifier is included in the..,3: The process identifier is included in the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use MDAm[3:0] as the domain identifier,1: Use the input DID as the domain identifier,2: Use MDAm[3:2] concatenated with the low-order..,?..."
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "MDA_W0_2_DFMT1,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Use MDAn[3:0] as the domain identifier,1: Use the DID input as the domain identifier"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SA,Secure attribute" "0: Force the bus attribute for this master to..,1: Force the bus attribute for this master to..,2: Use the bus master's secure/nonsecure..,3: Use the bus master's secure/nonsecure.."
|
|
bitfld.long 0x00 4.--5. "PA,Privileged attribute" "0: Force the bus attribute for this master to user,1: Force the bus attribute for this master to..,2: Use the bus master's privileged/user..,3: Use the bus master's privileged/user.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "MDA_W0_3_DFMT1,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Use MDAn[3:0] as the domain identifier,1: Use the DID input as the domain identifier"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SA,Secure attribute" "0: Force the bus attribute for this master to..,1: Force the bus attribute for this master to..,2: Use the bus master's secure/nonsecure..,3: Use the bus master's secure/nonsecure.."
|
|
bitfld.long 0x00 4.--5. "PA,Privileged attribute" "0: Force the bus attribute for this master to user,1: Force the bus attribute for this master to..,2: Use the bus master's privileged/user..,3: Use the bus master's privileged/user.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "MDA_W0_4_DFMT1,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Use MDAn[3:0] as the domain identifier,1: Use the DID input as the domain identifier"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SA,Secure attribute" "0: Force the bus attribute for this master to..,1: Force the bus attribute for this master to..,2: Use the bus master's secure/nonsecure..,3: Use the bus master's secure/nonsecure.."
|
|
bitfld.long 0x00 4.--5. "PA,Privileged attribute" "0: Force the bus attribute for this master to user,1: Force the bus attribute for this master to..,2: Use the bus master's privileged/user..,3: Use the bus master's privileged/user.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "MDA_W0_32_DFMT0,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. "PE,Process identifier enable" "0: No process identifier is included in the..,1: No process identifier is included in the..,2: The process identifier is included in the..,3: The process identifier is included in the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use MDAm[3:0] as the domain identifier,1: Use the input DID as the domain identifier,2: Use MDAm[3:2] concatenated with the low-order..,?..."
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "MDA_W1_32_DFMT0,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--7. "PE,Process identifier enable" "0: No process identifier is included in the..,1: No process identifier is included in the..,2: The process identifier is included in the..,3: The process identifier is included in the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use MDAm[3:0] as the domain identifier,1: Use the input DID as the domain identifier,2: Use MDAm[3:2] concatenated with the low-order..,?..."
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "MDA_W0_33_DFMT1,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Use MDAn[3:0] as the domain identifier,1: Use the DID input as the domain identifier"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SA,Secure attribute" "0: Force the bus attribute for this master to..,1: Force the bus attribute for this master to..,2: Use the bus master's secure/nonsecure..,3: Use the bus master's secure/nonsecure.."
|
|
bitfld.long 0x00 4.--5. "PA,Privileged attribute" "0: Force the bus attribute for this master to user,1: Force the bus attribute for this master to..,2: Use the bus master's privileged/user..,3: Use the bus master's privileged/user.."
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|
newline
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "MDA_W0_34_DFMT1,Master Domain Assignment"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The Wr domain assignment is invalid,1: The Wr domain assignment is valid"
|
|
bitfld.long 0x00 30. "LK1,1-bit Lock" "0: Register can be written by any secure..,1: Register is locked (read-only) until the next.."
|
|
newline
|
|
rbitfld.long 0x00 29. "DFMT,Domain format" "0: Processor-core domain assignment,1: Non-processor domain assignment"
|
|
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Use MDAn[3:0] as the domain identifier,1: Use the DID input as the domain identifier"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SA,Secure attribute" "0: Force the bus attribute for this master to..,1: Force the bus attribute for this master to..,2: Use the bus master's secure/nonsecure..,3: Use the bus master's secure/nonsecure.."
|
|
bitfld.long 0x00 4.--5. "PA,Privileged attribute" "0: Force the bus attribute for this master to user,1: Force the bus attribute for this master to..,2: Use the bus master's privileged/user..,3: Use the bus master's privileged/user.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DID,Domain identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "PDAC_W0_0_1,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "PDAC_W1_0_1,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "PDAC_W0_0_3,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x101C++0x03
|
|
line.long 0x00 "PDAC_W1_0_3,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "PDAC_W0_0_4,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "PDAC_W1_0_4,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "PDAC_W0_0_8,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1044++0x03
|
|
line.long 0x00 "PDAC_W1_0_8,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "PDAC_W0_0_9,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "PDAC_W1_0_9,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "PDAC_W0_0_12,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1064++0x03
|
|
line.long 0x00 "PDAC_W1_0_12,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "PDAC_W0_0_15,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x107C++0x03
|
|
line.long 0x00 "PDAC_W1_0_15,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "PDAC_W0_0_20,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10A4++0x03
|
|
line.long 0x00 "PDAC_W1_0_20,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "PDAC_W0_0_21,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "PDAC_W1_0_21,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "PDAC_W0_0_22,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10B4++0x03
|
|
line.long 0x00 "PDAC_W1_0_22,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "PDAC_W0_0_23,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10BC++0x03
|
|
line.long 0x00 "PDAC_W1_0_23,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "PDAC_W0_0_27,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10DC++0x03
|
|
line.long 0x00 "PDAC_W1_0_27,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "PDAC_W0_0_32,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1104++0x03
|
|
line.long 0x00 "PDAC_W1_0_32,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "PDAC_W0_0_33,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "PDAC_W1_0_33,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "PDAC_W0_0_34,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1114++0x03
|
|
line.long 0x00 "PDAC_W1_0_34,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "PDAC_W0_0_35,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x111C++0x03
|
|
line.long 0x00 "PDAC_W1_0_35,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "PDAC_W0_0_36,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1124++0x03
|
|
line.long 0x00 "PDAC_W1_0_36,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "PDAC_W0_0_37,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "PDAC_W1_0_37,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "PDAC_W0_0_38,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1134++0x03
|
|
line.long 0x00 "PDAC_W1_0_38,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "PDAC_W0_0_39,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x113C++0x03
|
|
line.long 0x00 "PDAC_W1_0_39,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "PDAC_W0_0_40,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1144++0x03
|
|
line.long 0x00 "PDAC_W1_0_40,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "PDAC_W0_0_41,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x114C++0x03
|
|
line.long 0x00 "PDAC_W1_0_41,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "PDAC_W0_0_42,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1154++0x03
|
|
line.long 0x00 "PDAC_W1_0_42,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "PDAC_W0_0_43,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x115C++0x03
|
|
line.long 0x00 "PDAC_W1_0_43,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "PDAC_W0_0_44,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1164++0x03
|
|
line.long 0x00 "PDAC_W1_0_44,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "PDAC_W0_0_45,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x116C++0x03
|
|
line.long 0x00 "PDAC_W1_0_45,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "PDAC_W0_0_46,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1174++0x03
|
|
line.long 0x00 "PDAC_W1_0_46,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "PDAC_W0_0_47,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x117C++0x03
|
|
line.long 0x00 "PDAC_W1_0_47,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "PDAC_W0_0_48,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1184++0x03
|
|
line.long 0x00 "PDAC_W1_0_48,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "PDAC_W0_0_49,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x118C++0x03
|
|
line.long 0x00 "PDAC_W1_0_49,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "PDAC_W0_0_50,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1194++0x03
|
|
line.long 0x00 "PDAC_W1_0_50,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "PDAC_W0_0_51,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x119C++0x03
|
|
line.long 0x00 "PDAC_W1_0_51,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "PDAC_W0_0_52,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11A4++0x03
|
|
line.long 0x00 "PDAC_W1_0_52,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "PDAC_W0_0_53,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "PDAC_W1_0_53,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "PDAC_W0_0_54,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11B4++0x03
|
|
line.long 0x00 "PDAC_W1_0_54,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "PDAC_W0_0_55,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11BC++0x03
|
|
line.long 0x00 "PDAC_W1_0_55,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "PDAC_W0_0_56,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C4++0x03
|
|
line.long 0x00 "PDAC_W1_0_56,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "PDAC_W0_0_57,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11CC++0x03
|
|
line.long 0x00 "PDAC_W1_0_57,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "PDAC_W0_0_58,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11D4++0x03
|
|
line.long 0x00 "PDAC_W1_0_58,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "PDAC_W0_0_59,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11DC++0x03
|
|
line.long 0x00 "PDAC_W1_0_59,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "PDAC_W0_0_60,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11E4++0x03
|
|
line.long 0x00 "PDAC_W1_0_60,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "PDAC_W0_0_61,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11EC++0x03
|
|
line.long 0x00 "PDAC_W1_0_61,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "PDAC_W0_0_62,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11F4++0x03
|
|
line.long 0x00 "PDAC_W1_0_62,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "PDAC_W0_0_63,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11FC++0x03
|
|
line.long 0x00 "PDAC_W1_0_63,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "PDAC_W0_0_64,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1204++0x03
|
|
line.long 0x00 "PDAC_W1_0_64,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1208++0x03
|
|
line.long 0x00 "PDAC_W0_0_65,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120C++0x03
|
|
line.long 0x00 "PDAC_W1_0_65,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1210++0x03
|
|
line.long 0x00 "PDAC_W0_0_66,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1214++0x03
|
|
line.long 0x00 "PDAC_W1_0_66,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1218++0x03
|
|
line.long 0x00 "PDAC_W0_0_67,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x121C++0x03
|
|
line.long 0x00 "PDAC_W1_0_67,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1220++0x03
|
|
line.long 0x00 "PDAC_W0_0_68,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1224++0x03
|
|
line.long 0x00 "PDAC_W1_0_68,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1228++0x03
|
|
line.long 0x00 "PDAC_W0_0_69,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x122C++0x03
|
|
line.long 0x00 "PDAC_W1_0_69,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1230++0x03
|
|
line.long 0x00 "PDAC_W0_0_70,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1234++0x03
|
|
line.long 0x00 "PDAC_W1_0_70,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1238++0x03
|
|
line.long 0x00 "PDAC_W0_0_71,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x123C++0x03
|
|
line.long 0x00 "PDAC_W1_0_71,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1240++0x03
|
|
line.long 0x00 "PDAC_W0_0_72,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1244++0x03
|
|
line.long 0x00 "PDAC_W1_0_72,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1248++0x03
|
|
line.long 0x00 "PDAC_W0_0_73,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x124C++0x03
|
|
line.long 0x00 "PDAC_W1_0_73,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1250++0x03
|
|
line.long 0x00 "PDAC_W0_0_74,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1254++0x03
|
|
line.long 0x00 "PDAC_W1_0_74,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1258++0x03
|
|
line.long 0x00 "PDAC_W0_0_75,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x125C++0x03
|
|
line.long 0x00 "PDAC_W1_0_75,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1260++0x03
|
|
line.long 0x00 "PDAC_W0_0_76,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1264++0x03
|
|
line.long 0x00 "PDAC_W1_0_76,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1268++0x03
|
|
line.long 0x00 "PDAC_W0_0_77,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x126C++0x03
|
|
line.long 0x00 "PDAC_W1_0_77,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1270++0x03
|
|
line.long 0x00 "PDAC_W0_0_78,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1274++0x03
|
|
line.long 0x00 "PDAC_W1_0_78,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x13E8++0x03
|
|
line.long 0x00 "PDAC_W0_0_125,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x13EC++0x03
|
|
line.long 0x00 "PDAC_W1_0_125,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x13F0++0x03
|
|
line.long 0x00 "PDAC_W0_0_126,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x13F4++0x03
|
|
line.long 0x00 "PDAC_W1_0_126,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x13F8++0x03
|
|
line.long 0x00 "PDAC_W0_0_127,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x13FC++0x03
|
|
line.long 0x00 "PDAC_W1_0_127,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1440++0x03
|
|
line.long 0x00 "PDAC_W0_1_8,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1444++0x03
|
|
line.long 0x00 "PDAC_W1_1_8,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1448++0x03
|
|
line.long 0x00 "PDAC_W0_1_9,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x144C++0x03
|
|
line.long 0x00 "PDAC_W1_1_9,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1478++0x03
|
|
line.long 0x00 "PDAC_W0_1_15,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x147C++0x03
|
|
line.long 0x00 "PDAC_W1_1_15,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x14D8++0x03
|
|
line.long 0x00 "PDAC_W0_1_27,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14DC++0x03
|
|
line.long 0x00 "PDAC_W1_1_27,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "PDAC_W0_1_32,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1504++0x03
|
|
line.long 0x00 "PDAC_W1_1_32,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1508++0x03
|
|
line.long 0x00 "PDAC_W0_1_33,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150C++0x03
|
|
line.long 0x00 "PDAC_W1_1_33,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1510++0x03
|
|
line.long 0x00 "PDAC_W0_1_34,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1514++0x03
|
|
line.long 0x00 "PDAC_W1_1_34,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1518++0x03
|
|
line.long 0x00 "PDAC_W0_1_35,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x151C++0x03
|
|
line.long 0x00 "PDAC_W1_1_35,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1520++0x03
|
|
line.long 0x00 "PDAC_W0_1_36,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1524++0x03
|
|
line.long 0x00 "PDAC_W1_1_36,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1528++0x03
|
|
line.long 0x00 "PDAC_W0_1_37,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x152C++0x03
|
|
line.long 0x00 "PDAC_W1_1_37,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1530++0x03
|
|
line.long 0x00 "PDAC_W0_1_38,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1534++0x03
|
|
line.long 0x00 "PDAC_W1_1_38,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1538++0x03
|
|
line.long 0x00 "PDAC_W0_1_39,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x153C++0x03
|
|
line.long 0x00 "PDAC_W1_1_39,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1540++0x03
|
|
line.long 0x00 "PDAC_W0_1_40,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1544++0x03
|
|
line.long 0x00 "PDAC_W1_1_40,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1548++0x03
|
|
line.long 0x00 "PDAC_W0_1_41,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x154C++0x03
|
|
line.long 0x00 "PDAC_W1_1_41,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1550++0x03
|
|
line.long 0x00 "PDAC_W0_1_42,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1554++0x03
|
|
line.long 0x00 "PDAC_W1_1_42,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1558++0x03
|
|
line.long 0x00 "PDAC_W0_1_43,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x155C++0x03
|
|
line.long 0x00 "PDAC_W1_1_43,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1560++0x03
|
|
line.long 0x00 "PDAC_W0_1_44,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1564++0x03
|
|
line.long 0x00 "PDAC_W1_1_44,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1568++0x03
|
|
line.long 0x00 "PDAC_W0_1_45,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x156C++0x03
|
|
line.long 0x00 "PDAC_W1_1_45,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1570++0x03
|
|
line.long 0x00 "PDAC_W0_1_46,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1574++0x03
|
|
line.long 0x00 "PDAC_W1_1_46,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1578++0x03
|
|
line.long 0x00 "PDAC_W0_1_47,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x157C++0x03
|
|
line.long 0x00 "PDAC_W1_1_47,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1580++0x03
|
|
line.long 0x00 "PDAC_W0_1_48,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1584++0x03
|
|
line.long 0x00 "PDAC_W1_1_48,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1588++0x03
|
|
line.long 0x00 "PDAC_W0_1_49,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x158C++0x03
|
|
line.long 0x00 "PDAC_W1_1_49,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1590++0x03
|
|
line.long 0x00 "PDAC_W0_1_50,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1594++0x03
|
|
line.long 0x00 "PDAC_W1_1_50,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1598++0x03
|
|
line.long 0x00 "PDAC_W0_1_51,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x159C++0x03
|
|
line.long 0x00 "PDAC_W1_1_51,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x15A0++0x03
|
|
line.long 0x00 "PDAC_W0_1_52,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x15A4++0x03
|
|
line.long 0x00 "PDAC_W1_1_52,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x15A8++0x03
|
|
line.long 0x00 "PDAC_W0_1_53,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x15AC++0x03
|
|
line.long 0x00 "PDAC_W1_1_53,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x15B0++0x03
|
|
line.long 0x00 "PDAC_W0_1_54,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x15B4++0x03
|
|
line.long 0x00 "PDAC_W1_1_54,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x15B8++0x03
|
|
line.long 0x00 "PDAC_W0_1_55,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x15BC++0x03
|
|
line.long 0x00 "PDAC_W1_1_55,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x15C0++0x03
|
|
line.long 0x00 "PDAC_W0_1_56,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x15C4++0x03
|
|
line.long 0x00 "PDAC_W1_1_56,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "PDAC_W0_2_16,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "PDAC_W1_2_16,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x1900++0x03
|
|
line.long 0x00 "PDAC_W0_2_32,Peripheral Domain Access Control"
|
|
rbitfld.long 0x00 24.--27. "EALO,Excessive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2ACP,Domain 2 access control policy" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1ACP,Domain 1 access control policy" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0ACP,Domain 0 access control policy" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1904++0x03
|
|
line.long 0x00 "PDAC_W1_2_32,Peripheral Domain Access Control"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The PDACs assignment is invalid,1: The PDACs assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire PDACs can be written,1: Entire PDACs can be written,2: Domain x can only update the DxACP field and..,3: PDACs is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "MRGD_W0_0_0,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2004++0x03
|
|
line.long 0x00 "MRGD_W1_0_0,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2008++0x03
|
|
line.long 0x00 "MRGD_W2_0_0,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200C++0x03
|
|
line.long 0x00 "MRGD_W3_0_0,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2010++0x03
|
|
line.long 0x00 "MRGD_W4_0_0,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2020++0x03
|
|
line.long 0x00 "MRGD_W0_0_1,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2024++0x03
|
|
line.long 0x00 "MRGD_W1_0_1,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2028++0x03
|
|
line.long 0x00 "MRGD_W2_0_1,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x202C++0x03
|
|
line.long 0x00 "MRGD_W3_0_1,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2030++0x03
|
|
line.long 0x00 "MRGD_W4_0_1,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "MRGD_W0_0_2,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2044++0x03
|
|
line.long 0x00 "MRGD_W1_0_2,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "MRGD_W2_0_2,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "MRGD_W3_0_2,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2050++0x03
|
|
line.long 0x00 "MRGD_W4_0_2,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2060++0x03
|
|
line.long 0x00 "MRGD_W0_0_3,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "MRGD_W1_0_3,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2068++0x03
|
|
line.long 0x00 "MRGD_W2_0_3,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x206C++0x03
|
|
line.long 0x00 "MRGD_W3_0_3,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2070++0x03
|
|
line.long 0x00 "MRGD_W4_0_3,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2080++0x03
|
|
line.long 0x00 "MRGD_W0_0_4,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2084++0x03
|
|
line.long 0x00 "MRGD_W1_0_4,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2088++0x03
|
|
line.long 0x00 "MRGD_W2_0_4,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x208C++0x03
|
|
line.long 0x00 "MRGD_W3_0_4,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "MRGD_W4_0_4,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "MRGD_W0_0_5,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x20A4++0x03
|
|
line.long 0x00 "MRGD_W1_0_5,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x20A8++0x03
|
|
line.long 0x00 "MRGD_W2_0_5,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20AC++0x03
|
|
line.long 0x00 "MRGD_W3_0_5,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x20B0++0x03
|
|
line.long 0x00 "MRGD_W4_0_5,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x20C0++0x03
|
|
line.long 0x00 "MRGD_W0_0_6,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x20C4++0x03
|
|
line.long 0x00 "MRGD_W1_0_6,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x20C8++0x03
|
|
line.long 0x00 "MRGD_W2_0_6,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20CC++0x03
|
|
line.long 0x00 "MRGD_W3_0_6,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x20D0++0x03
|
|
line.long 0x00 "MRGD_W4_0_6,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "MRGD_W0_0_7,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x20E4++0x03
|
|
line.long 0x00 "MRGD_W1_0_7,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x20E8++0x03
|
|
line.long 0x00 "MRGD_W2_0_7,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20EC++0x03
|
|
line.long 0x00 "MRGD_W3_0_7,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x20F0++0x03
|
|
line.long 0x00 "MRGD_W4_0_7,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2200++0x03
|
|
line.long 0x00 "MRGD_W0_1_0,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2204++0x03
|
|
line.long 0x00 "MRGD_W1_1_0,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2208++0x03
|
|
line.long 0x00 "MRGD_W2_1_0,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220C++0x03
|
|
line.long 0x00 "MRGD_W3_1_0,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2210++0x03
|
|
line.long 0x00 "MRGD_W4_1_0,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2220++0x03
|
|
line.long 0x00 "MRGD_W0_1_1,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2224++0x03
|
|
line.long 0x00 "MRGD_W1_1_1,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2228++0x03
|
|
line.long 0x00 "MRGD_W2_1_1,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x222C++0x03
|
|
line.long 0x00 "MRGD_W3_1_1,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2230++0x03
|
|
line.long 0x00 "MRGD_W4_1_1,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2240++0x03
|
|
line.long 0x00 "MRGD_W0_1_2,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2244++0x03
|
|
line.long 0x00 "MRGD_W1_1_2,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2248++0x03
|
|
line.long 0x00 "MRGD_W2_1_2,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x224C++0x03
|
|
line.long 0x00 "MRGD_W3_1_2,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2250++0x03
|
|
line.long 0x00 "MRGD_W4_1_2,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2260++0x03
|
|
line.long 0x00 "MRGD_W0_1_3,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2264++0x03
|
|
line.long 0x00 "MRGD_W1_1_3,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2268++0x03
|
|
line.long 0x00 "MRGD_W2_1_3,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x226C++0x03
|
|
line.long 0x00 "MRGD_W3_1_3,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2270++0x03
|
|
line.long 0x00 "MRGD_W4_1_3,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x2280++0x03
|
|
line.long 0x00 "MRGD_W0_1_4,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x2284++0x03
|
|
line.long 0x00 "MRGD_W1_1_4,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x2288++0x03
|
|
line.long 0x00 "MRGD_W2_1_4,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x228C++0x03
|
|
line.long 0x00 "MRGD_W3_1_4,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x2290++0x03
|
|
line.long 0x00 "MRGD_W4_1_4,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x22A0++0x03
|
|
line.long 0x00 "MRGD_W0_1_5,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x22A4++0x03
|
|
line.long 0x00 "MRGD_W1_1_5,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x22A8++0x03
|
|
line.long 0x00 "MRGD_W2_1_5,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x22AC++0x03
|
|
line.long 0x00 "MRGD_W3_1_5,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x22B0++0x03
|
|
line.long 0x00 "MRGD_W4_1_5,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x22C0++0x03
|
|
line.long 0x00 "MRGD_W0_1_6,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x22C4++0x03
|
|
line.long 0x00 "MRGD_W1_1_6,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x22C8++0x03
|
|
line.long 0x00 "MRGD_W2_1_6,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x22CC++0x03
|
|
line.long 0x00 "MRGD_W3_1_6,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x22D0++0x03
|
|
line.long 0x00 "MRGD_W4_1_6,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
group.long 0x22E0++0x03
|
|
line.long 0x00 "MRGD_W0_1_7,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x22E4++0x03
|
|
line.long 0x00 "MRGD_W1_1_7,Memory Region Descriptor"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x22E8++0x03
|
|
line.long 0x00 "MRGD_W2_1_7,Memory Region Descriptor"
|
|
rbitfld.long 0x00 24.--27. "EALO,Exclusive Access Lock Owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--8. "D2SEL,Domain 2 select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "D1SEL,Domain 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "D0SEL,Domain 0 select" "0,1,2,3,4,5,6,7"
|
|
group.long 0x22EC++0x03
|
|
line.long 0x00 "MRGD_W3_1_7,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "CR,Code Region Indicator" "0,1"
|
|
bitfld.long 0x00 24.--25. "EAL,Exclusive Access Lock" "0: Lock disabled,1: Lock disabled until next reset,2: Lock enabled lock state = available,3: Lock enabled lock state = not available"
|
|
group.long 0x22F0++0x03
|
|
line.long 0x00 "MRGD_W4_1_7,Memory Region Descriptor"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: The MRGDn assignment is invalid,1: The MRGDn assignment is valid"
|
|
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Entire MRGDn can be written,1: Entire MRGDn can be written,2: Domain x can only update the DxACP field and..,3: MRGDn is locked (read-only) until the next.."
|
|
newline
|
|
bitfld.long 0x00 28. "LKAS2,Lock ACCSET2" "0: Writes to ACCSET2 affect lesser modes,1: ACCSET2 cannot be modified"
|
|
hexmask.long.word 0x00 16.--27. 1. "ACCSET2,SET 2 of Programmable access flags"
|
|
newline
|
|
bitfld.long 0x00 12. "LKAS1,Lock ACCSET1" "0: Writes to ACCSET1 affect lesser modes,1: ACCSET1 cannot be modified"
|
|
hexmask.long.word 0x00 0.--11. 1. "ACCSET1,SET 1 of Programmable access flags"
|
|
tree.end
|
|
endif
|
|
autoindent.off
|
|
newline
|