7567 lines
514 KiB
Plaintext
7567 lines
514 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: KEAx On-Chip Peripherals
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; @Props: Released
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; @Manufacturer: NXP - NXP Semiconductors
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; @Author: RTY, ZUO, LMH, MAF
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; @Changelog: 2017-01-04 MAF
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; @Doc: KEA64RM.pdf, KEA8RM.pdf,
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; KEA8RM.pdf: (Rev. 2, 2014-07)
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; KEA128RM.pdf: (Rev. 2, 2014-07), KEA64RM.pdf: (Rev. 2, 2014-07)
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; @Core: Cortex-M0P
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; @Chip: S9KEAZN8AMTG, S9KEAZN8ACTG, S9KEAZN8AMFK, S9KEAZN8AVTG
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; S9KEAZN8ACFK, S9KEAZ64ACLH, S9KEAZ128AMLK, S9KEAZN8AMFKR
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; S9KEAZ128AMLH, S9KEAZ64AMLH, S9KEAZ128ACLH, S9KEAZ128AVLH
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; S9KEAZ64AVLH, S9KEAZN64ACLH, S9KEAZ128AVLHR, S9KEAZ64AMLK
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; S9KEAZN16AMLC, S9KEAZN32ACLC, S9KEAZN32AMLH, S9KEAZN64AMLH
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; S9KEAZ128ACLK, S9KEAZ128AVLK, S9KEAZ64ACLK, S9KEAZ64AVLK
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; S9KEAZN32AMLC, S9KEAZN64AMLC, S9KEAZN64ACLC, S9KEAZN16ACLC
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; S9KEAZN32AVLC, S9KEAZN16ACLH, S9KEAZN32ACLH, S9KEAZN16AMLH
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perkinetisea.per 16106 2023-05-12 08:19:27Z kwisniewski $
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; Known problems:
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; Module Register Description
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; --------------------------------------------------------------------------------
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; All All This chips are not included in latest documents:
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; S9KEAZN64ACLC, S9KEAZN16ACLC, S9KEAZN32ACLC, S9KEAZN32AVLC, S9KEAZN16ACLH, S9KEAZN32ACLH, S9KEAZN8AVTG
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; and they are described based on their package type.
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config 16. 8.
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
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group.long 0xD9C++0x03 "Region 3"
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "PORT (Port Control)"
|
|
base ad:0x40049000
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PORT_IOFLT0,Port Filter Register 0"
|
|
bitfld.long 0x00 29.--31. " FLTDIV3 ,Port Filter Division Set 3" "LPOCLK,LPOCLK/2,LPOCLK/4,LPOCLK/8,LPOCLK/16,LPOCLK/32,LPOCLK/64,LPOCLK/128"
|
|
bitfld.long 0x00 26.--28. " FLTDIV2 ,Port Filter Division Set 2" "BUSCLK/32,BUSCLK/64,BUSCLK/128,BUSCLK/256,BUSCLK/512,BUSCLK/1024,BUSCLK/2048,BUSCLK/4096"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " FLTDIV1 ,Port Filter Division Set 1" "BUSCLK/2,BUSCLK/4,BUSCLK/8,BUSCLK/16"
|
|
bitfld.long 0x00 22.--23. " FLTNMI ,Filter Selection for Input from NMI" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FLTKBI1 ,Filter Selection for Input from KBI1" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 18.--19. " FLTKBI0 ,Filter selection for Input from KBI0" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 14.--15. " FLTH ,Filter Selection for Input from PTH" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " FLTG ,Filter Selection for Input from PTG" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 10.--11. " FLTF ,Filter Selection for Input from PTF" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " FLTE ,Filter Selection for Input from PTE" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FLTC ,Filter Selection for Input from PTC" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 2.--3. " FLTB ,Filter Selection for Input from PTB" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " FLTA ,Filter Selection for Input from PTA" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
line.long 0x04 "PORT_IOFLT1,Port Filter Register 1"
|
|
bitfld.long 0x04 14.--15. " FLTI2C1 ,Filter Selection For Input from SCL1/SDA1" "No filter,FLTDIV1,FLTDIV2,BUSCLK"
|
|
bitfld.long 0x04 12.--13. " FLTI2C0 ,Filter Selection For Input from SCL0/SDA0" "No filter,FLTDIV1,FLTDIV2,BUSCLK"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " FLTPWT ,Filter Selection For Input from PWT_IN1/PWT_IN0" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x04 8.--9. " FLTFTM1 ,Filter Selection For Input from FTM1CH0/FTM1CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " FLTFTM0 ,Filter Selection For Input from FTM0CH0/FTM0CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x04 4.--5. " FLTIRQ ,Filter Selection for Input from IRQ" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " FLTI ,Filter Selection for Input from PTI" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
line.long 0x08 "PORT_PUE0,Port Pullup Enable Register 0"
|
|
bitfld.long 0x08 31. " PTDPE7 ,Pull Enable for Port D Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " PTDPE6 ,Pull Enable for Port D Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " PTDPE5 ,Pull Enable for Port D Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " PTDPE4 ,Pull Enable for Port D Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " PTDPE3 ,Pull Enable for Port D Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " PTDPE2 ,Pull Enable for Port D Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PTDPE1 ,Pull Enable for Port D Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " PTDPE0 ,Pull Enable for Port D Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PTCPE7 ,Pull Enable for Port C Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " PTCPE6 ,Pull Enable for Port C Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " PTCPE5 ,Pull Enable for Port C Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " PTCPE4 ,Pull Enable for Port C Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTCPE3 ,Pull Enable for Port C Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " PTCPE2 ,Pull Enable for Port C Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " PTCPE1 ,Pull Enable for Port C Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " PTCPE0 ,Pull Enable for Port C Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " PTBPE7 ,Pull Enable for Port B Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " PTBPE6 ,Pull Enable for Port B Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PTBPE5 ,Pull Enable for Port B Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " PTBPE4 ,Pull Enable for Port B Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PTBPE3 ,Pull Enable for Port B Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " PTBPE2 ,Pull Enable for Port B Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PTBPE1 ,Pull Enable for Port B Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " PTBPE0 ,Pull Enable for Port B Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PTAPE7 ,Pull Enable for Port A Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PTAPE6 ,Pull Enable for Port A Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " PTAPE5 ,Pull Enable for Port A Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " PTAPE4 ,Pull Enable for Port A Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PTAPE3 ,Pull Enable for Port A Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PTAPE2 ,Pull Enable for Port A Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PTAPE1 ,Pull Enable for Port A Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PTAPE0 ,Pull Enable for Port A Bit 0" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_PUE1,Port Pullup Enable Register 1"
|
|
bitfld.long 0x00 31. " PTHPE7 ,Pull Enable for Port H Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PTHPE6 ,Pull Enable for Port H Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 29. " PTHPE5 ,Pull Enable for Port H Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PTHPE4 ,Pull Enable for Port H Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PTHPE3 ,Pull Enable for Port H Bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " PTHPE2 ,Pull Enable for Port H Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PTHPE1 ,Pull Enable for Port H Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PTHPE0 ,Pull Enable for Port H Bit 0" "Disabled,Enabled"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ64AVLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ128ACLK")
|
|
bitfld.long 0x00 23. " PTGPE7 ,Pull Enable for Port G Bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PTGPE6 ,Pull Enable for Port G Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PTGPE5 ,Pull Enable for Port G Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PTGPE4 ,Pull Enable for Port G Bit 4" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTGPE3 ,Pull Enable for Port G Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PTGPE2 ,Pull Enable for Port G Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PTGPE1 ,Pull Enable for Port G Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PTGPE0 ,Pull Enable for Port G Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PTFPE7 ,Pull Enable for Port F Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PTFPE6 ,Pull Enable for Port F Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PTFPE5 ,Pull Enable for Port F Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PTFPE4 ,Pull Enable for Port F Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTFPE3 ,Pull Enable for Port F Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PTFPE2 ,Pull Enable for Port F Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PTFPE1 ,Pull Enable for Port F Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PTFPE0 ,Pull Enable for Port F Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTEPE6 ,Pull Enable for Port E Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PTEPE5 ,Pull Enable for Port E Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTEPE4 ,Pull Enable for Port E Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTEPE3 ,Pull Enable for Port E Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PORT_PUE2,Port Pullup Enable Register 2"
|
|
bitfld.long 0x00 6. " PTIPE6 ,Pull Enable for Port I Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTIPE5 ,Pull Enable for Port I Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PTIPE4 ,Pull Enable for Port I Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTIPE3 ,Pull Enable for Port I Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTIPE2 ,Pull Enable for Port I Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTIPE1 ,Pull Enable for Port I Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTIPE0 ,Pull Enable for Port I Bit 0" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PORT_PUE2,Port Pullup Enable Register 2"
|
|
bitfld.long 0x00 4. " PTIPE4 ,Pull Enable for Port I Bit 4" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
bitfld.long 0x00 7. " PTH1 ,High Current Drive Capability of PTH1" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTH0 ,High Current Drive Capability of PTH0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PTE1 ,High Current Drive Capability of PTE1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTE0 ,High Current Drive Capability of PTE0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTD1 ,High Current Drive Capability of PTD1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTD0 ,High Current Drive Capability of PTD0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTB4 ,High Current Drive Capability of PTB4" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "PORT (Port Control)"
|
|
base ad:0x40049000
|
|
width 12.
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORT_IOFLT,Port Filter Register"
|
|
bitfld.long 0x00 29.--31. " FLTDIV3 ,Filter Division Set 3" "LPOCLK,LPOCLK/2,LPOCLK/4,LPOCLK/8,LPOCLK/16,LPOCLK/32,LPOCLK/64,LPOCLK/128"
|
|
bitfld.long 0x00 26.--28. " FLTDIV2 ,Filter Division Set 2" "BUSCLK/32,BUSCLK/64,BUSCLK/128,BUSCLK/256,BUSCLK/512,BUSCLK/1024,BUSCLK/2048,BUSCLK/4096"
|
|
bitfld.long 0x00 24.--25. " FLTDIV1 ,Filter Division Set 1" "BUSCLK/2,BUSCLK/4,BUSCLK/8,BUSCLK/16"
|
|
bitfld.long 0x00 22.--23. " FLTNMI ,Filter Selection for Input from NMI" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FLTKBI1 ,Filter Selection for Input from KBI1" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 18.--19. " FLTKBI0 ,Filter selection for Input from KBI0" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 14.--15. " FLTPWT ,Filter Selection For Input from PWT_IN1/PWT_IN0" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " FLTFTM0 ,Filter Selection For Input from FTM0CH0/FTM0CH1" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 10.--11. " FLTIIC ,Filter Selection For Input from SCL/SDA" "No filter,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 4.--5. " FLTC ,Filter Selection for Input from PTC" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 2.--3. " FLTB ,Filter Selection for Input from PTB" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " FLTA ,Filter Selection for Input from PTA" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PORT_IOFLT,Port Filter Register"
|
|
bitfld.long 0x00 29.--31. " FLTDIV3 ,Filter Division Set 3" "LPOCLK,LPOCLK/2,LPOCLK/4,LPOCLK/8,LPOCLK/16,LPOCLK/32,LPOCLK/64,LPOCLK/128"
|
|
bitfld.long 0x00 26.--28. " FLTDIV2 ,Filter Division Set 2" "BUSCLK/32,BUSCLK/64,BUSCLK/128,BUSCLK/256,BUSCLK/512,BUSCLK/1024,BUSCLK/2048,BUSCLK/4096"
|
|
bitfld.long 0x00 24.--25. " FLTDIV1 ,Filter Division Set 1" "BUSCLK/2,BUSCLK/4,BUSCLK/8,BUSCLK/16"
|
|
bitfld.long 0x00 22.--23. " FLTNMI ,Filter Selection for Input from NMI" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FLTKBI1 ,Filter Selection for Input from KBI1" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 18.--19. " FLTKBI0 ,Filter selection for Input from KBI0" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 16.--17. " FLTRST ,Filter Selection for Input from RESET/IRQ" "No filter,FLTDIV1/FLTDIV3(stop),FLTDIV2/FLTDIV3(stop),FLTDIV3"
|
|
bitfld.long 0x00 14.--15. " FLTH ,Filter Selection for Input from PTH" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " FLTG ,Filter Selection for Input from PTG" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 10.--11. " FLTF ,Filter Selection for Input from PTF" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 8.--9. " FLTE ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 6.--7. " FLTD ,Filter Selection for Input from PTD" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FLTC ,Filter Selection for Input from PTC" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 2.--3. " FLTB ,Filter Selection for Input from PTB" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
bitfld.long 0x00 0.--1. " FLTA ,Filter Selection for Input from PTA" "BUSCLK,FLTDIV1,FLTDIV2,FLTDIV3"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORT_PUEL,Port Pullup Enable Low Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")
|
|
bitfld.long 0x00 31. " PTDPE7 ,Pull Enable for Port D Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PTDPE6 ,Pull Enable for Port D Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PTDPE5 ,Pull Enable for Port D Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PTDPE4 ,Pull Enable for Port D Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")&&!cpuis("S9KEAZN8AMFKR")
|
|
bitfld.long 0x00 27. " PTDPE3 ,Pull Enable for Port D Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " PTDPE2 ,Pull Enable for Port D Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PTDPE1 ,Pull Enable for Port D Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PTDPE0 ,Pull Enable for Port D Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PTCPE7 ,Pull Enable for Port C Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PTCPE6 ,Pull Enable for Port C Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 21. " PTCPE5 ,Pull Enable for Port C Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PTCPE4 ,Pull Enable for Port C Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PTCPE3 ,Pull Enable for Port C Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PTCPE2 ,Pull Enable for Port C Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PTCPE1 ,Pull Enable for Port C Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PTCPE0 ,Pull Enable for Port C Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PTBPE7 ,Pull Enable for Port B Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PTBPE6 ,Pull Enable for Port B Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PTBPE5 ,Pull Enable for Port B Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PTBPE4 ,Pull Enable for Port B Bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTBPE3 ,Pull Enable for Port B Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PTBPE2 ,Pull Enable for Port B Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTBPE1 ,Pull Enable for Port B Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PTBPE0 ,Pull Enable for Port B Bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PTAPE7 ,Pull Enable for Port A Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTAPE6 ,Pull Enable for Port A Bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PTAPE5 ,Pull Enable for Port A Bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTAPE4 ,Pull Enable for Port A Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PTAPE3 ,Pull Enable for Port A Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTAPE2 ,Pull Enable for Port A Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTAPE1 ,Pull Enable for Port A Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTAPE0 ,Pull Enable for Port A Bit 0" "Disabled,Enabled"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PORT_PUEH,Port Pullup Enable High Register"
|
|
bitfld.long 0x00 31. " PTHPE7 ,Pull Enable for Port H Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PTHPE6 ,Pull Enable for Port H Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " PTHPE2 ,Pull Enable for Port H Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PTHPE1 ,Pull Enable for Port H Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PTHPE0 ,Pull Enable for Port H Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PTGPE3 ,Pull Enable for Port G Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PTGPE2 ,Pull Enable for Port G Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PTGPE1 ,Pull Enable for Port G Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PTGPE0 ,Pull Enable for Port G Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PTFPE7 ,Pull Enable for Port F Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PTFPE6 ,Pull Enable for Port F Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PTFPE5 ,Pull Enable for Port F Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PTFPE4 ,Pull Enable for Port F Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PTFPE3 ,Pull Enable for Port F Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PTFPE2 ,Pull Enable for Port F Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTFPE1 ,Pull Enable for Port F Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PTFPE0 ,Pull Enable for Port F Bit 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PTEPE7 ,Pull Enable for Port E Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTEPE6 ,Pull Enable for Port E Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTEPE5 ,Pull Enable for Port E Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PTEPE4 ,Pull Enable for Port E Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PTEPE3 ,Pull Enable for Port E Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTEPE2 ,Pull Enable for Port E Bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTEPE1 ,Pull Enable for Port E Bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTEPE0 ,Pull Enable for Port E Bit 0" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
bitfld.long 0x00 3. " PTC5 ,High Current Drive Capability of PTC5" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTC1 ,High Current Drive Capability of PTC1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
elif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8AVTG")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
elif cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
bitfld.long 0x00 7. " PTH1 ,High Current Drive Capability of PTH1" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PTH0 ,High Current Drive Capability of PTH0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PTE1 ,High Current Drive Capability of PTE1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PTE0 ,High Current Drive Capability of PTE0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PTD1 ,High Current Drive Capability of PTD1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTD0 ,High Current Drive Capability of PTD0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTB4 ,High Current Drive Capability of PTB4" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PORT_HDRVE,Port High Drive Enable Register"
|
|
bitfld.long 0x00 3. " PTD1 ,High Current Drive Capability of PTD1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PTD0 ,High Current Drive Capability of PTD0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PTB5 ,High Current Drive Capability of PTB5" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PTB4 ,High Current Drive Capability of PTB4" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "SIM (System Integration Module)"
|
|
base ad:0x40048000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SIM_SRSID,System Reset Status and ID Register"
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "KE0x,?..."
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,,,KEx4,,KEx6,?..."
|
|
hexmask.long.byte 0x00 20.--23. 1. " RevID ,Device Revision Number"
|
|
bitfld.long 0x00 16.--19. " PINID ,Device Pin ID" "8-pin,16-pin,20-pin,24-pin,32-pin,44-pin,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " SACKERR ,Stop Mode Acknowledge Error Reset" "No,Yes"
|
|
bitfld.long 0x00 11. " MDMAP ,MDM-AP System Reset Request" "No,Yes"
|
|
bitfld.long 0x00 10. " SW ,Software" "No,Yes"
|
|
bitfld.long 0x00 9. " LOCKUP ,Core Lockup" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POR ,Power-On Reset" "No,Yes"
|
|
bitfld.long 0x00 6. " PIN ,External Reset Pin" "No,Yes"
|
|
bitfld.long 0x00 5. " WDOG ,Watchdog (WDOG)" "No,Yes"
|
|
bitfld.long 0x00 2. " LOC ,Internal Clock Source Module Reset" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LVD ,Low Voltage Detect" "No,Yes"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "SIM_SOPT0,System Options Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DELAY ,FTM2 Trigger Delay"
|
|
rbitfld.long 0x00 23. " DLYACT ,FTM2 Trigger Delay Active" "Inactive,Active"
|
|
bitfld.long 0x00 20.--22. " ADHWT ,ADC Hardware Trigger Source" "RTC overflow,FTM0 init,FTM2 init,FTM2 match,PIT ch0 overflow,PIT ch1 overflow,ACMP0 out,ACMP1 out"
|
|
bitfld.long 0x00 19. " CLKOE ,Bus Clock Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " BUSREF ,BUS Clock Output select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 15. " TXDME ,UART0_TX Modulation Select" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " FTMSYNC ,FTM2 Synchronization Select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " RXDCE ,UART0_RX Capture Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ACIC ,Analog Comparator to Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RTCC ,Real-Time Counter Capture" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RXDFE ,UART0 RxD Filter Select" "Connected,Filtered by ACMP0,Filtered by ACMP1,?..."
|
|
bitfld.long 0x00 5. " ACTRG ,ACMP Trigger FTM2 selection" "ACMP0 out,ACMP1 out"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SWDE ,Single Wire Debug Port Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RSTPE ,PTA5/IRQ/FTM0_CLK/RESET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIE ,PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 Pin Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SIM_SOPT1,System Options Register"
|
|
bitfld.long 0x04 4.--5. " UARTPWTS ,PWT UART RX select" "UART0_RX,UART1_RX,UART2_RX,?..."
|
|
bitfld.long 0x04 3. " ACPWTS ,PWT ACMP_OUT select" "ACMP1_OUT,ACMP0_OUT"
|
|
bitfld.long 0x04 1. " I2C0OINV ,I2C0 Output Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " I2C04WEN ,I2C0 4-Wire Interface Enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SIM_PINSEL0,Pin Selection Register"
|
|
bitfld.long 0x00 30.--31. " PWTCLKPS ,PWT TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
bitfld.long 0x00 28.--29. " FTM2CLKPS ,FTM2 TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
bitfld.long 0x00 26.--27. " FTM1CLKPS ,FTM1 TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
bitfld.long 0x00 24.--25. " FTM0CLKPS ,FTM0 TCLK Pin Select" "TCLK0,TCLK1,TCLK2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " FTM1PS1 ,FTM1_CH1 Port Pin Select" "PTC5,PTC7"
|
|
bitfld.long 0x00 10. " FTM1PS0 ,FTM1_CH0 Port Pin Select" "PTC4,PTC2"
|
|
bitfld.long 0x00 9. " FTM0PS1 ,FTM0_CH1 Port Pin Select" "PTA1,PTB3"
|
|
bitfld.long 0x00 8. " FTM0PS0 ,FTM0_CH0 Port Pin Select" "PTA0,PTB2"
|
|
textline " "
|
|
bitfld.long 0x00 7. " UART0PS ,UART0 Pin Select" "PTB[0-1],PTA[2-3]"
|
|
bitfld.long 0x00 6. " SPI0PS ,SPI0 Pin Select" "PTB[2-5],PTE[0-3]"
|
|
bitfld.long 0x00 5. " I2C0PS ,I2C0 Port Pin Select" "PTA[2-3],PTB[6-7]"
|
|
bitfld.long 0x00 4. " RTCPS ,RTCO Pin Select" "PTC4,PTC5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " IRQPS ,IRQ Port Pin Select" "PTA5,PTI0,PTI1,PTI2,PTI3,PTI4,PTI5,PTI6"
|
|
line.long 0x04 "SIM_PINSEL1,Pin Selection Register 1"
|
|
bitfld.long 0x04 16. " MSCANPS ,MSCAN Pin Select(Transmitt/Receive)" "PTC7/PTC6,PTE7/PTH2"
|
|
bitfld.long 0x04 15. " PWTIN1PS ,PWTIN1 Pin Select" "PTB0,PTH7"
|
|
bitfld.long 0x04 14. " PWTIN0PS ,PWTIN0 Pin Select" "PTD5,PTE2"
|
|
bitfld.long 0x04 13. " UART2PS ,UART2 Pin Select(Transmitt/Receive)" "PTD7/PTD6,PTI1/PTH0"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UART1PS ,UART1 Pin Select(Transmitt/Receive)" "PTC7/PTC6,PTF3/PTF2"
|
|
bitfld.long 0x04 11. " SPI1PS ,SPI1 Pin Select" "PTD[0-3],PTG[4-7]"
|
|
bitfld.long 0x04 10. " I2C1PS ,I2C1 Pin Select(SCL/SDA)" "PTE1/PTE0,PTH4/PTH3"
|
|
bitfld.long 0x04 9. " FTM2PS5 ,FTM2 Channel 5 Pin Select" "PTB5,PTG7"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FTM2PS4 ,FTM2 Channel4 Pin Select" "PTB4,PTG6"
|
|
bitfld.long 0x04 6.--7. " FTM2PS3 ,FTM2 Channel 3 Pin Select" "PTC3,PTD1,PTG5,?..."
|
|
bitfld.long 0x04 4.--5. " FTM2PS2 ,FTM2 Channel 2 Pin Select" "PTC2,PTD0,PTG4,?..."
|
|
bitfld.long 0x04 2.--3. " FTM2PS1 ,FTM2 Channel 1 Pin Select" "PTC1,PTH1,PTF1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " FTM2PS0 ,FTM2 Channel 0 Pin Select" "PTC0,PTH0,PTF0,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SIM_SCGC,System Clock Gating Control Register"
|
|
bitfld.long 0x00 31. " ACMP1 ,ACMP1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACMP0 ,ACMP0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADC ,ADC Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IRQ ,IRQ Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KBI1 ,KBI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBI0 ,KBI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UART2 ,UART2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " UART1 ,UART1 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SPI1 ,SPI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI0 ,SPI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " I2C1 ,I2C1 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " I2C0 ,I2C0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MSCAN ,MSCAN Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SWD ,SWD Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FLASH ,Flash Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CRC ,CRC Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FTM2 ,FTM2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FTM1 ,FTM1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FTM0 ,FTM0 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PWT ,PWT Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PIT ,PIT Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RTC ,RTC Clock Gate Control" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x0B
|
|
line.long 0x00 "SIM_UUIDL,Universally Unique Identifier Low Register"
|
|
line.long 0x04 "SIM_UUIDML,Universally Unique Identifier Middle Low Register"
|
|
line.long 0x08 "SIM_UUIDMH,Universally Unique Identifier High Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ID[80:64] ,Universally Unique Identifier"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SIM_CLKDIV,Clock Divider Register"
|
|
bitfld.long 0x00 28.--29. " OUTDIV1 ,Clock 1 output divider value" "ICSOUTCLK,ICSOUTCLK/2,ICSOUTCLK/3,ICSOUTCLK/4"
|
|
bitfld.long 0x00 24. " OUTDIV2 ,Clock 2 output divider value" "Not divided,/2"
|
|
bitfld.long 0x00 20. " OUTDIV3 ,Clock 3 output divider value" "ICSOUTCLK,ICSOUTCLK/2"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SIM (System Integration Module)"
|
|
base ad:0x40048000
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SIM_SRSID,System Reset Status and ID Register"
|
|
bitfld.long 0x00 28.--31. " FAMID ,Kinetis family ID" "KE0x,?..."
|
|
sif cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,,,KEx4,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,KEx2,?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--23. 1. " RevID ,Device Revision Number"
|
|
bitfld.long 0x00 16.--19. " PINID ,Device Pin ID" "8-pin,16-pin,20-pin,24-pin,32-pin,44-pin,48-pin,64-pin,80-pin,,100-pin,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " SACKERR ,Stop Mode Acknowledge Error Reset" "No,Yes"
|
|
bitfld.long 0x00 11. " MDMAP ,MDM-AP System Reset Request" "No,Yes"
|
|
bitfld.long 0x00 10. " SW ,Software" "No,Yes"
|
|
bitfld.long 0x00 9. " LOCKUP ,Core Lockup" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POR ,Power-On Reset" "No,Yes"
|
|
bitfld.long 0x00 6. " PIN ,External Reset Pin" "No,Yes"
|
|
bitfld.long 0x00 5. " WDOG ,Watchdog (WDOG)" "No,Yes"
|
|
bitfld.long 0x00 2. " LOC ,Internal Clock Source Module Reset" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LVD ,Low Voltage Detect" "No,Yes"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SIM_SOPT,System Options Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DELAY ,FTM2 Trigger Delay"
|
|
rbitfld.long 0x00 23. " DLYACT ,FTM2 Trigger Delay Active" "Inactive,Active"
|
|
bitfld.long 0x00 20.--22. " ADHWT ,ADC Hardware Trigger Source" "RTC overflow,FTM0 init,FTM2 init,FTM2 match,PIT ch0 overflow,PIT ch1 overflow,ACMP0 out,ACMP1 out"
|
|
bitfld.long 0x00 19. " CLKOE ,Bus Clock Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " BUSREF ,BUS Clock Output select" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 15. " TXDME ,UART0_TX Modulation Select" "Not selected,FTM0"
|
|
bitfld.long 0x00 14. " FTMSYNC ,FTM2 Synchronization Select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " RXDCE ,UART0_RX Capture Select" "Not selected,FTM0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RXDFE ,UART0 RxD Filter Select" "Connected,Filtered by ACMP0,Filtered by ACMP1,"
|
|
bitfld.long 0x00 6.--7. " FTMIC ,FTM0CH0 Input Capture Source" "FTM0_CH0 pin,ACMP0 OUT,ACMP1 OUT,RTC overflow"
|
|
bitfld.long 0x00 5. " ACTRG ,ACMP Trigger FTM2 selection" "ACMP0 out,ACMP1 out"
|
|
bitfld.long 0x00 3. " SWDE ,Single Wire Debug Port Pin Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTPE ,PTA5/IRQ/FTM0_CLK/RESET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIE ,PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 Pin Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SIM_SOPT,System Options Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DELAY ,FTM2 Trigger Delay"
|
|
rbitfld.long 0x00 23. " DLYACT ,FTM2 Trigger Delay Active" "Inactive,Active"
|
|
bitfld.long 0x00 19. " CLKOE ,Bus Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " BUSREF ,BUS Clock Output select" "Bus,Bus/2,Bus/4,Bus/8,Bus/16,Bus/32,Bus/64,Bus/128"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TXDME ,UART0_TX Modulation Select" "Not selected,FTM0"
|
|
bitfld.long 0x00 14. " FTMSYNC ,FTM2 Synchronization Select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " RXDFE ,UART0_RX Filter Select" "Not selected,ACMP"
|
|
bitfld.long 0x00 12. " RXDCE ,UART0_RX Capture Select" "Not selected,FTM0"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ACIC ,Analog Comparator to Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RTCC ,Real-Time Counter Capture" "Disabled,FTM1"
|
|
bitfld.long 0x00 8.--9. " ADHWT ,ADC Hardware Trigger Source" "RTC_overflow,PIT_overflow,FTM2_init,FTM2_match"
|
|
bitfld.long 0x00 3. " SWDE ,Single Wire Debug Port Pin Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTPE ,PTA5/IRQ/FTM0_CLK/RESET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NMIE ,PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 Pin Enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SIM_PINSEL,Pin Selection Register"
|
|
bitfld.long 0x00 31. " PWTCLKPS ,PWT TCLK Pin Select" "TCLK1,TCLK2"
|
|
bitfld.long 0x00 30. " FTM2CLKPS ,FTM2 TCLK Pin Select" "TCLK1,TCLK2"
|
|
bitfld.long 0x00 28. " FTM0CLKPS ,FTM0 TCLK Pin Select" "TCLK1,TCLK2"
|
|
bitfld.long 0x00 15. " FTM2PS3 ,FTM2_CH3 Port Pin Select" "PTC3,PTC5"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FTM2PS2 ,FTM2_CH2 Port Pin Select" "PTC2,PTC4"
|
|
bitfld.long 0x00 9. " FTM0PS1 ,FTM0_CH1 Port Pin Select" "PTA1,PTB3"
|
|
bitfld.long 0x00 8. " FTM0PS0 ,FTM0_CH0 Port Pin Select" "PTA0,PTB2"
|
|
bitfld.long 0x00 7. " UART0PS ,UART0 Pin Select" "PTB[0-1],PTA[2-3]"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI0PS ,SPI0 Pin Select" "PTB[2-5],PTA[6-7]_&_PTB[0-1]"
|
|
bitfld.long 0x00 5. " I2C0PS ,I2C0 Port Pin Select" "PTA[2-3],PTB[6-7]"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SIM_PINSEL,Pin Selection Register"
|
|
bitfld.long 0x00 15. " FTM2PS3 ,FTM2_CH3 Port Pin Select" "PTC3,PTD1"
|
|
bitfld.long 0x00 14. " FTM2PS2 ,FTM2_CH2 Port Pin Select" "PTC2,PTD0"
|
|
bitfld.long 0x00 13. " FTM2PS1 ,FTM2_CH1 Port Pin Select" "PTC1,PTH1"
|
|
bitfld.long 0x00 12. " FTM2PS0 ,FTM2_CH0 Port Pin Select" "PTC0,PTH0"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FTM1PS1 ,FTM1_CH1 Port Pin Select" "PTC5,PTE7"
|
|
bitfld.long 0x00 10. " FTM1PS0 ,FTM1_CH0 Port Pin Select" "PTC4,PTH2"
|
|
bitfld.long 0x00 9. " FTM0PS1 ,FTM0_CH1 Port Pin Select" "PTA1,PTB3"
|
|
bitfld.long 0x00 8. " FTM0PS0 ,FTM0_CH0 Port Pin Select" "PTA0,PTB2"
|
|
textline " "
|
|
bitfld.long 0x00 7. " UART0PS ,UART0 Pin Select" "PTB0/PTB1,PTA2/PTA3"
|
|
bitfld.long 0x00 6. " SPI0PS ,SPI0 Pin Select" "PTB[2-5],PTE[0-3]"
|
|
bitfld.long 0x00 5. " I2C0PS ,I2C0 Port Pin Select" "PTA3/PTA2,PTB7/PTB6"
|
|
bitfld.long 0x00 4. " RTCPS ,RTCO Pin Select" "PTC4,PTC5"
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIM_SCGC,System Clock Gating Control Register"
|
|
bitfld.long 0x00 31. " ACMP1 ,ACMP1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACMP0 ,ACMP0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADC ,ADC Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IRQ ,IRQ Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KBI1 ,KBI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBI0 ,KBI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI0 ,SPI0 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I2C ,I2C Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SWD ,SWD Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FLASH ,Flash Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CRC ,CRC Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FTM2 ,FTM2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FTM0 ,FTM0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PWT ,PWT Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PIT ,PIT Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RTC ,RTC Clock Gate Control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIM_SCGC,System Clock Gating Control Register"
|
|
bitfld.long 0x00 31. " ACMP1 ,ACMP1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACMP0 ,ACMP0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ADC ,ADC Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IRQ ,IRQ Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KBI1 ,KBI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBI0 ,KBI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UART2 ,UART2 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " UART1 ,UART1 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " UART0 ,UART0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SPI1 ,SPI1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI0 ,SPI0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " I2C ,I2C Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SWD ,SWD Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FLASH ,Flash Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CRC ,CRC Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FTM2 ,FTM2 Clock Gate Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FTM1 ,FTM1 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FTM0 ,FTM0 Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PIT ,PIT Clock Gate Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RTC ,RTC Clock Gate Control" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SIM_UUIDL,Universally Unique Identifier Low Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "SIM_UUIDML,Universally Unique Identifier Middle Low Register"
|
|
line.long 0x04 "SIM_UUIDMH,Universally Unique Identifier High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ID[80:64] ,Universally Unique Identifier"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SIM_CLKDIV,Clock Divider Register"
|
|
bitfld.long 0x00 28.--29. " OUTDIV1 ,Clock 1 output divider value" "ICSOUTCLK,ICSOUTCLK/2,ICSOUTCLK/3,ICSOUTCLK/4"
|
|
bitfld.long 0x00 24. " OUTDIV2 ,Clock 2 output divider value" "Not divided,/2"
|
|
bitfld.long 0x00 20. " OUTDIV3 ,Clock 3 output divider value" "ICSOUTCLK,ICSOUTCLK/2"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SIM_UUIDH,Universally Unique Identifier High Register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SIM_BUSDIV,BUS Clock Divider Register"
|
|
bitfld.long 0x00 0. " BUSDIV ,BUS Clock Divider" "ICSOUTCLK,ICSOUTCLK/2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x4007D000
|
|
width 12.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "PMC_SPMSC1,System Power Management Status and Control 1 Register"
|
|
rbitfld.byte 0x00 7. " LVWF ,Low-Voltage Warning Flag" "No warning,Warning"
|
|
bitfld.byte 0x00 6. " LVWACK ,Low-Voltage Warning Acknowledge [read/write]" "Not occurred/No effect,Occurred/Acknowledge"
|
|
bitfld.byte 0x00 5. " LVWIE ,Low-Voltage Warning Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LVDRE ,Low-Voltage Detect Reset Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LVDSE ,Low-Voltage Detect Stop Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LVDE ,Low-Voltage Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " BGBE ,Bandgap Buffer Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "PMC_SPMSC2,System Power Management Status and Control 2 Register"
|
|
bitfld.byte 0x01 6. " LVDV ,Low-Voltage Detect Voltage Select" "V_LVDL,V_LVDH"
|
|
bitfld.byte 0x01 4.--5. " LVWV ,Low-Voltage Warning Voltage Select" "V_LVW1,V_LVW2,V_LVW3,V_LVW4"
|
|
width 0xB
|
|
tree.end
|
|
tree "MCM (Miscellaneous Control Module)"
|
|
base ad:0xF0003008
|
|
width 11.
|
|
rgroup.word 0x00++0x03
|
|
line.word 0x00 "MCM_PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
bitfld.word 0x00 7. " ASC7 ,Crossbar Switch Slave Input Port 7 Connection Present" "Absent,Present"
|
|
bitfld.word 0x00 6. " ASC6 ,Crossbar Switch Slave Input Port 6 Connection Present" "Absent,Present"
|
|
bitfld.word 0x00 5. " ASC5 ,Crossbar Switch Slave Input Port 5 Connection Present" "Absent,Present"
|
|
bitfld.word 0x00 4. " ASC4 ,Crossbar Switch Slave Input Port 4 Connection Present" "Absent,Present"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ASC3 ,Crossbar Switch Slave Input Port 3 Connection Present" "Absent,Present"
|
|
bitfld.word 0x00 2. " ASC2 ,Crossbar Switch Slave Input Port 2 Connection Present" "Absent,Present"
|
|
bitfld.word 0x00 1. " ASC1 ,Crossbar Switch Slave Input Port 1 Connection Present" "Absent,Present"
|
|
bitfld.word 0x00 0. " ASC0 ,Crossbar Switch Slave Input Port 0 Connection Present" "Absent,Present"
|
|
line.word 0x02 "MCM_PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
bitfld.word 0x02 7. " AMC7 ,Crossbar Switch Master Input Port 7 Connection Present" "Absent,Present"
|
|
bitfld.word 0x02 6. " AMC6 ,Crossbar Switch Master Input Port 6 Connection Present" "Absent,Present"
|
|
bitfld.word 0x02 5. " AMC5 ,Crossbar Switch Master Input Port 5 Connection Present" "Absent,Present"
|
|
bitfld.word 0x02 4. " AMC4 ,Crossbar Switch Master Input Port 4 Connection Present" "Absent,Present"
|
|
textline " "
|
|
bitfld.word 0x02 3. " AMC3 ,Crossbar Switch Master Input Port 3 Connection Present" "Absent,Present"
|
|
bitfld.word 0x02 2. " AMC2 ,Crossbar Switch Master Input Port 2 Connection Present" "Absent,Present"
|
|
bitfld.word 0x02 1. " AMC1 ,Crossbar Switch Master Input Port 1 Connection Present" "Absent,Present"
|
|
bitfld.word 0x02 0. " AMC0 ,Crossbar Switch Master Input Port 0 Connection Present" "Absent,Present"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MCM_PLACR,Platform Control Register"
|
|
bitfld.long 0x00 16. " ESFC ,Enable Stalling Flash Controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DFCS ,Disable Flash Controller Speculation" "No,Yes"
|
|
bitfld.long 0x00 14. " EFDS ,Enable Flash Data Speculation" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DFCC ,Disable Flash Controller Cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DFCIC ,Disable Flash Controller Instruction Caching" "No,Yes"
|
|
bitfld.long 0x00 11. " DFCDA ,Disable Flash Controller Data Caching" "No,Yes"
|
|
bitfld.long 0x00 10. " CFCC ,Clear Flash Controller Cache" "Not cleared,Cleared"
|
|
width 0xB
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x40052000
|
|
width 13.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "WDOG_CS1,Watchdog Control and Status Register 1"
|
|
bitfld.byte 0x00 7. " EN ,Watchdog Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " INT ,Watchdog Interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " UPDATE ,Allow updates" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 3.--4. " TST ,Watchdog Test" "Disabled,User enabled,Test enabled(WDOG_CNTL),Test enabled(WDOG_CNTH)"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DBG ,Debug Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " WAIT ,Wait Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " STOP ,Stop Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "WDOG_CS2,Watchdog Control and Status Register 2"
|
|
bitfld.byte 0x01 7. " WIN ,Watchdog Window" "Disabled,Enabled"
|
|
eventfld.byte 0x01 6. " FLG ,Watchdog Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " PRES ,Watchdog Prescalar" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0.--1. " CLK ,Watchdog Clock" "BUSclk,LPOCLK,ICSIRCLK,External"
|
|
rgroup.byte 0x02++0x01
|
|
line.byte 0x00 "WDOG_CNTH,Watchdog Counter Register: High"
|
|
line.byte 0x01 "WDOG_CNTL,Watchdog Counter Register: Low"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
hgroup.byte 0x04++0x01
|
|
hide.byte 0x00 "WDOG_TOVALH,Watchdog Timeout Value Register: High"
|
|
hide.byte 0x01 "WDOG_TOVALL,Watchdog Timeout Value Register: Low"
|
|
else
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "WDOG_TOVALH,Watchdog Timeout Value Register: High"
|
|
line.byte 0x01 "WDOG_TOVALL,Watchdog Timeout Value Register: Low"
|
|
endif
|
|
if ((per.b(ad:0x40052000+0x01)&0x80)==0x80)
|
|
group.byte 0x06++0x01
|
|
line.byte 0x00 "WDOG_WINH,Watchdog Window Register: High"
|
|
line.byte 0x01 "WDOG_WINL,Watchdog Window Register: Low"
|
|
else
|
|
hgroup.byte 0x06++0x01
|
|
hide.byte 0x00 "WDOG_WINH,Watchdog Window Register: High"
|
|
hide.byte 0x01 "WDOG_WINL,Watchdog Window Register: Low"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "FTMRE (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 9.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "FCCOBIX,Flash CCOB Index Register"
|
|
bitfld.byte 0x00 0.--2. " CCOBIX ,Common Command Register Index" "FCMD[7:0]+Global addr[23:16],Global addr[15:0],Data 0[15:0],Data 1[15:0],Data 2[15:0],Data 3[15:0],?..."
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor Key Security Enable Bits" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash Security Bits" "Secured,Secured,Unsecured,Secured"
|
|
if ((per.b(ad:0x40020000+0x05)&0x80)==0x80)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
rbitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,20.6-21.6,21.6-22.6,22.6-23.6,23.6-24.6,24.6-25.6,?..."
|
|
else
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
bitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,20.6-21.6,21.6-22.6,22.6-23.6,23.6-24.6,24.6-25.6,?..."
|
|
endif
|
|
sif cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
eventfld.byte 0x00 7. " CCIF ,Command Complete Interrupt Flag" "Not completed,Completed"
|
|
eventfld.byte 0x00 5. " ACCERR ,Flash Access Error Flag" "Not detected,Detected"
|
|
eventfld.byte 0x00 4. " FPVIOL ,Flash Protection Violation Flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " MGBUSY ,Memory Controller Busy Flag" "Idle,Busy"
|
|
rbitfld.byte 0x00 1. " MGSTAT1 ,Memory Controller Command Completion Status Flag 1 (Any Error)" "No error,Error"
|
|
rbitfld.byte 0x00 0. " MGSTAT0 ,Memory Controller Command Completion Status Flag 0 (Non correctable Error)" "No error,Error"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
bitfld.byte 0x00 7. " CCIF ,Command Complete Interrupt Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 5. " ACCERR ,Flash Access Error Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 4. " FPVIOL ,Flash Protection Violation Flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " MGBUSY ,Memory Controller Busy Flag" "Idle,Busy"
|
|
rbitfld.byte 0x00 1. " MGSTAT1 ,Memory Controller Command Completion Status Flag 1 (Any Error)" "No error,Error"
|
|
rbitfld.byte 0x00 0. " MGSTAT0 ,Memory Controller Command Completion Status Flag 0 (Non correctable Error)" "No error,Error"
|
|
endif
|
|
group.byte 0x07++0x02
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. " CCIE ,Command Complete Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 5. " ERSAREQ ,Debugger Mass Erase Request" "Not requested,Requested"
|
|
line.byte 0x01 "FCCOBLO,Flash Common Command Object Register: Low"
|
|
line.byte 0x02 "FCCOBHI,Flash Common Command Object Register: High"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
if ((per.b(ad:0x40020000+0x0B)&0x80)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Unprotection Higher Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Unprotection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x04)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Unprotection Higher Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Unprotection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x80)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x80)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x04)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x20)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Unprotection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Unprotection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x04)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x20)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Unprotection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Unprotection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x80)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x20)==0x20)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
endif
|
|
else
|
|
if ((per.b(ad:0x40020000+0x0B)&0x80)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Unprotection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x00)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x04)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Unprotection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
elif ((per.b(ad:0x40020000+0x0B)&0x80)==0x80)&&((per.b((ad:0x40020000)+0x0B)&0x04)==0x00)
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
else
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
endif
|
|
endif
|
|
rgroup.byte 0x0F++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "FTMRH (Flash Memory Module)"
|
|
base ad:0x40020000
|
|
width 9.
|
|
if ((per.b(ad:0x40020000+0x06)&0x80)==0x80)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
rbitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,..."
|
|
else
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "FCLKDIV,Flash Clock Divider Register"
|
|
bitfld.byte 0x00 7. " FDIVLD ,Clock Divider Loaded" "Not written,Written"
|
|
bitfld.byte 0x00 6. " FDIVLCK ,Clock Divider Locked" "Not locked,Locked"
|
|
bitfld.byte 0x00 0.--5. " FDIV ,Clock Divider Bits" "1.0-1.6,1.6-2.6,2.6-3.6,3.6-4.6,4.6-5.6,5.6-6.6,6.6-7.6,7.6-8.6,8.6-9.6,9.6-10.6,10.6-11.6,11.6-12.6,12.6-13.6,13.6-14.6,14.6-15.6,15.6-16.6,16.6-17.6,17.6-18.6,18.6-19.6,19.6-20.6,..."
|
|
endif
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor Key Security Enable Bits" "Disabled,Disabled,Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--1. " SEC ,Flash Security Bits" "Secured,Secured,Unsecured,Secured"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "FCCOBIX,Flash CCOB Index Register"
|
|
bitfld.byte 0x00 0.--2. " CCOBIX ,Common Command Register Index" "FCMD[7:0]+Global addr[23:16],Global addr[15:0],Data 0[15:0],Data 1[15:0],Data 2[15:0],Data 3[15:0],..."
|
|
group.byte 0x04++0x02
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. " CCIE ,Command Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " IGNSF ,Ignore Single Bit Fault" "Reported,Not reported"
|
|
bitfld.byte 0x00 1. " FDFD ,Force Double Bit Fault Detect" "DFDIF,DFDIF+interrupt"
|
|
bitfld.byte 0x00 0. " FSFD ,Force Single Bit Fault Detect" "SFDIF,SFDIF+interrupt"
|
|
line.byte 0x01 "FERCNFG,Flash Error Configuration Register"
|
|
bitfld.byte 0x01 1. " DFDIE ,Double Bit Fault Detect Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SFDIE ,Single Bit Fault Detect Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "FSTAT,Flash Status Register"
|
|
bitfld.byte 0x02 7. " CCIF ,Command Complete Interrupt Flag" "Not completed,Completed"
|
|
bitfld.byte 0x02 5. " ACCERR ,Flash Access Error Flag" "Not detected,Detected"
|
|
eventfld.byte 0x02 4. " FPVIOL ,Flash Protection Violation Flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.byte 0x02 3. " MGBUSY ,Memory Controller Busy Flag" "Idle,Busy"
|
|
rbitfld.byte 0x02 0.--1. " MGSTAT ,Memory Controller Command Completion Status Flag" "No error,Non-correctable error,Any error,Non-correctable/Any"
|
|
if ((per.b(ad:0x40020000+0x04)&0x10)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
eventfld.byte 0x00 1. " DFDIF ,Double Bit Fault Detect Interrupt Flag" "Not detected,Detected"
|
|
eventfld.byte 0x00 0. " SFDIF ,Single Bit Fault Detect Interrupt Flag" "Not detected,Detected"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
eventfld.byte 0x00 1. " DFDIF ,Double Bit Fault Detect Interrupt Flag" "Not detected,Detected"
|
|
endif
|
|
if ((per.b(ad:0x40020000+0x08)&0x04)==0x04)&&((per.b((ad:0x40020000)+0x08)&0x20)==0x20)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "No,Yes"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x08)&0x04)==0x00)&&((per.b((ad:0x40020000)+0x08)&0x20)==0x20)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "Enabled,Disabled"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
elif ((per.b(ad:0x40020000+0x08)&0x04)==0x04)&&((per.b((ad:0x40020000)+0x08)&0x20)==0x00)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "Enabled,Disabled"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "FPROT,Flash Protection Register"
|
|
bitfld.byte 0x00 7. " FPOPEN ,Flash Protection Operation Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FPHDIS ,Flash Protection Higher Address Range Disable" "Enabled,Disabled"
|
|
rbitfld.byte 0x00 3.--4. " FPHS ,Flash Protection Higher Address Size" "1 KB,2 KB,4 KB,8 KB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FPLDIS ,Flash Protection Lower Address Range Disable" "Enabled,Disabled"
|
|
rbitfld.byte 0x00 0.--1. " FPLS ,Flash Protection Lower Address Size" "2 KB,4 KB,8 KB,16 KB"
|
|
endif
|
|
group.byte 0x09++0x02
|
|
line.byte 0x00 "EEPROT,EEPROM Protection Register"
|
|
bitfld.byte 0x00 7. " DPOPEN ,EEPROM Protection Control" "Enabled,Disabled"
|
|
bitfld.byte 0x00 0.--2. " DPS ,EEPROM Protection Size" "32 bytes,64 bytes,96 bytes,128 bytes,160 bytes,192 bytes,224 bytes,256 bytes"
|
|
line.byte 0x01 "FCCOBHI,Flash Common Command Object Register:High"
|
|
line.byte 0x02 "FCCOBLO,Flash Common Command Object Register: Low"
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "ICS (Internal Clock Source)"
|
|
base ad:0x40064000
|
|
width 8.
|
|
if ((per.b(ad:0x40065000)&0x04)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICS_C1,ICS Control Register 1"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock Source Select" "Output FLL,Internal,External,?..."
|
|
bitfld.byte 0x00 3.--5. " RDIV ,Reference Divider" "1,2,4,8,16,32,64,128"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal Reference Select" "External,Internal"
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal Reference Clock Enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " REFSTEN ,Internal Reference Stop Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICS_C1,ICS Control Register 1"
|
|
bitfld.byte 0x00 6.--7. " CLKS ,Clock Source Select" "Output FLL,Internal,External,"
|
|
bitfld.byte 0x00 3.--5. " RDIV ,Reference Divider" "32,64,128,256,512,1024,,"
|
|
bitfld.byte 0x00 2. " IREFS ,Internal Reference Select" "External,Internal"
|
|
bitfld.byte 0x00 1. " IRCLKEN ,Internal Reference Clock Enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " REFSTEN ,Internal Reference Stop Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x01++0x03
|
|
line.byte 0x00 "ICS_C2,ICS Control Register 2"
|
|
bitfld.byte 0x00 5.--7. " BDIV ,Bus Frequency Divider" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 4. " LP ,Low Power Select" "FLL enabled,FLL disabled"
|
|
line.byte 0x01 "ICS_C3,ICS Control Register 3"
|
|
line.byte 0x02 "ICS_C4,ICS Control Register 4"
|
|
bitfld.byte 0x02 7. " LOLIE ,Loss of Lock Interrupt" "Not requested,Requested"
|
|
bitfld.byte 0x02 5. " CME ,Clock Monitor Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SCFTRIM ,Slow Internal Reference Clock Fine Trim" "Decrease,Increase"
|
|
line.byte 0x03 "ICS_S,ICS Status Register"
|
|
eventfld.byte 0x03 7. " LOLS ,Loss of Lock Status" "Not lost,Lost"
|
|
rbitfld.byte 0x03 6. " LOCK ,Lock Status" "Unlocked,Locked"
|
|
rbitfld.byte 0x03 4. " IREFST ,Internal Reference Status" "External,Internal"
|
|
rbitfld.byte 0x03 2.--3. " CLKST ,Clock Mode Status" "Output FLL,Internal,External,?..."
|
|
width 0xB
|
|
tree.end
|
|
tree "OSC (Oscillator)"
|
|
base ad:0x40065000
|
|
width 8.
|
|
if (((per.b(ad:0x40065000)&0x80)==0x80)||((per.b(ad:0x40064000)&0xC0)==0x80))
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "OSC_CR,OSC Control Register"
|
|
bitfld.byte 0x00 7. " OSCEN ,OSC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " OSCSTEN ,OSC Enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OSCOS ,OSC Output Select" "External,Oscillator"
|
|
rbitfld.byte 0x00 2. " RANGE ,Frequency Range Select" "Low,High"
|
|
bitfld.byte 0x00 1. " HGO ,High Gain Oscillator Select" "Low-power,High-gain"
|
|
rbitfld.byte 0x00 0. " OSCINIT ,OSC Initialization" "Not completed,Completed"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "OSC_CR,OSC Control Register"
|
|
bitfld.byte 0x00 7. " OSCEN ,OSC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " OSCSTEN ,OSC Enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " OSCOS ,OSC Output Select" "External,Oscillator"
|
|
bitfld.byte 0x00 2. " RANGE ,Frequency Range Select" "Low,High"
|
|
bitfld.byte 0x00 1. " HGO ,High Gain Oscillator Select" "Low-power,High-gain"
|
|
rbitfld.byte 0x00 0. " OSCINIT ,OSC Initialization" "Not completed,Completed"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40032000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " HU ,CRC High Upper Byte"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " HL ,CRC High Lower Byte"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " LU ,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " LL ,CRC Low Lower Byte"
|
|
if ((per.l((ad:0x40032000)+0x08)&0x01000000)==0x01000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " HIGH ,High Polynominal Half-word"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " LOW ,Low Polynominal Half-word"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " LOW ,Low Polynominal Half-word"
|
|
endif
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_CTRL,CRC Control register"
|
|
bitfld.long 0x00 30.--31. " TOT ,Type Of Transpose For Writes" "No transposition,Only bits transposed,Bits & bytes transposed,Only bytes transposed"
|
|
bitfld.long 0x00 28.--29. " TOTR ,Type Of Transpose For Read" "No transposition,Only bits transposed,Bits & bytes transposed,Only bytes transposed"
|
|
bitfld.long 0x00 26. " FXOR ,Complement Read Of CRC Data Register" "No XOR,Invert/Complement"
|
|
bitfld.long 0x00 25. " WAS ,Write CRC Data Register As Seed" "Data values,Seed values"
|
|
bitfld.long 0x00 24. " TCRC ,Width of CRC protocol" "16bit,32bit"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IRQ (Interrupt)"
|
|
base ad:0x40031000
|
|
width 8.
|
|
if ((per.b(ad:0x40031000)&0x10)==0x10)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "IRQ_SC,Interrupt Pin Request Status and Control Register"
|
|
bitfld.byte 0x00 6. " IRQPDD ,Interrupt Request (IRQ) Pull Device Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " IRQEDG ,Interrupt Request (IRQ) Edge Select" "Falling edge/Low level,Rising edge/High level"
|
|
bitfld.byte 0x00 4. " IRQPE ,IRQ Pin Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " IRQF ,IRQ Flag" "No requested,Detected"
|
|
bitfld.byte 0x00 2. " IRQACK ,IRQ Acknowledge" "No effect,Clear IRQF"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRQIE ,IRQ Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IRQMOD ,IRQ Detection Mode" "Both edges,Both edges and levels"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "IRQ_SC,Interrupt Pin Request Status and Control Register"
|
|
bitfld.byte 0x00 5. " IRQEDG ,Interrupt Request (IRQ) Edge Select" "Falling edge/Low level,Rising edge/High level"
|
|
bitfld.byte 0x00 4. " IRQPE ,IRQ Pin Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 3. " IRQF ,IRQ Flag" "No requested,Detected"
|
|
bitfld.byte 0x00 2. " IRQACK ,IRQ Acknowledge" "No effect,Clear IRQF"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IRQIE ,IRQ Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " IRQMOD ,IRQ Detection Mode" "Both edges,Both edges and levels"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "ADC (A/C Control Registers)"
|
|
base ad:0x4003B000
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "ADC_SC1,Status and Control Register 1"
|
|
rbitfld.long 0x00 7. " COCO ,Conversion Complete Flag" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Interrupt disabled,Interrupt enabled"
|
|
bitfld.long 0x00 5. " ADCO ,Continuous Conversion Enable" "Disabled,Enabled"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "AD0,AD1,,,AD4,AD5,AD6,AD7,,,,,Vss,Vss,Vss,Vss,Vss,Vss,Vss,Vss,,,Temperature Sensor,Bandgap,,,,,,VREFH,VREFL,Module disabled"
|
|
elif cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,Vss,Vss,Vss,Vss,Vss,Vss,Vss,Vss,,,Temperature Sensor,Bandgap,,,,,,VREFH,VREFL,Module disabled"
|
|
elif cpuis("S9KEAZN16AMLC")||cpuis("S9KEAZN32AMLC")||cpuis("S9KEAZN64AMLC")||cpuis("S9KEAZN64ACLC")||cpuis("S9KEAZN16ACLC")||cpuis("S9KEAZN32ACLC")||cpuis("S9KEAZN32AVLC")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,Vss,Vss,Vss,Vss,,,Temperature Sensor,Bandgap,,,,,,VREFH,VREFL,Module disabled"
|
|
elif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 0.--4. " ADCH ,Input Channel Select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,Vss,Vss,Vss,Vss,,,Temperature Sensor,Bandgap,,,,,,VREFH,VREFL,Module disabled"
|
|
endif
|
|
line.long 0x04 "ADC_SC2,Status and Control Register 2"
|
|
rbitfld.long 0x04 7. " ADACT ,Conversion Active" "Not in progress,In progress"
|
|
bitfld.long 0x04 6. " ADTRG ,Conversion Trigger Select" "Software,Hardware"
|
|
bitfld.long 0x04 5. " ACFE ,Compare Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ACFGT ,Compare Function Greater Than Enable" "Less,Greater/Equal"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " FEMPTY ,Result FIFO empty" "Valid,No valid"
|
|
rbitfld.long 0x04 2. " FFULL ,Result FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 0.--1. " REFSEL ,Voltage Reference Selection" "Default(VREFH/VREFL),Analog(VDDA/VSSA),?..."
|
|
line.long 0x08 "ADC_SC3,Status and Control Register 3"
|
|
bitfld.long 0x08 7. " ADLPC ,Low-Power Configuration" "High speed,Low power"
|
|
bitfld.long 0x08 5.--6. " ADIV ,Clock Divide Select" "/1,/2,/4,/8"
|
|
bitfld.long 0x08 4. " ADLSMP ,Long Sample Time Configuration" "Short,Long"
|
|
bitfld.long 0x08 2.--3. " MODE ,Conversion Mode Selection" "8-bit,10-bit,12-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " ADICLK ,Input Clock Select" "Bus,Bus/2,Alternate(ALTCLK),Asynchronous(ADACK)"
|
|
sif cpuis("S9KEAZN16AMLC")||cpuis("S9KEAZN32AMLC")||cpuis("S9KEAZN64AMLC")||cpuis("S9KEAZN64ACLC")||cpuis("S9KEAZN16ACLC")||cpuis("S9KEAZN32ACLC")||cpuis("S9KEAZN32AVLC")||cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")
|
|
if ((per.l(ad:0x4003B000+0x0C)&0x07)!=0)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SC4,Status and Control Register 4"
|
|
bitfld.long 0x00 6. " ASCANE ,FIFO Scan Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACFSEL ,Compare function select OR/AND" "OR,AND"
|
|
bitfld.long 0x00 0.--2. " AFDEP ,FIFO Depth" "Disabled,2-level,3-level,4-level,5-level,6-level,7-level,8-level"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "ADC_R,Conversion Result Register"
|
|
IN
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SC4,Status and Control Register 4"
|
|
bitfld.long 0x00 0.--2. " AFDEP ,FIFO Depth" "Disabled,2-level,3-level,4-level,5-level,6-level,7-level,8-level"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC_R,Conversion Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADR ,Conversion Result"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4003B000+0x0C)&0x07)!=0)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SC4,Status and Control Register 4"
|
|
bitfld.long 0x00 8. " HTRGME ,Hardware Trigger Multiple Conversion Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASCANE ,FIFO Scan Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACFSEL ,Compare function select OR/AND" "OR,AND"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " AFDEP ,FIFO Depth" "Disabled,2-level,3-level,4-level,5-level,6-level,7-level,8-level"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "ADC_R,Conversion Result Register"
|
|
IN
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SC4,Status and Control Register 4"
|
|
bitfld.long 0x00 8. " HTRGME ,Hardware Trigger Multiple Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " AFDEP ,FIFO Depth" "Disabled,2-level,3-level,4-level,5-level,6-level,7-level,8-level"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC_R,Conversion Result Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " ADR ,Conversion Result"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADC_CV,Compare Value Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " CV ,Conversion Result"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_APCTL1,Pin Control 1 Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 15. " ADPC_15 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " ADPC_14 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " ADPC_13 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " ADPC_12 ,ADC PIN Control" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " ADPC_7 ,ADC PIN Control for channel 7 (Input: PTB3/ADP7)" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ADPC_6 ,ADC PIN Control for channel 6 (Input: PTB2/ADP6)" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " ADPC_5 ,ADC PIN Control for channel 5 (Input: PTB1/ADP5)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADPC_4 ,ADC PIN Control for channel 4 (Input: PTB0/ADP4)" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " ADPC_1 ,ADC PIN Control for channel 1 (Input: PTA1/ADP1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ADPC_0 ,ADC PIN Control for channel 0 (Input: PTA0/ADP0)" "Enabled,Disabled"
|
|
textline " "
|
|
elif cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")
|
|
bitfld.long 0x00 11. " ADPC_11 ,ADC PIN Control for channel 11 (Input: PTC3/ADP11)" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " ADPC_10 ,ADC PIN Control for channel 10 (Input: PTC2/ADP10)" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " ADPC_9 ,ADC PIN Control for channel 9 (Input: PTC1/ADP9)" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ADPC_8 ,ADC PIN Control for channel 8 (Input: PTC0/ADP8)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADPC_7 ,ADC PIN Control for channel 7 (Input: PTB3/ADP7)" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ADPC_6 ,ADC PIN Control for channel 6 (Input: PTB2/ADP6)" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " ADPC_5 ,ADC PIN Control for channel 5 (Input: PTB1/ADP5)" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " ADPC_4 ,ADC PIN Control for channel 4 (Input: PTB0/ADP4)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADPC_3 ,ADC PIN Control for channel 3 (Input: PTA7/ADP3)" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " ADPC_2 ,ADC PIN Control for channel 2 (Input: PTA6/ADP2)" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " ADPC_1 ,ADC PIN Control for channel 1 (Input: PTA1/ADP1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ADPC_0 ,ADC PIN Control for channel 0 (Input: PTA0/ADP0)" "Enabled,Disabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 11. " ADPC_11 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " ADPC_10 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " ADPC_9 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " ADPC_8 ,ADC PIN Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADPC_7 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ADPC_6 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " ADPC_5 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " ADPC_4 ,ADC PIN Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADPC_3 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " ADPC_2 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " ADPC_1 ,ADC PIN Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ADPC_0 ,ADC PIN Control" "Enabled,Disabled"
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC_SC5,Status and Control Register 5"
|
|
bitfld.long 0x00 1. " HTRGMASKE ,Hardware Trigger Mask Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HTRGMASKSEL ,Hardware Trigger Mask Mode Select" "HTRGMASKE,Automatically"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "ACMP (Analog Comparator)"
|
|
base ad:0x40073000
|
|
width 10.
|
|
group.byte 0x00++0x03 "ACMP0"
|
|
line.byte 0x00 "ACMP0_CS,ACMP Control and Status Register"
|
|
bitfld.byte 0x00 7. " ACE ,Analog Comparator Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " HYST ,Analog Comparator Hysterisis Selection" "20 mV,30 mV"
|
|
bitfld.byte 0x00 5. " ACF ,ACMP Interrupt Flag Bit" "Cleared,No effected"
|
|
bitfld.byte 0x00 4. " ACIE ,ACMP Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ACO ,ACMP Output" "0,1"
|
|
bitfld.byte 0x00 2. " ACOPE ,ACMP Output Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " ACMOD ,ACMP MOD" "Falling edge,Rising edge,Falling edge,Falling/Rising edge"
|
|
line.byte 0x01 "ACMP0_C0,ACMP Control Register 0"
|
|
bitfld.byte 0x01 4.--5. " ACPSEL ,ACMP Positive Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
bitfld.byte 0x01 0.--1. " ACNSEL ,ACMP Negative Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
line.byte 0x02 "ACMP0_C1,ACMP Control Register 1"
|
|
bitfld.byte 0x02 7. " DACEN ,DAC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " DACREF ,DAC Reference Select" "Bandgap,VDDA"
|
|
bitfld.byte 0x02 0.--5. " DACVAL ,DAC Output Level Selection" "LOW,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,HIGH"
|
|
line.byte 0x03 "ACMP0_C2,ACMP Control Register 2"
|
|
bitfld.byte 0x03 2. " ACIPE_2 ,ACMP_2 Input Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " ACIPE_1 ,ACMP_1 Input Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " ACIPE_0 ,ACMP_0 Input Pin Enable" "Disabled,Enabled"
|
|
group.byte 0x1000++0x03 "ACMP1"
|
|
line.byte 0x00 "ACMP1_CS,ACMP Control and Status Register"
|
|
bitfld.byte 0x00 7. " ACE ,Analog Comparator Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " HYST ,Analog Comparator Hysterisis Selection" "20 mV,30 mV"
|
|
bitfld.byte 0x00 5. " ACF ,ACMP Interrupt Flag Bit" "Cleared,No effected"
|
|
bitfld.byte 0x00 4. " ACIE ,ACMP Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ACO ,ACMP Output" "0,1"
|
|
bitfld.byte 0x00 2. " ACOPE ,ACMP Output Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " ACMOD ,ACMP MOD" "Falling edge,Rising edge,Falling edge,Falling/Rising edge"
|
|
line.byte 0x01 "ACMP1_C0,ACMP Control Register 0"
|
|
bitfld.byte 0x01 4.--5. " ACPSEL ,ACMP Positive Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
bitfld.byte 0x01 0.--1. " ACNSEL ,ACMP Negative Input Select" "External ref. 0,External ref. 1,External ref. 2,DAC output"
|
|
line.byte 0x02 "ACMP1_C1,ACMP Control Register 1"
|
|
bitfld.byte 0x02 7. " DACEN ,DAC Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " DACREF ,DAC Reference Select" "Bandgap,VDDA"
|
|
bitfld.byte 0x02 0.--5. " DACVAL ,DAC Output Level Selection" "LOW,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,HIGH"
|
|
line.byte 0x03 "ACMP1_C2,ACMP Control Register 2"
|
|
bitfld.byte 0x03 2. " ACIPE_2 ,ACMP_2 Input Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " ACIPE_1 ,ACMP_1 Input Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " ACIPE_0 ,ACMP_0 Input Pin Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "FTM (FlexTimer)"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")||cpuis("S9KEAZN16AMLC")||cpuis("S9KEAZN32AMLC")||cpuis("S9KEAZN64AMLC")||cpuis("S9KEAZN64ACLC")||cpuis("S9KEAZN16ACLC")||cpuis("S9KEAZN32ACLC")||cpuis("S9KEAZN32AVLC")||cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
tree "FTM0"
|
|
base ad:0x40038000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM0_SC,FTM0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM0_CNT,FTM0 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM0_MOD,FTM0 Modulo register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
group.long (0xC+0x00)++0x3
|
|
line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0xC+0x04)++0x3
|
|
line.long 0x00 "FTM0_C0V,FTM0 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 Value"
|
|
group.long (0x14+0x00)++0x3
|
|
line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "FTM0_C1V,FTM0 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
tree "FTM1"
|
|
base ad:0x40039000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM1_SC,FTM1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM1_CNT,FTM1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM1_MOD,FTM1 Modulo register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
group.long (0xC+0x00)++0x3
|
|
line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0xC+0x04)++0x3
|
|
line.long 0x00 "FTM1_C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 Value"
|
|
group.long (0x14+0x00)++0x3
|
|
line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "FTM1_C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 Value"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "FTM2"
|
|
base ad:0x4003A000
|
|
width 13.
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM2_SC,FTM2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM2_SC,FTM2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
rbitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,FTM2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM2_MOD,FTM2 Modulo register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
if (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "C4SC,Channel (4) Status And Control"
|
|
endif
|
|
group.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "FTM2_C4V,FTM2 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 Value"
|
|
if (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x4003A000+0x64))&0x10000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "C5SC,Channel (5) Status And Control"
|
|
endif
|
|
group.long (0x34+0x04)++0x3
|
|
line.long 0x00 "FTM2_C5V,FTM2 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 Value"
|
|
else
|
|
if (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
endif
|
|
group.long (0xC+0x04)++0x3
|
|
line.long 0x00 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 Value"
|
|
if (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
endif
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 Value"
|
|
if (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
endif
|
|
group.long (0x1C+0x04)++0x3
|
|
line.long 0x00 "FTM2_C2V,FTM2 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 Value"
|
|
if (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
endif
|
|
group.long (0x24+0x04)++0x3
|
|
line.long 0x00 "FTM2_C3V,FTM2 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 Value"
|
|
if (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
endif
|
|
group.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "FTM2_C4V,FTM2 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 Value"
|
|
if (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x10)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Toggle output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==(0x20||0x30))&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Intput capture,Output compare,Edge-eligned PWM,Edge-eligned PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&((per.l(ad:0x4003A000)&0x20)==0x20)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Set output,Clear output,Set output"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" ",Low-true pulses,High-true pulses,Low-true pulses"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
elif (((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&((per.l(ad:0x4003A000)&0x20)==0x00)&&((per.l(ad:0x4003A000+0x54)&0x04)==0x00)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising edge,Falling edge,Both edge"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
endif
|
|
group.long (0x34+0x04)++0x3
|
|
line.long 0x00 "FTM2_C5V,FTM2 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 Value"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x01)==0x00)
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value of FTM2 Counter"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value of FTM2 Counter"
|
|
endif
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM2_STATUS,FTM2 Capture and Compare Status Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 5. " CHF[5] ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CHF[4] ,Channel 4 Flag" "Not occurred,Occurred"
|
|
else
|
|
bitfld.long 0x00 5. " CHF[5] ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CHF[4] ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CHF[3] ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CHF[2] ,Channel 2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHF[1] ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CHF[0] ,Channel 0 Flag" "Not occurred,Occurred"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode (Channels/Fault clearing)" "Disabled,Even/Manual,All/Manual,All/Auto"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the Channels Output" "No effect,Initialize"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode (Channels/Fault clearing)" "Disabled,Even/Manual,All/ Manual,All/Auto"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the Channels Output" "No effect,Initialize"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x01)==0x00)
|
|
rgroup.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "At rising edges of sys clk,By PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization by Synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State for Channels Output Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 5. " CHOI[5] ,Channel 5 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 4. " CHOI[4] ,Channel 4 Output Initialization Value" "0,1"
|
|
else
|
|
bitfld.long 0x04 5. " CHOI[5] ,Channel 5 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 4. " CHOI[4] ,Channel 4 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 3. " CHOI[3] ,Channel 3 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 2. " CHOI[2] ,Channel 2 Output Initialization Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHOI[1] ,Channel 1 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 0. " CHOI[0] ,Channel 0 Output Initialization Value" "0,1"
|
|
endif
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 5. " CHOM[5] ,Channel 5 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CHOM[4] ,Channel 4 Output Mask" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x08 5. " CHOM[5] ,Channel 5 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CHOM[4] ,Channel 4 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " CHOM[3] ,Channel 3 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CHOM[2] ,Channel 2 Output Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CHOM[1] ,Channel 1 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CHOM[0] ,Channel 0 Output Mask" "Not masked,Masked"
|
|
endif
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function for Linked Channels Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
else
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary Mode for Channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM Synchronization Enable (C0V,C1V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary Mode for Channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "At rising edges of sys clk,By PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization by Synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State for Channels Output Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 5. " CHOI[5] ,Channel 5 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 4. " CHOI[4] ,Channel 4 Output Initialization Value" "0,1"
|
|
else
|
|
bitfld.long 0x04 5. " CHOI[5] ,Channel 5 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 4. " CHOI[4] ,Channel 4 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 3. " CHOI[3] ,Channel 3 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 2. " CHOI[2] ,Channel 2 Output Initialization Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHOI[1] ,Channel 1 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 0. " CHOI[0] ,Channel 0 Output Initialization Value" "0,1"
|
|
endif
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 5. " CHOM[5] ,Channel 5 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CHOM[4] ,Channel 4 Output Mask" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x08 5. " CHOM[5] ,Channel 5 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " CHOM[4] ,Channel 4 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " CHOM[3] ,Channel 3 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " CHOM[2] ,Channel 2 Output Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CHOM[1] ,Channel 1 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " CHOM[0] ,Channel 0 Output Mask" "Not masked,Masked"
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function for Linked Channels Register"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
else
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary Mode for Channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM Synchronization Enable (C0V,C1V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary Mode for Channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function for Linked Channels Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for Channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary Mode for Channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM Synchronization Enable (C0V,C1V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for Channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary Mode for Channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4003A000+0x54))&0x01)==0x00)
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 5. " POL[5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL[4] ,Channel 4 Polarity" "Active high,Active low"
|
|
else
|
|
bitfld.long 0x00 5. " POL[5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL[4] ,Channel 4 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL[3] ,Channel 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL[2] ,Channel 2 Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL[1] ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL[0] ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
sif !CPUIS("S9KEAZN8AVTG")
|
|
rgroup.long 0x74++0x07
|
|
line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
bitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1"
|
|
bitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULTF1l ,Fault Detection Flag 1" "Not detected,Detected"
|
|
line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x7C++0x3
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode (FTM Counter/FTM Channels Output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional"
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif !CPUIS("S9KEAZN8AVTG")
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low"
|
|
endif
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM Synchronization Mode" "Legacy,Enhanced"
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared"
|
|
sif !CPUIS("S9KEAZN8AVTG")
|
|
line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x04 3. " INVEN[3] ,Pair Channels 3 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INVEN[2] ,Pair Channels 2 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INVEN[1] ,Pair Channels 1 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INVEN[0] ,Pair Channels 0 Inverting Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 13. " CHOCV[5] ,Channel 5 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 12. " CHOCV[4] ,Channel 4 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 5. " CHOC[5] ,Channel 5 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CHOC[4] ,Channel 4 Software Output Control Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 13. " CHOCV[5] ,Channel 5 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 12. " CHOCV[4] ,Channel 4 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 11. " CHOCV[3] ,Channel 3 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 10. " CHOCV[2] ,Channel 2 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CHOCV[1] ,Channel 1 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 8. " CHOCV[0] ,Channel 0 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CHOC[5] ,Channel 5 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CHOC[4] ,Channel 4 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CHOC[3] ,Channel 3 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CHOC[2] ,Channel 2 Software Output Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CHOC[1] ,Channel 1 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CHOC[0] ,Channel 0 Software Output Control Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x0C 9. " LDOK ,Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " CHSE[5] ,Channel 5 Select" "Not included,Included"
|
|
bitfld.long 0x0C 4. " CHSE[4] ,Channel 4 Select" "Not included,Included"
|
|
else
|
|
bitfld.long 0x0C 9. " LDOK ,Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " CHSE[5] ,Channel 5 Select" "Not included,Included"
|
|
bitfld.long 0x0C 4. " CHSE[4] ,Channel 4 Select" "Not included,Included"
|
|
bitfld.long 0x0C 3. " CHSE[3] ,Channel 3 Select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CHSE[2] ,Channel 2 Select" "Not included,Included"
|
|
bitfld.long 0x0C 1. " CHSE[1] ,Channel 1 Select" "Not included,Included"
|
|
bitfld.long 0x0C 0. " CHSE[0] ,Channel 0 Select" "Not included,Included"
|
|
endif
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 5. " POL[5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL[4] ,Channel 4 Polarity" "Active high,Active low"
|
|
else
|
|
bitfld.long 0x00 5. " POL[5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL[4] ,Channel 4 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL[3] ,Channel 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL[2] ,Channel 2 Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL[1] ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL[0] ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 5. " POL[5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL[4] ,Channel 4 Polarity" "Active high,Active low"
|
|
else
|
|
bitfld.long 0x00 5. " POL[5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " POL[4] ,Channel 4 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 3. " POL[3] ,Channel 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " POL[2] ,Channel 2 Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POL[1] ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " POL[0] ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
endif
|
|
sif !CPUIS("S9KEAZN8AVTG")
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1"
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULTF1l ,Fault Detection Flag 1" "Not detected,Detected"
|
|
line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode (FTM Counter/FTM Channels Output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional"
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif !CPUIS("S9KEAZN8AVTG")
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low"
|
|
endif
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM Synchronization Mode" "Legacy,Enhanced"
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared"
|
|
sif !CPUIS("S9KEAZN8AVTG")
|
|
line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x04 3. " INVEN[3] ,Pair Channels 3 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INVEN[2] ,Pair Channels 2 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " INVEN[1] ,Pair Channels 1 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INVEN[0] ,Pair Channels 0 Inverting Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 13. " CHOCV[5] ,Channel 5 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 12. " CHOCV[4] ,Channel 4 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 5. " CHOC[5] ,Channel 5 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CHOC[4] ,Channel 4 Software Output Control Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 13. " CHOCV[5] ,Channel 5 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 12. " CHOCV[4] ,Channel 4 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 11. " CHOCV[3] ,Channel 3 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 10. " CHOCV[2] ,Channel 2 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CHOCV[1] ,Channel 1 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 8. " CHOCV[0] ,Channel 0 Software Output Control Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CHOC[5] ,Channel 5 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CHOC[4] ,Channel 4 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CHOC[3] ,Channel 3 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CHOC[2] ,Channel 2 Software Output Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CHOC[1] ,Channel 1 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CHOC[0] ,Channel 0 Software Output Control Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
sif CPUIS("S9KEAZN8AVTG")
|
|
bitfld.long 0x0C 9. " LDOK ,Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " CHSE[5] ,Channel 5 Select" "Not included,Included"
|
|
bitfld.long 0x0C 4. " CHSE[4] ,Channel 4 Select" "Not included,Included"
|
|
else
|
|
bitfld.long 0x0C 9. " LDOK ,Load Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " CHSE[5] ,Channel 5 Select" "Not included,Included"
|
|
bitfld.long 0x0C 4. " CHSE[4] ,Channel 4 Select" "Not included,Included"
|
|
bitfld.long 0x0C 3. " CHSE[3] ,Channel 3 Select" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CHSE[2] ,Channel 2 Select" "Not included,Included"
|
|
bitfld.long 0x0C 1. " CHSE[1] ,Channel 1 Select" "Not included,Included"
|
|
bitfld.long 0x0C 0. " CHSE[0] ,Channel 0 Select" "Not included,Included"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "FTM0"
|
|
base ad:0x40038000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM0_SC,FTM0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM0_CNT,FTM0 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM0_MOD,FTM0 Modulo register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
group.long (0xC+0x00)++0x3
|
|
line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0xC+0x04)++0x3
|
|
line.long 0x00 "FTM0_C0V,FTM0 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 Value"
|
|
group.long (0x14+0x00)++0x3
|
|
line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "FTM0_C1V,FTM0 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 Value"
|
|
textline " "
|
|
width 14.
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")
|
|
tree "FTM1"
|
|
base ad:0x40039000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM1_SC,FTM1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM1_CNT,FTM1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM1_MOD,FTM1 Modulo register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
group.long (0xC+0x00)++0x3
|
|
line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0xC+0x04)++0x3
|
|
line.long 0x00 "FTM1_C0V,FTM1 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 Value"
|
|
group.long (0x14+0x00)++0x3
|
|
line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "FTM1_C1V,FTM1 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 Value"
|
|
textline " "
|
|
width 14.
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "FTM2"
|
|
base ad:0x4003A000
|
|
width 11.
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM2_SC,FTM2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
bitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
bitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FTM2_SC,FTM2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " TOF ,Timer Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM Select" "Up counting,Up-Down counting"
|
|
rbitfld.long 0x00 3.--4. " CLKS ,Clock Source Selection" "No clk,System,Fixed frequency,Ext clk"
|
|
rbitfld.long 0x00 0.--2. " PS ,Prescale Factor Selection" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "FTM2_CNT,FTM2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value"
|
|
line.long 0x04 "FTM2_MOD,FTM2 Modulo register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long (0xC+0x00)++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
else
|
|
group.long (0xC+0x00)++0x3
|
|
line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 0 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 Mode Select" "00,01,10,11"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
endif
|
|
group.long (0xC+0x04)++0x3
|
|
line.long 0x00 "FTM2_C0V,FTM2 Channel 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 Value"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long (0x14+0x00)++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
else
|
|
group.long (0x14+0x00)++0x3
|
|
line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 Mode Select" "00,01,10,11"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
endif
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "FTM2_C1V,FTM2 Channel 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 Value"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long (0x1C+0x00)++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
else
|
|
group.long (0x1C+0x00)++0x3
|
|
line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 Mode Select" "00,01,10,11"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
endif
|
|
group.long (0x1C+0x04)++0x3
|
|
line.long 0x00 "FTM2_C2V,FTM2 Channel 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 Value"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long (0x24+0x00)++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
else
|
|
group.long (0x24+0x00)++0x3
|
|
line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 Mode Select" "00,01,10,11"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
endif
|
|
group.long (0x24+0x04)++0x3
|
|
line.long 0x00 "FTM2_C3V,FTM2 Channel 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 Value"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long (0x2C+0x00)++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
else
|
|
group.long (0x2C+0x00)++0x3
|
|
line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 Mode Select" "00,01,10,11"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
endif
|
|
group.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "FTM2_C4V,FTM2 Channel 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 Value"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long (0x34+0x00)++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "00,01,10,11"
|
|
bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
else
|
|
group.long (0x34+0x00)++0x3
|
|
line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status and Control Register"
|
|
rbitfld.long 0x00 7. " CHF ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " CHIE ,Channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 Mode Select" "00,01,10,11"
|
|
rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or Level Select" "No edge,Rising,Falling,Both"
|
|
endif
|
|
group.long (0x34+0x04)++0x3
|
|
line.long 0x00 "FTM2_C5V,FTM2 Channel 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 Value"
|
|
textline " "
|
|
width 14.
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value of FTM2 Counter"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "FTM2_STATUS,FTM2 Capture and Compare Status Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x00 7. " CHF [7] ,Channel 7 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " CHF [5] ,Channel 5 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
width 14.
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode (Channels/Fault clearing)" "Disabled,Even/Manual,All/Manual,All/Auto"
|
|
bitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the Channels Output" "No effect,Initialize"
|
|
bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register"
|
|
bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode (Channels/Fault clearing)" "Disabled,Even/Manual,All/ Manual,All/Auto"
|
|
rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " INIT ,Initialize the Channels Output" "No effect,Initialize"
|
|
rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register"
|
|
bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "At rising edges of sys clk,By PWM sync"
|
|
bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization by Synchronization" "Normal,Updated on trigger"
|
|
bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State for Channels Output Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x04 7. " CHOI [7] ,Channel 7 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 6. " [6] ,Channel 6 Output Initialization Value" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " CHOI [5] ,Channel 5 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 4. " [4] ,Channel 4 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 3. " [3] ,Channel 3 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 2. " [2] ,Channel 2 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 1. " [1] ,Channel 1 Output Initialization Value" "0,1"
|
|
bitfld.long 0x04 0. " [0] ,Channel 0 Output Initialization Value" "0,1"
|
|
line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x08 7. " CHOM [7] ,Channel 7 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [6] ,Channel 6 Output Mask" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 5. " CHOM [5] ,Channel 5 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Channel 4 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " [3] ,Channel 3 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Channel 2 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " [1] ,Channel 1 Output Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [0] ,Channel 0 Output Mask" "Not masked,Masked"
|
|
textline " "
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function for Linked Channels Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable in Channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM Synchronization Enable (C6V,C7V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEN2 ,Deadtime Enable in Channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for Channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COMP3 ,Complementary Mode for Channels 6 and 7" "CH5 same as CH4,CH5 complement of CH4"
|
|
bitfld.long 0x00 24. " COMBINE3 ,Combine Channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH7 same as CH6,CH7 complement of CH6"
|
|
bitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " COMP1 ,Complementary Mode for Channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
bitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM Synchronization Enable (C0V,C1V)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COMP0 ,Complementary Mode for Channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FTM2_COMBINE,FTM2 Function for Linked Channels Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable in Channels 6 and 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SYNCEN3 ,PWM Synchronization Enable (C6V,C7V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " DTEN2 ,Deadtime Enable in Channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for Channels 6 and 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " COMP3 ,Complementary Mode for Channels 6 and 7" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 24. " COMBINE3 ,Combine Channels 6 and 7" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCEN2 ,PWM Synchronization Enable (C4V,C5V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable in Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for Channels 4 and 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " COMP2 ,Complementary Mode for Channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4"
|
|
rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels 4 and 5" "Independent,Combined"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable in Channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for Channels 2 and 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " COMP1 ,Complementary Mode for Channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2"
|
|
rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels 2 and 3" "Independent,Combined"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCEN0 ,PWM Synchronization Enable (C0V,C1V)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable in Channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures" "Inactive,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for Channels 0 and 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " COMP0 ,Complementary Mode for Channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0"
|
|
rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1" "Independent,Combined"
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register"
|
|
bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16"
|
|
bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "No counts,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register"
|
|
rbitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled"
|
|
sif !cpuis("S9KEAZN8AMTG")
|
|
bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled"
|
|
sif !cpuis("S9KEAZN8AMTG")
|
|
bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x00 7. " POL [7] ,Channel 7 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 Polarity" "Active high,Active low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " POL [5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 Polarity" "Active high,Active low"
|
|
sif !cpuis("S9KEAZN8AMTG")
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x00 7. " POL [7] ,Channel 7 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 Polarity" "Active high,Active low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " POL [5] ,Channel 5 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 Polarity" "Active high,Active low"
|
|
sif !cpuis("S9KEAZN8AMTG")
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 Polarity" "Active high,Active low"
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 14.
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register"
|
|
rbitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1"
|
|
rbitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected"
|
|
rbitfld.long 0x00 1. " FAULTF1l ,Fault Detection Flag 1" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "Not detected,Detected"
|
|
line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register"
|
|
bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register"
|
|
bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FTM2_CONF,FTM2 Configuration Register"
|
|
bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode (FTM Counter/FTM Channels Output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional"
|
|
bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if ((per.l(ad:0x4003A000+0x54)&0x04)==0x04)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register"
|
|
bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register"
|
|
bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " SYNCMODE ,PWM Synchronization Mode" "Legacy,Enhanced"
|
|
bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared"
|
|
textline " "
|
|
line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register"
|
|
bitfld.long 0x04 3. " INVEN [3] ,Pair Channels 3 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Pair Channels 2 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Pair Channels 1 Inverting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Pair Channels 0 Inverting Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x08 15. " CHOCV [7] ,Channel 7 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 14. " [6] ,Channel 6 Software Output Control Value" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 13. " CHOCV [5] ,Channel 5 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 12. " [4] ,Channel 4 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 11. " [3] ,Channel 3 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 10. " [2] ,Channel 2 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 9. " [1] ,Channel 1 Software Output Control Value" "0,1"
|
|
bitfld.long 0x08 8. " [0] ,Channel 0 Software Output Control Value" "0,1"
|
|
textline " "
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x08 7. " CHOC [7] ,Channel 7 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Channel 6 Software Output Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 5. " CHOC [5] ,Channel 5 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Channel 4 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [3] ,Channel 3 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Channel 2 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Channel 1 Software Output Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Channel 0 Software Output Control Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register"
|
|
bitfld.long 0x0C 9. " LDOK ,Load Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.long 0x0C 7. "CHSE [7] ,Channel 7 Select" "Not included,Included"
|
|
bitfld.long 0x0C 6. " [6] ,Channel 6 Select" "Not included,Included"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 5. "CHSE [5] ,Channel 5 Select" "Not included,Included"
|
|
bitfld.long 0x0C 4. " [4] ,Channel 4 Select" "Not included,Included"
|
|
bitfld.long 0x0C 3. " [3] ,Channel 3 Select" "Not included,Included"
|
|
bitfld.long 0x0C 2. " [2] ,Channel 2 Select" "Not included,Included"
|
|
bitfld.long 0x0C 1. " [1] ,Channel 1 Select" "Not included,Included"
|
|
bitfld.long 0x0C 0. " [0] ,Channel 0 Select" "Not included,Included"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN8AVTG")
|
|
tree "PWT (Pulse Width Timer)"
|
|
base ad:0x40033000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWT_R1,Pulse Width Timer Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " PPW ,Positive Pulse Width"
|
|
bitfld.long 0x00 15. " PCLKS ,PWT Clock Source Selection" "Bus clk,Alternative clk"
|
|
bitfld.long 0x00 13.--14. " PINSEL ,PWT Pulse Inputs Selection" "PWTIN[0],PWTIN[1],PWTIN[2],PWTIN[3]"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " EDGE ,PWT input edge sensitivity (first edge,all subsequent edges) " "Falling/Falling,Rising/All edges,Falling/All edges,Rising/Rising"
|
|
bitfld.long 0x00 8.--10. " PRE ,PWT Clock Pre-scaler(CLKPRE) Setting" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 7. " PWTEN ,PWT Module Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PWTIE ,PWT module interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PRDYIE ,PWT Pulse Width Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " POVIE ,PWT counter overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWTSR ,PWT Soft Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " PWTRDY ,PWT pulse width valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " PWTOV ,PWT counter overflow" "No overflow,Overflow"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PWT_R2,Pulse Width Timer Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " PWTC ,PWT counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " NPW ,Negative Pulse Width"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "PIT (Periodic Interrupt Timer)"
|
|
base ad:0x40037000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PIT_MCR,PIT Module Control Register"
|
|
bitfld.long 0x00 1. " MDIS ,Module Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " FRZ ,Freeze" "Not stopped,Stopped"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIT_LDVAL0,Timer Load Value Register 0"
|
|
rgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "PIT_CVAL0,Current Timer Value Register 0"
|
|
group.long (0x100+0x8)++0x07
|
|
line.long 0x00 "PIT_TCTRL0,Timer Control Register 0"
|
|
bitfld.long 0x00 1. " TIE ,Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PIT_TFLG0,Timer Flag Register 0"
|
|
eventfld.long 0x04 0. " TIF ,Timer Interrupt Flag" "Not occurred,Occurred"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIT_LDVAL1,Timer Load Value Register 1"
|
|
rgroup.long (0x110+0x04)++0x03
|
|
line.long 0x00 "PIT_CVAL1,Current Timer Value Register 1"
|
|
group.long (0x110+0x8)++0x07
|
|
line.long 0x00 "PIT_TCTRL1,Timer Control Register 1"
|
|
bitfld.long 0x00 2. " CHN ,Chain Mode" "Not chained,Chained"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIE ,Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEN ,Timer Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PIT_TFLG1,Timer Flag Register 1"
|
|
eventfld.long 0x04 0. " TIF ,Timer Interrupt Flag" "Not occurred,Occurred"
|
|
width 0xB
|
|
tree.end
|
|
tree "RTC (Real-Time Counter)"
|
|
base ad:0x4003D000
|
|
width 9.
|
|
if ((per.l(ad:0x4003D000)&0x4000)==0x4000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_SC,RTC Status and Control Register"
|
|
bitfld.long 0x00 14.--15. " RTCLKS ,Real-Time Clock Source Select" "External,LPOCLK,ICSIRCLK,BUS Clk"
|
|
bitfld.long 0x00 8.--10. " RTCPS ,Real-Time Clock Prescaler Select" "OFF,/128,/256,/512,/1024,/2048,/100,/1000"
|
|
eventfld.long 0x00 7. " RTIF ,Real-Time Interrupt Flag" "Not reached,Reached"
|
|
bitfld.long 0x00 6. " RTIE ,Real-Time Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTCO ,Real-Time Counter Output" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_SC,RTC Status and Control Register"
|
|
bitfld.long 0x00 14.--15. " RTCLKS ,Real-Time Clock Source Select" "External,LPOCLK,ICSIRCLK,BUS Clk"
|
|
bitfld.long 0x00 8.--10. " RTCPS ,Real-Time Clock Prescaler Select" "OFF,/1,/2,/4,/8,/16,/32,/64"
|
|
eventfld.long 0x00 7. " RTIF ,Real-Time Interrupt Flag" "Not reached,Reached"
|
|
bitfld.long 0x00 6. " RTIE ,Real-Time Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RTCO ,Real-Time Counter Output" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_MOD,RTC Modulo Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MOD ,RTC Modulo"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,RTC Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " CNT ,RTC Count"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x40076000
|
|
width 9.
|
|
if ((per.b(ad:0x40076000+0x1)&0x10)==0x10)&&((per.b(ad:0x40076000)&0x10)==0x10)
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SPI0_C1,SPI0 control register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Mode fault input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000+0x1)&0x10)==0x0)&&((per.b(ad:0x40076000)&0x10)==0x10)
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SPI0_C1,SPI0 control register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "General-purpose I/O,General-purpose I/O"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x0)
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SPI0_C1,SPI0 control register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
if ((per.b(ad:0x40076000)&0x10)==0x10)&&((per.b(ad:0x40076000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI0_C2,SPI0 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x10)&&((per.b(ad:0x40076000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI0_C2,SPI0 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x0)&&((per.b(ad:0x40076000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI0_C2,SPI0 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
elif ((per.b(ad:0x40076000)&0x10)==0x0)&&((per.b(ad:0x40076000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI0_C2,SPI0 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI0_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI Baud Rate Prescale Divisor" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI Baud Rate Divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..."
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "SPI0_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI Read Buffer Full Flag" "No data available,Data available"
|
|
bitfld.byte 0x00 6. " SPMF ,SPI Match Flag" "Not matched,Matched"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI Transmit Buffer Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 4. " MODF ,Master Mode Fault Flag" "No error,Error"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SPI0_D,SPI Data Register"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SPI0_M,SPI Match Register"
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
tree "SPI1"
|
|
base ad:0x40077000
|
|
width 9.
|
|
if ((per.b(ad:0x40077000+0x1)&0x10)==0x10)&&((per.b(ad:0x40077000)&0x10)==0x10)
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SPI1_C1,SPI1 control register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Mode fault input,Output"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000+0x1)&0x10)==0x0)&&((per.b(ad:0x40077000)&0x10)==0x10)
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SPI1_C1,SPI1 control register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "General-purpose I/O,General-purpose I/O"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x0)
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SPI1_C1,SPI1 control register 1"
|
|
bitfld.byte 0x00 7. " SPIE ,SPI interrupt enable (SPRF,MODF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MSTR ,Master/slave mode select" "Slave,Master"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low"
|
|
bitfld.byte 0x00 2. " CPHA ,Clock phase (of the first cycle)" "Middle,Start"
|
|
bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Input,Input"
|
|
bitfld.byte 0x00 0. " LSBFE ,LSB first (shifter direction)" "MSB,LSB"
|
|
endif
|
|
if ((per.b(ad:0x40077000)&0x10)==0x10)&&((per.b(ad:0x40077000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI1_C2,SPI1 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x10)&&((per.b(ad:0x40077000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI1_C2,SPI1 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x0)&&((per.b(ad:0x40077000+0x1)&0x1)==0x1)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI1_C2,SPI1 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
elif ((per.b(ad:0x40077000)&0x10)==0x0)&&((per.b(ad:0x40077000+0x1)&0x1)==0x0)
|
|
group.byte 0x01++0x0
|
|
line.byte 0x00 "SPI1_C2,SPI1 control register 2"
|
|
bitfld.byte 0x00 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x00 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SPI1_BR,SPI Baud Rate Register"
|
|
bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI Baud Rate Prescale Divisor" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI Baud Rate Divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..."
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "SPI1_S,SPI Status Register"
|
|
bitfld.byte 0x00 7. " SPRF ,SPI Read Buffer Full Flag" "No data available,Data available"
|
|
bitfld.byte 0x00 6. " SPMF ,SPI Match Flag" "Not matched,Matched"
|
|
bitfld.byte 0x00 5. " SPTEF ,SPI Transmit Buffer Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 4. " MODF ,Master Mode Fault Flag" "No error,Error"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SPI1_D,SPI Data Register"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SPI1_M,SPI Match Register"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C0"
|
|
base ad:0x40066000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "I2C0_A1,I2C Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,I2C Primary Slave Address"
|
|
line.byte 0x01 "I2C0_F,I2C Frequency Divider Register"
|
|
bitfld.byte 0x01 6.--7. " MULT ,Multiplier Factor" "1,2,4,?..."
|
|
bitfld.byte 0x01 0.--5. " ICR ,ClockRate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.b((ad:0x40066000)+0x08)&0x80)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C0_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Following Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C0_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Current Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x01
|
|
line.byte 0x00 "I2C0_S,I2C Status register"
|
|
rbitfld.byte 0x00 7. " TCF ,Transfer Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 6. " IAAS ,Addressed As A Slave" "Not addressed,Slave"
|
|
rbitfld.byte 0x00 5. " BUSY ,Bus Busy" "Idle,Busy"
|
|
eventfld.byte 0x00 4. " ARBL ,Arbitration Lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RAM ,Range Address Match" "Not addressed,Addressed"
|
|
rbitfld.byte 0x00 2. " SRW ,Slave Read/Write" "Receive,Transmit"
|
|
eventfld.byte 0x00 1. " IICIF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " RXAK ,Receive Acknowledge" "Acknowledged,No acknowledged"
|
|
line.byte 0x01 "I2C0_D,I2C Data I/O register"
|
|
if ((per.b((ad:0x40066000)+0x05)&0x40)==0x40)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C0_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address Extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave Baud Rate Control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range Address Matching Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave Address bits" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C0_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address Extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave Baud Rate Control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range Address Matching Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "I2C0_FLT,I2C Programmable Input Glitch Filter Register"
|
|
bitfld.byte 0x00 7. " SHEN ,Stop Hold Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C Bus Stop Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C Bus Stop or Start Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 4. " STARTF ,I2C Bus Start Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C Programmable Filter Factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b((ad:0x40066000)+0x05)&0x40)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "I2C0_RA,I2C Range Address register"
|
|
hexmask.byte 0x00 1.--7. 0x02 " RAD ,Range Slave Address"
|
|
else
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "I2C0_RA,I2C Range Address register"
|
|
endif
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "I2C0_SMB,I2C SMBus Control and Status register"
|
|
bitfld.byte 0x00 7. " FACK ,Fast NACK/ACK Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ALERTEN ,SMBus Alert Response Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SIICAEN ,Second I2C Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TCKSEL ,Timeout Counter Clock Select" "Bus clock / 64 freq,Bus clock freq"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " SLTF ,SCL Low Timeout Flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " SHTF1 ,SCL High Timeout Flag 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 1. " SHTF2 ,SCL High Timeout Flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SHTF2IE ,SHTF2 Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "I2C0_A2,I2C Address Register 2"
|
|
hexmask.byte 0x01 1.--7. 0x02 " SAD ,SMBus Address Register 2"
|
|
line.byte 0x02 "I2C0_SLTH,I2C SCL Low Timeout Register High"
|
|
line.byte 0x03 "I2C0_SLTL,I2C SCL Low Timeout Register Low"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "I2C1"
|
|
base ad:0x40067000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "I2C1_A1,I2C Address Register 1"
|
|
hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,I2C Primary Slave Address"
|
|
line.byte 0x01 "I2C1_F,I2C Frequency Divider Register"
|
|
bitfld.byte 0x01 6.--7. " MULT ,Multiplier Factor" "1,2,4,?..."
|
|
bitfld.byte 0x01 0.--5. " ICR ,ClockRate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.b((ad:0x40067000)+0x08)&0x80)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C1_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Following Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "I2C1_C1,I2C Control Register 1"
|
|
bitfld.byte 0x00 7. " IICEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICIE ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " MST ,Master Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 4. " TX ,Transmit Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TXAK ,Transmit Acknowledge Enable On The Current Receiving Byte" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " RSTA ,Repeat START" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " WUEN ,Wakeup Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x01
|
|
line.byte 0x00 "I2C1_S,I2C Status register"
|
|
rbitfld.byte 0x00 7. " TCF ,Transfer Complete Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 6. " IAAS ,Addressed As A Slave" "Not addressed,Slave"
|
|
rbitfld.byte 0x00 5. " BUSY ,Bus Busy" "Idle,Busy"
|
|
eventfld.byte 0x00 4. " ARBL ,Arbitration Lost" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RAM ,Range Address Match" "Not addressed,Addressed"
|
|
rbitfld.byte 0x00 2. " SRW ,Slave Read/Write" "Receive,Transmit"
|
|
eventfld.byte 0x00 1. " IICIF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " RXAK ,Receive Acknowledge" "Acknowledged,No acknowledged"
|
|
line.byte 0x01 "I2C1_D,I2C Data I/O register"
|
|
if ((per.b((ad:0x40067000)+0x05)&0x40)==0x40)
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C1_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address Extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave Baud Rate Control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range Address Matching Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave Address bits" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "I2C1_C2,I2C Control Register 2"
|
|
bitfld.byte 0x00 7. " GCAEN ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ADEXT ,Address Extension" "7-bit,10-bit"
|
|
bitfld.byte 0x00 4. " SBRC ,Slave Baud Rate Control" "Master,Independent"
|
|
bitfld.byte 0x00 3. " RMEN ,Range Address Matching Enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "I2C1_FLT,I2C Programmable Input Glitch Filter Register"
|
|
bitfld.byte 0x00 7. " SHEN ,Stop Hold Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 6. " STOPF ,I2C Bus Stop Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 5. " SSIE ,I2C Bus Stop or Start Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.byte 0x00 4. " STARTF ,I2C Bus Start Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " FLT ,I2C Programmable Filter Factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if ((per.b((ad:0x40067000)+0x05)&0x40)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "I2C1_RA,I2C Range Address register"
|
|
hexmask.byte 0x00 1.--7. 0x02 " RAD ,Range Slave Address"
|
|
else
|
|
hgroup.byte 0x07++0x00
|
|
hide.byte 0x00 "I2C1_RA,I2C Range Address register"
|
|
endif
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "I2C1_SMB,I2C SMBus Control and Status register"
|
|
bitfld.byte 0x00 7. " FACK ,Fast NACK/ACK Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ALERTEN ,SMBus Alert Response Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SIICAEN ,Second I2C Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " TCKSEL ,Timeout Counter Clock Select" "Bus clock / 64 freq,Bus clock freq"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " SLTF ,SCL Low Timeout Flag" "Not occurred,Occurred"
|
|
rbitfld.byte 0x00 2. " SHTF1 ,SCL High Timeout Flag 1" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 1. " SHTF2 ,SCL High Timeout Flag 2" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SHTF2IE ,SHTF2 Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "I2C1_A2,I2C Address Register 2"
|
|
hexmask.byte 0x01 1.--7. 0x02 " SAD ,SMBus Address Register 2"
|
|
line.byte 0x02 "I2C1_SLTH,I2C SCL Low Timeout Register High"
|
|
line.byte 0x03 "I2C1_SLTL,I2C SCL Low Timeout Register Low"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK ")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "MSCAN (Scalable Controller Area Network)"
|
|
base ad:0x40024000
|
|
width 16.
|
|
if ((per.b(ad:0x40024000)&0x01)==0x00)&&((per.b(ad:0x40024000+0x01)&0x21)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL0,MSCAN Control Register 0"
|
|
eventfld.byte 0x00 7. " RXFRM ,Received Frame Flag" "No valid,Valid"
|
|
rbitfld.byte 0x00 6. " RXACT ,Receiver Active Status" "Transmitting/Idle,Receiving"
|
|
bitfld.byte 0x00 5. " CSWAI ,CAN Stops in Wait Mode" "No,Yes"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized"
|
|
bitfld.byte 0x00 3. " TIME ,Timer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WUPE ,WakeUp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SLPRQ ,Sleep Mode Request" "Normal,Sleep mode"
|
|
bitfld.byte 0x00 0. " INITRQ ,Initialization Mode Request" "Normal,Initialization"
|
|
elif ((per.b(ad:0x40024000)&0x01)==0x00)&&((per.b(ad:0x40024000+0x01)&0x21)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL0,MSCAN Control Register 0"
|
|
bitfld.byte 0x00 5. " CSWAI ,CAN Stops in Wait Mode" "No,Yes"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized"
|
|
bitfld.byte 0x00 3. " TIME ,Timer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " WUPE ,WakeUp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SLPRQ ,Sleep Mode Request" "Normal,Sleep mode"
|
|
bitfld.byte 0x00 0. " INITRQ ,Initialization Mode Request" "Normal,Initialization"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL0,MSCAN Control Register 0"
|
|
rbitfld.byte 0x00 7. " RXFRM ,Received Frame Flag" "No valid,Valid"
|
|
rbitfld.byte 0x00 6. " RXACT ,Receiver Active Status" "Transmitting/Idle,Receiving"
|
|
rbitfld.byte 0x00 5. " CSWAI ,CAN Stops in Wait Mode" "No,Yes"
|
|
textline " "
|
|
rbitfld.byte 0x00 4. " SYNCH ,Synchronized Status" "Not synchronized,Synchronized"
|
|
rbitfld.byte 0x00 3. " TIME ,Timer Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " WUPE ,WakeUp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SLPRQ ,Sleep Mode Request" "Normal,Sleep mode"
|
|
bitfld.byte 0x00 0. " INITRQ ,Initialization Mode Request" "Normal,Initialization"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x05)==0x05)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL1,MSCAN Control Register 1"
|
|
bitfld.byte 0x00 7. " CANE ,MSCAN Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CLKSRC ,MSCAN Clock Source" "Oscillator,Bus"
|
|
bitfld.byte 0x00 5. " LOOPB ,Loopback Self Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LISTEN ,Listen Only Mode" "Normal,Activated"
|
|
bitfld.byte 0x00 3. " BORM ,Bus-Off Recovery Mode" "Automatic,Manual"
|
|
bitfld.byte 0x00 2. " WUPM ,WakeUp Mode" "Any level,T_wup"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SLPAK ,Sleep Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
rbitfld.byte 0x00 0. " INITAK ,Initialization Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
elif ((per.b(ad:0x40024000)&0x05)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL1,MSCAN Control Register 1"
|
|
bitfld.byte 0x00 7. " CANE ,MSCAN Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CLKSRC ,MSCAN Clock Source" "Oscillator,Bus"
|
|
bitfld.byte 0x00 5. " LOOPB ,Loopback Self Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LISTEN ,Listen Only Mode" "Normal,Activated"
|
|
bitfld.byte 0x00 3. " BORM ,Bus-Off Recovery Mode" "Automatic,Manual"
|
|
rbitfld.byte 0x00 1. " SLPAK ,Sleep Mode Acknowledge" "Not acknowledge,Acknowledged"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " INITAK ,Initialization Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "MSCAN_CANCTL1,MSCAN Control Register 1"
|
|
bitfld.byte 0x00 7. " CANE ,MSCAN Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CLKSRC ,MSCAN Clock Source" "Oscillator,Bus"
|
|
bitfld.byte 0x00 5. " LOOPB ,Loopback Self Test Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " LISTEN ,Listen Only Mode" "Normal,Activated"
|
|
bitfld.byte 0x00 3. " BORM ,Bus-Off Recovery Mode" "Automatic,Manual"
|
|
bitfld.byte 0x00 2. " WUPM ,WakeUp Mode" "Any level,T_wup"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SLPAK ,Sleep Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
rbitfld.byte 0x00 0. " INITAK ,Initialization Mode Acknowledge" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR0,MSCAN Bus Timing Register 0"
|
|
bitfld.byte 0x00 6.--7. " SJW ,Synchronization Jump Width" "1 Tq cycle,2 Tq cycles,3 Tq cycles,4 Tq cycles"
|
|
bitfld.byte 0x00 0.--5. " BRP ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
else
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR0,MSCAN Bus Timing Register 0"
|
|
bitfld.byte 0x00 6.--7. " SJW ,Synchronization Jump Width" "1 Tq cycle,2 Tq cycles,3 Tq cycles,4 Tq cycles"
|
|
bitfld.byte 0x00 0.--5. " BRP ,Baud Rate Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR1,MSCAN Bus Timing Register 1"
|
|
bitfld.byte 0x00 7. " SAMP ,Sampling" "1 sample,3 samples"
|
|
bitfld.byte 0x00 4.--6. " TSEG2 ,Time Segment 2" ",2 Tq cycles,3 Tq cycles,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles"
|
|
bitfld.byte 0x00 0.--3. " TSEG1 ,Time Segment 1" ",,,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles,9 Tq cycles,10 Tq cycles,11 Tq cycles,12 Tq cycles,13 Tq cycles,14 Tq cycles,15 Tq cycles,16 Tq cycles"
|
|
else
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "MSCAN_CANBTR1,MSCAN Bus Timing Register 1"
|
|
bitfld.byte 0x00 7. " SAMP ,Sampling" "1 sample,3 samples"
|
|
bitfld.byte 0x00 4.--6. " TSEG2 ,Time Segment 2" ",2 Tq cycles,3 Tq cycles,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles"
|
|
bitfld.byte 0x00 0.--3. " TSEG1 ,Time Segment 1" ",,,4 Tq cycles,5 Tq cycles,6 Tq cycles,7 Tq cycles,8 Tq cycles,9 Tq cycles,10 Tq cycles,11 Tq cycles,12 Tq cycles,13 Tq cycles,14 Tq cycles,15 Tq cycles,16 Tq cycles"
|
|
endif
|
|
if (((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01))||(((per.b(ad:0x40024000)&0x04)==0x04)&&((per.b(ad:0x40024000)&0x02)==0x02))
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "MSCAN_CANRFLG,MSCAN Receiver Flag Register"
|
|
bitfld.byte 0x00 7. " WUPIF ,Wake-Up Interrupt Flag" "No wakeup,Wakeup"
|
|
bitfld.byte 0x00 6. " CSCIF ,CAN Status Change Interrupt Flag" "No occurred,Occurred"
|
|
bitfld.byte 0x00 4.--5. " RSTAT ,Receiver Status" "RxOK,RxWRN,RxERR,Bus-off"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTAT ,Transmitter Status" "TxOK,TxWRN,TxERR,Bus-off"
|
|
bitfld.byte 0x00 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 0. " RXF ,Receive Buffer Full Flag" "Empty,Not empty"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "MSCAN_CANRFLG,MSCAN Receiver Flag Register"
|
|
bitfld.byte 0x00 6. " CSCIF ,CAN Status Change Interrupt Flag" "No wakeup,Wakeup"
|
|
rbitfld.byte 0x00 4.--5. " RSTAT ,Receiver Status" "RxOK,RxWRN,RxERR,Bus-off"
|
|
rbitfld.byte 0x00 2.--3. " TSTAT ,Transmitter Status" "TxOK,TxWRN,TxERR,Bus-off"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " OVRIF ,Overrun Interrupt Flag" "No overrun,Overrun"
|
|
bitfld.byte 0x00 0. " RXF ,Receive Buffer Full Flag" "Empty,Not empty"
|
|
endif
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x05++0x03
|
|
line.byte 0x00 "MSCAN_CANRIER,MSCAN Receiver Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " WUPIE ,WakeUp Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CSCIE ,CAN Status Change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " RSTATE ,Receiver Status Change Enable" "Not generated,Bus-off,RxErr/Bus-off,All"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTATE ,Transmitter Status Change Enable" "Not generated,Bus-off,TxErr/Bus-off,All"
|
|
bitfld.byte 0x00 1. " OVRIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXFIE ,Receiver Full Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "MSCAN_CANTFLG,MSCAN Transmitter Flag Register"
|
|
bitfld.byte 0x01 2. " TXE2 ,Transmitter Buffer 2 Empty" "Full,Empty"
|
|
bitfld.byte 0x01 1. " TXE1 ,Transmitter Buffer 1 Empty" "Full,Empty"
|
|
bitfld.byte 0x01 0. " TXE0 ,Transmitter Buffer 0 Empty" "Full,Empty"
|
|
line.byte 0x02 "MSCAN_CANTIER,MSCAN Transmitter Interrupt Enable Register"
|
|
bitfld.byte 0x02 2. " TXEIE2 ,Transmitter 2 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " TXEIE1 ,Transmitter 1 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " TXEIE0 ,Transmitter 0 Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "MSCAN_CANTARQ,MSCAN Transmitter Message Abort Request Register"
|
|
bitfld.byte 0x03 2. " ABTRQ2 ,Abort 2 Request" "Not requested,Requested"
|
|
bitfld.byte 0x03 1. " ABTRQ1 ,Abort 1 Request" "Not requested,Requested"
|
|
bitfld.byte 0x03 0. " ABTRQ0 ,Abort 0 Request" "Not requested,Requested"
|
|
else
|
|
group.byte 0x05++0x03
|
|
line.byte 0x00 "MSCAN_CANRIER,MSCAN Receiver Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " WUPIE ,WakeUp Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CSCIE ,CAN Status Change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " RSTATE ,Receiver Status Change Enable" "Not generated,Bus-off,RxErr/Bus-off,All"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " TSTATE ,Transmitter Status Change Enable" "Not generated,Bus-off,TxErr/Bus-off,All"
|
|
bitfld.byte 0x00 1. " OVRIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXFIE ,Receiver Full Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "MSCAN_CANTFLG,MSCAN Transmitter Flag Register"
|
|
bitfld.byte 0x01 2. " TXE2 ,Transmitter Buffer 2 Empty" "Full,Empty"
|
|
bitfld.byte 0x01 1. " TXE1 ,Transmitter Buffer 1 Empty" "Full,Empty"
|
|
bitfld.byte 0x01 0. " TXE0 ,Transmitter Buffer 0 Empty" "Full,Empty"
|
|
line.byte 0x02 "MSCAN_CANTIER,MSCAN Transmitter Interrupt Enable Register"
|
|
bitfld.byte 0x02 2. " TXEIE2 ,Transmitter 2 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " TXEIE1 ,Transmitter 1 Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " TXEIE0 ,Transmitter 0 Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "MSCAN_CANTARQ,MSCAN Transmitter Message Abort Request Register"
|
|
bitfld.byte 0x03 2. " ABTRQ2 ,Abort 2 Request" "Not requested,Requested"
|
|
bitfld.byte 0x03 1. " ABTRQ1 ,Abort 1 Request" "Not requested,Requested"
|
|
bitfld.byte 0x03 0. " ABTRQ0 ,Abort 0 Request" "Not requested,Requested"
|
|
endif
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "MSCAN_CANTAAK,MSCAN Transmitter Message Abort Acknowledge Register"
|
|
bitfld.byte 0x00 2. " ABTAK2 ,Abort Acknowledge" "Not aborted,Aborted"
|
|
bitfld.byte 0x00 1. " ABTAK1 ,Abort Acknowledge" "Not aborted,Aborted"
|
|
bitfld.byte 0x00 0. " ABTAK0 ,Abort Acknowledge" "Not aborted,Aborted"
|
|
if ((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01)
|
|
rgroup.byte 0x0A++0x01
|
|
line.byte 0x00 "MSCAN_CANTBSEL,MSCAN Transmit Buffer Selection Register"
|
|
bitfld.byte 0x00 2. " TX2 ,Transmit Buffer 2 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 1. " TX1 ,Transmit Buffer 1 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " TX0 ,Transmit Buffer 0 Select" "Not selected,Selected"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAC,MSCAN Identifier Acceptance Control Register"
|
|
bitfld.byte 0x00 4.--5. " IDAM ,Identifier Acceptance Mode" "2x(32-bit) filters,4x(16-bit) filters,8x(8-bit) filters,Filter closed"
|
|
rbitfld.byte 0x00 0.--2. " IDHIT ,Identifier Acceptance Hit Indicator" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.byte 0x0A++0x01
|
|
line.byte 0x00 "MSCAN_CANTBSEL,MSCAN Transmit Buffer Selection Register"
|
|
bitfld.byte 0x00 2. " TX2 ,Transmit Buffer 2 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 1. " TX1 ,Transmit Buffer 1 Select" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " TX0 ,Transmit Buffer 0 Select" "Not selected,Selected"
|
|
rgroup.byte 0x0B++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAC,MSCAN Identifier Acceptance Control Register"
|
|
bitfld.byte 0x00 4.--5. " IDAM ,Identifier Acceptance Mode" "2x(32-bit) filters,4x(16-bit) filters,8x(8-bit) filters,Filter closed"
|
|
bitfld.byte 0x00 0.--2. " IDHIT ,Identifier Acceptance Hit Indicator" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
if ((per.b(ad:0x40024000+0x01)&0x08)==0x08)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "MSCAN_CANMISC,MSCAN Miscellaneous Register"
|
|
eventfld.byte 0x00 0. " BOHOLD ,Bus-off State Hold Until User Request" "Not bus-off/Recovery,Bus-off"
|
|
else
|
|
rgroup.byte 0x0D++0x00
|
|
line.byte 0x00 "MSCAN_CANMISC,MSCAN Miscellaneous Register"
|
|
bitfld.byte 0x00 0. " BOHOLD ,Bus-off State Hold Until User Request" "Not bus-off/Recovery,Bus-off"
|
|
endif
|
|
if (((per.b(ad:0x40024000)&0x01)==0x01)&&((per.b(ad:0x40024000+0x01)&0x01)==0x01))||(((per.b(ad:0x40024000)&0x02)==0x02)&&((per.b(ad:0x40024000+0x01)&0x02)==0x02))
|
|
rgroup.byte 0x0E++0x01
|
|
line.byte 0x00 "MSCAN_CANRXERR,MSCAN Receive Error Counter"
|
|
line.byte 0x01 "MSCAN_CANTXERR,MSCAN Transmit Error Counter"
|
|
else
|
|
hgroup.byte 0x0E++0x01
|
|
hide.byte 0x00 "MSCAN_CANRXERR,MSCAN Receive Error Counter"
|
|
hide.byte 0x01 "MSCAN_CANTXERR,MSCAN Transmit Error Counter"
|
|
endif
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR0,MSCAN Identifier Acceptance Register 0 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR1,MSCAN Identifier Acceptance Register 1 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR2,MSCAN Identifier Acceptance Register 2 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR3,MSCAN Identifier Acceptance Register 3 of First Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR4,MSCAN Identifier Mask Register 4 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR5,MSCAN Identifier Mask Register 5 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR6,MSCAN Identifier Mask Register 6 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR7,MSCAN Identifier Mask Register 7 of First Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR0,MSCAN Identifier Acceptance Register 0 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR1,MSCAN Identifier Acceptance Register 1 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR2,MSCAN Identifier Acceptance Register 2 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MSCAN_CANIDAR3,MSCAN Identifier Acceptance Register 3 of Second Bank"
|
|
bitfld.byte 0x00 7. " AC7 ,Acceptance Code Bit 7" "No,Yes"
|
|
bitfld.byte 0x00 6. " AC6 ,Acceptance Code Bit 6" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 5. " AC5 ,Acceptance Code Bit 5" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AC4 ,Acceptance Code Bit 4" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 3. " AC3 ,Acceptance Code Bit 3" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 2. " AC2 ,Acceptance Code Bit 2" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AC1 ,Acceptance Code Bit 1" "Not accepted,Accepted"
|
|
bitfld.byte 0x00 0. " AC0 ,Acceptance Code Bit 0" "Not accepted,Accepted"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR4,MSCAN Identifier Mask Register 4 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR5,MSCAN Identifier Mask Register 5 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR6,MSCAN Identifier Mask Register 6 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "MSCAN_CANIDMR7,MSCAN Identifier Mask Register 7 of Second Bank"
|
|
bitfld.byte 0x00 7. " AM7 ,Acceptance Mask Bit 7" "Matched,Ignored"
|
|
bitfld.byte 0x00 6. " AM6 ,Acceptance Mask Bit 6" "Matched,Ignored"
|
|
bitfld.byte 0x00 5. " AM5 ,Acceptance Mask Bit 5" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AM4 ,Acceptance Mask Bit 4" "Matched,Ignored"
|
|
bitfld.byte 0x00 3. " AM3 ,Acceptance Mask Bit 3" "Matched,Ignored"
|
|
bitfld.byte 0x00 2. " AM2 ,Acceptance Mask Bit 2" "Matched,Ignored"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " AM1 ,Acceptance Mask Bit 1" "Matched,Ignored"
|
|
bitfld.byte 0x00 0. " AM0 ,Acceptance Mask Bit 0" "Matched,Ignored"
|
|
if ((per.b(ad:0x40024000+0x21)&0x08)==0x08)
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MSCAN_REIDR0,Receive Extended Identifier Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MSCAN_REIDR1,Receive Extended Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " REID20_REID18 ,Extended Format Identifier 20-18" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RSRR ,Substitute Remote Request" "None,Transmission buffers"
|
|
bitfld.byte 0x00 3. " REIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " REID17_REID15 ,Extended Format Identifier 17-15" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x22++0x01
|
|
line.byte 0x00 "MSCAN_REIDR2,Receive Extended Identifier Register 2"
|
|
line.byte 0x01 "MSCAN_REIDR3,Receive Extended Identifier Register 3"
|
|
hexmask.byte 0x01 1.--7. 1. " REID6_REID0 ,Extended Format Identifier 6-0"
|
|
bitfld.byte 0x01 0. " RERTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
elif ((per.b(ad:0x40024000+0x21)&0x08)==0x00)
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MSCAN_RSIDR0,Receive Standard Identifier Register 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MSCAN_RSIDR1,Receive Standard Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " RSID2_RSID0 ,Standard Format Identifier 2-0" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RSRTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
bitfld.byte 0x00 3. " RSIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
endif
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR0,Receive Extended Data Segment Register 0"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR1,Receive Extended Data Segment Register 1"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR2,Receive Extended Data Segment Register 2"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR3,Receive Extended Data Segment Register 3"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR4,Receive Extended Data Segment Register 4"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR5,Receive Extended Data Segment Register 5"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR6,Receive Extended Data Segment Register 6"
|
|
group.byte 0x24++0x0C
|
|
line.byte 0x00 "MSCAN_REDSR7,Receive Extended Data Segment Register 7"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "MSCAN_RDLR,Receive Data Length Register"
|
|
bitfld.byte 0x00 0.--3. " RDLC ,Data Length Code Bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
rgroup.byte 0x2E++0x01
|
|
line.byte 0x00 "MSCAN_RTSRH,Receive Time Stamp Register High"
|
|
line.byte 0x01 "MSCAN_RTSRL,Receive Time Stamp Register Low"
|
|
if ((per.b(ad:0x40024000+0x31)&0x08)==0x08)
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "MSCAN_TEIDR0,Transmit Extended Identifier Register 0"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "MSCAN_TEIDR1,Transmit Extended Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " TEID20_TEID18 ,Extended Format Identifier 20-18" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " TSRR ,Substitute Remote Request" "None,Transmission buffers"
|
|
bitfld.byte 0x00 3. " TEIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " TEID17_TEID15 ,Extended Format Identifier 17-15" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x32++0x01
|
|
line.byte 0x00 "MSCAN_TEIDR2,Transmit Extended Identifier Register 2"
|
|
line.byte 0x01 "MSCAN_TEIDR3,Transmit Extended Identifier Register 3"
|
|
hexmask.byte 0x01 1.--7. 1. " TEID6_TEID0 ,Extended Format Identifier 6-0"
|
|
bitfld.byte 0x01 0. " TERTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
elif ((per.b(ad:0x40024000+0x31)&0x08)==0x00)
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "MSCAN_TSIDR0,Transmit Standard Identifier Register 0"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "MSCAN_TSIDR1,Transmit Standard Identifier Register 1"
|
|
bitfld.byte 0x00 5.--7. " TSID2_TSID0 ,Standard Format Identifier 2-0" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " TSRTR ,Remote Transmission Request" "Data frame,Remote frame"
|
|
bitfld.byte 0x00 3. " TSIDE ,ID Extended" "Standard 11bit,Extended 29bit"
|
|
endif
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR0,Transmit Extended Data Segment Register 0"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR1,Transmit Extended Data Segment Register 1"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR2,Transmit Extended Data Segment Register 2"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR3,Transmit Extended Data Segment Register 3"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR4,Transmit Extended Data Segment Register 4"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR5,Transmit Extended Data Segment Register 5"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR6,Transmit Extended Data Segment Register 6"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "MSCAN_TEDSR7,Transmit Extended Data Segment Register 7"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "MSCAN_TDLR,Transmit Data Length Register"
|
|
bitfld.byte 0x00 0.--3. " TDLC ,Data Length Code Bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
if (((((per.b(ad:0x40024000+0x06))&0x04)==0x04)&&(((per.b(ad:0x40024000+0x0A))&0x04)==0x04))||((((per.b(ad:0x40024000+0x06))&0x02)==0x02)&&(((per.b(ad:0x40024000+0x0A))&0x02)==0x02))||((((per.b(ad:0x40024000+0x06))&0x01)==0x01)&&(((per.b(ad:0x40024000+0x0A))&0x01)==0x01)))
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "MSCAN_TBPR,Transmit Buffer Priority Register"
|
|
group.byte 0x3E++0x01
|
|
line.byte 0x00 "MSCAN_TTSRH,Transmit Time Stamp Register High"
|
|
line.byte 0x01 "MSCAN_TTSRL,Transmit Time Stamp Register Low"
|
|
else
|
|
hgroup.byte 0x3D++0x00
|
|
hide.byte 0x00 "MSCAN_TBPR,Transmit Buffer Priority Register"
|
|
hgroup.byte 0x3E++0x01
|
|
hide.byte 0x00 "MSCAN_TTSRH,Transmit Time Stamp Register High"
|
|
hide.byte 0x01 "MSCAN_TTSRL,Transmit Time Stamp Register Low"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x4006A000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART0_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "One,Two"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART0_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop Mode Select" "Not selected,Selected"
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART Stops in Wait Mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver Source Select" "Internal loop-back mode,Single-wire UART"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit Mode Select" "Start+8 data bits+stop,Start+9 data bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity Type" "Even,Odd"
|
|
line.byte 0x03 "UART0_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-Up"
|
|
bitfld.byte 0x03 0. " SBK ,Send Break" "Normal,Break"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||CPUIS("S9KEAZN8AMTG")||CPUIS("S9KEAZN8ACTG")||CPUIS("S9KEAZN8AMFK")||CPUIS("S9KEAZN8ACFK")||CPUIS("S9KEAZ128AMLH")||CPUIS("S9KEAZ64AMLH")||CPUIS("S9KEAZ128ACLH")||CPUIS("S9KEAZ128AVLH")||CPUIS("S9KEAZ64ACLH")||CPUIS("S9KEAZ64AVLH")||CPUIS("S9KEAZN64ACLH")||CPUIS("S9KEAZ128AVLHR")||CPUIS("S9KEAZ64AMLK")||CPUIS("S9KEAZ128AMLK")||CPUIS("S9KEAZ128ACLK")||CPUIS("S9KEAZ128AVLK")||CPUIS("S9KEAZ64ACLK")||CPUIS("S9KEAZ64AVLK")||CPUIS("S9KEAZN16AMLC")||CPUIS("S9KEAZN32AMLC")||CPUIS("S9KEAZN64AMLC")||CPUIS("S9KEAZN64ACLC")||CPUIS("S9KEAZN16ACLC")||CPUIS("S9KEAZN32ACLC")||CPUIS("S9KEAZN32AVLC")||CPUIS("S9KEAZN16ACLH")||CPUIS("S9KEAZN32ACLH")||CPUIS("S9KEAZN16AMLH")||CPUIS("S9KEAZN32AMLH")||CPUIS("S9KEAZN64AMLH")||CPUIS("S9KEAZN8AMFKR")||CPUIS("S9KEAZN8AVTG")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
in
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART0_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit Complete Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.b(ad:0x4006A000)&0x20)==0)&&((per.b(ad:0x4006A000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "10 bit,13 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006A000)&0x20)==0x20)&&((per.b(ad:0x4006A000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "12 bit,15 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART0_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "11 bit,14 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART0_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART0_D,UART Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
tree "UART1"
|
|
base ad:0x4006B000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART1_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "One,Two"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART1_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop Mode Select" "Not selected,Selected"
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART Stops in Wait Mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver Source Select" "Internal loop-back mode,Single-wire UART"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit Mode Select" "Start+8 data bits+stop,Start+9 data bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity Type" "Even,Odd"
|
|
line.byte 0x03 "UART1_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-Up"
|
|
bitfld.byte 0x03 0. " SBK ,Send Break" "Normal,Break"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||CPUIS("S9KEAZN8AMTG")||CPUIS("S9KEAZN8ACTG")||CPUIS("S9KEAZN8AMFK")||CPUIS("S9KEAZN8ACFK")||CPUIS("S9KEAZ128AMLH")||CPUIS("S9KEAZ64AMLH")||CPUIS("S9KEAZ128ACLH")||CPUIS("S9KEAZ128AVLH")||CPUIS("S9KEAZ64ACLH")||CPUIS("S9KEAZ64AVLH")||CPUIS("S9KEAZN64ACLH")||CPUIS("S9KEAZ128AVLHR")||CPUIS("S9KEAZ64AMLK")||CPUIS("S9KEAZ128AMLK")||CPUIS("S9KEAZ128ACLK")||CPUIS("S9KEAZ128AVLK")||CPUIS("S9KEAZ64ACLK")||CPUIS("S9KEAZ64AVLK")||CPUIS("S9KEAZN16AMLC")||CPUIS("S9KEAZN32AMLC")||CPUIS("S9KEAZN64AMLC")||CPUIS("S9KEAZN64ACLC")||CPUIS("S9KEAZN16ACLC")||CPUIS("S9KEAZN32ACLC")||CPUIS("S9KEAZN32AVLC")||CPUIS("S9KEAZN16ACLH")||CPUIS("S9KEAZN32ACLH")||CPUIS("S9KEAZN16AMLH")||CPUIS("S9KEAZN32AMLH")||CPUIS("S9KEAZN64AMLH")||CPUIS("S9KEAZN8AMFKR")||CPUIS("S9KEAZN8AVTG")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
in
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART1_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit Complete Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.b(ad:0x4006B000)&0x20)==0)&&((per.b(ad:0x4006B000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "10 bit,13 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006B000)&0x20)==0x20)&&((per.b(ad:0x4006B000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "12 bit,15 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART1_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "11 bit,14 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART1_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART1_D,UART Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x4006C000
|
|
width 11.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "UART2_BDH,UART Baud Rate Register High"
|
|
bitfld.byte 0x00 7. " LBKDIE ,LIN Break Detect Interrupt Enable (for LBKDIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RXEDGIE ,RxD Input Active Edge Interrupt Enable (for RXEDGIF)" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SBNS ,Stop Bit Number Select" "One,Two"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--4. " SBR ,UART Baud Rate Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low"
|
|
line.byte 0x02 "UART2_C1,UART Control Register 1"
|
|
bitfld.byte 0x02 7. " LOOPS ,Loop Mode Select" "Not selected,Selected"
|
|
bitfld.byte 0x02 6. " UARTSWAI ,UART Stops in Wait Mode" "Not stopped,Stopped"
|
|
bitfld.byte 0x02 5. " RSRC ,Receiver Source Select" "Internal loop-back mode,Single-wire UART"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " M ,9-bit or 8-bit Mode Select" "Start+8 data bits+stop,Start+9 data bits+stop"
|
|
bitfld.byte 0x02 3. " WAKE ,Receiver Wakeup Method Select" "Idle-line,Address-mark"
|
|
bitfld.byte 0x02 2. " ILT ,Idle Line Type Select" "After start bit,After stop bit"
|
|
textline " "
|
|
bitfld.byte 0x02 1. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " PT ,Parity Type" "Even,Odd"
|
|
line.byte 0x03 "UART2_C2,UART Control Register 2"
|
|
bitfld.byte 0x03 7. " TIE ,Transmitter Interrupt Enable for TDRE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TCIE ,Transmission Complete Interrupt Enable for TC" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receiver Interrupt Enable for RDRF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " ILIE ,Idle Line Interrupt Enable for IDLE" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " RWU ,Receiver Wakeup Control" "Normal,Wake-Up"
|
|
bitfld.byte 0x03 0. " SBK ,Send Break" "Normal,Break"
|
|
sif cpuis("MKE04Z64VLD4")||cpuis("MKE04Z128VLD4")||cpuis("MKE04Z64VQH4")||cpuis("MKE04Z128VQH4")||cpuis("MKE04Z64VLH4")||cpuis("MKE04Z128VLH4")||cpuis("MKE04Z64VLK4")||cpuis("MKE04Z128VLK4")||CPUIS("S9KEAZN8AMTG")||CPUIS("S9KEAZN8ACTG")||CPUIS("S9KEAZN8AMFK")||CPUIS("S9KEAZN8ACFK")||CPUIS("S9KEAZ128AMLH")||CPUIS("S9KEAZ64AMLH")||CPUIS("S9KEAZ128ACLH")||CPUIS("S9KEAZ128AVLH")||CPUIS("S9KEAZ64ACLH")||CPUIS("S9KEAZ64AVLH")||CPUIS("S9KEAZN64ACLH")||CPUIS("S9KEAZ128AVLHR")||CPUIS("S9KEAZ64AMLK")||CPUIS("S9KEAZ128AMLK")||CPUIS("S9KEAZ128ACLK")||CPUIS("S9KEAZ128AVLK")||CPUIS("S9KEAZ64ACLK")||CPUIS("S9KEAZ64AVLK")||CPUIS("S9KEAZN16AMLC")||CPUIS("S9KEAZN32AMLC")||CPUIS("S9KEAZN64AMLC")||CPUIS("S9KEAZN64ACLC")||CPUIS("S9KEAZN16ACLC")||CPUIS("S9KEAZN32ACLC")||CPUIS("S9KEAZN32AVLC")||CPUIS("S9KEAZN16ACLH")||CPUIS("S9KEAZN32ACLH")||CPUIS("S9KEAZN16AMLH")||CPUIS("S9KEAZN32AMLH")||CPUIS("S9KEAZN64AMLH")||CPUIS("S9KEAZN8AMFKR")||CPUIS("S9KEAZN8AVTG")
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
in
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "UART2_S1,UART Status Register 1"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Register Empty Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " TC ,Transmit Complete Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 5. " RDRF ,Receive Data Register Full Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " IDLE ,Idle Line Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 3. " OR ,Receiver Overrun Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " NF ,Noise Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FE ,Framing Error Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " PF ,Parity Error Flag" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.b(ad:0x4006C000)&0x20)==0)&&((per.b(ad:0x4006C000+0x02)&0x10)==0))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "10 bit,13 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,11 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
elif (((per.b(ad:0x4006C000)&0x20)==0x20)&&((per.b(ad:0x4006C000+0x02)&0x10)==0x10))
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "12 bit,15 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,13 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
else
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "UART2_S2,UART Status Register 2"
|
|
eventfld.byte 0x00 7. " LBKDIF ,LIN Break Detect Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.byte 0x00 6. " RXEDGIF ,RxD Pin Active Edge Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RXINV ,Receive Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " RWUID ,Receive Wakeup Idle Detect" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " BRK13 ,Break Transmit Character Length" "11 bit,14 bit"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBKDE ,LIN Break Detection Enable" "Disabled,12 bit"
|
|
rbitfld.byte 0x00 0. " RAF ,Receiver Active Flag" "Idle,Active"
|
|
endif
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "UART2_C3,UART Control Register 3"
|
|
rbitfld.byte 0x00 7. " R8 ,Ninth Data Bit for Receiver" "0,1"
|
|
bitfld.byte 0x00 6. " T8 ,Ninth Data Bit for Transmitter" "0,1"
|
|
bitfld.byte 0x00 5. " TXDIR ,TxD Pin Direction in Single-Wire Mode" "Input,Output"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TXINV ,Transmit Data Inversion" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " NEIE ,Noise Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEIE ,Framing Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PEIE ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
hgroup.byte 0x07++0x0
|
|
hide.byte 0x00 "UART2_D,UART Data Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "GPIO (General-Purpose Input/Output)"
|
|
tree "GPIO_A"
|
|
base ad:0x400FF000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_PDOR,Port Data Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDO[30] ,Port Data Output PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDO[29] ,Port Data Output PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDO[28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDO[25] ,Port Data Output PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDO[24] ,Port Data Output PTD0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PDO[23] ,Port Data Output PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDO[22] ,Port Data Output PTC6" "Low level,High level"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDO[21] ,Port Data Output PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDO[20] ,Port Data Output PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDO[19] ,Port Data Output PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDO[18] ,Port Data Output PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " PDO[16] ,Port Data Output PTC0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PDO[15] ,Port Data Output PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDO[14] ,Port Data Output PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDO[13] ,Port Data Output PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " PDO[12] ,Port Data Output PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PDO[11] ,Port Data Output PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDO[10] ,Port Data Output PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDO[9] ,Port Data Output PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " PDO[8] ,Port Data Output PTB0" "Low level,High level"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PDO[7] ,Port Data Output PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTA6" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PDO[5] ,Port Data Output PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTA4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDO[3] ,Port Data Output PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDO[2] ,Port Data Output PTA2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDO[1] ,Port Data Output PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDO[0] ,Port Data Output PTA0" "Low level,High level"
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "GPIOA_PSOR,Port Set Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 30. " PTSO[30] ,Port Set Output PTD6" "No effect,Set"
|
|
bitfld.long 0x00 29. " PTSO[29] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 28. " PTSO[28] ,Port Set Output PTD4" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTD3" "No effect,Set"
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTD2" "No effect,Set"
|
|
bitfld.long 0x00 25. " PTSO[25] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 24. " PTSO[24] ,Port Set Output PTD0" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PTSO[23] ,Port Set Output PTC7" "No effect,Set"
|
|
bitfld.long 0x00 22. " PTSO[22] ,Port Set Output PTC6" "No effect,Set"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PTSO[21] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 20. " PTSO[20] ,Port Set Output PTC4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTSO[19] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 18. " PTSO[18] ,Port Set Output PTC2" "No effect,Set"
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTC1" "No effect,Set"
|
|
bitfld.long 0x00 16. " PTSO[16] ,Port Set Output PTC0" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PTSO[15] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 14. " PTSO[14] ,Port Set Output PTB6" "No effect,Set"
|
|
bitfld.long 0x00 13. " PTSO[13] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 12. " PTSO[12] ,Port Set Output PTB4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTSO[11] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 10. " PTSO[10] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 9. " PTSO[9] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 8. " PTSO[8] ,Port Set Output PTB0" "No effect,Set"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PTSO[7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTA6" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PTSO[5] ,Port Set Output PTA5" "No effect,Set"
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTA4" "No effect,Set"
|
|
bitfld.long 0x00 3. " PTSO[3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " PTSO[2] ,Port Set Output PTA2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTSO[1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " PTSO[0] ,Port Set Output PTA0" "No effect,Set"
|
|
line.long 0x04 "GPIOA_PCOR,Port Clear Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PTCO[31] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x04 30. " PTCO[30] ,Port Clear Output PTD6" "No effect,Clear"
|
|
bitfld.long 0x04 29. " PTCO[29] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x04 28. " PTCO[28] ,Port Clear Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 27. " PTCO[27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
bitfld.long 0x04 26. " PTCO[26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
bitfld.long 0x04 25. " PTCO[25] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x04 24. " PTCO[24] ,Port Clear Output PTD0" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 23. " PTCO[23] ,Port Clear Output PTC7" "No effect,Clear"
|
|
bitfld.long 0x04 22. " PTCO[22] ,Port Clear Output PTC6" "No effect,Clear"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x04 21. " PTCO[21] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x04 20. " PTCO[20] ,Port Clear Output PTC4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PTCO[19] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x04 18. " PTCO[18] ,Port Clear Output PTC2" "No effect,Clear"
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTC1" "No effect,Clear"
|
|
bitfld.long 0x04 16. " PTCO[16] ,Port Clear Output PTC0" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " PTCO[15] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x04 14. " PTCO[14] ,Port Clear Output PTB6" "No effect,Clear"
|
|
bitfld.long 0x04 13. " PTCO[13] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x04 12. " PTCO[12] ,Port Clear Output PTB4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PTCO[11] ,Port Set Output PTB3" "No effect,Clear"
|
|
bitfld.long 0x04 10. " PTCO[10] ,Port Set Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x04 9. " PTCO[9] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x04 8. " PTCO[8] ,Port Clear Output PTB0" "No effect,Clear"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 7. " PTCO[7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " PTCO[6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " PTCO[5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PTCO[3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " PTCO[2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PTCO[1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " PTCO[0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
line.long 0x08 "GPIOA_PTOR,Port Toggle Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x08 31. " PTTO[31] ,Port Toggle Output PTD7" "No effect,Toggled"
|
|
bitfld.long 0x08 30. " PTTO[30] ,Port Toggle Output PTD6" "No effect,Toggled"
|
|
bitfld.long 0x08 29. " PTTO[29] ,Port Toggle Output PTD5" "No effect,Toggled"
|
|
bitfld.long 0x08 28. " PTTO[28] ,Port Toggle Output PTD4" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 27. " PTTO[27] ,Port Toggle Output PTD3" "No effect,Toggled"
|
|
bitfld.long 0x08 26. " PTTO[26] ,Port Toggle Output PTD2" "No effect,Toggled"
|
|
bitfld.long 0x08 25. " PTTO[25] ,Port Toggle Output PTD1" "No effect,Toggled"
|
|
bitfld.long 0x08 24. " PTTO[24] ,Port Toggle Output PTD0" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 23. " PTTO[23] ,Port Toggle Output PTC7" "No effect,Toggled"
|
|
bitfld.long 0x08 22. " PTTO[22] ,Port Toggle Output PTC6" "No effect,Toggled"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x08 21. " PTTO[21] ,Port Toggle Output PTC5" "No effect,Toggled"
|
|
bitfld.long 0x08 20. " PTTO[20] ,Port Toggle Output PTC4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTTO[19] ,Port Toggle Output PTC3" "No effect,Toggled"
|
|
bitfld.long 0x08 18. " PTTO[18] ,Port Toggle Output PTC2" "No effect,Toggled"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTC1" "No effect,Toggled"
|
|
bitfld.long 0x08 16. " PTTO[16] ,Port Toggle Output PTC0" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15. " PTTO[15] ,Port Toggle Output PTB7" "No effect,Toggled"
|
|
bitfld.long 0x08 14. " PTTO[14] ,Port Toggle Output PTB6" "No effect,Toggled"
|
|
bitfld.long 0x08 13. " PTTO[13] ,Port Toggle Output PTB5" "No effect,Toggled"
|
|
bitfld.long 0x08 12. " PTTO[12] ,Port Toggle Output PTB4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PTTO[11] ,Port Toggle Output PTB3" "No effect,Toggled"
|
|
bitfld.long 0x08 10. " PTTO[10] ,Port Toggle Output PTB2" "No effect,Toggled"
|
|
bitfld.long 0x08 9. " PTTO[9] ,Port Toggle Output PTB1" "No effect,Toggled"
|
|
bitfld.long 0x08 8. " PTTO[8] ,Port Toggle Output PTB0" "No effect,Toggled"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 7. " PTTO[7] ,Port Toggle Output PTA7" "No effect,Toggled"
|
|
bitfld.long 0x08 6. " PTTO[6] ,Port Toggle Output PTA6" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 5. " PTTO[5] ,Port Toggle Output PTA5" "No effect,Toggled"
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTA4" "No effect,Toggled"
|
|
bitfld.long 0x08 3. " PTTO[3] ,Port Toggle Output PTA3" "No effect,Toggled"
|
|
bitfld.long 0x08 2. " PTTO[2] ,Port Toggle Output PTA2" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PTTO[1] ,Port Toggle Output PTA1" "No effect,Toggled"
|
|
bitfld.long 0x08 0. " PTTO[0] ,Port Toggle Output PTA0" "No effect,Toggled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_PDIR,Port Data Input Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port Data Input PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port Data Input PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDI[28] ,Port Data Input PTD4" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port Data Input PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port Data Input PTD0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PDI[23] ,Port Data Input PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port Data Input PTC6" "Low level,High level"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDI[21] ,Port Data Input PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port Data Input PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDI[19] ,Port Data Input PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port Data Input PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port Data Input PTC0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PDI[15] ,Port Data Input PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port Data Input PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port Data Input PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port Data Input PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PDI[11] ,Port Data Input PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port Data Input PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port Data Input PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port Data Input PTB0" "Low level,High level"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PDI[7] ,Port Data Input PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTA6" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PDI[5] ,Port Data Input PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTA4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port Data Input PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port Data Input PTA2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDI[1] ,Port Data Input PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port Data Input PTA0" "Low level,High level"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "GPIOA_PDDR,Port Data Direction Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port Data Direction PTD6" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 28. " PDD[28] ,Port Data Direction PTD4" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTD3" "Input,Output"
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTD2" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port Data Direction PTD0" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PDD[23] ,Port Data Direction PTC7" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port Data Direction PTC6" "Input,Output"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDD[21] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port Data Direction PTC4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDD[19] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port Data Direction PTC2" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTC1" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port Data Direction PTC0" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PDD[15] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port Data Direction PTB6" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port Data Direction PTB4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PDD[11] ,Port Data Direction PTB3" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port Data Direction PTB0" "Input,Output"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PDD[7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTA6" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PDD[5] ,Port Data Direction PTA5" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTA4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port Data Direction PTA2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDD[1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port Data Direction PTA0" "Input,Output"
|
|
line.long 0x04 "GPIOA_PIDR,Port Input Disable Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PID[31] ,Port Input Disable PTD7" "No,Yes"
|
|
bitfld.long 0x04 30. " PID[30] ,Port Input Disable PTD6" "No,Yes"
|
|
bitfld.long 0x04 29. " PID[29] ,Port Input Disable PTD5" "No,Yes"
|
|
bitfld.long 0x04 28. " PID[28] ,Port Input Disable PTD4" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 27. " PID[27] ,Port Input Disable PTD3" "No,Yes"
|
|
bitfld.long 0x04 26. " PID[26] ,Port Input Disable PTD2" "No,Yes"
|
|
bitfld.long 0x04 25. " PID[25] ,Port Input Disable PTD1" "No,Yes"
|
|
bitfld.long 0x04 24. " PID[24] ,Port Input Disable PTD0" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 23. " PID[23] ,Port Input Disable PTC7" "No,Yes"
|
|
bitfld.long 0x04 22. " PID[22] ,Port Input Disable PTC6" "No,Yes"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x04 21. " PID[21] ,Port Input Disable PTC5" "No,Yes"
|
|
bitfld.long 0x04 20. " PID[20] ,Port Input Disable PTC4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PID[19] ,Port Input Disable PTC3" "No,Yes"
|
|
bitfld.long 0x04 18. " PID[18] ,Port Input Disable PTC2" "No,Yes"
|
|
bitfld.long 0x04 17. " PID[17] ,Port Input Disable PTC1" "No,Yes"
|
|
bitfld.long 0x04 16. " PID[16] ,Port Input Disable PTC0" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " PID[15] ,Port Input Disable PTB7" "No,Yes"
|
|
bitfld.long 0x04 14. " PID[14] ,Port Input Disable PTB6" "No,Yes"
|
|
bitfld.long 0x04 13. " PID[13] ,Port Input Disable PTB5" "No,Yes"
|
|
bitfld.long 0x04 12. " PID[12] ,Port Input Disable PTB4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PID[11] ,Port Input Disable PTB3" "No,Yes"
|
|
bitfld.long 0x04 10. " PID[10] ,Port Input Disable PTB2" "No,Yes"
|
|
bitfld.long 0x04 9. " PID[9] ,Port Input Disable PTB1" "No,Yes"
|
|
bitfld.long 0x04 8. " PID[8] ,Port Input Disable PTB0" "No,Yes"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 7. " PID[7] ,Port Input Disable PTA7" "No,Yes"
|
|
bitfld.long 0x04 6. " PID[6] ,Port Input Disable PTA6" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " PID[5] ,Port Input Disable PTA5" "No,Yes"
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTA4" "No,Yes"
|
|
bitfld.long 0x04 3. " PID[3] ,Port Input Disable PTA3" "No,Yes"
|
|
bitfld.long 0x04 2. " PID[2] ,Port Input Disable PTA2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PID[1] ,Port Input Disable PTA1" "No,Yes"
|
|
bitfld.long 0x04 0. " PID[0] ,Port Input Disable PTA0" "No,Yes"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "GPIO_B"
|
|
base ad:0x400FF040
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDO[30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDO[29] ,Port Data Output PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDO[28] ,Port Data Output PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDO[25] ,Port Data Output PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDO[24] ,Port Data Output PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PDO[23] ,Port Data Output PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDO[22] ,Port Data Output PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " PDO[21] ,Port Data Output PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDO[20] ,Port Data Output PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDO[19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDO[18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTG1" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDO[30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDO[25] ,Port Data Output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PDO[24] ,Port Data Output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " PDO[19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDO[18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTG1" "Low level,High level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDO[16] ,Port Data Output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " PDO[15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDO[14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDO[13] ,Port Data Output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDO[12] ,Port Data Output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " PDO[11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDO[10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDO[9] ,Port Data Output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PDO[8] ,Port Data Output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " PDO[7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDO[5] ,Port Data Output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDO[3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDO[2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDO[1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDO[0] ,Port Data Output PTE0" "Low level,High level"
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "GPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
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|
bitfld.long 0x00 30. " PTSO[30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 29. " PTSO[29] ,Port Set Output PTH5" "No effect,Set"
|
|
bitfld.long 0x00 28. " PTSO[28] ,Port Set Output PTH4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTH3" "No effect,Set"
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " PTSO[25] ,Port Set Output PTH1" "No effect,Set"
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|
bitfld.long 0x00 24. " PTSO[24] ,Port Set Output PTH0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PTSO[23] ,Port Set Output PTG7" "No effect,Set"
|
|
bitfld.long 0x00 22. " PTSO[22] ,Port Set Output PTG6" "No effect,Set"
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|
bitfld.long 0x00 21. " PTSO[21] ,Port Set Output PTG5" "No effect,Set"
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|
bitfld.long 0x00 20. " PTSO[20] ,Port Set Output PTG4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTSO[19] ,Port Set Output PTG3" "No effect,Set"
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|
bitfld.long 0x00 18. " PTSO[18] ,Port Set Output PTG2" "No effect,Set"
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bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTG1" "No effect,Set"
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|
else
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
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|
bitfld.long 0x00 30. " PTSO[30] ,Port Set Output PTH6" "No effect,Set"
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|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
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|
bitfld.long 0x00 25. " PTSO[25] ,Port Set Output PTH1" "No effect,Set"
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|
textline " "
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bitfld.long 0x00 24. " PTSO[24] ,Port Set Output PTH0" "No effect,Set"
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bitfld.long 0x00 19. " PTSO[19] ,Port Set Output PTG3" "No effect,Set"
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|
bitfld.long 0x00 18. " PTSO[18] ,Port Set Output PTG2" "No effect,Set"
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bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTG1" "No effect,Set"
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|
endif
|
|
textline " "
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|
bitfld.long 0x00 16. " PTSO[16] ,Port Set Output PTG0" "No effect,Set"
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|
bitfld.long 0x00 15. " PTSO[15] ,Port Set Output PTF7" "No effect,Set"
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|
bitfld.long 0x00 14. " PTSO[14] ,Port Set Output PTF6" "No effect,Set"
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|
bitfld.long 0x00 13. " PTSO[13] ,Port Set Output PTF5" "No effect,Set"
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|
textline " "
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bitfld.long 0x00 12. " PTSO[12] ,Port Set Output PTF4" "No effect,Set"
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|
bitfld.long 0x00 11. " PTSO[11] ,Port Set Output PTB3" "No effect,Set"
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bitfld.long 0x00 10. " PTSO[10] ,Port Set Output PTF2" "No effect,Set"
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bitfld.long 0x00 9. " PTSO[9] ,Port Set Output PTF1" "No effect,Set"
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|
textline " "
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bitfld.long 0x00 8. " PTSO[8] ,Port Set Output PTF0" "No effect,Set"
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bitfld.long 0x00 7. " PTSO[7] ,Port Set Output PTE7" "No effect,Set"
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bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTE6" "No effect,Set"
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bitfld.long 0x00 5. " PTSO[5] ,Port Set Output PTE5" "No effect,Set"
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|
textline " "
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bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTE4" "No effect,Set"
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bitfld.long 0x00 3. " PTSO[3] ,Port Set Output PTA3" "No effect,Set"
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bitfld.long 0x00 2. " PTSO[2] ,Port Set Output PTE2" "No effect,Set"
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bitfld.long 0x00 1. " PTSO[1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
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bitfld.long 0x00 0. " PTSO[0] ,Port Set Output PTE0" "No effect,Set"
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line.long 0x04 "GPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
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bitfld.long 0x04 31. " PTCO[31] ,Port Clear Output PTH7" "No effect,Clear"
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bitfld.long 0x04 30. " PTCO[30] ,Port Clear Output PTH6" "No effect,Clear"
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bitfld.long 0x04 29. " PTCO[29] ,Port Clear Output PTH5" "No effect,Clear"
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bitfld.long 0x04 28. " PTCO[28] ,Port Clear Output PTH4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PTCO[27] ,Port Clear Output PTH3" "No effect,Clear"
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bitfld.long 0x04 26. " PTCO[26] ,Port Clear Output PTH2" "No effect,Clear"
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bitfld.long 0x04 25. " PTCO[25] ,Port Clear Output PTH1" "No effect,Clear"
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bitfld.long 0x04 24. " PTCO[24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
textline " "
|
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bitfld.long 0x04 23. " PTCO[23] ,Port Clear Output PTG7" "No effect,Clear"
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bitfld.long 0x04 22. " PTCO[22] ,Port Clear Output PTG6" "No effect,Clear"
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bitfld.long 0x04 21. " PTCO[21] ,Port Clear Output PTG5" "No effect,Clear"
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bitfld.long 0x04 20. " PTCO[20] ,Port Clear Output PTG4" "No effect,Clear"
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|
textline " "
|
|
bitfld.long 0x04 19. " PTCO[19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x04 18. " PTCO[18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 31. " PTCO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x04 30. " PTCO[30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x04 26. " PTCO[26] ,Port Clear Output PTH2" "No effect,Clear"
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bitfld.long 0x04 25. " PTCO[25] ,Port Clear Output PTH1" "No effect,Clear"
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|
textline " "
|
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bitfld.long 0x04 24. " PTCO[24] ,Port Clear Output PTH0" "No effect,Clear"
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|
bitfld.long 0x04 19. " PTCO[19] ,Port Clear Output PTG3" "No effect,Clear"
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bitfld.long 0x04 18. " PTCO[18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16. " PTCO[16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
bitfld.long 0x04 15. " PTCO[15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x04 14. " PTCO[14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x04 13. " PTCO[13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PTCO[12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
bitfld.long 0x04 11. " PTCO[11] ,Port Set Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x04 10. " PTCO[10] ,Port Set Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x04 9. " PTCO[9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PTCO[8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
bitfld.long 0x04 7. " PTCO[7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " PTCO[6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " PTCO[5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PTCO[3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " PTCO[2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " PTCO[1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PTCO[0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
line.long 0x08 "GPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x08 31. " PTTO[31] ,Port Toggled Output PTH7" "No effect,Toggled"
|
|
bitfld.long 0x08 30. " PTTO[30] ,Port Toggled Output PTH6" "No effect,Toggled"
|
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bitfld.long 0x08 29. " PTTO[29] ,Port Toggled Output PTH5" "No effect,Toggled"
|
|
bitfld.long 0x08 28. " PTTO[28] ,Port Toggled Output PTH4" "No effect,Toggled"
|
|
textline " "
|
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bitfld.long 0x08 27. " PTTO[27] ,Port Toggled Output PTH3" "No effect,Toggled"
|
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bitfld.long 0x08 26. " PTTO[26] ,Port Toggled Output PTH2" "No effect,Toggled"
|
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bitfld.long 0x08 25. " PTTO[25] ,Port Toggled Output PTH1" "No effect,Toggled"
|
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bitfld.long 0x08 24. " PTTO[24] ,Port Toggled Output PTH0" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PTTO[23] ,Port Toggled Output PTG7" "No effect,Toggled"
|
|
bitfld.long 0x08 22. " PTTO[22] ,Port Toggled Output PTG6" "No effect,Toggled"
|
|
bitfld.long 0x08 21. " PTTO[21] ,Port Toggled Output PTG5" "No effect,Toggled"
|
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bitfld.long 0x08 20. " PTTO[20] ,Port Toggled Output PTG4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTTO[19] ,Port Toggled Output PTG3" "No effect,Toggled"
|
|
bitfld.long 0x08 18. " PTTO[18] ,Port Toggled Output PTG2" "No effect,Toggled"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggled Output PTG1" "No effect,Toggled"
|
|
else
|
|
bitfld.long 0x08 31. " PTTO[31] ,Port Toggle Output PTH7" "No effect,Toggled"
|
|
bitfld.long 0x08 30. " PTTO[30] ,Port Toggle Output PTH6" "No effect,Toggled"
|
|
bitfld.long 0x08 26. " PTTO[26] ,Port Toggle Output PTH2" "No effect,Toggled"
|
|
bitfld.long 0x08 25. " PTTO[25] ,Port Toggle Output PTH1" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " PTTO[24] ,Port Toggle Output PTH0" "No effect,Toggled"
|
|
bitfld.long 0x08 19. " PTTO[19] ,Port Toggle Output PTG3" "No effect,Toggled"
|
|
bitfld.long 0x08 18. " PTTO[18] ,Port Toggle Output PTG2" "No effect,Toggled"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTG1" "No effect,Toggled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 16. " PTTO[16] ,Port Toggle Output PTG0" "No effect,Toggled"
|
|
bitfld.long 0x08 15. " PTTO[15] ,Port Toggle Output PTF7" "No effect,Toggled"
|
|
bitfld.long 0x08 14. " PTTO[14] ,Port Toggle Output PTF6" "No effect,Toggled"
|
|
bitfld.long 0x08 13. " PTTO[13] ,Port Toggle Output PTF5" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PTTO[12] ,Port Toggle Output PTF4" "No effect,Toggled"
|
|
bitfld.long 0x08 11. " PTTO[11] ,Port Toggle Output PTF3" "No effect,Toggled"
|
|
bitfld.long 0x08 10. " PTTO[10] ,Port Toggle Output PTF2" "No effect,Toggled"
|
|
bitfld.long 0x08 9. " PTTO[9] ,Port Toggle Output PTF1" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PTTO[8] ,Port Toggle Output PTF0" "No effect,Toggled"
|
|
bitfld.long 0x08 7. " PTTO[7] ,Port Toggle Output PTE7" "No effect,Toggled"
|
|
bitfld.long 0x08 6. " PTTO[6] ,Port Toggle Output PTE6" "No effect,Toggled"
|
|
bitfld.long 0x08 5. " PTTO[5] ,Port Toggle Output PTE5" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTE4" "No effect,Toggled"
|
|
bitfld.long 0x08 3. " PTTO[3] ,Port Toggle Output PTE3" "No effect,Toggled"
|
|
bitfld.long 0x08 2. " PTTO[2] ,Port Toggle Output PTE2" "No effect,Toggled"
|
|
bitfld.long 0x08 1. " PTTO[1] ,Port Toggle Output PTE1" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PTTO[0] ,Port Toggle Output PTE0" "No effect,Toggled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port Data Input PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDI[28] ,Port Data Input PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port Data Input PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port Data Input PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PDI[23] ,Port Data Input PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port Data Input PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port Data Input PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port Data Input PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDI[19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTG1" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port Data Input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PDI[24] ,Port Data Input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTG1" "Low level,High level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDI[16] ,Port Data Input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port Data Input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI[12] ,Port Data Input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port Data Input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PDI[8] ,Port Data Input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port Data Input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDI[0] ,Port Data Input PTE0" "Low level,High level"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "GPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port Data Direction PTH5" "Input,Output"
|
|
bitfld.long 0x00 28. " PDD[28] ,Port Data Direction PTH4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTH3" "Input,Output"
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port Data Direction PTH1" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port Data Direction PTH0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PDD[23] ,Port Data Direction PTG7" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port Data Direction PTG6" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port Data Direction PTG5" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port Data Direction PTG4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDD[19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTG1" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port Data Direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PDD[24] ,Port Data Direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTG1" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDD[16] ,Port Data Direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port Data Direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDD[12] ,Port Data Direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port Data Direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PDD[8] ,Port Data Direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port Data Direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDD[0] ,Port Data Direction PTE0" "Input,Output"
|
|
line.long 0x04 "GPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x04 30. " PID[30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x04 29. " PID[29] ,Port Input Disable PTH5" "No,Yes"
|
|
bitfld.long 0x04 28. " PID[28] ,Port Input Disable PTH4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PID[27] ,Port Input Disable PTH3" "No,Yes"
|
|
bitfld.long 0x04 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x04 25. " PID[25] ,Port Input Disable PTH1" "No,Yes"
|
|
bitfld.long 0x04 24. " PID[24] ,Port Input Disable PTH0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PID[23] ,Port Input Disable PTG7" "No,Yes"
|
|
bitfld.long 0x04 22. " PID[22] ,Port Input Disable PTG6" "No,Yes"
|
|
bitfld.long 0x04 21. " PID[21] ,Port Input Disable PTG5" "No,Yes"
|
|
bitfld.long 0x04 20. " PID[20] ,Port Input Disable PTG4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PID[19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x04 18. " PID[18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x04 17. " PID[17] ,Port Input Disable PTG1" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x04 30. " PID[30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x04 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x04 25. " PID[25] ,Port Input Disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PID[24] ,Port Input Disable PTH0" "No,Yes"
|
|
bitfld.long 0x04 19. " PID[19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x04 18. " PID[18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x04 17. " PID[17] ,Port Input Disable PTG1" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16. " PID[16] ,Port Input Disable PTG0" "No,Yes"
|
|
bitfld.long 0x04 15. " PID[15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x04 14. " PID[14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x04 13. " PID[13] ,Port Input Disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PID[12] ,Port Input Disable PTF4" "No,Yes"
|
|
bitfld.long 0x04 11. " PID[11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x04 10. " PID[10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x04 9. " PID[9] ,Port Input Disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PID[8] ,Port Input Disable PTF0" "No,Yes"
|
|
bitfld.long 0x04 7. " PID[7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x04 6. " PID[6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x04 5. " PID[5] ,Port Input Disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTE4" "No,Yes"
|
|
bitfld.long 0x04 3. " PID[3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x04 2. " PID[2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x04 1. " PID[1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PID[0] ,Port Input Disable PTE0" "No,Yes"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "GPIO_C"
|
|
base ad:0x400FF080
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOC_PDOR,Port Data Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTI4" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDO[5] ,Port Data Output PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTI4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDO[3] ,Port Data Output PTI3" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDO[2] ,Port Data Output PTI2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDO[1] ,Port Data Output PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDO[0] ,Port Data Output PTI0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "GPIOC_PSOR,Port Set Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTI4" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTI6" "No effect,Set"
|
|
bitfld.long 0x00 5. " PTSO[5] ,Port Set Output PTI5" "No effect,Set"
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTI4" "No effect,Set"
|
|
bitfld.long 0x00 3. " PTSO[3] ,Port Set Output PTI3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTSO[2] ,Port Set Output PTI2" "No effect,Set"
|
|
bitfld.long 0x00 1. " PTSO[1] ,Port Set Output PTI1" "No effect,Set"
|
|
bitfld.long 0x00 0. " PTSO[0] ,Port Set Output PTI0" "No effect,Set"
|
|
endif
|
|
line.long 0x04 "GPIOC_PCOR,Port Clear Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 6. " PTCO[6] ,Port Clear Output PTI6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " PTCO[5] ,Port Clear Output PTI5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PTCO[3] ,Port Clear Output PTI3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PTCO[2] ,Port Clear Output PTI2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " PTCO[1] ,Port Clear Output PTI1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " PTCO[0] ,Port Clear Output PTI0" "No effect,Clear"
|
|
endif
|
|
line.long 0x08 "GPIOC_PTOR,Port Toggle Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTI4" "No effect,Toggled"
|
|
else
|
|
bitfld.long 0x08 6. " PTTO[6] ,Port Toggle Output PTI6" "No effect,Toggled"
|
|
bitfld.long 0x08 5. " PTTO[5] ,Port Toggle Output PTE5" "No effect,Toggled"
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTI4" "No effect,Toggled"
|
|
bitfld.long 0x08 3. " PTTO[3] ,Port Toggle Output PTI3" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PTTO[2] ,Port Toggle Output PTI2" "No effect,Toggled"
|
|
bitfld.long 0x08 1. " PTTO[1] ,Port Toggle Output PTI1" "No effect,Toggled"
|
|
bitfld.long 0x08 0. " PTTO[0] ,Port Toggle Output PTI0" "No effect,Toggled"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_PDIR,Port Data Input Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTI4" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port Data Input PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTI4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port Data Input PTI3" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDI[2] ,Port Data Input PTI2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port Data Input PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port Data Input PTI0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "GPIOC_PDDR,Port Data Direction Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTI4" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTI6" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port Data Direction PTI5" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTI4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port Data Direction PTI3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDD[2] ,Port Data Direction PTI2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port Data Direction PTI1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port Data Direction PTI0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "GPIOC_PIDR,Port Input Disable Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTI4" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 6. " PID[6] ,Port Input Disable PTI6" "No,Yes"
|
|
bitfld.long 0x04 5. " PID[5] ,Port Input Disable PTI5" "No,Yes"
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTI4" "No,Yes"
|
|
bitfld.long 0x04 3. " PID[3] ,Port Input Disable PTI3" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PID[2] ,Port Input Disable PTI2" "No,Yes"
|
|
bitfld.long 0x04 1. " PID[1] ,Port Input Disable PTI1" "No,Yes"
|
|
bitfld.long 0x04 0. " PID[0] ,Port Input Disable PTI0" "No,Yes"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "FGPIO_A"
|
|
base ad:0xF8000000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIOA_PDOR,Port Data Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDO[30] ,Port Data Output PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDO[29] ,Port Data Output PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDO[28] ,Port Data Output PTD4" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDO[25] ,Port Data Output PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDO[24] ,Port Data Output PTD0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PDO[23] ,Port Data Output PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDO[22] ,Port Data Output PTC6" "Low level,High level"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDO[21] ,Port Data Output PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDO[20] ,Port Data Output PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDO[19] ,Port Data Output PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDO[18] ,Port Data Output PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " PDO[16] ,Port Data Output PTC0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PDO[15] ,Port Data Output PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDO[14] ,Port Data Output PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDO[13] ,Port Data Output PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " PDO[12] ,Port Data Output PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PDO[11] ,Port Data Output PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDO[10] ,Port Data Output PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDO[9] ,Port Data Output PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " PDO[8] ,Port Data Output PTB0" "Low level,High level"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PDO[7] ,Port Data Output PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTA6" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PDO[5] ,Port Data Output PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTA4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDO[3] ,Port Data Output PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDO[2] ,Port Data Output PTA2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDO[1] ,Port Data Output PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDO[0] ,Port Data Output PTA0" "Low level,High level"
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "FGPIOA_PSOR,Port Set Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTD7" "No effect,Set"
|
|
bitfld.long 0x00 30. " PTSO[30] ,Port Set Output PTD6" "No effect,Set"
|
|
bitfld.long 0x00 29. " PTSO[29] ,Port Set Output PTD5" "No effect,Set"
|
|
bitfld.long 0x00 28. " PTSO[28] ,Port Set Output PTD4" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTD3" "No effect,Set"
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTD2" "No effect,Set"
|
|
bitfld.long 0x00 25. " PTSO[25] ,Port Set Output PTD1" "No effect,Set"
|
|
bitfld.long 0x00 24. " PTSO[24] ,Port Set Output PTD0" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PTSO[23] ,Port Set Output PTC7" "No effect,Set"
|
|
bitfld.long 0x00 22. " PTSO[22] ,Port Set Output PTC6" "No effect,Set"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PTSO[21] ,Port Set Output PTC5" "No effect,Set"
|
|
bitfld.long 0x00 20. " PTSO[20] ,Port Set Output PTC4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTSO[19] ,Port Set Output PTC3" "No effect,Set"
|
|
bitfld.long 0x00 18. " PTSO[18] ,Port Set Output PTC2" "No effect,Set"
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTC1" "No effect,Set"
|
|
bitfld.long 0x00 16. " PTSO[16] ,Port Set Output PTC0" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PTSO[15] ,Port Set Output PTB7" "No effect,Set"
|
|
bitfld.long 0x00 14. " PTSO[14] ,Port Set Output PTB6" "No effect,Set"
|
|
bitfld.long 0x00 13. " PTSO[13] ,Port Set Output PTB5" "No effect,Set"
|
|
bitfld.long 0x00 12. " PTSO[12] ,Port Set Output PTB4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PTSO[11] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 10. " PTSO[10] ,Port Set Output PTB2" "No effect,Set"
|
|
bitfld.long 0x00 9. " PTSO[9] ,Port Set Output PTB1" "No effect,Set"
|
|
bitfld.long 0x00 8. " PTSO[8] ,Port Set Output PTB0" "No effect,Set"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PTSO[7] ,Port Set Output PTA7" "No effect,Set"
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTA6" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PTSO[5] ,Port Set Output PTA5" "No effect,Set"
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTA4" "No effect,Set"
|
|
bitfld.long 0x00 3. " PTSO[3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " PTSO[2] ,Port Set Output PTA2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PTSO[1] ,Port Set Output PTA1" "No effect,Set"
|
|
bitfld.long 0x00 0. " PTSO[0] ,Port Set Output PTA0" "No effect,Set"
|
|
line.long 0x04 "FGPIOA_PCOR,Port Clear Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PTCO[31] ,Port Clear Output PTD7" "No effect,Clear"
|
|
bitfld.long 0x04 30. " PTCO[30] ,Port Clear Output PTD6" "No effect,Clear"
|
|
bitfld.long 0x04 29. " PTCO[29] ,Port Clear Output PTD5" "No effect,Clear"
|
|
bitfld.long 0x04 28. " PTCO[28] ,Port Clear Output PTD4" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 27. " PTCO[27] ,Port Clear Output PTD3" "No effect,Clear"
|
|
bitfld.long 0x04 26. " PTCO[26] ,Port Clear Output PTD2" "No effect,Clear"
|
|
bitfld.long 0x04 25. " PTCO[25] ,Port Clear Output PTD1" "No effect,Clear"
|
|
bitfld.long 0x04 24. " PTCO[24] ,Port Clear Output PTD0" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 23. " PTCO[23] ,Port Clear Output PTC7" "No effect,Clear"
|
|
bitfld.long 0x04 22. " PTCO[22] ,Port Clear Output PTC6" "No effect,Clear"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x04 21. " PTCO[21] ,Port Clear Output PTC5" "No effect,Clear"
|
|
bitfld.long 0x04 20. " PTCO[20] ,Port Clear Output PTC4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PTCO[19] ,Port Clear Output PTC3" "No effect,Clear"
|
|
bitfld.long 0x04 18. " PTCO[18] ,Port Clear Output PTC2" "No effect,Clear"
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTC1" "No effect,Clear"
|
|
bitfld.long 0x04 16. " PTCO[16] ,Port Clear Output PTC0" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " PTCO[15] ,Port Clear Output PTB7" "No effect,Clear"
|
|
bitfld.long 0x04 14. " PTCO[14] ,Port Clear Output PTB6" "No effect,Clear"
|
|
bitfld.long 0x04 13. " PTCO[13] ,Port Clear Output PTB5" "No effect,Clear"
|
|
bitfld.long 0x04 12. " PTCO[12] ,Port Clear Output PTB4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PTCO[11] ,Port Set Output PTB3" "No effect,Clear"
|
|
bitfld.long 0x04 10. " PTCO[10] ,Port Set Output PTB2" "No effect,Clear"
|
|
bitfld.long 0x04 9. " PTCO[9] ,Port Clear Output PTB1" "No effect,Clear"
|
|
bitfld.long 0x04 8. " PTCO[8] ,Port Clear Output PTB0" "No effect,Clear"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 7. " PTCO[7] ,Port Clear Output PTA7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " PTCO[6] ,Port Clear Output PTA6" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " PTCO[5] ,Port Clear Output PTA5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTA4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PTCO[3] ,Port Clear Output PTA3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " PTCO[2] ,Port Clear Output PTA2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PTCO[1] ,Port Clear Output PTA1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " PTCO[0] ,Port Clear Output PTA0" "No effect,Clear"
|
|
line.long 0x08 "FGPIOA_PTOR,Port Toggle Output Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x08 31. " PTTO[31] ,Port Toggle Output PTD7" "No effect,Toggled"
|
|
bitfld.long 0x08 30. " PTTO[30] ,Port Toggle Output PTD6" "No effect,Toggled"
|
|
bitfld.long 0x08 29. " PTTO[29] ,Port Toggle Output PTD5" "No effect,Toggled"
|
|
bitfld.long 0x08 28. " PTTO[28] ,Port Toggle Output PTD4" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 27. " PTTO[27] ,Port Toggle Output PTD3" "No effect,Toggled"
|
|
bitfld.long 0x08 26. " PTTO[26] ,Port Toggle Output PTD2" "No effect,Toggled"
|
|
bitfld.long 0x08 25. " PTTO[25] ,Port Toggle Output PTD1" "No effect,Toggled"
|
|
bitfld.long 0x08 24. " PTTO[24] ,Port Toggle Output PTD0" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 23. " PTTO[23] ,Port Toggle Output PTC7" "No effect,Toggled"
|
|
bitfld.long 0x08 22. " PTTO[22] ,Port Toggle Output PTC6" "No effect,Toggled"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x08 21. " PTTO[21] ,Port Toggle Output PTC5" "No effect,Toggled"
|
|
bitfld.long 0x08 20. " PTTO[20] ,Port Toggle Output PTC4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTTO[19] ,Port Toggle Output PTC3" "No effect,Toggled"
|
|
bitfld.long 0x08 18. " PTTO[18] ,Port Toggle Output PTC2" "No effect,Toggled"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTC1" "No effect,Toggled"
|
|
bitfld.long 0x08 16. " PTTO[16] ,Port Toggle Output PTC0" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15. " PTTO[15] ,Port Toggle Output PTB7" "No effect,Toggled"
|
|
bitfld.long 0x08 14. " PTTO[14] ,Port Toggle Output PTB6" "No effect,Toggled"
|
|
bitfld.long 0x08 13. " PTTO[13] ,Port Toggle Output PTB5" "No effect,Toggled"
|
|
bitfld.long 0x08 12. " PTTO[12] ,Port Toggle Output PTB4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PTTO[11] ,Port Toggle Output PTB3" "No effect,Toggled"
|
|
bitfld.long 0x08 10. " PTTO[10] ,Port Toggle Output PTB2" "No effect,Toggled"
|
|
bitfld.long 0x08 9. " PTTO[9] ,Port Toggle Output PTB1" "No effect,Toggled"
|
|
bitfld.long 0x08 8. " PTTO[8] ,Port Toggle Output PTB0" "No effect,Toggled"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x08 7. " PTTO[7] ,Port Toggle Output PTA7" "No effect,Toggled"
|
|
bitfld.long 0x08 6. " PTTO[6] ,Port Toggle Output PTA6" "No effect,Toggled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 5. " PTTO[5] ,Port Toggle Output PTA5" "No effect,Toggled"
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTA4" "No effect,Toggled"
|
|
bitfld.long 0x08 3. " PTTO[3] ,Port Toggle Output PTA3" "No effect,Toggled"
|
|
bitfld.long 0x08 2. " PTTO[2] ,Port Toggle Output PTA2" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PTTO[1] ,Port Toggle Output PTA1" "No effect,Toggled"
|
|
bitfld.long 0x08 0. " PTTO[0] ,Port Toggle Output PTA0" "No effect,Toggled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIOA_PDIR,Port Data Input Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTD7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port Data Input PTD6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port Data Input PTD5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDI[28] ,Port Data Input PTD4" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTD3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTD2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port Data Input PTD1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port Data Input PTD0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PDI[23] ,Port Data Input PTC7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port Data Input PTC6" "Low level,High level"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDI[21] ,Port Data Input PTC5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port Data Input PTC4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDI[19] ,Port Data Input PTC3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port Data Input PTC2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTC1" "Low level,High level"
|
|
bitfld.long 0x00 16. " PDI[16] ,Port Data Input PTC0" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PDI[15] ,Port Data Input PTB7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port Data Input PTB6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port Data Input PTB5" "Low level,High level"
|
|
bitfld.long 0x00 12. " PDI[12] ,Port Data Input PTB4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PDI[11] ,Port Data Input PTB3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port Data Input PTB2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port Data Input PTB1" "Low level,High level"
|
|
bitfld.long 0x00 8. " PDI[8] ,Port Data Input PTB0" "Low level,High level"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PDI[7] ,Port Data Input PTA7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTA6" "Low level,High level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PDI[5] ,Port Data Input PTA5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTA4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port Data Input PTA3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port Data Input PTA2" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDI[1] ,Port Data Input PTA1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port Data Input PTA0" "Low level,High level"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "FGPIOA_PDDR,Port Data Direction Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTD7" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port Data Direction PTD6" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port Data Direction PTD5" "Input,Output"
|
|
bitfld.long 0x00 28. " PDD[28] ,Port Data Direction PTD4" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTD3" "Input,Output"
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTD2" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port Data Direction PTD1" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port Data Direction PTD0" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 23. " PDD[23] ,Port Data Direction PTC7" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port Data Direction PTC6" "Input,Output"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x00 21. " PDD[21] ,Port Data Direction PTC5" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port Data Direction PTC4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDD[19] ,Port Data Direction PTC3" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port Data Direction PTC2" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTC1" "Input,Output"
|
|
bitfld.long 0x00 16. " PDD[16] ,Port Data Direction PTC0" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PDD[15] ,Port Data Direction PTB7" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port Data Direction PTB6" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port Data Direction PTB5" "Input,Output"
|
|
bitfld.long 0x00 12. " PDD[12] ,Port Data Direction PTB4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PDD[11] ,Port Data Direction PTB3" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port Data Direction PTB2" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port Data Direction PTB1" "Input,Output"
|
|
bitfld.long 0x00 8. " PDD[8] ,Port Data Direction PTB0" "Input,Output"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x00 7. " PDD[7] ,Port Data Direction PTA7" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTA6" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PDD[5] ,Port Data Direction PTA5" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTA4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port Data Direction PTA3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port Data Direction PTA2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDD[1] ,Port Data Direction PTA1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port Data Direction PTA0" "Input,Output"
|
|
line.long 0x04 "FGPIOA_PIDR,Port Input Disable Register"
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PID[31] ,Port Input Disable PTD7" "No,Yes"
|
|
bitfld.long 0x04 30. " PID[30] ,Port Input Disable PTD6" "No,Yes"
|
|
bitfld.long 0x04 29. " PID[29] ,Port Input Disable PTD5" "No,Yes"
|
|
bitfld.long 0x04 28. " PID[28] ,Port Input Disable PTD4" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 27. " PID[27] ,Port Input Disable PTD3" "No,Yes"
|
|
bitfld.long 0x04 26. " PID[26] ,Port Input Disable PTD2" "No,Yes"
|
|
bitfld.long 0x04 25. " PID[25] ,Port Input Disable PTD1" "No,Yes"
|
|
bitfld.long 0x04 24. " PID[24] ,Port Input Disable PTD0" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AMFK")&&!cpuis("S9KEAZN8ACFK")&&!cpuis("S9KEAZN8AMFKR")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 23. " PID[23] ,Port Input Disable PTC7" "No,Yes"
|
|
bitfld.long 0x04 22. " PID[22] ,Port Input Disable PTC6" "No,Yes"
|
|
endif
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
textline " "
|
|
bitfld.long 0x04 21. " PID[21] ,Port Input Disable PTC5" "No,Yes"
|
|
bitfld.long 0x04 20. " PID[20] ,Port Input Disable PTC4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PID[19] ,Port Input Disable PTC3" "No,Yes"
|
|
bitfld.long 0x04 18. " PID[18] ,Port Input Disable PTC2" "No,Yes"
|
|
bitfld.long 0x04 17. " PID[17] ,Port Input Disable PTC1" "No,Yes"
|
|
bitfld.long 0x04 16. " PID[16] ,Port Input Disable PTC0" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " PID[15] ,Port Input Disable PTB7" "No,Yes"
|
|
bitfld.long 0x04 14. " PID[14] ,Port Input Disable PTB6" "No,Yes"
|
|
bitfld.long 0x04 13. " PID[13] ,Port Input Disable PTB5" "No,Yes"
|
|
bitfld.long 0x04 12. " PID[12] ,Port Input Disable PTB4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PID[11] ,Port Input Disable PTB3" "No,Yes"
|
|
bitfld.long 0x04 10. " PID[10] ,Port Input Disable PTB2" "No,Yes"
|
|
bitfld.long 0x04 9. " PID[9] ,Port Input Disable PTB1" "No,Yes"
|
|
bitfld.long 0x04 8. " PID[8] ,Port Input Disable PTB0" "No,Yes"
|
|
textline " "
|
|
sif !cpuis("S9KEAZN8AMTG")&&!cpuis("S9KEAZN8ACTG")&&!cpuis("S9KEAZN8AVTG")
|
|
bitfld.long 0x04 7. " PID[7] ,Port Input Disable PTA7" "No,Yes"
|
|
bitfld.long 0x04 6. " PID[6] ,Port Input Disable PTA6" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " PID[5] ,Port Input Disable PTA5" "No,Yes"
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTA4" "No,Yes"
|
|
bitfld.long 0x04 3. " PID[3] ,Port Input Disable PTA3" "No,Yes"
|
|
bitfld.long 0x04 2. " PID[2] ,Port Input Disable PTA2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PID[1] ,Port Input Disable PTA1" "No,Yes"
|
|
bitfld.long 0x04 0. " PID[0] ,Port Input Disable PTA0" "No,Yes"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "FGPIO_B"
|
|
base ad:0xF8000040
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIOB_PDOR,Port Data Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDO[30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDO[29] ,Port Data Output PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDO[28] ,Port Data Output PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PDO[27] ,Port Data Output PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDO[25] ,Port Data Output PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDO[24] ,Port Data Output PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PDO[23] ,Port Data Output PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDO[22] ,Port Data Output PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " PDO[21] ,Port Data Output PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDO[20] ,Port Data Output PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDO[19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDO[18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTG1" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDO[31] ,Port Data Output PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDO[30] ,Port Data Output PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDO[26] ,Port Data Output PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDO[25] ,Port Data Output PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PDO[24] ,Port Data Output PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " PDO[19] ,Port Data Output PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDO[18] ,Port Data Output PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDO[17] ,Port Data Output PTG1" "Low level,High level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDO[16] ,Port Data Output PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " PDO[15] ,Port Data Output PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDO[14] ,Port Data Output PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDO[13] ,Port Data Output PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDO[12] ,Port Data Output PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " PDO[11] ,Port Data Output PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDO[10] ,Port Data Output PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDO[9] ,Port Data Output PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PDO[8] ,Port Data Output PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " PDO[7] ,Port Data Output PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDO[5] ,Port Data Output PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDO[3] ,Port Data Output PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDO[2] ,Port Data Output PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDO[1] ,Port Data Output PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDO[0] ,Port Data Output PTE0" "Low level,High level"
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "FGPIOB_PSOR,Port Set Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " PTSO[30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 29. " PTSO[29] ,Port Set Output PTH5" "No effect,Set"
|
|
bitfld.long 0x00 28. " PTSO[28] ,Port Set Output PTH4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PTSO[27] ,Port Set Output PTH3" "No effect,Set"
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " PTSO[25] ,Port Set Output PTH1" "No effect,Set"
|
|
bitfld.long 0x00 24. " PTSO[24] ,Port Set Output PTH0" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PTSO[23] ,Port Set Output PTG7" "No effect,Set"
|
|
bitfld.long 0x00 22. " PTSO[22] ,Port Set Output PTG6" "No effect,Set"
|
|
bitfld.long 0x00 21. " PTSO[21] ,Port Set Output PTG5" "No effect,Set"
|
|
bitfld.long 0x00 20. " PTSO[20] ,Port Set Output PTG4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTSO[19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " PTSO[18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTG1" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 31. " PTSO[31] ,Port Set Output PTH7" "No effect,Set"
|
|
bitfld.long 0x00 30. " PTSO[30] ,Port Set Output PTH6" "No effect,Set"
|
|
bitfld.long 0x00 26. " PTSO[26] ,Port Set Output PTH2" "No effect,Set"
|
|
bitfld.long 0x00 25. " PTSO[25] ,Port Set Output PTH1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PTSO[24] ,Port Set Output PTH0" "No effect,Set"
|
|
bitfld.long 0x00 19. " PTSO[19] ,Port Set Output PTG3" "No effect,Set"
|
|
bitfld.long 0x00 18. " PTSO[18] ,Port Set Output PTG2" "No effect,Set"
|
|
bitfld.long 0x00 17. " PTSO[17] ,Port Set Output PTG1" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PTSO[16] ,Port Set Output PTG0" "No effect,Set"
|
|
bitfld.long 0x00 15. " PTSO[15] ,Port Set Output PTF7" "No effect,Set"
|
|
bitfld.long 0x00 14. " PTSO[14] ,Port Set Output PTF6" "No effect,Set"
|
|
bitfld.long 0x00 13. " PTSO[13] ,Port Set Output PTF5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PTSO[12] ,Port Set Output PTF4" "No effect,Set"
|
|
bitfld.long 0x00 11. " PTSO[11] ,Port Set Output PTB3" "No effect,Set"
|
|
bitfld.long 0x00 10. " PTSO[10] ,Port Set Output PTF2" "No effect,Set"
|
|
bitfld.long 0x00 9. " PTSO[9] ,Port Set Output PTF1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PTSO[8] ,Port Set Output PTF0" "No effect,Set"
|
|
bitfld.long 0x00 7. " PTSO[7] ,Port Set Output PTE7" "No effect,Set"
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTE6" "No effect,Set"
|
|
bitfld.long 0x00 5. " PTSO[5] ,Port Set Output PTE5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTE4" "No effect,Set"
|
|
bitfld.long 0x00 3. " PTSO[3] ,Port Set Output PTA3" "No effect,Set"
|
|
bitfld.long 0x00 2. " PTSO[2] ,Port Set Output PTE2" "No effect,Set"
|
|
bitfld.long 0x00 1. " PTSO[1] ,Port Set Output PTE1" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PTSO[0] ,Port Set Output PTE0" "No effect,Set"
|
|
line.long 0x04 "FGPIOB_PCOR,Port Clear Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PTCO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x04 30. " PTCO[30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x04 29. " PTCO[29] ,Port Clear Output PTH5" "No effect,Clear"
|
|
bitfld.long 0x04 28. " PTCO[28] ,Port Clear Output PTH4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PTCO[27] ,Port Clear Output PTH3" "No effect,Clear"
|
|
bitfld.long 0x04 26. " PTCO[26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x04 25. " PTCO[25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
bitfld.long 0x04 24. " PTCO[24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PTCO[23] ,Port Clear Output PTG7" "No effect,Clear"
|
|
bitfld.long 0x04 22. " PTCO[22] ,Port Clear Output PTG6" "No effect,Clear"
|
|
bitfld.long 0x04 21. " PTCO[21] ,Port Clear Output PTG5" "No effect,Clear"
|
|
bitfld.long 0x04 20. " PTCO[20] ,Port Clear Output PTG4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PTCO[19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x04 18. " PTCO[18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 31. " PTCO[31] ,Port Clear Output PTH7" "No effect,Clear"
|
|
bitfld.long 0x04 30. " PTCO[30] ,Port Clear Output PTH6" "No effect,Clear"
|
|
bitfld.long 0x04 26. " PTCO[26] ,Port Clear Output PTH2" "No effect,Clear"
|
|
bitfld.long 0x04 25. " PTCO[25] ,Port Clear Output PTH1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PTCO[24] ,Port Clear Output PTH0" "No effect,Clear"
|
|
bitfld.long 0x04 19. " PTCO[19] ,Port Clear Output PTG3" "No effect,Clear"
|
|
bitfld.long 0x04 18. " PTCO[18] ,Port Clear Output PTG2" "No effect,Clear"
|
|
bitfld.long 0x04 17. " PTCO[17] ,Port Clear Output PTG1" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16. " PTCO[16] ,Port Clear Output PTG0" "No effect,Clear"
|
|
bitfld.long 0x04 15. " PTCO[15] ,Port Clear Output PTF7" "No effect,Clear"
|
|
bitfld.long 0x04 14. " PTCO[14] ,Port Clear Output PTF6" "No effect,Clear"
|
|
bitfld.long 0x04 13. " PTCO[13] ,Port Clear Output PTF5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PTCO[12] ,Port Clear Output PTF4" "No effect,Clear"
|
|
bitfld.long 0x04 11. " PTCO[11] ,Port Set Output PTF3" "No effect,Clear"
|
|
bitfld.long 0x04 10. " PTCO[10] ,Port Set Output PTF2" "No effect,Clear"
|
|
bitfld.long 0x04 9. " PTCO[9] ,Port Clear Output PTF1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PTCO[8] ,Port Clear Output PTF0" "No effect,Clear"
|
|
bitfld.long 0x04 7. " PTCO[7] ,Port Clear Output PTE7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " PTCO[6] ,Port Clear Output PTE6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " PTCO[5] ,Port Clear Output PTE5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTE4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PTCO[3] ,Port Clear Output PTE3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " PTCO[2] ,Port Clear Output PTE2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " PTCO[1] ,Port Clear Output PTE1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PTCO[0] ,Port Clear Output PTE0" "No effect,Clear"
|
|
line.long 0x08 "FGPIOB_PTOR,Port Toggle Output Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x08 31. " PTTO[31] ,Port Toggled Output PTH7" "No effect,Toggled"
|
|
bitfld.long 0x08 30. " PTTO[30] ,Port Toggled Output PTH6" "No effect,Toggled"
|
|
bitfld.long 0x08 29. " PTTO[29] ,Port Toggled Output PTH5" "No effect,Toggled"
|
|
bitfld.long 0x08 28. " PTTO[28] ,Port Toggled Output PTH4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " PTTO[27] ,Port Toggled Output PTH3" "No effect,Toggled"
|
|
bitfld.long 0x08 26. " PTTO[26] ,Port Toggled Output PTH2" "No effect,Toggled"
|
|
bitfld.long 0x08 25. " PTTO[25] ,Port Toggled Output PTH1" "No effect,Toggled"
|
|
bitfld.long 0x08 24. " PTTO[24] ,Port Toggled Output PTH0" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " PTTO[23] ,Port Toggled Output PTG7" "No effect,Toggled"
|
|
bitfld.long 0x08 22. " PTTO[22] ,Port Toggled Output PTG6" "No effect,Toggled"
|
|
bitfld.long 0x08 21. " PTTO[21] ,Port Toggled Output PTG5" "No effect,Toggled"
|
|
bitfld.long 0x08 20. " PTTO[20] ,Port Toggled Output PTG4" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PTTO[19] ,Port Toggled Output PTG3" "No effect,Toggled"
|
|
bitfld.long 0x08 18. " PTTO[18] ,Port Toggled Output PTG2" "No effect,Toggled"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggled Output PTG1" "No effect,Toggled"
|
|
else
|
|
bitfld.long 0x08 31. " PTTO[31] ,Port Toggle Output PTH7" "No effect,Toggled"
|
|
bitfld.long 0x08 30. " PTTO[30] ,Port Toggle Output PTH6" "No effect,Toggled"
|
|
bitfld.long 0x08 26. " PTTO[26] ,Port Toggle Output PTH2" "No effect,Toggled"
|
|
bitfld.long 0x08 25. " PTTO[25] ,Port Toggle Output PTH1" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " PTTO[24] ,Port Toggle Output PTH0" "No effect,Toggled"
|
|
bitfld.long 0x08 19. " PTTO[19] ,Port Toggle Output PTG3" "No effect,Toggled"
|
|
bitfld.long 0x08 18. " PTTO[18] ,Port Toggle Output PTG2" "No effect,Toggled"
|
|
bitfld.long 0x08 17. " PTTO[17] ,Port Toggle Output PTG1" "No effect,Toggled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 16. " PTTO[16] ,Port Toggle Output PTG0" "No effect,Toggled"
|
|
bitfld.long 0x08 15. " PTTO[15] ,Port Toggle Output PTF7" "No effect,Toggled"
|
|
bitfld.long 0x08 14. " PTTO[14] ,Port Toggle Output PTF6" "No effect,Toggled"
|
|
bitfld.long 0x08 13. " PTTO[13] ,Port Toggle Output PTF5" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PTTO[12] ,Port Toggle Output PTF4" "No effect,Toggled"
|
|
bitfld.long 0x08 11. " PTTO[11] ,Port Toggle Output PTF3" "No effect,Toggled"
|
|
bitfld.long 0x08 10. " PTTO[10] ,Port Toggle Output PTF2" "No effect,Toggled"
|
|
bitfld.long 0x08 9. " PTTO[9] ,Port Toggle Output PTF1" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PTTO[8] ,Port Toggle Output PTF0" "No effect,Toggled"
|
|
bitfld.long 0x08 7. " PTTO[7] ,Port Toggle Output PTE7" "No effect,Toggled"
|
|
bitfld.long 0x08 6. " PTTO[6] ,Port Toggle Output PTE6" "No effect,Toggled"
|
|
bitfld.long 0x08 5. " PTTO[5] ,Port Toggle Output PTE5" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTE4" "No effect,Toggled"
|
|
bitfld.long 0x08 3. " PTTO[3] ,Port Toggle Output PTE3" "No effect,Toggled"
|
|
bitfld.long 0x08 2. " PTTO[2] ,Port Toggle Output PTE2" "No effect,Toggled"
|
|
bitfld.long 0x08 1. " PTTO[1] ,Port Toggle Output PTE1" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PTTO[0] ,Port Toggle Output PTE0" "No effect,Toggled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIOB_PDIR,Port Data Input Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 29. " PDI[29] ,Port Data Input PTH5" "Low level,High level"
|
|
bitfld.long 0x00 28. " PDI[28] ,Port Data Input PTH4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PDI[27] ,Port Data Input PTH3" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port Data Input PTH1" "Low level,High level"
|
|
bitfld.long 0x00 24. " PDI[24] ,Port Data Input PTH0" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PDI[23] ,Port Data Input PTG7" "Low level,High level"
|
|
bitfld.long 0x00 22. " PDI[22] ,Port Data Input PTG6" "Low level,High level"
|
|
bitfld.long 0x00 21. " PDI[21] ,Port Data Input PTG5" "Low level,High level"
|
|
bitfld.long 0x00 20. " PDI[20] ,Port Data Input PTG4" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDI[19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTG1" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 31. " PDI[31] ,Port Data Input PTH7" "Low level,High level"
|
|
bitfld.long 0x00 30. " PDI[30] ,Port Data Input PTH6" "Low level,High level"
|
|
bitfld.long 0x00 26. " PDI[26] ,Port Data Input PTH2" "Low level,High level"
|
|
bitfld.long 0x00 25. " PDI[25] ,Port Data Input PTH1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PDI[24] ,Port Data Input PTH0" "Low level,High level"
|
|
bitfld.long 0x00 19. " PDI[19] ,Port Data Input PTG3" "Low level,High level"
|
|
bitfld.long 0x00 18. " PDI[18] ,Port Data Input PTG2" "Low level,High level"
|
|
bitfld.long 0x00 17. " PDI[17] ,Port Data Input PTG1" "Low level,High level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDI[16] ,Port Data Input PTG0" "Low level,High level"
|
|
bitfld.long 0x00 15. " PDI[15] ,Port Data Input PTF7" "Low level,High level"
|
|
bitfld.long 0x00 14. " PDI[14] ,Port Data Input PTF6" "Low level,High level"
|
|
bitfld.long 0x00 13. " PDI[13] ,Port Data Input PTF5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI[12] ,Port Data Input PTF4" "Low level,High level"
|
|
bitfld.long 0x00 11. " PDI[11] ,Port Data Input PTF3" "Low level,High level"
|
|
bitfld.long 0x00 10. " PDI[10] ,Port Data Input PTF2" "Low level,High level"
|
|
bitfld.long 0x00 9. " PDI[9] ,Port Data Input PTF1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PDI[8] ,Port Data Input PTF0" "Low level,High level"
|
|
bitfld.long 0x00 7. " PDI[7] ,Port Data Input PTE7" "Low level,High level"
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTE6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port Data Input PTE5" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTE4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port Data Input PTE3" "Low level,High level"
|
|
bitfld.long 0x00 2. " PDI[2] ,Port Data Input PTE2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port Data Input PTE1" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDI[0] ,Port Data Input PTE0" "Low level,High level"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "FGPIOB_PDDR,Port Data Direction Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 29. " PDD[29] ,Port Data Direction PTH5" "Input,Output"
|
|
bitfld.long 0x00 28. " PDD[28] ,Port Data Direction PTH4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PDD[27] ,Port Data Direction PTH3" "Input,Output"
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port Data Direction PTH1" "Input,Output"
|
|
bitfld.long 0x00 24. " PDD[24] ,Port Data Direction PTH0" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PDD[23] ,Port Data Direction PTG7" "Input,Output"
|
|
bitfld.long 0x00 22. " PDD[22] ,Port Data Direction PTG6" "Input,Output"
|
|
bitfld.long 0x00 21. " PDD[21] ,Port Data Direction PTG5" "Input,Output"
|
|
bitfld.long 0x00 20. " PDD[20] ,Port Data Direction PTG4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDD[19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTG1" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 31. " PDD[31] ,Port Data Direction PTH7" "Input,Output"
|
|
bitfld.long 0x00 30. " PDD[30] ,Port Data Direction PTH6" "Input,Output"
|
|
bitfld.long 0x00 26. " PDD[26] ,Port Data Direction PTH2" "Input,Output"
|
|
bitfld.long 0x00 25. " PDD[25] ,Port Data Direction PTH1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PDD[24] ,Port Data Direction PTH0" "Input,Output"
|
|
bitfld.long 0x00 19. " PDD[19] ,Port Data Direction PTG3" "Input,Output"
|
|
bitfld.long 0x00 18. " PDD[18] ,Port Data Direction PTG2" "Input,Output"
|
|
bitfld.long 0x00 17. " PDD[17] ,Port Data Direction PTG1" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " PDD[16] ,Port Data Direction PTG0" "Input,Output"
|
|
bitfld.long 0x00 15. " PDD[15] ,Port Data Direction PTF7" "Input,Output"
|
|
bitfld.long 0x00 14. " PDD[14] ,Port Data Direction PTF6" "Input,Output"
|
|
bitfld.long 0x00 13. " PDD[13] ,Port Data Direction PTF5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDD[12] ,Port Data Direction PTF4" "Input,Output"
|
|
bitfld.long 0x00 11. " PDD[11] ,Port Data Direction PTF3" "Input,Output"
|
|
bitfld.long 0x00 10. " PDD[10] ,Port Data Direction PTF2" "Input,Output"
|
|
bitfld.long 0x00 9. " PDD[9] ,Port Data Direction PTF1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PDD[8] ,Port Data Direction PTF0" "Input,Output"
|
|
bitfld.long 0x00 7. " PDD[7] ,Port Data Direction PTE7" "Input,Output"
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTE6" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port Data Direction PTE5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTE4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port Data Direction PTE3" "Input,Output"
|
|
bitfld.long 0x00 2. " PDD[2] ,Port Data Direction PTE2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port Data Direction PTE1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDD[0] ,Port Data Direction PTE0" "Input,Output"
|
|
line.long 0x04 "FGPIOB_PIDR,Port Input Disable Register"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x04 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x04 30. " PID[30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x04 29. " PID[29] ,Port Input Disable PTH5" "No,Yes"
|
|
bitfld.long 0x04 28. " PID[28] ,Port Input Disable PTH4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PID[27] ,Port Input Disable PTH3" "No,Yes"
|
|
bitfld.long 0x04 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x04 25. " PID[25] ,Port Input Disable PTH1" "No,Yes"
|
|
bitfld.long 0x04 24. " PID[24] ,Port Input Disable PTH0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PID[23] ,Port Input Disable PTG7" "No,Yes"
|
|
bitfld.long 0x04 22. " PID[22] ,Port Input Disable PTG6" "No,Yes"
|
|
bitfld.long 0x04 21. " PID[21] ,Port Input Disable PTG5" "No,Yes"
|
|
bitfld.long 0x04 20. " PID[20] ,Port Input Disable PTG4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PID[19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x04 18. " PID[18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x04 17. " PID[17] ,Port Input Disable PTG1" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 31. " PID[31] ,Port Input Disable PTH7" "No,Yes"
|
|
bitfld.long 0x04 30. " PID[30] ,Port Input Disable PTH6" "No,Yes"
|
|
bitfld.long 0x04 26. " PID[26] ,Port Input Disable PTH2" "No,Yes"
|
|
bitfld.long 0x04 25. " PID[25] ,Port Input Disable PTH1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PID[24] ,Port Input Disable PTH0" "No,Yes"
|
|
bitfld.long 0x04 19. " PID[19] ,Port Input Disable PTG3" "No,Yes"
|
|
bitfld.long 0x04 18. " PID[18] ,Port Input Disable PTG2" "No,Yes"
|
|
bitfld.long 0x04 17. " PID[17] ,Port Input Disable PTG1" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 16. " PID[16] ,Port Input Disable PTG0" "No,Yes"
|
|
bitfld.long 0x04 15. " PID[15] ,Port Input Disable PTF7" "No,Yes"
|
|
bitfld.long 0x04 14. " PID[14] ,Port Input Disable PTF6" "No,Yes"
|
|
bitfld.long 0x04 13. " PID[13] ,Port Input Disable PTF5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PID[12] ,Port Input Disable PTF4" "No,Yes"
|
|
bitfld.long 0x04 11. " PID[11] ,Port Input Disable PTF3" "No,Yes"
|
|
bitfld.long 0x04 10. " PID[10] ,Port Input Disable PTF2" "No,Yes"
|
|
bitfld.long 0x04 9. " PID[9] ,Port Input Disable PTF1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PID[8] ,Port Input Disable PTF0" "No,Yes"
|
|
bitfld.long 0x04 7. " PID[7] ,Port Input Disable PTE7" "No,Yes"
|
|
bitfld.long 0x04 6. " PID[6] ,Port Input Disable PTE6" "No,Yes"
|
|
bitfld.long 0x04 5. " PID[5] ,Port Input Disable PTE5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTE4" "No,Yes"
|
|
bitfld.long 0x04 3. " PID[3] ,Port Input Disable PTE3" "No,Yes"
|
|
bitfld.long 0x04 2. " PID[2] ,Port Input Disable PTE2" "No,Yes"
|
|
bitfld.long 0x04 1. " PID[1] ,Port Input Disable PTE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PID[0] ,Port Input Disable PTE0" "No,Yes"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
tree "FGPIO_C"
|
|
base ad:0xF8000080
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FGPIOC_PDOR,Port Data Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTI4" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 6. " PDO[6] ,Port Data Output PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDO[5] ,Port Data Output PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDO[4] ,Port Data Output PTI4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDO[3] ,Port Data Output PTI3" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDO[2] ,Port Data Output PTI2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDO[1] ,Port Data Output PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDO[0] ,Port Data Output PTI0" "Low level,High level"
|
|
endif
|
|
wgroup.long 0x04++0x0B
|
|
line.long 0x00 "FGPIOC_PSOR,Port Set Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTI4" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 6. " PTSO[6] ,Port Set Output PTI6" "No effect,Set"
|
|
bitfld.long 0x00 5. " PTSO[5] ,Port Set Output PTI5" "No effect,Set"
|
|
bitfld.long 0x00 4. " PTSO[4] ,Port Set Output PTI4" "No effect,Set"
|
|
bitfld.long 0x00 3. " PTSO[3] ,Port Set Output PTI3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTSO[2] ,Port Set Output PTI2" "No effect,Set"
|
|
bitfld.long 0x00 1. " PTSO[1] ,Port Set Output PTI1" "No effect,Set"
|
|
bitfld.long 0x00 0. " PTSO[0] ,Port Set Output PTI0" "No effect,Set"
|
|
endif
|
|
line.long 0x04 "FGPIOC_PCOR,Port Clear Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 6. " PTCO[6] ,Port Clear Output PTI6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " PTCO[5] ,Port Clear Output PTI5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " PTCO[4] ,Port Clear Output PTI4" "No effect,Clear"
|
|
bitfld.long 0x04 3. " PTCO[3] ,Port Clear Output PTI3" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PTCO[2] ,Port Clear Output PTI2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " PTCO[1] ,Port Clear Output PTI1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " PTCO[0] ,Port Clear Output PTI0" "No effect,Clear"
|
|
endif
|
|
line.long 0x08 "FGPIOC_PTOR,Port Toggle Output Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTI4" "No effect,Toggled"
|
|
else
|
|
bitfld.long 0x08 6. " PTTO[6] ,Port Toggle Output PTI6" "No effect,Toggled"
|
|
bitfld.long 0x08 5. " PTTO[5] ,Port Toggle Output PTE5" "No effect,Toggled"
|
|
bitfld.long 0x08 4. " PTTO[4] ,Port Toggle Output PTI4" "No effect,Toggled"
|
|
bitfld.long 0x08 3. " PTTO[3] ,Port Toggle Output PTI3" "No effect,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PTTO[2] ,Port Toggle Output PTI2" "No effect,Toggled"
|
|
bitfld.long 0x08 1. " PTTO[1] ,Port Toggle Output PTI1" "No effect,Toggled"
|
|
bitfld.long 0x08 0. " PTTO[0] ,Port Toggle Output PTI0" "No effect,Toggled"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FGPIOC_PDIR,Port Data Input Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTI4" "Low level,High level"
|
|
else
|
|
bitfld.long 0x00 6. " PDI[6] ,Port Data Input PTI6" "Low level,High level"
|
|
bitfld.long 0x00 5. " PDI[5] ,Port Data Input PTI5" "Low level,High level"
|
|
bitfld.long 0x00 4. " PDI[4] ,Port Data Input PTI4" "Low level,High level"
|
|
bitfld.long 0x00 3. " PDI[3] ,Port Data Input PTI3" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDI[2] ,Port Data Input PTI2" "Low level,High level"
|
|
bitfld.long 0x00 1. " PDI[1] ,Port Data Input PTI1" "Low level,High level"
|
|
bitfld.long 0x00 0. " PDI[0] ,Port Data Input PTI0" "Low level,High level"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "FGPIOC_PDDR,Port Data Direction Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTI4" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 6. " PDD[6] ,Port Data Direction PTI6" "Input,Output"
|
|
bitfld.long 0x00 5. " PDD[5] ,Port Data Direction PTI5" "Input,Output"
|
|
bitfld.long 0x00 4. " PDD[4] ,Port Data Direction PTI4" "Input,Output"
|
|
bitfld.long 0x00 3. " PDD[3] ,Port Data Direction PTI3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDD[2] ,Port Data Direction PTI2" "Input,Output"
|
|
bitfld.long 0x00 1. " PDD[1] ,Port Data Direction PTI1" "Input,Output"
|
|
bitfld.long 0x00 0. " PDD[0] ,Port Data Direction PTI0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "FGPIOC_PIDR,Port Input Disable Register"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTI4" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 6. " PID[6] ,Port Input Disable PTI6" "No,Yes"
|
|
bitfld.long 0x04 5. " PID[5] ,Port Input Disable PTI5" "No,Yes"
|
|
bitfld.long 0x04 4. " PID[4] ,Port Input Disable PTI4" "No,Yes"
|
|
bitfld.long 0x04 3. " PID[3] ,Port Input Disable PTI3" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PID[2] ,Port Input Disable PTI2" "No,Yes"
|
|
bitfld.long 0x04 1. " PID[1] ,Port Input Disable PTI1" "No,Yes"
|
|
bitfld.long 0x04 0. " PID[0] ,Port Input Disable PTI0" "No,Yes"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "KBI (Keyboard Interrupts)"
|
|
tree "KBI0"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
base ad:0x40079000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "KBI0_PE,KBI0 Pin Enable Register"
|
|
bitfld.long 0x00 31. " KBIPE[31] ,KBI Pin 31 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " KBIPE[30] ,KBI Pin 30 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " KBIPE[29] ,KBI Pin 29 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " KBIPE[28] ,KBI Pin 28 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KBIPE[27] ,KBI Pin 27 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " KBIPE[26] ,KBI Pin 26 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " KBIPE[25] ,KBI Pin 25 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBIPE[24] ,KBI Pin 24 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " KBIPE[23] ,KBI Pin 23 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " KBIPE[22] ,KBI Pin 22 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " KBIPE[21] ,KBI Pin 21 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " KBIPE[20] ,KBI Pin 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " KBIPE[19] ,KBI Pin 19 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " KBIPE[18] ,KBI Pin 18 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " KBIPE[17] ,KBI Pin 17 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " KBIPE[16] ,KBI Pin 16 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " KBIPE[15] ,KBI Pin 15 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " KBIPE[14] ,KBI Pin 14 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " KBIPE[13] ,KBI Pin 13 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " KBIPE[12] ,KBI Pin 12 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " KBIPE[11] ,KBI Pin 11 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " KBIPE[10] ,KBI Pin 10 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " KBIPE[9] ,KBI Pin 9 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " KBIPE[8] ,KBI Pin 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBIPE[7] ,KBI Pin 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " KBIPE[6] ,KBI Pin 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " KBIPE[5] ,KBI Pin 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " KBIPE[4] ,KBI Pin 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " KBIPE[3] ,KBI Pin 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " KBIPE[2] ,KBI Pin 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " KBIPE[1] ,KBI Pin 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " KBIPE[0] ,KBI Pin 0 Enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40079000+0x08))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI 31 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 30. " KBEDG[30] ,KBI 30 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 29. " KBEDG[29] ,KBI 29 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 28. " KBEDG[28] ,KBI 28 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KBEDG[27] ,KBI 27 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 26. " KBEDG[26] ,KBI 26 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 25. " KBEDG[25] ,KBI 25 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 24. " KBEDG[24] ,KBI 24 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 23. " KBEDG[23] ,KBI 23 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 22. " KBEDG[22] ,KBI 22 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 21. " KBEDG[21] ,KBI 21 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 20. " KBEDG[20] ,KBI 20 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 19. " KBEDG[19] ,KBI 19 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 18. " KBEDG[18] ,KBI 18 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 17. " KBEDG[17] ,KBI 17 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 16. " KBEDG[16] ,KBI 16 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 15. " KBEDG[15] ,KBI 15 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 14. " KBEDG[14] ,KBI 14 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 13. " KBEDG[13] ,KBI 13 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 12. " KBEDG[12] ,KBI 12 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " KBEDG[11] ,KBI 11 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 10. " KBEDG[10] ,KBI 10 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 9. " KBEDG[9] ,KBI 9 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 8. " KBEDG[8] ,KBI 8 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBEDG[7] ,KBI 7 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 6. " KBEDG[6] ,KBI 6 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 5. " KBEDG[5] ,KBI 5 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 4. " KBEDG[4] ,KBI 4 Edge Selects" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 3. " KBEDG[3] ,KBI 3 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 2. " KBEDG[2] ,KBI 2 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 1. " KBEDG[1] ,KBI 1 Edge Selects" "Falling,Rising"
|
|
bitfld.long 0x00 0. " KBEDG[0] ,KBI 0 Edge Selects" "Falling,Rising"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI 31 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 30. " KBEDG[30] ,KBI 30 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 29. " KBEDG[29] ,KBI 29 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 28. " KBEDG[28] ,KBI 28 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " KBEDG[27] ,KBI 27 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 26. " KBEDG[26] ,KBI 26 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 25. " KBEDG[25] ,KBI 25 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 24. " KBEDG[24] ,KBI 24 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " KBEDG[23] ,KBI 23 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 22. " KBEDG[22] ,KBI 22 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 21. " KBEDG[21] ,KBI 21 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 20. " KBEDG[20] ,KBI 20 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " KBEDG[19] ,KBI 19 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 18. " KBEDG[18] ,KBI 18 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 17. " KBEDG[17] ,KBI 17 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 16. " KBEDG[16] ,KBI 16 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " KBEDG[15] ,KBI 15 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 14. " KBEDG[14] ,KBI 14 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 13. " KBEDG[13] ,KBI 13 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 12. " KBEDG[12] ,KBI 12 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " KBEDG[11] ,KBI 11 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 10. " KBEDG[10] ,KBI 10 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 9. " KBEDG[9] ,KBI 9 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 8. " KBEDG[8] ,KBI 8 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBEDG[7] ,KBI 7 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 6. " KBEDG[6] ,KBI 6 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 5. " KBEDG[5] ,KBI 5 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 4. " KBEDG[4] ,KBI 4 Edge Selects" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " KBEDG[3] ,KBI 3 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 2. " KBEDG[2] ,KBI 2 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 1. " KBEDG[1] ,KBI 1 Edge Selects" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 0. " KBEDG[0] ,KBI 0 Edge Selects" "Falling/Low,Rising/High"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "KBI0_SC,KBI Status and Control Register"
|
|
bitfld.long 0x00 5. " RSTKBSP ,Reset KBI_SP register" "Not reset,Reset"
|
|
bitfld.long 0x00 4. " KBSPEN ,Real KBI_SP register enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " KBF ,KBI Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Edges/Levels"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "KBI0_SP,KBI Source Pin Register"
|
|
bitfld.long 0x00 31. " SP[31] ,KBI Source Pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " SP[30] ,KBI Source Pin 30" "Low,High"
|
|
bitfld.long 0x00 29. " SP[29] ,KBI Source Pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " SP[28] ,KBI Source Pin 28" "Low,High"
|
|
bitfld.long 0x00 27. " SP[27] ,KBI Source Pin 27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SP[26] ,KBI Source Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " SP[25] ,KBI Source Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " SP[24] ,KBI Source Pin 24" "Low,High"
|
|
bitfld.long 0x00 23. " SP[23] ,KBI Source Pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " SP[22] ,KBI Source Pin 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SP[21] ,KBI Source Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " SP[20] ,KBI Source Pin 20" "Low,High"
|
|
bitfld.long 0x00 19. " SP[19] ,KBI Source Pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " SP[18] ,KBI Source Pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " SP[17] ,KBI Source Pin 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SP[16] ,KBI Source Pin 16" "Low,High"
|
|
bitfld.long 0x00 15. " SP[15] ,KBI Source Pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " SP[14] ,KBI Source Pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " SP[13] ,KBI Source Pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " SP[12] ,KBI Source Pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SP[11] ,KBI Source Pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " SP[10] ,KBI Source Pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " SP[9] ,KBI Source Pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " SP[8] ,KBI Source Pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " SP[7] ,KBI Source Pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SP[6] ,KBI Source Pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " SP[5] ,KBI Source Pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " SP[4] ,KBI Source Pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " SP[3] ,KBI Source Pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " SP[2] ,KBI Source Pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SP[1] ,KBI Source Pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " SP[0] ,KBI Source Pin 0" "Low,High"
|
|
width 0xB
|
|
else
|
|
base ad:0x40079000
|
|
width 9.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "KBI0_SC,KBI Status and Control Register"
|
|
rbitfld.byte 0x00 3. " KBF ,KBI Interrupt Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
bitfld.byte 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Both edges & levels"
|
|
line.byte 0x01 "KBI0_PE,KBI0 Pin Enable Register"
|
|
bitfld.byte 0x01 7. " KBIPE[7] ,KBI Pin 7 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " KBIPE[6] ,KBI Pin 6 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " KBIPE[5] ,KBI Pin 5 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " KBIPE[4] ,KBI Pin 4 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " KBIPE[3] ,KBI Pin 3 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " KBIPE[2] ,KBI Pin 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " KBIPE[1] ,KBI Pin 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " KBIPE[0] ,KBI Pin 0 Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "KBI0_ES,KBI0 Edge Select Register"
|
|
bitfld.byte 0x02 7. " KBEDG[7] ,KBI 7 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 6. " KBEDG[6] ,KBI 6 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 5. " KBEDG[5] ,KBI 5 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 4. " KBEDG[4] ,KBI 4 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " KBEDG[3] ,KBI 3 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 2. " KBEDG[2] ,KBI 2 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 1. " KBEDG[1] ,KBI 1 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 0. " KBEDG[0] ,KBI 0 Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "KBI1"
|
|
sif cpuis("S9KEAZ128AMLH")||cpuis("S9KEAZ64AMLH")||cpuis("S9KEAZ128ACLH")||cpuis("S9KEAZ128AVLH")||cpuis("S9KEAZ64ACLH")||cpuis("S9KEAZ64AVLH")||cpuis("S9KEAZN64ACLH")||cpuis("S9KEAZ128AVLHR")||cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
base ad:0x4007A000
|
|
width 9.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "KBI1_PE,KBI1 Pin Enable Register"
|
|
bitfld.long 0x00 31. " KBIPE[31] ,KBI Pin 31 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " KBPIPE[30] ,KBI Pin 30 Interrupt Enables" "Disabled,Enabled"
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
textline " "
|
|
bitfld.long 0x00 29. " KBPIPE[29] ,KBI Pin 29 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " KBIPE[28] ,KBI Pin 28 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " KBIPE[27] ,KBI Pin 27 Interrupt Enables" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 26. " KBIPE[26] ,KBI Pin 26 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " KBIPE[25] ,KBI Pin 25 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBIPE[24] ,KBI Pin 24 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 23. " KBIPE[23] ,KBI Pin 23 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " KBIPE[22] ,KBI Pin 22 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " KBIPE[21] ,KBI Pin 21 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " KBIPE[20] ,KBI Pin 20 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " KBIPE[19] ,KBI Pin 19 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " KBIPE[18] ,KBI Pin 18 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " KBIPE[17] ,KBI Pin 17 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " KBIPE[16] ,KBI Pin 16 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " KBIPE[15] ,KBI Pin 15 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " KBIPE[14] ,KBI Pin 14 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " KBIPE[13] ,KBI Pin 13 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " KBIPE[12] ,KBI Pin 12 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " KBIPE[11] ,KBI Pin 11 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " KBIPE[10] ,KBI Pin 10 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " KBIPE[9] ,KBI Pin 9 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " KBIPE[8] ,KBI Pin 8 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBIPE[7] ,KBI Pin 7 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " KBIPE[6] ,KBI Pin 6 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " KBIPE[5] ,KBI Pin 5 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " KBIPE[4] ,KBI Pin 4 Interrupt Enables" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " KBIPE[3] ,KBI Pin 3 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " KBIPE[2] ,KBI Pin 2 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " KBIPE[1] ,KBI Pin 1 Interrupt Enables" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " KBIPE[0] ,KBI Pin 0 Interrupt Enables" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4007A000+0x08))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI1_ES,KBI1 Edge Select Register"
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI Pin 31 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 30. " KBEDG[30] ,KBI Pin 30 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 29. " KBEDG[29] ,KBI Pin 29 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 28. " KBEDG[28] ,KBI Pin 28 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 27. " KBEDG[27] ,KBI Pin 27 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " KBEDG[26] ,KBI Pin 26 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 25. " KBEDG[25] ,KBI Pin 25 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 24. " KBEDG[24] ,KBI Pin 24 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 23. " KBEDG[23] ,KBI Pin 23 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 22. " KBEDG[22] ,KBI Pin 22 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 21. " KBEDG[21] ,KBI Pin 21 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 20. " KBEDG[20] ,KBI Pin 20 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " KBEDG[19] ,KBI Pin 19 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 18. " KBEDG[18] ,KBI Pin 18 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 17. " KBEDG[17] ,KBI Pin 17 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 16. " KBEDG[16] ,KBI Pin 16 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 15. " KBEDG[15] ,KBI Pin 15 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 14. " KBEDG[14] ,KBI Pin 14 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 13. " KBEDG[13] ,KBI Pin 13 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 12. " KBEDG[12] ,KBI Pin 12 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 11. " KBEDG[11] ,KBI Pin 11 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 10. " KBEDG[10] ,KBI Pin 10 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 9. " KBEDG[9] ,KBI Pin 9 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 8. " KBEDG[8] ,KBI Pin 8 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBEDG[7] ,KBI Pin PTE7 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 6. " KBEDG[6] ,KBI Pin 6 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 5. " KBEDG[5] ,KBI Pin 5 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 4. " KBEDG[4] ,KBI Pin 4 Edge Select [Edge]" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 3. " KBEDG[3] ,KBI Pin PTE3 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 2. " KBEDG[2] ,KBI Pin 2 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 1. " KBEDG[1] ,KBI Pin 1 Edge Select [Edge]" "Falling,Rising"
|
|
bitfld.long 0x00 0. " KBEDG[0] ,KBI Pin 0 Edge Select [Edge]" "Falling,Rising"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "KBI1_ES,KBI1 Edge Select Register"
|
|
bitfld.long 0x00 31. " KBEDG[31] ,KBI Pin 31 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 30. " KBEDG[30] ,KBI Pin 30 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 29. " KBEDG[29] ,KBI Pin 29 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 28. " KBEDG[28] ,KBI Pin 28 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 27. " KBEDG[27] ,KBI Pin 27 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " KBEDG[26] ,KBI Pin 26 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 25. " KBEDG[25] ,KBI Pin 25 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 24. " KBEDG[24] ,KBI Pin 24 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
|
bitfld.long 0x00 23. " KBEDG[23] ,KBI Pin 23 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 22. " KBEDG[22] ,KBI Pin 22 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 21. " KBEDG[21] ,KBI Pin 21 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 20. " KBEDG[20] ,KBI Pin 20 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " KBEDG[19] ,KBI Pin 19 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 18. " KBEDG[18] ,KBI Pin 18 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 17. " KBEDG[17] ,KBI Pin 17 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 16. " KBEDG[16] ,KBI Pin 16 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " KBEDG[15] ,KBI Pin 15 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 14. " KBEDG[14] ,KBI Pin 14 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 13. " KBEDG[13] ,KBI Pin 13 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 12. " KBEDG[12] ,KBI Pin 12 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " KBEDG[11] ,KBI Pin 11 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 10. " KBEDG[10] ,KBI Pin 10 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 9. " KBEDG[9] ,KBI Pin 9 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 8. " KBEDG[8] ,KBI Pin 8 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBEDG[7] ,KBI Pin 7 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
bitfld.long 0x00 6. " KBEDG[6] ,KBI Pin 6 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
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bitfld.long 0x00 5. " KBEDG[5] ,KBI Pin 5 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
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bitfld.long 0x00 4. " KBEDG[4] ,KBI Pin 4 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
|
textline " "
|
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bitfld.long 0x00 3. " KBEDG[3] ,KBI Pin 3 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
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bitfld.long 0x00 2. " KBEDG[2] ,KBI Pin 2 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
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bitfld.long 0x00 1. " KBEDG[1] ,KBI Pin 1 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
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bitfld.long 0x00 0. " KBEDG[0] ,KBI Pin 0 Edge/Level Select [Edge/Level]" "Falling/Low,Rising/High"
|
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endif
|
|
group.long 0x08++0x03
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line.long 0x00 "KBI1_SC,KBI Status and Control Register"
|
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bitfld.long 0x00 5. " RSTKBSP ,Reset KBI_SP register" "Not reset,Reset"
|
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bitfld.long 0x00 4. " KBSPEN ,Real KBI_SP register enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " KBF ,KBI Interrupt Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
textline " "
|
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bitfld.long 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
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bitfld.long 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Edges/Levels"
|
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group.long 0x0C++0x03
|
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line.long 0x00 "KBI1_SP,KBI Source Pin Register"
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bitfld.long 0x00 31. " SP[31] ,KBI Source Pin 31" "Low,High"
|
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bitfld.long 0x00 30. " SP[30] ,KBI Source Pin 30" "Low,High"
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|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
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bitfld.long 0x00 29. " SP[29] ,KBI Source Pin 29" "Low,High"
|
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bitfld.long 0x00 28. " SP[28] ,KBI Source Pin 28" "Low,High"
|
|
bitfld.long 0x00 27. " SP[27] ,KBI Source Pin 27" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " SP[26] ,KBI Source Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " SP[25] ,KBI Source Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " SP[24] ,KBI Source Pin 24" "Low,High"
|
|
textline " "
|
|
sif cpuis("S9KEAZ64AMLK")||cpuis("S9KEAZ128AMLK")||cpuis("S9KEAZ128ACLK")||cpuis("S9KEAZ128AVLK")||cpuis("S9KEAZ64ACLK")||cpuis("S9KEAZ64AVLK")
|
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bitfld.long 0x00 23. " SP[23] ,KBI Source Pin 23" "Low,High"
|
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bitfld.long 0x00 22. " SP[22] ,KBI Source Pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " SP[21] ,KBI Source Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " SP[20] ,KBI Source Pin 20" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " SP[19] ,KBI Source Pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " SP[18] ,KBI Source Pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " SP[17] ,KBI Source Pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " SP[16] ,KBI Source Pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SP[15] ,KBI Source Pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " SP[14] ,KBI Source Pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " SP[13] ,KBI Source Pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " SP[12] ,KBI Source Pin 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SP[11] ,KBI Source Pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " SP[10] ,KBI Source Pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " SP[9] ,KBI Source Pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " SP[8] ,KBI Source Pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SP[7] ,KBI Source Pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " SP[6] ,KBI Source Pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " SP[5] ,KBI Source Pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " SP[4] ,KBI Source Pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SP[3] ,KBI Source Pin 3 - PTE3" "Low,High"
|
|
bitfld.long 0x00 2. " SP[2] ,KBI Source Pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " SP[1] ,KBI Source Pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " SP[0] ,KBI Source Pin 0" "Low,High"
|
|
width 0xB
|
|
else
|
|
base ad:0x4007A000
|
|
width 9.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "KBI1_SC,KBI Status and Control Register"
|
|
rbitfld.byte 0x00 3. " KBF ,KBI Interrupt Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " KBACK ,KBI Acknowledge" "None,KBF cleared"
|
|
bitfld.byte 0x00 1. " KBIE ,KBI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " KBMOD ,KBI Detection Mode" "Edges only,Both edges & levels"
|
|
sif cpuis("S9KEAZN8AVTG")
|
|
line.byte 0x01 "KBI1_PE,KBI0 Pin Enable Register"
|
|
bitfld.byte 0x01 7. " KBIPE[7] ,KBI Pin 7 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " KBIPE[6] ,KBI Pin 6 Enable" "Disabled,Enabled"
|
|
else
|
|
line.byte 0x01 "KBI1_PE,KBI0 Pin Enable Register"
|
|
sif cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")||cpuis("S9KEAZN8AMFKR")||cpuis("S9KEAZN16ACLH")||cpuis("S9KEAZN32ACLH")||cpuis("S9KEAZN16AMLH")||cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")
|
|
bitfld.byte 0x01 7. " KBIPE[7] ,KBI Pin 7 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " KBIPE[6] ,KBI Pin 6 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " KBIPE[5] ,KBI Pin 5 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " KBIPE[4] ,KBI Pin 4 Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x01 3. " KBIPE[3] ,KBI Pin Enables" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " KBIPE[2] ,KBI Pin 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " KBIPE[1] ,KBI Pin 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " KBIPE[0] ,KBI Pin 0 Enable" "Disabled,Enabled"
|
|
endif
|
|
line.byte 0x02 "KBI1_ES,KBI0 Edge Select Register"
|
|
sif cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("SKEAZN8MFK4")||cpuis("SKEAZN8MTG4")||cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.byte 0x02 7. " KBEDG[7] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 6. " KBEDG[6] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
endif
|
|
sif cpuis("S9KEAZN32AMLH")||cpuis("S9KEAZN64AMLH")||cpuis("SKEAZN8MFK4")||cpuis("S9KEAZN8AMTG")||cpuis("S9KEAZN8ACTG")||cpuis("S9KEAZN8AMFK")||cpuis("S9KEAZN8ACFK")
|
|
bitfld.byte 0x02 5. " KBEDG[5] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 4. " KBEDG[4] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x02 3. " KBEDG[3] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 2. " KBEDG[2] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 1. " KBEDG[1] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
bitfld.byte 0x02 0. " KBEDG[0] ,KBI Edge Selects" "Falling edge/low level,Rising edge/high level"
|
|
textline " "
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
textline ""
|