2755 lines
276 KiB
Plaintext
2755 lines
276 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: ISD91200 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2023-04-07 NEJ
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; 2023-11-08 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; ISD91200_v1_fixed.svd (Ver. 1.0)
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; @Core: Cortex-M0
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; @Chip: ISD91230GRI, ISD91230PRI, ISD91230RI, ISD91230YI, ISD91260CRI,
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; ISD91260CYI, ISD91260GRI, ISD91260RI, ISD91260YI
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perisd91200.per 16971 2023-11-09 16:09:22Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ALC (Automatic Level Control)"
|
|
base ad:0x400B0090
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "ALC_CTL,ALC Control Register"
|
|
bitfld.long 0x0 31. "PKLIMEN,ALC Peak Limiter Enable. Default is '0' . Please set as '1'" "0,1"
|
|
bitfld.long 0x0 30. "PKSEL,ALC Gain Peak Detector Select." "0: use absolute peak value for ALC training (default),1: use peak-to-peak value for ALC training"
|
|
newline
|
|
bitfld.long 0x0 29. "NGPKSEL,ALC Noise Gate Peak Detector Select." "0: use peak-to-peak value for noise gate threshold..,1: use absolute peak value for noise gate threshold.."
|
|
bitfld.long 0x0 28. "ALCEN,ALC Select." "0: ALC disabled (default),1: ALC enabled"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "MAXGAIN,ALC Maximum Gain." "0: -6.75 dB,1: -0.75 dB,2: +5.25 dB,3: +11.25 dB,4: +17.25 dB,5: +23.25 dB,6: +29.25 dB,7: +35.25 dB"
|
|
bitfld.long 0x0 22.--24. "MINGAIN,ALC Minimum Gain." "0: -12 dB,1: -6 dB,2: 0 dB,3: 6 dB,4: 12 dB,5: 18 dB,6: 24 dB,7: 30 dB"
|
|
newline
|
|
bitfld.long 0x0 21. "ALCRANGESEL,ALC Target range selection." "0: ALC target range -28.5~ -6dB,1: ALC target range -22.5 ~-1.5dB"
|
|
hexmask.long.byte 0x0 17.--20. 1. "HOLDTIME,ALC Hold Time ."
|
|
newline
|
|
hexmask.long.byte 0x0 13.--16. 1. "TARGETLV,ALC Target Level."
|
|
bitfld.long 0x0 12. "MODESEL,ALC Mode." "0: ALC normal operation mode,1: ALC limiter mode"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DECAYSEL,ALC Decay Time . (Value: 0~10)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "ATKSEL,ALC Attack Time . (Value: 0~10)."
|
|
newline
|
|
bitfld.long 0x0 3. "NGEN,Noise Gate Enable." "0: Noise gate disabled,1: Noise gate enabled"
|
|
bitfld.long 0x0 0.--2. "NGTHBST,Noise Gate Threshold. 000 --- -39dB . 001--- -45dB. 010---- -51dB. 011 --- -57dB. 100 --- -63dB. 101 --- -69dB. 110 --- -75dB. 111 --- -81dB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "ALC_GAIN,ALC GAIN Control Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "PKLIMIT,ALC Peak Limiter Threshold. Full scale - 0x7fff. Default value is 0x6fdc - 87.5% of full scale"
|
|
bitfld.long 0x4 7. "INITGAINEN,ALC Update Initial Gain." "0: ALC PGA GAIN load automatic calculating gain,1: ALC PGA GAIN load ALCINIT_GAIN"
|
|
newline
|
|
bitfld.long 0x4 6. "ZCEN,ALC Zero Crossing Enable ." "0: zero crossing disabled,1: zero crossing enabled when update gain"
|
|
hexmask.long.byte 0x4 0.--5. 1. "INITGAIN,ALC Initial Gain. Set ALC initial gain.. Selects the PGA gain setting from -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB"
|
|
line.long 0x8 "ALC_STS,ALC Status Register"
|
|
hexmask.long.byte 0x8 20.--25. 1. "ALCGAIN,ALC GAIN. Current ADC gain setting"
|
|
hexmask.long.word 0x8 11.--19. 1. "PEAKVAL,Peak Value. 9 MSBs of measured absolute peak value"
|
|
newline
|
|
hexmask.long.word 0x8 2.--10. 1. "P2PVAL,Peak-to-peak Value. 9 MSBs of measured peak-to-peak value"
|
|
bitfld.long 0x8 1. "NOISEF,Noise Flag. Asserted when signal level is detected to be below NGTHBST" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CLIPF,Clipping Flag. Asserted when signal level is detected to be above 87.5% of full scale" "0,1"
|
|
line.long 0xC "ALC_INTCTL,ALC Interrupt Control Register"
|
|
bitfld.long 0xC 31. "ALCIF,ALC Interrupt flag. This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled.. Write a 1 to this register to clear." "0,1"
|
|
bitfld.long 0xC 13. "GMINIF,GAIN less than minimum GAIN interrupt flag." "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "GMAXIF,GAIN more than maximum GAIN interrupt flag." "0,1"
|
|
bitfld.long 0xC 11. "GDECIF,GAIN Decrease interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "GINCIF,GAIN Increase interrupt flag" "0,1"
|
|
bitfld.long 0xC 9. "NGIF,ALC noise gating interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "PLMTIF,ALC Peak limiting Interrupt flag" "0,1"
|
|
bitfld.long 0xC 5. "GMINIE,GAIN less than minimum GAIN interrupt enable control" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "GMAXIE,GAIN more than maximum GAIN interrupt enable control" "0,1"
|
|
bitfld.long 0xC 3. "GDECIE,GAIN Decrease interrupt enable control" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "GINCIE,GAIN Increase interrupt enable control" "0,1"
|
|
bitfld.long 0xC 1. "NGIE,ALC noise gating interrupt enable control" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "PLMTIE,ALC Peak limiting Interrupt enable control. Reserved" "0,1"
|
|
tree.end
|
|
tree "ANA (Analog Functional Blocks)"
|
|
base ad:0x40080000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ANA_VMID,VMID Reference Control Register"
|
|
bitfld.long 0x0 2. "PDHIRES,Power Down High (360kOhm) Resistance Reference." "0: Connect the High Resistance reference to VMID.,1: The High Resistance reference is disconnected.."
|
|
bitfld.long 0x0 1. "PDLORES,Power Down Low (4.8kOhm) Resistance Reference." "0: Connect the Low Resistance reference to VMID.,1: The Low Resistance reference is disconnected.."
|
|
newline
|
|
bitfld.long 0x0 0. "PULLDOWN,VMID Pulldown." "0: Release VMID pin for reference operation,1: Pull VMID pin to ground. Default power down and.."
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "ANA_LDOSEL,LDO Voltage Select Register"
|
|
bitfld.long 0x0 0.--2. "LDOSEL,Select LDO Output Voltage. Note that maximum I/O pad operation speed only specified for voltage >2.4V. ." "0: 1.8V,1: 2.4V,2: 2.5V,3: 2.7V,4: 3.0V,5: 3.3V,6: 1.5V,7: 1.7V"
|
|
line.long 0x4 "ANA_LDOPD,LDO Power Down Register"
|
|
bitfld.long 0x4 1. "DISCHAR,Discharge." "0: Don't discharge VD33,1: Switch discharge resistor to VD33"
|
|
bitfld.long 0x4 0. "PD,Power Down LDO. When powered down no current delivered to VD33.." "0: Enable LDO,1: Power Down"
|
|
line.long 0x8 "ANA_MICBSEL,Microphone Bias Voltage Level Selection"
|
|
bitfld.long 0x8 0.--2. "LVL,LVL controls the voltage output of the MICBIAS generator voltages are encoded as following: 0 - 1.5V1 - 1.8V2 - 1.95V3 - 2.1V4 - 2.25V5 - 2.4V6 - 2.55V 7 - 2.7. Note: MICBIAS voltage should be at least 300mV lower than VCCA." "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "ANA_MICBEN,Microphone Bias Enable Register"
|
|
bitfld.long 0xC 0. "PD,Power Down Microphone Bias. Note: MICBIAS output needs VMID enable together." "0: Enable Microphone Bias,1: Power Down Microphone Bias"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "ANA_TRIM,Oscillator Trim Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "COARSE,COARSE . Current COARSE range setting of the oscillator. Read Only"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OSCTRIM,Oscillator Trim. Reads current oscillator trim setting. Read Only."
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ANA_FQMMCTL,Frequency Measurement Control Register"
|
|
bitfld.long 0x0 31. "FQMMEN,FQMMEN." "0: Disable/Reset block,1: Start Frequency Measurement"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CYCLESEL,Frequency Measurement Cycles. Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us) set CYCLESEL to 7 then measurement period would be 30.5175*(7+1) 244.1us."
|
|
newline
|
|
bitfld.long 0x0 2. "MMSTS,Measurement Done." "0: Measurement Ongoing,1: Measurement Complete"
|
|
bitfld.long 0x0 0.--1. "CLKSEL,Reference Clock Source. 00b: OSC10k . 01b: OSC32K (default) . 1xb: I2S_WS - can be GPIOA[4 8 12] according to SYS_GPA_MFP register configure I2S in SLAVE mode to enable." "0,1,2,3"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "ANA_FQMMCNT,Frequency Measurement Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FQMMCNT,Frequency Measurement Count. Maximum resolution of measurement is Fref /(CYCLESEL+1)*2 Hz"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "ANA_FQMMCYC,Frequency Measurement Cycle Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "FQMMCYC,Frequency Measurement Cycles."
|
|
tree.end
|
|
tree "BIQ (Biquad Filter)"
|
|
base ad:0x400B0000
|
|
group.long 0x0++0x77
|
|
line.long 0x0 "BIQ_COEFF0,Coefficient B0 in H(z) Transfer Function. (3.16 Format) - 1st Stage BIQ Coefficients"
|
|
hexmask.long 0x0 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x4 "BIQ_COEFF1,Coefficient B1 in H(z) Transfer Function. (3.16 Format) - 1st Stage BIQ Coefficients"
|
|
hexmask.long 0x4 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x8 "BIQ_COEFF2,Coefficient B2 in H(z) Transfer Function. (3.16 Format) - 1st Stage BIQ Coefficients"
|
|
hexmask.long 0x8 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0xC "BIQ_COEFF3,Coefficient A1 in H(z) Transfer Function. (3.16 Format) - 1st Stage BIQ Coefficients"
|
|
hexmask.long 0xC 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x10 "BIQ_COEFF4,Coefficient A2 in H(z) Transfer Function. (3.16 Format) - 1st Stage BIQ Coefficients"
|
|
hexmask.long 0x10 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x14 "BIQ_COEFF5,Coefficient B0 in H(z) Transfer Function. (3.16 Format) - 2nd Stage BIQ Coefficients"
|
|
hexmask.long 0x14 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x18 "BIQ_COEFF6,Coefficient B1 in H(z) Transfer Function. (3.16 Format) - 2nd Stage BIQ Coefficients"
|
|
hexmask.long 0x18 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x1C "BIQ_COEFF7,Coefficient B2 in H(z) Transfer Function. (3.16 Format) - 2nd Stage BIQ Coefficients"
|
|
hexmask.long 0x1C 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x20 "BIQ_COEFF8,Coefficient A1 in H(z) Transfer Function. (3.16 Format) - 2nd Stage BIQ Coefficients"
|
|
hexmask.long 0x20 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x24 "BIQ_COEFF9,Coefficient A2 in H(z) Transfer Function. (3.16 Format) - 2nd Stage BIQ Coefficients"
|
|
hexmask.long 0x24 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x28 "BIQ_COEFF10,Coefficient B0 in H(z) Transfer Function. (3.16 Format) - 3rd Stage BIQ Coefficients"
|
|
hexmask.long 0x28 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x2C "BIQ_COEFF11,Coefficient B1 in H(z) Transfer Function. (3.16 Format) - 3rd Stage BIQ Coefficients"
|
|
hexmask.long 0x2C 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x30 "BIQ_COEFF12,Coefficient B2 in H(z) Transfer Function. (3.16 Format) - 3rd Stage BIQ Coefficients"
|
|
hexmask.long 0x30 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x34 "BIQ_COEFF13,Coefficient A1 in H(z) Transfer Function. (3.16 Format) - 3rd Stage BIQ Coefficients"
|
|
hexmask.long 0x34 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x38 "BIQ_COEFF14,Coefficient A2 in H(z) Transfer Function. (3.16 Format) - 3rd Stage BIQ Coefficients"
|
|
hexmask.long 0x38 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x3C "BIQ_COEFF15,Coefficient B0 in H(z) Transfer Function. (3.16 Format) - 4st Stage BIQ Coefficients"
|
|
hexmask.long 0x3C 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x40 "BIQ_COEFF16,Coefficient B1 in H(z) Transfer Function. (3.16 Format) - 4st Stage BIQ Coefficients"
|
|
hexmask.long 0x40 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x44 "BIQ_COEFF17,Coefficient B2 in H(z) Transfer Function. (3.16 Format) - 4st Stage BIQ Coefficients"
|
|
hexmask.long 0x44 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x48 "BIQ_COEFF18,Coefficient A1 in H(z) Transfer Function. (3.16 Format) - 4st Stage BIQ Coefficients"
|
|
hexmask.long 0x48 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x4C "BIQ_COEFF19,Coefficient A2 in H(z) Transfer Function. (3.16 Format) - 4st Stage BIQ Coefficients"
|
|
hexmask.long 0x4C 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x50 "BIQ_COEFF20,Coefficient B0 in H(z) Transfer Function. (3.16 Format) - 5nd Stage BIQ Coefficients"
|
|
hexmask.long 0x50 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x54 "BIQ_COEFF21,Coefficient B1 in H(z) Transfer Function. (3.16 Format) - 5nd Stage BIQ Coefficients"
|
|
hexmask.long 0x54 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x58 "BIQ_COEFF22,Coefficient B2 in H(z) Transfer Function. (3.16 Format) - 5nd Stage BIQ Coefficients"
|
|
hexmask.long 0x58 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x5C "BIQ_COEFF23,Coefficient A1 in H(z) Transfer Function. (3.16 Format) - 5nd Stage BIQ Coefficients"
|
|
hexmask.long 0x5C 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x60 "BIQ_COEFF24,Coefficient A2 in H(z) Transfer Function. (3.16 Format) - 5nd Stage BIQ Coefficients"
|
|
hexmask.long 0x60 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x64 "BIQ_COEFF25,Coefficient B0 in H(z) Transfer Function. (3.16 Format) - 6rd Stage BIQ Coefficients"
|
|
hexmask.long 0x64 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x68 "BIQ_COEFF26,Coefficient B1 in H(z) Transfer Function. (3.16 Format) - 6rd Stage BIQ Coefficients"
|
|
hexmask.long 0x68 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x6C "BIQ_COEFF27,Coefficient B2 in H(z) Transfer Function. (3.16 Format) - 6rd Stage BIQ Coefficients"
|
|
hexmask.long 0x6C 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x70 "BIQ_COEFF28,Coefficient A1 in H(z) Transfer Function. (3.16 Format) - 6rd Stage BIQ Coefficients"
|
|
hexmask.long 0x70 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
line.long 0x74 "BIQ_COEFF29,Coefficient A2 in H(z) Transfer Function. (3.16 Format) - 6rd Stage BIQ Coefficients"
|
|
hexmask.long 0x74 0.--31. 1. "COEFFDAT,Coefficient Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "BIQ_CTL,BIQ Control Register"
|
|
hexmask.long.word 0x0 16.--28. 1. "SRDIV,SR Divider"
|
|
bitfld.long 0x0 11. "STAGE,BIQ Stage Number Control." "0: 6 stage,1: 5 stage"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "DPWMPUSR,DPWM Path Up Sample Rate (From SRDIV Result). 0001 --- up 1x ( no up sample). 0010 --- up 2x. 0011 --- up 3x. 0100 --- up 4x. 0110 --- up 6x. Others reserved" "?,1: up 1x,?,?,?,?,?,?"
|
|
bitfld.long 0x0 7. "PRGCOEFF,Programming Mode Coefficient Control Bit. This bit must be turned off when BIQEN is on." "0: Coefficient RAM is in normal mode,1: coefficient RAM is under programming mode"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SDADCWNSR,SDADC Down Sample. 001--- 1x (no down sample). 010 --- 2x. 011 --- 3x. 100 --- 4x. 11 0--- 6x. Others reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "DLCOEFF,Move BIQ Out of Reset State ." "0: BIQ filter is in reset state,1: When this bit is on the default coefficients.."
|
|
newline
|
|
bitfld.long 0x0 2. "PATHSEL,AC Path Selection for BIQ." "0: used in SDADC path,1: used in DPWM path"
|
|
bitfld.long 0x0 1. "HPFON,High Pass Filter On. Note : . If this register is on BIQ only 5 stage left.for user.. SDADC path sixth stage coefficient is for HPF filter coefficient.. DPWM path first stage coefficient is for HPF filter coefficient." "0: disable high pass filter,1: enable high pass filter"
|
|
newline
|
|
bitfld.long 0x0 0. "BIQEN,BIQ Filter Start to Run." "0: BIQ filter is not processing,1: BIQ filter is on"
|
|
line.long 0x4 "BIQ_STS,BIQ Status Register"
|
|
bitfld.long 0x4 31. "RAMINITF,Coefficient Ram Initial Default Done Flag." "0: initial default value done,1: still working on"
|
|
bitfld.long 0x4 2. "BISTDONE,RAM BIST testing DONE flag for internal use" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "BISTFAILED,RAM BIST testing FAILED indicator for internal use" "0,1"
|
|
bitfld.long 0x4 0. "BISTEN,RAM BIST testing Enable for internal use" "0,1"
|
|
tree.end
|
|
tree "BOD (Brown Out Detector)"
|
|
base ad:0x40084000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "BOD_BODSEL,Brown Out Detector Select Register"
|
|
bitfld.long 0x0 4. "BODHYS,BOD Hysteresis ." "0: Hysteresis Disabled,1: Enable Hysteresis of BOD detection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BODVL,BOD Voltage Level."
|
|
line.long 0x4 "BOD_BODCTL,Brown Out Detector Enable Register"
|
|
bitfld.long 0x4 17.--18. "LVR_FILTER,Default value is 00." "0: LVR output will be filtered by 1 HCLK,1: LVR output will be filtered by 2 HCLK,?,?"
|
|
bitfld.long 0x4 16. "LVR_EN,Low Voltage Reset (LVR) Enable (Initialized & Protected Bit). The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR config0[27]. ." "0: Disable LVR function,1: Enable LVR function"
|
|
bitfld.long 0x4 5. "BODRST,BOD Reset. 1: Reset device when BOD is triggered." "?,1: Reset device when BOD is triggered"
|
|
newline
|
|
bitfld.long 0x4 4. "BODOUT,Output of BOD Detection Block." "0,1"
|
|
bitfld.long 0x4 3. "BODIF,Current Status of Interrupt." "0,1"
|
|
bitfld.long 0x4 2. "BODINTEN,BOD Interrupt Enable." "0: Disable BOD Interrupt,1: Enable BOD Interrupt"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "BODEN,BOD Enable." "0,1,2,3"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "BOD_BODDTMR,Brown Out Detector Timer Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DURTON,Time BOD Detector Is Active. (DURTON+1) * 100us. Minimum value is 1. (default is 400us)"
|
|
hexmask.long.word 0x0 0.--15. 1. "DURTOFF,Time BOD Detector Is Off. (DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)"
|
|
tree.end
|
|
tree "CLK (Clock Control)"
|
|
base ad:0x50000200
|
|
group.long 0x0++0x2F
|
|
line.long 0x0 "CLK_PWRCTL,System Power Control Register"
|
|
bitfld.long 0x0 27. "WKPUEN,Wakeup Pin Pull-up Control. This signal is latched in deep power down and preserved.." "0: pull-up enable,1: tri-state (default)"
|
|
bitfld.long 0x0 26. "PORWKF,POR Wakeup Flag. Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TMRWKF,Timer Wakeup Flag. Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10khz oscillator. Flag is cleared when DPD mode is entered." "0,1"
|
|
bitfld.long 0x0 24. "WKPINWKF,Pin Wakeup Flag. Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "FLASHEN,Flash ROM Control Enable/Disable. Bit [19]: for Stop mode operation. Bit [18]: for Sleep mode operation. 1: Turn off flash. 0: Normal. Note: It takes 10us to turn on the flash to normal" "0: Normal,1: Turn off flash,?,?"
|
|
bitfld.long 0x0 17. "LIRCDPDEN,OSC10k Enabled Control. Determines whether OSC10k is enabled in DPD mode. If OSC10k is disabled device cannot wake from DPD with SELWKTMR delay.." "0: enabled,1: disabled"
|
|
newline
|
|
bitfld.long 0x0 16. "WKPINEN,Wakeup Pin Enabled Control. Determines whether WAKEUP pin is enabled in DPD mode.." "0: enabled,1: disabled"
|
|
bitfld.long 0x0 14. "IOSTATE,'1': IO held from SPD '0': IO released." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RELEASEIO,Write '1' to this bit to release IO state after exiting SPD if hold request was made with the HOLD_IO bit." "0,1"
|
|
bitfld.long 0x0 12. "HOLDIO,When entering SPD mode IO state is automatically held If this bit is set to '1' then this sate upon resuming full power mode will be hold until the RELEASE_IO bit is written '1'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DPDEN,Deep Power Down (DPD) Bit. Set to '1' and issue WFI/WFE instruction to enter DPD mode." "0,1"
|
|
bitfld.long 0x0 10. "SPDEN,Standby Power Down (SPD) Bit. Set to '1' and issue WFI/WFE instruction to enter SPD mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STOPEN,Stop. Set to '1' and issue WFI/WFE instruction to enter STOP mode." "0,1"
|
|
bitfld.long 0x0 4. "HXTEN,HXT Oscillator Enable Bit." "0: disable (default),1: enable"
|
|
newline
|
|
bitfld.long 0x0 3. "LIRCEN,LIRC Oscillator Enable Bit." "0: disable,1: enable (default)"
|
|
bitfld.long 0x0 2. "HIRCEN,HIRC Oscillator Enable Bit." "0: disable,1: enable (default)"
|
|
newline
|
|
bitfld.long 0x0 1. "LXTEN,External 32.768 KHz Crystal Enable Bit." "0: disable (default),1: enable"
|
|
line.long 0x4 "CLK_AHBCLK,AHB Device Clock Enable Control Register"
|
|
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Control." "0: To disable the Flash ISP engine clock,1: To enable the Flash ISP engine clock"
|
|
bitfld.long 0x4 1. "PDMACKEN,PDMA Controller Clock Enable Control." "0: To disable the PDMA engine clock,1: To enable the PDMA engine clock"
|
|
newline
|
|
bitfld.long 0x4 0. "HCLKEN,CPU Clock Enable (HCLK). Must be left as 1 for normal operation." "0,1"
|
|
line.long 0x8 "CLK_APBCLK0,APB Device Clock Enable Control Register"
|
|
bitfld.long 0x8 30. "ANACKEN,Analog Block Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 29. "I2S0CKEN,I2S Clock Enable Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 28. "SDADCCKEN,Delta-Sigma Analog-digital-converter (ADC) Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 21. "PWM0CH23CKEN,PWM0CH2 and PWM0CH3 Block Clock Enable Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 20. "PWM0CH01CKEN,PWM0CH0 and PWM0CH1 Block Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 18. "BIQALCKEN,BIQ and ALC Clock Enable Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 17. "SARADCKEN,SAR Analog-digital-converter (ADC) Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 15. "UART1CKEN,UART1 Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 13. "DPWMCKEN,Differential PWM Speaker Driver Clock Enable Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 11. "SPI1CKEN,SPI1 Clock Enable Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 7. "TMR1CKEN,Timer1 Clock Enable Control." "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x8 6. "TMR0CKEN,Timer0 Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 5. "RTCCKEN,Real-time-clock APB Interface Clock Control." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x8 0. "WDTCKEN,Watchdog Clock Enable Control." "0: Disable,1: Enable"
|
|
line.long 0xC "CLK_DPDSTATE,Deep Power Down State Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "DPDSTSRD,DPD State Read Back. Read back of CLK_DPDSTATE register. This register was preserved from last DPD event ."
|
|
hexmask.long.byte 0xC 0.--7. 1. "DPDSTSWR,DPD State Write Register. Read back of CLK_DPDSTATE register. This register was preserved from last DPD event ."
|
|
line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
|
|
bitfld.long 0x10 6.--7. "HIRCFSEL,High Frequency RC Oscilltor Frequency Select Register.. These bits are protected to write to bits first perform the unlock sequence.." "0: Trim for 49.152MHz selected,1: Trim for 32.768MHz selected,?,?"
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|
bitfld.long 0x10 3.--5. "STCLKSEL,MCU Cortex_M0 SYST Clock Source Select. These bits are protected to write to bits first perform the unlock sequence.. Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of SYST_CSR must be set to 0." "0: clock source from LIRC,1: clock source from LXT.. clock source from HCLK/2..,?,?,?,?,?,?"
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|
newline
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bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Select. Ensure that related clock sources (pre-select and new-select) are enabled before updating register.. These bits are protected to write to bits first perform the unlock sequence.." "0: clock source from HIRC. (deafult),1: clock source from LXT,?,?,?,?,?,?"
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line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
|
|
bitfld.long 0x14 30.--31. "PWM0CH23SEL,PWM0CH23 Clock Source Select. PWM0 CH2 and CH3 uses the same clock source and pre-scaler." "0: clock source from LIRC,1: clock source from LXT,?,?"
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bitfld.long 0x14 28.--29. "PWM0CH01SEL,PWM0CH01 Clock Source Select. PWM0 CH0 and CH1 uses the same clock source and pre-scaler." "0: clock source from LIRC,1: clock source from LXT,?,?"
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newline
|
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bitfld.long 0x14 24.--25. "SARADCSEL,SAR ADC Clock Source Select." "0: clock source from HCLK (default),1: clock source from LIRC,?,?"
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bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Select." "0: clock source from LIRC,1: clock source from LXT.. clock source from..,?,?,?,?,?,?"
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newline
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bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Select." "0: clock source from LIRC,1: clock source from LXT.. clock source from..,?,?,?,?,?,?"
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bitfld.long 0x14 4.--5. "DPWMSEL,Differential Speaker Driver PWM Clock Source Select." "0: clock source from HCLK/(DPWMDIV+1). (default),1: clock source from HXT. Reserved,?,?"
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newline
|
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bitfld.long 0x14 2.--3. "SDADCSEL,SD ADC Clock Source Select (output is MCLK after clock enable)." "0: clock source from HCLK/(SDADCDIV+1). (default),1: clock source from HXT. Reserved,?,?"
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|
bitfld.long 0x14 0.--1. "WDTSEL,WDT Clock Source Select." "0: clock source from HIRC,1: clock source from LXT,?,?"
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|
line.long 0x18 "CLK_CLKDIV0,Clock Divider Number Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "SARADCDIV,SARADC Clock Divide Number From ADC Clock Source."
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|
hexmask.long.byte 0x18 16.--23. 1. "SDADCDIV,SDADC Clock Divide Number From ADC Clock Source."
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|
newline
|
|
hexmask.long.byte 0x18 12.--15. 1. "DPWMDIV,DPWM Clock Divide Number From HCLK Clock Source."
|
|
hexmask.long.byte 0x18 8.--11. 1. "UARTDIV,UART Clock Divide Number From UART Clock Source."
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|
newline
|
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hexmask.long.byte 0x18 4.--7. 1. "BIQDIV,BIQ Clock Divide Number From HCLK Clock Source."
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|
hexmask.long.byte 0x18 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source."
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|
line.long 0x1C "CLK_CLKSEL2,Clock Source Select Control Register 2"
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|
hexmask.long.byte 0x1C 8.--11. 1. "UART1DIV,UART1 Clock Divide Number From UART Clock Source."
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|
bitfld.long 0x1C 0.--1. "I2S0SEL,I2S0 Clock Source Select." "0: clock source from internal 10kHz..,1: clock source from external 32kHz crystal clock,?,?"
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|
line.long 0x20 "CLK_SLEEPCTL,Sleep Clock Source Select Register"
|
|
bitfld.long 0x20 30. "ANACKEN,Analog Block Sleep Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x20 29. "I2SCKEN,I2S Sleep Clock Enable Control." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x20 28. "SDADCCKEN,Delta-Sigma Analog-digital-converter (ADC) Sleep Clock Enable Control." "0: Disable,1: Enable"
|
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bitfld.long 0x20 21. "PWM0CH23CKEN,PWM0CH2 and PWM0CH3 Block Sleep Clock Enable Control." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x20 20. "PWM0CH01CKEN,PWM0CH0 and PWM0CH1 Block Sleep Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x20 18. "BIQALCKEN,BIQ and ALCSleep Clock Enable Control." "0: Disable,1: Enable"
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|
newline
|
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bitfld.long 0x20 17. "SARADCCKEN,SARADC Sleep Clock Enable Control." "0: Disable,1: Enable"
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|
bitfld.long 0x20 16. "UART0CKEN,UART0 Sleep Clock Enable Control." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x20 15. "UART1CKEN,UART1 Sleep Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x20 13. "DPWMCKEN,Differential PWM Speaker Driver Sleep Clock Enable Control." "0: Disable,1: Enable"
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|
newline
|
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bitfld.long 0x20 12. "SPI0CKEN,SPI0 Sleep Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x20 11. "SPI1CHEN,SPI1 Sleep Clock Enable Control." "0: Disable,1: Enable"
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|
newline
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bitfld.long 0x20 8. "I2C0CKEN,I2C0 Sleep Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x20 7. "TMR1CKEN,Timer1 Sleep Clock Enable Control." "0: Disable,1: Enable"
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newline
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bitfld.long 0x20 6. "TMR0CKEN,Timer0 Sleep Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x20 5. "RTCCKEN,Real-time- Sleep Clock APB Interface Clock Control." "0: Disable,1: Enable"
|
|
newline
|
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bitfld.long 0x20 4. "WDTCKEN,Watchdog Sleep Clock Enable Control." "0: Disable,1: Enable"
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|
bitfld.long 0x20 2. "ISPCKEN,Flash ISP Controller Sleep Clock Enable Control." "0: Disable,1: Enable"
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|
newline
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bitfld.long 0x20 1. "PDMACKEN,PDMA Controller Sleep Clock Enable Control." "0: Disable,1: Enable"
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|
bitfld.long 0x20 0. "HCLKCKEN,CPU Clock Sleep Enable (HCLK). Must be left as '1' for normal operation.." "0: Disable,1: Enable"
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line.long 0x24 "CLK_PWRSTSF,Power State Flag Register"
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bitfld.long 0x24 2. "SPDF,Powered Down Flag. This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag." "0,1"
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bitfld.long 0x24 1. "STOPF,Stop Flag. This flag is set if core logic was stopped but not powered down. Write '1' to clear flag." "0,1"
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newline
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bitfld.long 0x24 0. "DSF,Deep Sleep Flag. This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag." "0,1"
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|
line.long 0x28 "CLK_DBGPD,Debug Port Power Down Disable Register"
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|
bitfld.long 0x28 7. "ICEDATST,ICEDATST Pin State. Read Only. Current state of ICE_DAT pin." "0,1"
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|
bitfld.long 0x28 6. "ICECLKST,ICECLKST Pin State. Read Only. Current state of ICE_CLK pin." "0,1"
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|
newline
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bitfld.long 0x28 0. "DISPDREQ,Disable Power Down." "0: Enable power down requests,1: Disable power down requests"
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|
line.long 0x2C "CLK_WAKE10K,Deep Power Down 10K Wakeup Timer"
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bitfld.long 0x2C 31. "WAKE10KEN,Enable WAKE from DPD on 10kHz timer" "0,1"
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hexmask.long.word 0x2C 16.--29. 1. "WKTMRSTS,Current Wakeup Timer Setting. Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode."
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newline
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hexmask.long.word 0x2C 0.--13. 1. "SELWKTMR,Select Wakeup Timer. WAKEUP after 64* (SELWKTMR+1) OSC10k clocks (6.4 * (SELWKTMR+1) ms)"
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tree.end
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tree "CSCAN (CAP SENSE)"
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|
base ad:0x400D0000
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|
group.long 0x0++0x1B
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|
line.long 0x0 "CSCAN_CTRL,CSCAN Control Register"
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bitfld.long 0x0 31. "PD,Power Down. 0: Enable analog circuit. 1: Power down analog circuit and block." "0: Enable analog circuit,1: Power down analog circuit and block"
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bitfld.long 0x0 30. "EN,CSCAN Enable. Write 1 to start. Reset by hardware when operation finished." "0,1"
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newline
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hexmask.long.byte 0x0 24.--27. 1. "DUR_CNT,CSCAN Duration Count. This counter is used to set a wakeup time after a capacitive sensing scan is complete. It is in units of low frewquency clock period (either LXT or LIRC clock) and gives delay of 160 320 480 640 800 960 1120 1280 .."
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bitfld.long 0x0 23. "MODE1,CSCAN Mode1." "0: Interrupt when scan finished,1: Interrupt when DUR_CNT delay occurs"
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newline
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bitfld.long 0x0 22. "MODE0,CSCAN Mode0." "0: Single shot Capacitive sense,1: Scans each channel set in SCAN_MASK and stores.."
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bitfld.long 0x0 21. "SLOW_CLK,CSCAN Slow Clock . **Notes:. In low speed mode for CYCLE_CNT <5 the minimum frequency of oscillation of a CAPSENSE GPIO must be > Fclk/2. Where Fclk is the frequency of LXT or LIRC depending which is selected as reference." "0: Timebase clock is HIRC,1: Timebase clock is LIRC (XTAL32K_EN = 0) or XTAL.."
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newline
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bitfld.long 0x0 20. "INT_EN,CSCAN Enable Interrupt." "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x0 18.--19. "ReservedBIAS,CSCAN Comparator bias current . Controls the bais current of relaxation comparators. Suggest default 0. Can select lower for marginal power savings and less accuracy.. 0:Normal 1:Half 3:Quarter. Keep with 0" "0: Normal 1:Half 3:Quarter,?,?,?"
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newline
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bitfld.long 0x0 16.--17. "CURRENT,CSCAN Oscillator current . Controls the analog bais current of the capacitive relaxation oscillator.. 0:300nA 1:450nA 2:600nA 3:1200nA" "0,1,2,3"
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hexmask.long.word 0x0 0.--15. 1. "SEL,CSCAN Select. In single mode selects the channel (GPIOB[15:0]) to perform measurement on."
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line.long 0x4 "CSCAN_CYCCNT,CSCAN Cycle Count Control Register"
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hexmask.long.word 0x4 16.--31. 1. "MASK,Scan Mask Register. If MASK[n] is set then GPIOB[n] is included in scan of capacitive sensing."
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hexmask.long.byte 0x4 0.--3. 1. "CYCLE_CNT,CSCAN Cycle Count."
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line.long 0x8 "CSCAN_COUNT,CSCAN Count Status Register"
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hexmask.long.word 0x8 0.--15. 1. "COUNT,CSCAN Count. Count result of single scan."
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line.long 0xC "CSCAN_INT,CSCAN Interrupt Register"
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bitfld.long 0xC 0. "INT,CSCAN Interrupt active. Write '1' to clear." "0,1"
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line.long 0x10 "CSCAN_AGPIO,CSCAN Analog GPIO Function Register"
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hexmask.long.word 0x10 0.--15. 1. "AGPIO,CSCAN AGPIO. If bit set to 1 then corresponding GPIOB[n] is forced to an analog mode where digital input output and pullup is disabled. Can be used to set pad into analog mode for CapSensing SAR ADC and OPAMP functions."
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line.long 0x14 "CSCAN_OPACTL,Operational Amplifier Control Register"
|
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bitfld.long 0x14 26. "A1O2CIN,OPA1 output to comparator input control bit ." "0: disable,1: enable"
|
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bitfld.long 0x14 25. "A0O2CIN,OPA0 output to comparator input control bit ." "0: disable,1: enable"
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newline
|
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bitfld.long 0x14 24. "LPWREN,Enable Opamps in STOP/SPD modes." "0: disable,1: enable"
|
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bitfld.long 0x14 23. "A0O2A1N,OPA0 Output to OPA0 Inverting Input Control Bit ." "0: disable,1: enable"
|
|
newline
|
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bitfld.long 0x14 22. "A0O2A1P,OPA0 Output to OPA1 Non-inverting Input Control Bit ." "0: disable,1: enable"
|
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bitfld.long 0x14 20. "VREFEN,Enable OPA and Comparator Reference Voltage Generator ." "0: disable,1: enable"
|
|
newline
|
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bitfld.long 0x14 19. "PGAEN,OPA1 PGA Gain Enable Control Bits ." "0: disable,1: Enable"
|
|
bitfld.long 0x14 16.--18. "PGA,OPA1 Gain Control Bits." "0: 1,1: 8,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x14 15. "A1X,Operational amplifier 1 output; positive logic This bit is read only" "0,1"
|
|
bitfld.long 0x14 14. "A102N,OPA1 Output to OPA1 Inverting Input Control Bit ." "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x14 12.--13. "A1PSEL,OPA1 Non-inverting Input Selection Bit ." "0: no connection,1: from VH1 (0.9xVDDA),?,?"
|
|
bitfld.long 0x14 11. "A1PS,A1P Pin to OPA1 Non-inverting Input Control Bit ." "0: no connection,1: from A0P pin"
|
|
newline
|
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bitfld.long 0x14 10. "A1NS,A1N Pin to OPA1 Inverting Input Control Bit ." "0: no connection,1: from A0N pin"
|
|
bitfld.long 0x14 9. "A1OEN,OPA1 Output Enable or Disable Control Bit ." "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x14 8. "A1EN,OPA1 Enable or Disable Control Bit ." "0: disable,1: enable"
|
|
bitfld.long 0x14 7. "A0X,Operational amplifier 0 output; positive logic This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "A0O2N,OPA0 Output to OPA0 Inverting Input Control Bit ." "0: disable,1: enable"
|
|
bitfld.long 0x14 4.--5. "A0PSEL,OPA0 Non-inverting Input Selection Bit ." "0: no connection,1: from VH1 (0.9xVDDA),?,?"
|
|
newline
|
|
bitfld.long 0x14 3. "A0PS,A0P Pin to OPA0 Non-inverting Input Control Bit ." "0: no connection,1: from A0P pin"
|
|
bitfld.long 0x14 2. "A0NS,A0N Pin to OPA0 Inverting Input Control Bit ." "0: no connection,1: from A0N pin"
|
|
newline
|
|
bitfld.long 0x14 1. "A0OEN,OPA0 Output Enable or Disable Control Bit ." "0: disable,1: enable"
|
|
bitfld.long 0x14 0. "A0EN,OPA0 Enable or Disable Control Bit ." "0: disable,1: enable"
|
|
line.long 0x18 "CSCAN_CMPCTL,Comparator Control Register"
|
|
bitfld.long 0x18 24. "LPWREN,Comparator Low power mode enable. If '1' comparator will remain enabled in STOP/SPD power modes." "0,1"
|
|
bitfld.long 0x18 17. "C2OUT,Comparator 2 Output.. Real time readback of comparator 2." "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "C1OUT,Comparator 1 Output.. Real time readback of comparator 1." "0,1"
|
|
bitfld.long 0x18 14.--15. "CMPES,Interrupt edge control bits ." "0: disable,1: rising edge trigger,?,?"
|
|
newline
|
|
bitfld.long 0x18 11. "C2INTEN,Comparator 2 interrupt control ." "0: disable,1: enable"
|
|
bitfld.long 0x18 10. "C2OUTEN,Comparator 2 output pin control bit." "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x18 9. "C2PSEL,Comparator 2 inverting input control ." "0: from VL0,1: from C2P pin"
|
|
bitfld.long 0x18 8. "CMP2EN,Comparator 2 enable or disable control ." "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x18 7. "CNPSEL,Comparator non-inverting input control ." "0: from OPA output,1: from CNP pin"
|
|
bitfld.long 0x18 4. "CMP_INT,Comparator Interrupt.. Set by harddware.. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "C1INTEN,Comparator 1 interrupt control ." "0: disable,1: enable"
|
|
bitfld.long 0x18 2. "C1OUTEN,Comparator 1 output pin control bit." "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x18 1. "C1NSEL,Comparator 1 inverting input control ." "0: from VH0,1: from C1N pin"
|
|
bitfld.long 0x18 0. "CMP1EN,Comparator 1 enable or disable control ." "0: disable,1: enable"
|
|
tree.end
|
|
tree "DPWM (Differential Audio PWM Output)"
|
|
base ad:0x40070000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DPWM_CTL,DPWM Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RXTH,DPWM FIFO Threshold. If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting the RXTHIF bit will set to 1 else the RXTHIF bit will be cleared to 0."
|
|
bitfld.long 0x0 11. "RXTHIE,DPWM FIFO Threshold Interrupt." "0: DPWM FIFO threshold interrupt Disabled,1: DPWM FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 10. "ReservedMUTEEN,ReservedDPWM NOSIE REMOVER Enable (rev C still has problem)." "0: turn off noise remover function,1: turn on remover function"
|
|
bitfld.long 0x0 8.--9. "ReservedMUTETM,ReservedDPWM MUTE Waite Time." "0: mute afer 2^13 DPWM CLOCK cycle at MUTEEN = 1,1: mute afer 2^14 DPWM CLOCK cycle at MUTEEN = 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "DWPMDRVEN,DPWM Driver Enable." "0: Disable DPWM Driver,1: Enable DPWM Diver"
|
|
bitfld.long 0x0 6. "DPWMEN,DPWM Enable ." "0: Disable DPWM,1: Enable DPWM"
|
|
newline
|
|
bitfld.long 0x0 3. "DEADTIME,DPWM Driver DEADTIME Control. . Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors." "0,1"
|
|
bitfld.long 0x0 0.--1. "FIFOWIDTH,DPWM FIFO DATA WIDTH SELETION From PDMA." "0: PDMA MSB 24bits PWDATA[31:8],1: PDMA 16 bits PWDATA[15:0],?,?"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DPWM_STS,DPWM DATA FIFO Status Register"
|
|
bitfld.long 0x0 31. "BISTEN,BIST Enable. DPWM FIFO can be testing by Cortex-M0 . Internal use" "0: disable DPWM FIFO BIST testing,1: enable DPWM FIFO BIST testing"
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFOPTR,DPWM FIFO Pointer (Read Only). The FULL bit and FIFOPOINTER indicates the field that the valid data count within the DPWM FIFO buffer.. The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16 The FULL.."
|
|
newline
|
|
bitfld.long 0x0 2. "RXTHIF,DPWM FIFO Threshold Interrupt Status (Read Only)." "0: The valid data count within the DPWM FIFO buffer..,1: The valid data count within the transmit FIFO.."
|
|
bitfld.long 0x0 1. "EMPTY,FIFO Empty." "0: FIFO is not empty,1: FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "FULL,FIFO Full." "0: FIFO is not full,1: FIFO is full"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DPWM_DMACTL,DPWM PDMA Control Register"
|
|
bitfld.long 0x0 0. "DMAEN,Enable DPWM DMA Interface." "0: Disable PDMA. No requests will be made to PDMA..,1: Enable PDMA. Block will request data from PDMA.."
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "DPWM_DATA,DPWM DATA FIFO Input"
|
|
hexmask.long 0x0 0.--31. 1. "INDATA,DPWM FIFO Audio Data Input. A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DPWM_ZOHDIV,DPWM Zero Order Hold Division Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ZOHDIV,DPWM Zero Order Hold Down-sampling Divisor. The input sample rate of the DPWM is set by DPWM_CLK frequency and the divisor set in this register by the following formula:. Default is 6 which gives a sample rate of 16kHz up-sample 256 for a.."
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|
tree.end
|
|
tree "FMC (Flash Memory Control)"
|
|
base ad:0x5000C000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x0 21. "CACHEDIS,Cache Disable. When set to 1 caching of flash memory reads is disabled." "0,1"
|
|
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag. This bit is set by hardware when a triggered ISP meets any of the following conditions:. (1) APROM writes to itself.. (2) LDROM writes to itself. . (3) Destination address is illegal such as over an available range.. Write 1 to clear." "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable. LDROM update enable bit. ." "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM"
|
|
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable. When enabled ISP functions can access the CONFIG address space and modify device configuration area." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 3. "APUWEN,APU Write Enable." "0: APROM can't write itself. ISPFF with '1',1: APROM write to itself"
|
|
bitfld.long 0x0 1. "BS,Boot Select . Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in.." "0: APROM,1: LDROM"
|
|
newline
|
|
bitfld.long 0x0 0. "ISPEN,ISP Enable." "0: Disable ISP function,1: Enable ISP function"
|
|
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address Register. This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only consequently ISPADDR [1:0] must be 00b for correct ISP operation."
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line.long 0x8 "FMC_ISPDAT,ISP Data Register"
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|
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data Register. Write data to this register before an ISP program operation.. Read data from this register after an ISP read operation"
|
|
line.long 0xC "FMC_ISPCMD,ISP Command Register"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CMD,ISP Command . Operation Mode : CMD. Standby : 0x3X. Read : 0x00. Program : 0x21. Page Erase : 0x22. Read CID : 0x0B. Read DID : 0x0C"
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|
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
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|
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger. Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished.. After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee.." "0: ISP operation is finished,1: ISP is on going"
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|
rgroup.long 0x14++0x3
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|
line.long 0x0 "FMC_DFBA,Data Flash Base Address"
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|
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address. This register reports the data flash starting address. It is a read only register.. Data flash size is defined by user configuration; register content is loaded from Config1 when chip is reset."
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tree.end
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tree "GPIO (General Purpose I/Os)"
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base ad:0x50004000
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group.long 0x0++0xF
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|
line.long 0x0 "PA_MODE,GPIO Port A Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 26.--27. "MODE13,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
|
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bitfld.long 0x0 2.--3. "MODE1,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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|
line.long 0x4 "PA_DINOFF,GPIO Port A Pin Input Disable"
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hexmask.long.word 0x4 16.--31. 1. "DINOFF,GPIOx Pin[n] OFF Digital Input Path Enable."
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|
line.long 0x8 "PA_DOUT,GPIO Port A Data Output Value"
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|
hexmask.long.word 0x8 0.--15. 1. "DOUT,Px Pin[n] Output Value. Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output open-drain or quasi-bidirectional mode.."
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|
line.long 0xC "PA_DATMSK,GPIO Port A Data Output Write Mask"
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hexmask.long.word 0xC 0.--15. 1. "DATMSK,Port [A/B] Data Output Write Mask. These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to '1' the corresponding DOUTn bit is writing protected. ."
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rgroup.long 0x10++0x3
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|
line.long 0x0 "PA_PIN,GPIO Port A Pin Value"
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hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin Values. The value read from each of these bit reflects the actual status of the respective GPIO pin"
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group.long 0x14++0xF
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line.long 0x0 "PA_DBEN,GPIO Port A De-bounce Enable"
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|
hexmask.long.word 0x0 0.--15. 1. "DBEN,Port [A/B] De-bounce Enable Control. DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated input signal must be valid for two consecutive de-bounce periods. The de-bounce time is.."
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line.long 0x4 "PA_INTTYPE,GPIO Port A Interrupt Trigger Type"
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hexmask.long.word 0x4 0.--15. 1. "TYPE,Port [A/B] Edge or Level Detection Interrupt Trigger Type. TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered edge de-bounce is controlled by the DBEN register. If the.."
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|
line.long 0x8 "PA_INTEN,GPIO Port A Interrupt Enable"
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hexmask.long.word 0x8 16.--31. 1. "RHIEN,Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High. RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.. If the interrupt is configured in level.."
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hexmask.long.word 0x8 0.--15. 1. "FLIEN,Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low. FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.. If the interrupt is configured in level.."
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line.long 0xC "PA_INTSRC,GPIO Port A Interrupt Source Flag"
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hexmask.long.word 0xC 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag. Read :."
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|
group.long 0x40++0xF
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|
line.long 0x0 "PB_MODE,GPIO Port B Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 26.--27. "MODE13,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
|
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bitfld.long 0x0 22.--23. "MODE11,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
|
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bitfld.long 0x0 18.--19. "MODE9,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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|
newline
|
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bitfld.long 0x0 14.--15. "MODE7,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
|
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bitfld.long 0x0 10.--11. "MODE5,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
|
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bitfld.long 0x0 6.--7. "MODE3,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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newline
|
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bitfld.long 0x0 2.--3. "MODE1,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Px I/O Pin[n] Mode Control . Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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line.long 0x4 "PB_DINOFF,GPIO Port B Pin Input Disable"
|
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hexmask.long.word 0x4 16.--31. 1. "DINOFF,GPIOx Pin[n] OFF Digital Input Path Enable."
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|
line.long 0x8 "PB_DOUT,GPIO Port B Data Output Value"
|
|
hexmask.long.word 0x8 0.--15. 1. "DOUT,Px Pin[n] Output Value. Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output open-drain or quasi-bidirectional mode.."
|
|
line.long 0xC "PB_DATMSK,GPIO Port B Data Output Write Mask"
|
|
hexmask.long.word 0xC 0.--15. 1. "DATMSK,Port [A/B] Data Output Write Mask. These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to '1' the corresponding DOUTn bit is writing protected. ."
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rgroup.long 0x50++0x3
|
|
line.long 0x0 "PB_PIN,GPIO Port B Pin Value"
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|
hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin Values. The value read from each of these bit reflects the actual status of the respective GPIO pin"
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|
group.long 0x54++0xF
|
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line.long 0x0 "PB_DBEN,GPIO Port B De-bounce Enable"
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|
hexmask.long.word 0x0 0.--15. 1. "DBEN,Port [A/B] De-bounce Enable Control. DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated input signal must be valid for two consecutive de-bounce periods. The de-bounce time is.."
|
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line.long 0x4 "PB_INTTYPE,GPIO Port B Interrupt Trigger Type"
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hexmask.long.word 0x4 0.--15. 1. "TYPE,Port [A/B] Edge or Level Detection Interrupt Trigger Type. TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered edge de-bounce is controlled by the DBEN register. If the.."
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line.long 0x8 "PB_INTEN,GPIO Port B Interrupt Enable"
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hexmask.long.word 0x8 16.--31. 1. "RHIEN,Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High. RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.. If the interrupt is configured in level.."
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|
hexmask.long.word 0x8 0.--15. 1. "FLIEN,Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low. FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.. If the interrupt is configured in level.."
|
|
line.long 0xC "PB_INTSRC,GPIO Port B Interrupt Source Flag"
|
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hexmask.long.word 0xC 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag. Read :."
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|
group.long 0x180++0x3
|
|
line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control"
|
|
bitfld.long 0x0 5. "ICLKON,Interrupt Clock on Mode. Set this bit '0' will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.." "0: disable the clock if the GPIOx[n] interrupt is..,1: Interrupt generation clock always active"
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bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Select." "0: De-bounce counter clock source is HCLK,1: De-bounce counter clock source is the internal.."
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection ."
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "I2C_CTL,I2C Control Register"
|
|
bitfld.long 0x0 7. "INTEN,Enable Interrupt." "0: Disable interrupt,1: Enable interrupt CPU"
|
|
bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit. Set to enable I2C serial function block." "0: Disable,1: Enable"
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|
bitfld.long 0x0 5. "STA,I2C START Control Bit. Setting STA to logic 1 will enter master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "STO,I2C STOP Control Bit. In master mode set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode setting STO resets I2C.." "0,1"
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|
bitfld.long 0x0 3. "SI,I2C Interrupt Flag. When a new SIO state is present in the I2C_STATUS register the SI flag is set by hardware and if bit INTEN (I2C_CTL[7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit." "0,1"
|
|
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit." "0,1"
|
|
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address Register. The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
|
|
bitfld.long 0x4 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
|
|
line.long 0x8 "I2C_DAT,I2C DATA Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data Register. During master or slave transmit mode data to be transmitted is written to this register. During master or slave receive mode data that has been received may be read from this register."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Register. The status register of I2C:."
|
|
group.long 0x10++0x23
|
|
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided Register."
|
|
line.long 0x4 "I2C_TOCTL,I2C Time Out Control Register"
|
|
bitfld.long 0x4 2. "TOCEN,Time-out Counter Control Bit. When enabled the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divide by 4 . When enabled the time-out clock is PCLK/4." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "TOIF,Time-out Flag." "0: No time-out,1: Time-out flag is set by H/W. It can interrupt.."
|
|
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address Register. The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
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|
bitfld.long 0x8 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
|
|
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address Register. The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
|
|
bitfld.long 0xC 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
|
|
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address Register. The content of this register is irrelevant when I2C is in master mode. In the slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
|
|
bitfld.long 0x10 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
|
|
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask Register. I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison."
|
|
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask Register. I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison."
|
|
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask Register. I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison."
|
|
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask Register. I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison."
|
|
tree.end
|
|
tree "I2S (Inter-IC Sound)"
|
|
base ad:0x400A0000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "I2S_CTL,I2S Control Register"
|
|
bitfld.long 0x0 21. "RXPDMAEN,Enable Receive DMA. When RX DMA is enabled I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.." "0: Disable RX DMA,1: Enable RX DMA"
|
|
bitfld.long 0x0 20. "TXPDMAEN,Enable Transmit DMA. When TX DMA is enables I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.." "0: Disable TX DMA,1: Enable TX DMA"
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|
newline
|
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bitfld.long 0x0 19. "RXCLR,Clear Receive FIFO. Write 1 to clear receive FIFO internal pointer is reset to FIFO start point and I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty.. This bit is cleared by hardware automatically when clear operation complete." "0,1"
|
|
bitfld.long 0x0 18. "TXCLR,Clear Transmit FIFO. Write 1 to clear transmit FIFO internal pointer is reset to FIFO start point and I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed. . This bit is cleared by hardware.." "0,1"
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|
newline
|
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detect Enable. If this bit is set to 1 when left channel data sign bit changes or data bits are all zero the LZCIF flag in I2S_STATUS register will be set to 1. ." "0: Disable left channel zero cross detect,1: Enable left channel zero cross detect"
|
|
bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detect Enable. If this bit is set to 1 when right channel data sign bit changes or data bits are all zero the RZCIF flag in I2S_STATUS register will be set to 1. ." "0: Disable right channel zero cross detect,1: Enable right channel zero cross detect"
|
|
newline
|
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable. The I91200can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous then data will be periodically corrupted. Software needs to implement a way to.." "0: Disable master clock,1: Enable master clock"
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|
bitfld.long 0x0 12.--14. "RXTH,Receive FIFO Threshold Level. When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set. ." "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 9.--11. "TXTH,Transmit FIFO Threshold Level. If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.." "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x0 8. "SLAVE,Slave Mode. I2S can operate as a master or slave. For master mode I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from I91200. In slave mode I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "FORMAT,Data Format." "0: I2S data format,1: MSB justified data format"
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bitfld.long 0x0 6. "MONO,Monaural Data. This parameter sets whether mono or stereo data is processed. See Figure 581 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.." "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width. This parameter sets the word width of audio data. See Figure 581 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.." "0: data is 8 bit,1: data is 16 bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable." "0: Transmit data is shifted from FIFO,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable." "0: Disable data receive,1: Enable data receive"
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bitfld.long 0x0 1. "TXEN,Transmit Enable." "0: Disable data transmit,1: Enable data transmit"
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newline
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bitfld.long 0x0 0. "I2SEN,Enable I2S Controller." "0: Disable,1: Enable"
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line.long 0x4 "I2S_CLK,I2S Clock Divider Register"
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hexmask.long.byte 0x4 8.--15. 1. "BCLKDIV,Bit Clock Divider. If I2S operates in master mode bit clock is provided by I91200. Software can program these bits to generate bit clock frequency for the desired sample rate.. For sample rate Fs the desired bit clock frequency is:."
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bitfld.long 0x4 0.--2. "MCLKDIV,Master Clock Divider. I91200can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0 MCLK is the same as I2S_CLKDIV clock input otherwise MCLK frequency is given by:." "0,1,2,3,4,5,6,7"
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line.long 0x8 "I2S_IEN,I2S Interrupt Enable Register"
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bitfld.long 0x8 12. "LZCIEN,Left Channel Zero Cross Interrupt Enable. Interrupt will occur if this bit is set to 1 and left channel has zero cross event." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 11. "RZCIEN,Right Channel Zero Cross Interrupt Enable. Interrupt will occur if this bit is set to 1 and right channel has zero cross event." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable. Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 9. "TXOVIEN,Transmit FIFO Overflow Interrupt Enable. Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 8. "TXUDIEN,Transmit FIFO Underflow Interrupt Enable. Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt. Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].." "0: Disable interrupt,1: Enable interrupt"
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newline
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bitfld.long 0x8 1. "RXOVIEN,Receive FIFO Overflow Interrupt Enable." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 0. "RXUDIEN,Receive FIFO Underflow Interrupt Enable. If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1. ." "0: Disable interrupt,1: Enable interrupt"
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line.long 0xC "I2S_STATUS,I2S Status Register"
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hexmask.long.byte 0xC 28.--31. 1. "TXCNT,Transmit FIFO Level (Read Only)."
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hexmask.long.byte 0xC 24.--27. 1. "RXCNT,Receive FIFO Level (Read Only)."
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bitfld.long 0xC 23. "LZCIF,Left Channel Zero Cross Flag (Write '1' to Clear or Clear LZCEN)." "0: No zero cross detected,1: Left channel zero cross is detected"
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bitfld.long 0xC 22. "RZCIF,Right Channel Zero Cross Flag (Write '1' to Clear or Clear RZCEN)." "0: No zero cross,1: Right channel zero cross is detected"
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newline
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rbitfld.long 0xC 21. "TXBUSY,Transmit Busy (Read Only). This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register. ." "0: Transmit shift register is empty,1: Transmit shift register is busy"
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rbitfld.long 0xC 20. "TXEMPTY,Transmit FIFO Empty (Read Only). This is set when transmit FIFO is empty.." "0: Not empty,1: Empty"
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rbitfld.long 0xC 19. "TXFULL,Transmit FIFO Full (Read Only). This bit is set when transmit FIFO is full.." "0: Not full,1: Full"
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rbitfld.long 0xC 18. "TXTHIF,Transmit FIFO Threshold Flag (Read Only). When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by.." "0: Data word(s) in FIFO is greater than threshold..,1: Data word(s) in FIFO is less than or equal to.."
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newline
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bitfld.long 0xC 17. "TXOVIF,Transmit FIFO Overflow Flag (Write '1' to Clear). This flag is set if data is written to transmit FIFO when it is full. ." "0: No overflow,1: Overflow"
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bitfld.long 0xC 16. "TXUDIF,Transmit FIFO Underflow Flag (Write '1' to Clear). This flag is set if I2S controller requests data when transmit FIFO is empty. ." "0: No underflow,1: Underflow"
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newline
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rbitfld.long 0xC 12. "RXEMPTY,Receive FIFO Empty (Read Only). This is set when receive FIFO is empty.." "0: Not empty,1: Empty"
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rbitfld.long 0xC 11. "RXFULL,Receive FIFO Full (Read Only). This bit is set when receive FIFO is full.." "0: Not full,1: Full"
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newline
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rbitfld.long 0xC 10. "RXTHIF,Receive FIFO Threshold Flag (Read Only). When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by.." "0: Data word(s) in FIFO is less than threshold level,1: Data word(s) in FIFO is greater than or equal to.."
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bitfld.long 0xC 9. "RXOVIF,Receive FIFO Overflow Flag (Write '1' to Clear). This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.." "0: No overflow,1: Overflow"
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newline
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bitfld.long 0xC 8. "RXUDIF,Receive FIFO Underflow Flag (Write '1' to Clear). This flag is set if attempt is made to read receive FIFO while it is empty. ." "0: No underflow,1: Underflow"
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rbitfld.long 0xC 3. "RIGHT,Right Channel Active (Read Only). This bit indicates current data being transmitted/received belongs to right channel." "0: Left channel,1: Right channel"
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newline
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rbitfld.long 0xC 2. "TXIF,I2S Transmit Interrupt (Read Only). This indicates that there is an active transmit interrupt source. This could be TXOVIF TXUDIF TXTHIF LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding.." "0: No transmit interrupt,1: Transmit interrupt occurred"
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rbitfld.long 0xC 1. "RXIF,I2S Receive Interrupt (Read Only). This indicates that there is an active receive interrupt source. This could be RXOVIF RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be.." "0: No receive interrupt,1: Receive interrupt occurred"
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newline
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rbitfld.long 0xC 0. "I2SIF,I2S Interrupt (Read Only). This bit is set if any enabled I2S interrupt is active.." "0: No I2S interrupt,1: I2S interrupt active"
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wgroup.long 0x10++0x3
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line.long 0x0 "I2S_TX,I2S Transmit FIFO Register"
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hexmask.long 0x0 0.--31. 1. "TX,Transmit FIFO Register (Write Only). A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT."
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rgroup.long 0x14++0x3
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line.long 0x0 "I2S_RX,I2S Receive FIFO Register"
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hexmask.long 0x0 0.--31. 1. "RX,Receive FIFO Register (Read Only). A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT."
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tree.end
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tree "INT (Interrupt Multiplexer)"
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base ad:0x50000300
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rgroup.long 0x0++0x7F
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line.long 0x0 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity Register"
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bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: BOD_INT" "0: BOD_INT,?,?,?,?,?,?,?"
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line.long 0x4 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity Register"
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bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: WDT_INT" "0: WDT_INT,?,?,?,?,?,?,?"
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line.long 0x8 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity Register"
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bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: INT0_INT" "0: INT0_INT,?,?,?,?,?,?,?"
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line.long 0xC "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity Register"
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bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: INT0_INT" "0: INT0_INT,?,?,?,?,?,?,?"
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line.long 0x10 "IRQ4_SRC,IRQ4 (GPA/B) Interrupt Source Identity Register"
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bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: GPB_INT. Bit0: GPA_INT" "0: GPA_INT,1: GPB_INT,?,?,?,?,?,?"
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line.long 0x14 "IRQ5_SRC,IRQ5 (ALC) Interrupt Source Identity Register"
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bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: ALC_INT" "0: ALC_INT,?,?,?,?,?,?,?"
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line.long 0x18 "IRQ6_SRC,IRQ6 (PWM0) Interrupt Source Identity Register"
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bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: PWM_INT" "0: PWM_INT,?,?,?,?,?,?,?"
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line.long 0x1C "IRQ7_SRC,IRQ7 (Reserved) Interrupt Source Identity Register"
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line.long 0x20 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity Register"
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bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: TMR0_INT" "0: TMR0_INT,?,?,?,?,?,?,?"
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line.long 0x24 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity Register"
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bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: TMR1_INT" "0: TMR1_INT,?,?,?,?,?,?,?"
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line.long 0x28 "IRQ10_SRC,IRQ10 (Reserved) Interrupt Source Identity Register"
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line.long 0x2C "IRQ11_SRC,IRQ11 (UART1) Interrupt Source Identity Register"
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bitfld.long 0x2C 0.--2. "INTSRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: UART1 INT" "0: UART1 INT,?,?,?,?,?,?,?"
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line.long 0x30 "IRQ12_SRC,IRQ12 (UART0) Interrupt Source Identity Register"
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bitfld.long 0x30 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: UART0_INT" "0: UART0_INT,?,?,?,?,?,?,?"
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line.long 0x34 "IRQ13_SRC,IRQ13 (SPI1) Interrupt Source Identity Register"
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bitfld.long 0x34 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: SPI1 INT" "0: SPI1 INT,?,?,?,?,?,?,?"
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line.long 0x38 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity Register"
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bitfld.long 0x38 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: SPI0_INT" "0: SPI0_INT,?,?,?,?,?,?,?"
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line.long 0x3C "IRQ15_SRC,IRQ15 (DPWM) Interrupt Source Identity Register"
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bitfld.long 0x3C 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: . Bit0: DPWM INT" "0: DPWM INT,?,?,?,?,?,?,?"
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line.long 0x40 "IRQ16_SRC,IRQ16 (Reserved) Interrupt Source Identity Register"
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line.long 0x44 "IRQ17_SRC,IRQ17 (Reserved) Interrupt Source Identity Register"
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line.long 0x48 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity Register"
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bitfld.long 0x48 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: I2C0_INT" "0: I2C0_INT,?,?,?,?,?,?,?"
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line.long 0x4C "IRQ19_SRC,IRQ19 (Reserved) Interrupt Source Identity Register"
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line.long 0x50 "IRQ20_SRC,IRQ20 (Reserved) Interrupt Source Identity Register"
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line.long 0x54 "IRQ21_SRC,IRQ21 (CMP) Interrupt Source Identity Register"
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bitfld.long 0x54 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: CMP INT" "0: CMP INT,?,?,?,?,?,?,?"
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line.long 0x58 "IRQ22_SRC,IRQ22 (MAC ) Interrupt Source Identity Register"
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bitfld.long 0x58 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: MAC INT" "0: MAC INT,?,?,?,?,?,?,?"
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line.long 0x5C "IRQ23_SRC,IRQ23 (Reserved) Interrupt Source Identity Register"
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line.long 0x60 "IRQ24_SRC,IRQ24 (Reserved) Interrupt Source Identity Register"
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line.long 0x64 "IRQ25_SRC,IRQ25 (SARADC) Interrupt Source Identity Register"
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bitfld.long 0x64 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: SARADC INT" "0: SARADC INT,?,?,?,?,?,?,?"
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line.long 0x68 "IRQ26_SRC,IRQ26 (PDMA) Interrupt Source Identity Register"
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bitfld.long 0x68 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: PDMA_INT" "0: PDMA_INT,?,?,?,?,?,?,?"
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line.long 0x6C "IRQ27_SRC,IRQ27 (I2S0) Interrupt Source Identity Register"
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bitfld.long 0x6C 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: I2S_INT" "0: I2S_INT,?,?,?,?,?,?,?"
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line.long 0x70 "IRQ28_SRC,IRQ28 (CAPS) Interrupt Source Identity Register"
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bitfld.long 0x70 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: CAPS_INT" "0: CAPS_INT,?,?,?,?,?,?,?"
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line.long 0x74 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity Register"
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bitfld.long 0x74 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: ADC_INT" "0: ADC_INT,?,?,?,?,?,?,?"
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line.long 0x78 "IRQ30_SRC,IRQ30 (Reserved) Interrupt Source Identity Register"
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line.long 0x7C "IRQ31_SRC,IRQ31 (RTC) Interrupt Source Identity Register"
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bitfld.long 0x7C 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: RTC_INT" "0: RTC_INT,?,?,?,?,?,?,?"
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group.long 0x80++0x7
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line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register"
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bitfld.long 0x0 7. "IRQ_TM,IRQ Test Mode. If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the MCU_IRQ register. This is a protected register to program first issue the unlock sequence." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Source Interrupt Select. The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]. The NMI_SEL bit[4:0] used to select the NMI interrupt source"
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line.long 0x4 "MCU_IRQ,MCU IRQ Number Identify Register"
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bitfld.long 0x4 31. "RTC,IRQ31 (RTC) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 29. "ADC,IRQ29 (ADC) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 28. "CAPS,IRQ28 (CAPS) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 27. "I2S0,IRQ27 (I2S0) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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newline
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bitfld.long 0x4 26. "PDMA,IRQ26 (PDMA) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 25. "SARADC,IRQ25 (SARADC) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 22. "MAC,IRQ22 (MAC ) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 21. "CMP,IRQ21 (CMP) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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newline
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bitfld.long 0x4 18. "I2C0,IRQ18 (I2C0) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 15. "DPWM,IRQ15 (DPWM) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 14. "SPI0,IRQ14 (SPI0) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 13. "SPI1,IRQ13 (SPI1) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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newline
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bitfld.long 0x4 12. "UART0,IRQ12 (UART0) Interrupt Source Identity Register . 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 11. "UART1,IRQ11 (UART1) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 9. "TMR1,RQ9 (TMR1) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 8. "TMR0,IRQ8 (TMR0) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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newline
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bitfld.long 0x4 6. "PWM0,IRQ6 (PWM0) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 5. "ALC,IRQ5 (ALC) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 4. "GPAB,IRQ4 (GPA/B) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 3. "EINT1,IRQ3 (EINT1) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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newline
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bitfld.long 0x4 2. "EINT0,IRQ2 (EINT0) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 1. "WDT,IRQ1 (WDT) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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bitfld.long 0x4 0. "BOD,IRQ0 (BOD) Interrupt Source Identity Register. 0: No effect.. 1: clear the interrupt" "0: No effect,1: clear the interrupt"
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tree.end
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tree "PDMA (Peripheral Direct Memory Access)"
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base ad:0x0
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tree "PDMA0"
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base ad:0x50008000
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group.long 0x0++0xF
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line.long 0x0 "PDMA_CTLn,PDMA Control Register of Channel n"
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bitfld.long 0x0 23. "TXEN,Trigger Enable - Start a PDMA Operation. Note: When PDMA transfer completed this bit will be cleared automatically.. If a bus error occurs all PDMA transfer will be stopped. Software must reset PDMA channel and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
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bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation.. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select . x1x1: Both half and w interrupts generated."
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bitfld.long 0x0 6.--7. "DASEL,Destination Address Select. This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the.." "0: Transfer Destination Address is incremented,1: Reserved,?,?"
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newline
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bitfld.long 0x0 4.--5. "SASEL,Source Address Select. This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the active.." "0: Transfer Source address is incremented,1: Reserved,?,?"
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bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select. This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
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newline
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bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
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bitfld.long 0x0 0. "CHEN,PDMA Channel Enable. Setting this bit to 1 enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.. Note: SWRST will clear this bit." "0,1"
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line.long 0x4 "PDMA_SADDRn,PDMA Transfer Source Address Register of Channel n"
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hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Transfer Source Address Register. This register holds the initial Source Address of PDMA transfer. . Note: The source address must be word aligned."
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line.long 0x8 "PDMA_DADDRn,PDMA Transfer Destination Address Register of Channel n"
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hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Transfer Destination Address Register. This register holds the initial Destination Address of PDMA transfer. . Note: The destination address must be word aligned."
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|
line.long 0xC "PDMA_TXCNTn,PDMA Transfer Byte Count Register of Channel n"
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hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Transfer Byte Count Register. This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.."
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rgroup.long 0x10++0xF
|
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line.long 0x0 "PDMA_INTPNTn,PDMA Internal Buffer Pointer Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--3. 1. "POINTER,PDMA Internal Buffer Pointer Register (Read Only). A PDMA transaction consists of two stages a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width.."
|
|
line.long 0x4 "PDMA_CURSADDRn,PDMA Current Source Address Register of Channel n"
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|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Current Source Address Register (Read Only). This register returns the source address from which the PDMA transfer is occurring.. This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0x8 "PDMA_CURDADDRn,PDMA Current Destination Address Register of Channel n"
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|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Current Destination Address Register (Read Only). This register returns the destination address to which the PDMA transfer is occurring. . This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs."
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|
line.long 0xC "PDMA_CURTXCNTn,PDMA Current Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Current Byte Count Register (Read Only). This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_INTENn,PDMA Interrupt Enable Control Register of Channel n"
|
|
bitfld.long 0x0 2. "WRAPIEN,Wraparound Interrupt Enable. If enabled and channel source or destination address is in wraparound mode the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of . PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
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|
bitfld.long 0x0 1. "TXIEN,PDMA Transfer Done Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
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|
newline
|
|
bitfld.long 0x0 0. "ABTIEN,PDMA Read/Write Target Abort Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
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|
line.long 0x4 "PDMA_INTSTSn,PDMA Interrupt Status Register of Channel n"
|
|
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only). This bit is the Interrupt pin status of PDMA channel." "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "WRAPIF,Wrap Around Transfer Byte Count Interrupt Flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.."
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|
newline
|
|
bitfld.long 0x4 1. "TXIF,Block Transfer Done Interrupt Flag. This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
|
|
bitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag. This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller.." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PDMA_SPANn,PDMA Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Span Increment Register. This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned then this number is added to the address register each transfer. The size of the.."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PDMA_CURSPANn,PDMA Current Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Current Span Increment Register. This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode."
|
|
tree.end
|
|
tree "PDMA1"
|
|
base ad:0x50008100
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CTLn,PDMA Control Register of Channel n"
|
|
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start a PDMA Operation. Note: When PDMA transfer completed this bit will be cleared automatically.. If a bus error occurs all PDMA transfer will be stopped. Software must reset PDMA channel and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
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|
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation.. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
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|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select . x1x1: Both half and w interrupts generated."
|
|
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select. This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the.." "0: Transfer Destination Address is incremented,1: Reserved,?,?"
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|
newline
|
|
bitfld.long 0x0 4.--5. "SASEL,Source Address Select. This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the active.." "0: Transfer Source address is incremented,1: Reserved,?,?"
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|
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select. This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
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|
newline
|
|
bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
|
|
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable. Setting this bit to 1 enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.. Note: SWRST will clear this bit." "0,1"
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|
line.long 0x4 "PDMA_SADDRn,PDMA Transfer Source Address Register of Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Transfer Source Address Register. This register holds the initial Source Address of PDMA transfer. . Note: The source address must be word aligned."
|
|
line.long 0x8 "PDMA_DADDRn,PDMA Transfer Destination Address Register of Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Transfer Destination Address Register. This register holds the initial Destination Address of PDMA transfer. . Note: The destination address must be word aligned."
|
|
line.long 0xC "PDMA_TXCNTn,PDMA Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Transfer Byte Count Register. This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_INTPNTn,PDMA Internal Buffer Pointer Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--3. 1. "POINTER,PDMA Internal Buffer Pointer Register (Read Only). A PDMA transaction consists of two stages a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width.."
|
|
line.long 0x4 "PDMA_CURSADDRn,PDMA Current Source Address Register of Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Current Source Address Register (Read Only). This register returns the source address from which the PDMA transfer is occurring.. This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0x8 "PDMA_CURDADDRn,PDMA Current Destination Address Register of Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Current Destination Address Register (Read Only). This register returns the destination address to which the PDMA transfer is occurring. . This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0xC "PDMA_CURTXCNTn,PDMA Current Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Current Byte Count Register (Read Only). This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_INTENn,PDMA Interrupt Enable Control Register of Channel n"
|
|
bitfld.long 0x0 2. "WRAPIEN,Wraparound Interrupt Enable. If enabled and channel source or destination address is in wraparound mode the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of . PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
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|
bitfld.long 0x0 1. "TXIEN,PDMA Transfer Done Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
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|
newline
|
|
bitfld.long 0x0 0. "ABTIEN,PDMA Read/Write Target Abort Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
|
|
line.long 0x4 "PDMA_INTSTSn,PDMA Interrupt Status Register of Channel n"
|
|
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only). This bit is the Interrupt pin status of PDMA channel." "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "WRAPIF,Wrap Around Transfer Byte Count Interrupt Flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.."
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|
newline
|
|
bitfld.long 0x4 1. "TXIF,Block Transfer Done Interrupt Flag. This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
|
|
bitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag. This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller.." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PDMA_SPANn,PDMA Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Span Increment Register. This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned then this number is added to the address register each transfer. The size of the.."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PDMA_CURSPANn,PDMA Current Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Current Span Increment Register. This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode."
|
|
tree.end
|
|
tree "PDMA2"
|
|
base ad:0x50008200
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CTLn,PDMA Control Register of Channel n"
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|
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start a PDMA Operation. Note: When PDMA transfer completed this bit will be cleared automatically.. If a bus error occurs all PDMA transfer will be stopped. Software must reset PDMA channel and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
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|
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation.. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select . x1x1: Both half and w interrupts generated."
|
|
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select. This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the.." "0: Transfer Destination Address is incremented,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "SASEL,Source Address Select. This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the active.." "0: Transfer Source address is incremented,1: Reserved,?,?"
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|
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select. This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
|
|
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable. Setting this bit to 1 enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.. Note: SWRST will clear this bit." "0,1"
|
|
line.long 0x4 "PDMA_SADDRn,PDMA Transfer Source Address Register of Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Transfer Source Address Register. This register holds the initial Source Address of PDMA transfer. . Note: The source address must be word aligned."
|
|
line.long 0x8 "PDMA_DADDRn,PDMA Transfer Destination Address Register of Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Transfer Destination Address Register. This register holds the initial Destination Address of PDMA transfer. . Note: The destination address must be word aligned."
|
|
line.long 0xC "PDMA_TXCNTn,PDMA Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Transfer Byte Count Register. This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_INTPNTn,PDMA Internal Buffer Pointer Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--3. 1. "POINTER,PDMA Internal Buffer Pointer Register (Read Only). A PDMA transaction consists of two stages a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width.."
|
|
line.long 0x4 "PDMA_CURSADDRn,PDMA Current Source Address Register of Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Current Source Address Register (Read Only). This register returns the source address from which the PDMA transfer is occurring.. This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0x8 "PDMA_CURDADDRn,PDMA Current Destination Address Register of Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Current Destination Address Register (Read Only). This register returns the destination address to which the PDMA transfer is occurring. . This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0xC "PDMA_CURTXCNTn,PDMA Current Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Current Byte Count Register (Read Only). This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_INTENn,PDMA Interrupt Enable Control Register of Channel n"
|
|
bitfld.long 0x0 2. "WRAPIEN,Wraparound Interrupt Enable. If enabled and channel source or destination address is in wraparound mode the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of . PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
|
|
bitfld.long 0x0 1. "TXIEN,PDMA Transfer Done Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
|
|
newline
|
|
bitfld.long 0x0 0. "ABTIEN,PDMA Read/Write Target Abort Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
|
|
line.long 0x4 "PDMA_INTSTSn,PDMA Interrupt Status Register of Channel n"
|
|
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only). This bit is the Interrupt pin status of PDMA channel." "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "WRAPIF,Wrap Around Transfer Byte Count Interrupt Flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.."
|
|
newline
|
|
bitfld.long 0x4 1. "TXIF,Block Transfer Done Interrupt Flag. This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
|
|
bitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag. This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller.." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PDMA_SPANn,PDMA Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Span Increment Register. This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned then this number is added to the address register each transfer. The size of the.."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PDMA_CURSPANn,PDMA Current Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Current Span Increment Register. This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode."
|
|
tree.end
|
|
tree "PDMA3"
|
|
base ad:0x50008300
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PDMA_CTLn,PDMA Control Register of Channel n"
|
|
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start a PDMA Operation. Note: When PDMA transfer completed this bit will be cleared automatically.. If a bus error occurs all PDMA transfer will be stopped. Software must reset PDMA channel and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
|
|
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation.. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select . x1x1: Both half and w interrupts generated."
|
|
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select. This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the.." "0: Transfer Destination Address is incremented,1: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "SASEL,Source Address Select. This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed incremented or wrapped.. When PDMA_CTLn.CHEN is disabled the PDMA will complete the active.." "0: Transfer Source address is incremented,1: Reserved,?,?"
|
|
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select. This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
|
|
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable. Setting this bit to 1 enables PDMA's operation. If this bit is cleared PDMA will ignore all PDMA request and force Bus Master into IDLE state.. Note: SWRST will clear this bit." "0,1"
|
|
line.long 0x4 "PDMA_SADDRn,PDMA Transfer Source Address Register of Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Transfer Source Address Register. This register holds the initial Source Address of PDMA transfer. . Note: The source address must be word aligned."
|
|
line.long 0x8 "PDMA_DADDRn,PDMA Transfer Destination Address Register of Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Transfer Destination Address Register. This register holds the initial Destination Address of PDMA transfer. . Note: The destination address must be word aligned."
|
|
line.long 0xC "PDMA_TXCNTn,PDMA Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Transfer Byte Count Register. This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.."
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "PDMA_INTPNTn,PDMA Internal Buffer Pointer Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--3. 1. "POINTER,PDMA Internal Buffer Pointer Register (Read Only). A PDMA transaction consists of two stages a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width.."
|
|
line.long 0x4 "PDMA_CURSADDRn,PDMA Current Source Address Register of Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,PDMA Current Source Address Register (Read Only). This register returns the source address from which the PDMA transfer is occurring.. This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0x8 "PDMA_CURDADDRn,PDMA Current Destination Address Register of Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,PDMA Current Destination Address Register (Read Only). This register returns the destination address to which the PDMA transfer is occurring. . This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs."
|
|
line.long 0xC "PDMA_CURTXCNTn,PDMA Current Transfer Byte Count Register of Channel n"
|
|
hexmask.long.word 0xC 0.--15. 1. "CNT,PDMA Current Byte Count Register (Read Only). This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "PDMA_INTENn,PDMA Interrupt Enable Control Register of Channel n"
|
|
bitfld.long 0x0 2. "WRAPIEN,Wraparound Interrupt Enable. If enabled and channel source or destination address is in wraparound mode the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of . PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
|
|
bitfld.long 0x0 1. "TXIEN,PDMA Transfer Done Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
|
|
newline
|
|
bitfld.long 0x0 0. "ABTIEN,PDMA Read/Write Target Abort Interrupt Enable. If enabled the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
|
|
line.long 0x4 "PDMA_INTSTSn,PDMA Interrupt Status Register of Channel n"
|
|
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only). This bit is the Interrupt pin status of PDMA channel." "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "WRAPIF,Wrap Around Transfer Byte Count Interrupt Flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.."
|
|
newline
|
|
bitfld.long 0x4 1. "TXIF,Block Transfer Done Interrupt Flag. This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
|
|
bitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag. This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller.." "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PDMA_SPANn,PDMA Span Increment Register of Channel n"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Span Increment Register. This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned then this number is added to the address register each transfer. The size of the.."
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group.long 0x38++0x3
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|
line.long 0x0 "PDMA_CURSPANn,PDMA Current Span Increment Register of Channel n"
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|
hexmask.long.byte 0x0 0.--7. 1. "SPAN,Current Span Increment Register. This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode."
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tree.end
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tree "PDMA_GCR"
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|
base ad:0x50008F00
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|
group.long 0x0++0xB
|
|
line.long 0x0 "PDMA_GCTL,PDMA Global Control Register"
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|
bitfld.long 0x0 11. "CH3CKEN,PDMA Controller Channel 3 Clock Enable Control. 1: Enable Channel 3 clock.. 0: Disable Channel 3 clock." "0: Disable Channel 3 clock,1: Enable Channel 3 clock"
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bitfld.long 0x0 10. "CH2CKEN,PDMA Controller Channel 2 Clock Enable Control. 1: Enable Channel 2 clock.. 0: Disable Channel 2 clock." "0: Disable Channel 2 clock,1: Enable Channel 2 clock"
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newline
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bitfld.long 0x0 9. "CH1CKEN,PDMA Controller Channel 1 Clock Enable Control. 1: Enable Channel 1 clock.. 0: Disable Channel 1 clock." "0: Disable Channel 1 clock,1: Enable Channel 1 clock"
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bitfld.long 0x0 8. "CH0CKEN,PDMA Controller Channel 0 Clock Enable Control. 1: Enable Channel 0 clock.. 0: Disable Channel 0 clock." "0: Disable Channel 0 clock,1: Enable Channel 0 clock"
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newline
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bitfld.long 0x0 0. "SWRST,PDMA Software Reset. Note: This bit can reset all channels (global reset)." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
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line.long 0x4 "PDMA_SVCSEL0,PDMA Service Selection Control Register 0"
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hexmask.long.byte 0x4 28.--31. 1. "I2STXSEL,PDMA I2S Transmit Selection. This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request."
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hexmask.long.byte 0x4 24.--27. 1. "I2SRXSEL,PDMA I2S Receive Selection. This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request."
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newline
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hexmask.long.byte 0x4 20.--23. 1. "UART0XSEL,PDMA UART0 Transmit Selection. This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request."
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hexmask.long.byte 0x4 16.--19. 1. "UART0RXSEL,PDMA UART0 Receive Selection. This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request."
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newline
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hexmask.long.byte 0x4 12.--15. 1. "DPWMTXSEL,PDMA DPWM Transmit Selection. This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request."
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hexmask.long.byte 0x4 8.--11. 1. "SDADCRXSEL,PDMA SDADC Receive Selection. This field defines which PDMA channel is connected to SDADC peripheral receive (PDMA source) request."
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newline
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hexmask.long.byte 0x4 4.--7. 1. "SPI0TXSEL,PDMA SPI0 Transmit Selection. This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request."
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hexmask.long.byte 0x4 0.--3. 1. "SPI0RXSEL,PDMA SPI0 Receive Selection. This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request."
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line.long 0x8 "PDMA_SVCSEL1,PDMA Service Selection Control Register 1"
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hexmask.long.byte 0x8 16.--19. 1. "SARADCRXSEL,PDMA SARADC Receive Selection. This field defines which PDMA channel is connected to SARADC peripheral receive (PDMA source) request."
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hexmask.long.byte 0x8 12.--15. 1. "SPI1TXSEL,PDMA SPI1 Transmit Selection. This field defines which PDMA channel is connected to SPI1 peripheral transmit (PDMA destination) request."
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newline
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hexmask.long.byte 0x8 8.--11. 1. "SPI1RXSEL,PDMA SPI1 Receive Selection. This field defines which PDMA channel is connected to SPI1 peripheral receive (PDMA source) request."
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hexmask.long.byte 0x8 4.--7. 1. "UART1XSEL,PDMA UART1 Transmit Selection. This field defines which PDMA channel is connected to UART1 peripheral transmit (PDMA destination) request."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "UART1RXSEL,PDMA UART1 Receive Selection. This field defines which PDMA channel is connected to UART1 peripheral receive (PDMA source) request."
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rgroup.long 0xC++0x3
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line.long 0x0 "PDMA_GINTSTS,PDMA Global Interrupt Status Register"
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bitfld.long 0x0 3. "CH3INTSTS,Interrupt Pin Status of Channel 3 (Read Only). This bit is the interrupt pin status of PDMA channel 3." "0,1"
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bitfld.long 0x0 2. "CH2INTSTS,Interrupt Pin Status of Channel 2 (Read Only). This bit is the interrupt pin status of PDMA channel 2." "0,1"
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newline
|
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bitfld.long 0x0 1. "CH1INTSTS,Interrupt Pin Status of Channel 1 (Read Only). This bit is the interrupt pin status of PDMA channel 1." "0,1"
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bitfld.long 0x0 0. "CH0INTSTS,Interrupt Pin Status of Channel 0 (Read Only). This bit is the interrupt pin status of PDMA channel 0." "0,1"
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tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulator)"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x13
|
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line.long 0x0 "PWM_CLKPSC,PWM Prescaler Register"
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hexmask.long.byte 0x0 24.--31. 1. "DTCNT23,Dead Zone Interval Register for Pair of PWM0CH2 and PWM0CH3. These 8 bits determine dead zone length.. The unit time of dead zone length is that from clock selector 0."
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hexmask.long.byte 0x0 16.--23. 1. "DTCNT01,Dead Zone Interval Register for Pair of PWM0CH0 and PWM0CH1. These 8 bits determine dead zone length.. The unit time of dead zone length is that from clock selector 0."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CLKPSC23,Clock Pre-scaler for Pair of PWM0CH2 and PWM0CH3. Clock input is divided by (CLKPSC23 + 1) . This implies PWM counter 2 and 3 will also be stopped."
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hexmask.long.byte 0x0 0.--7. 1. "CLKPSC01,Clock Pre-scaler Pair of PWM0CH0 and PWM0CH1. Clock input is divided by (CLKPSC01 + 1) . This implies PWM counter 0 and 1 will also be stopped."
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line.long 0x4 "PWM_CLKDIV,PWM Clock Select Register"
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bitfld.long 0x4 12.--14. "CLKDIV3,Timer 3 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 8.--10. "CLKDIV2,Timer 2 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 4.--6. "CLKDIV1,Timer 1 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "CLKDIV0,Timer 0 Clock Source Selection. Value : Input clock divided by. 0 : 2. 1 : 4. 2 : 8. 3 :.." "0,1,2,3,4,5,6,7"
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line.long 0x8 "PWM_CTL,PWM Control Register"
|
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bitfld.long 0x8 27. "CNTMODE3,PWM-timer 3 Auto-reload/One-shot Mode. Note: A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
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bitfld.long 0x8 26. "PINV3,PWM-timer 3 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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newline
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bitfld.long 0x8 24. "CNTEN3,PWM-timer 3 Enable/Disable Start Run." "0: Stop PWM-Timer 3,1: Enable PWM-Timer 3 Start/Run"
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bitfld.long 0x8 19. "CNTMODE2,PWM-timer 2 Auto-reload/One-shot Mode. Note: A rising transition of this bit will cause PWM_PERIOD2 and PWM_CMPDAT2 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
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newline
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bitfld.long 0x8 18. "PINV2,PWM-timer 2 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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|
bitfld.long 0x8 16. "CNTEN2,PWM-timer 2 Enable/Disable Start Run." "0: Stop PWM-Timer 2,1: Enable PWM-Timer 2 Start/Run"
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|
newline
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bitfld.long 0x8 11. "CNTMODE1,PWM-timer 1 Auto-reload/One-shot Mode. Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
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|
bitfld.long 0x8 10. "PINV1,PWM-timer 1 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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newline
|
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bitfld.long 0x8 8. "CNTEN1,PWM-timer 1 Enable/Disable Start Run." "0: Stop PWM-Timer 1,1: Enable PWM-Timer 1 Start/Run"
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bitfld.long 0x8 5. "DTEN23,Dead-zone 23 Generator Enable/Disable Pair of PWM0CH2 and PWM0CH3. Note: When Dead-Zone Generator is enabled the pair of PWM0CH2 and PWM0CH3 become a complementary pair." "0: Disable,1: Enable"
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newline
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bitfld.long 0x8 4. "DTEN01,Dead-zone 01 Generator Enable/Disable Pair of PWM0CH0 and PWM0CH1. Note: When Dead-Zone Generator is enabled the pair of PWM0CH0 and PWM0CH1 become a complementary pair." "0: Disable,1: Enable"
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bitfld.long 0x8 3. "CNTMODE0,PWM-timer 0 Auto-reload/One-shot Mode. Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared." "0: One-Shot Mode,1: Auto-reload Mode"
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newline
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bitfld.long 0x8 2. "PINV0,PWM-timer 0 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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|
bitfld.long 0x8 0. "CNTEN0,PWM-timer 0 Enable/Disable Start Run." "0: Stop PWM-Timer 0 Running,1: Enable PWM-Timer 0 Start/Run"
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|
line.long 0xC "PWM_PERIOD0,PWM Counter Register 0"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value. PERIOD determines the PWM period.. Note: . Any write to PERIOD will take effect in next PWM cycle."
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line.long 0x10 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty cycle.. Note: Any write to CMP will take effect in next PWM cycle."
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rgroup.long 0x14++0x3
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line.long 0x0 "PWM_CNT0,PWM Data Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register. Reports the current value of the 16-bit down counter."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "PWM_PERIOD1,PWM Counter Register 1"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value. PERIOD determines the PWM period.. Note: . Any write to PERIOD will take effect in next PWM cycle."
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line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty cycle.. Note: Any write to CMP will take effect in next PWM cycle."
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|
rgroup.long 0x20++0x3
|
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line.long 0x0 "PWM_CNT1,PWM Data Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register. Reports the current value of the 16-bit down counter."
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "PWM_PERIOD2,PWM Counter Register 2"
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|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value. PERIOD determines the PWM period.. Note: . Any write to PERIOD will take effect in next PWM cycle."
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line.long 0x4 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty cycle.. Note: Any write to CMP will take effect in next PWM cycle."
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "PWM_CNT2,PWM Data Register 2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register. Reports the current value of the 16-bit down counter."
|
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group.long 0x30++0x7
|
|
line.long 0x0 "PWM_PERIOD3,PWM Counter Register 3"
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|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value. PERIOD determines the PWM period.. Note: . Any write to PERIOD will take effect in next PWM cycle."
|
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line.long 0x4 "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty cycle.. Note: Any write to CMP will take effect in next PWM cycle."
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "PWM_CNT3,PWM Data Register 3"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register. Reports the current value of the 16-bit down counter."
|
|
group.long 0x40++0x7
|
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line.long 0x0 "PWM_INTEN,PWM Interrupt Enable Register"
|
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bitfld.long 0x0 3. "PIEN3,PWM Timer 3 Interrupt Enable." "0: Disable,1: Enable"
|
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bitfld.long 0x0 2. "PIEN2,PWM Timer 2 Interrupt Enable." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x0 1. "PIEN1,PWM Timer 1 Interrupt Enable." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "PIEN0,PWM Timer 0 Interrupt Enable." "0: Disable,1: Enable"
|
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line.long 0x4 "PWM_INTSTS,PWM Interrupt Flag Register"
|
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bitfld.long 0x4 3. "PIF3,PWM Timer 3 Interrupt Flag. Flag is set by hardware when PWM0CH3 down counter reaches zero software can clear this bit by writing '1' to it." "0,1"
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bitfld.long 0x4 2. "PIF2,PWM Timer 2 Interrupt Flag. Flag is set by hardware when PWM0CH2 down counter reaches zero software can clear this bit by writing '1' to it." "0,1"
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newline
|
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bitfld.long 0x4 1. "PIF1,PWM Timer 1 Interrupt Flag. Flag is set by hardware when PWM0CH1 down counter reaches zero software can clear this bit by writing '1' to it." "0,1"
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|
bitfld.long 0x4 0. "PIF0,PWM Timer 0 Interrupt Flag. Flag is set by hardware when PWM0CH0 down counter reaches zero software can clear this bit by writing '1' to it." "0,1"
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|
group.long 0x50++0x7
|
|
line.long 0x0 "PWM_CAPCTL01,Capture Control Register for Pair of PWM0CH0 and PWM0CH1"
|
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bitfld.long 0x0 23. "CFLIF1,PWM_FCAPDAT1 Latched Indicator Bit. When input channel 1 has a falling transition PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x0 22. "CRLIF1,PWM_RCAPDAT1 Latched Indicator Bit. When input channel 1 has a rising transition PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
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|
newline
|
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bitfld.long 0x0 20. "CAPIF1,Capture1 Interrupt Indication Flag." "0,1"
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|
bitfld.long 0x0 19. "CAPEN1,Capture Channel 1 Transition Enable/Disable. When enabled Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.. When disabled Capture function is inactive as is.." "0: Disable capture function on channel 1,1: Enable capture function on channel 1"
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newline
|
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bitfld.long 0x0 18. "CFLIEN1,Channel 1 Falling Latch Interrupt Enable . When enabled capture block generates an interrupt on falling edge of input." "0: Disable falling edge latch interrupt,1: Enable falling edge latch interrupt"
|
|
bitfld.long 0x0 17. "CRLIEN1,Channel 1 Rising Latch Interrupt Enable . When enabled capture block generates an interrupt on rising edge of input." "0: Disable rising edge latch interrupt,1: Enable rising edge latch interrupt"
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newline
|
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bitfld.long 0x0 16. "CAPINV1,Channel 1 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
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bitfld.long 0x0 7. "CFLIF0,PWM_FCAPDAT0 Latched Indicator Bit. When input channel 0 has a falling transition PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "CRLIF0,PWM_RCAPDAT0 Latched Indicator Bit. When input channel 0 has a rising transition PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
|
bitfld.long 0x0 4. "CAPIF0,Capture0 Interrupt Indication Flag." "0,1"
|
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newline
|
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bitfld.long 0x0 3. "CAPEN0,Capture Channel 0 Transition Enable/Disable. When enabled Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.. When disabled Capture function is inactive as is.." "0: Disable capture function on channel 0,1: Enable capture function on channel 0"
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bitfld.long 0x0 2. "CFLIEN0,Channel 0 Falling Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
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newline
|
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bitfld.long 0x0 1. "CRLIEN0,Channel 0 Rising Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
|
|
bitfld.long 0x0 0. "CAPINV0,Channel 0 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
|
|
line.long 0x4 "PWM_CAPCTL23,Capture Control Register for Pair of PWM0CH2 and PWM0CH3"
|
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bitfld.long 0x4 23. "CFLIF3,PWM_FCAPDAT3 Latched Indicator Bit. When input channel 3 has a falling transition PWM_FCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x4 22. "CRLIF3,PWM_RCAPDAT3 Latched Indicator Bit. When input channel 3 has a rising transition PWM_RCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
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newline
|
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bitfld.long 0x4 20. "CAPIF3,Capture3 Interrupt Indication Flag." "0,1"
|
|
bitfld.long 0x4 19. "CAPEN3,Capture Channel 3 Transition Enable/Disable. When enabled Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.. When disabled Capture function is inactive as is.." "0: Disable capture function on channel 1,1: Enable capture function on channel 1"
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|
newline
|
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bitfld.long 0x4 18. "CFLIEN3,Channel 3 Falling Latch Interrupt Enable . When enabled capture block generates an interrupt on falling edge of input." "0: Disable falling edge latch interrupt,1: Enable falling edge latch interrupt"
|
|
bitfld.long 0x4 17. "CRLIEN3,Channel 3 Rising Latch Interrupt Enable . When enabled capture block generates an interrupt on rising edge of input." "0: Disable rising edge latch interrupt,1: Enable rising edge latch interrupt"
|
|
newline
|
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bitfld.long 0x4 16. "CAPINV3,Channel 3 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
|
|
bitfld.long 0x4 7. "CFLIF2,PWM_FCAPDAT2 Latched Indicator Bit. When input channel 2 has a falling transition PWM_FCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "CRLIF2,PWM_RCAPDAT2 Latched Indicator Bit. When input channel 2 has a rising transition PWM_RCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
|
bitfld.long 0x4 4. "CAPIF2,Capture2 Interrupt Indication Flag." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CAPEN2,Capture Channel 2 Transition Enable/Disable. When enabled Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.. When disabled Capture function is inactive as is.." "0: Disable capture function on channel 0,1: Enable capture function on channel 0"
|
|
bitfld.long 0x4 2. "CFLIEN2,Channel 2 Falling Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
|
|
newline
|
|
bitfld.long 0x4 1. "CRLIEN2,Channel 2 Rising Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
|
|
bitfld.long 0x4 0. "CAPINV2,Channel 2 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
|
|
rgroup.long 0x58++0x1F
|
|
line.long 0x0 "PWM_RCAPDAT0,Capture Rising Latch Register (Channel 0)"
|
|
hexmask.long.word 0x0 0.--15. 1. "RCAPDAT,Capture Rising Latch Register. In Capture mode this register is latched with the value of the PWM counter on a rising edge of the input signal."
|
|
line.long 0x4 "PWM_FCAPDAT0,Capture Falling Latch Register (Channel 0)"
|
|
hexmask.long.word 0x4 0.--15. 1. "FCAPDAT,Capture Falling Latch Register. In Capture mode this register is latched with the value of the PWM counter on a falling edge of the input signal."
|
|
line.long 0x8 "PWM_RCAPDAT1,Capture Rising Latch Register (Channel 1)"
|
|
hexmask.long.word 0x8 0.--15. 1. "RCAPDAT,Capture Rising Latch Register. In Capture mode this register is latched with the value of the PWM counter on a rising edge of the input signal."
|
|
line.long 0xC "PWM_FCAPDAT1,Capture Falling Latch Register (Channel 1)"
|
|
hexmask.long.word 0xC 0.--15. 1. "FCAPDAT,Capture Falling Latch Register. In Capture mode this register is latched with the value of the PWM counter on a falling edge of the input signal."
|
|
line.long 0x10 "PWM_RCAPDAT2,Capture Rising Latch Register (Channel 2)"
|
|
hexmask.long.word 0x10 0.--15. 1. "RCAPDAT,Capture Rising Latch Register. In Capture mode this register is latched with the value of the PWM counter on a rising edge of the input signal."
|
|
line.long 0x14 "PWM_FCAPDAT2,Capture Falling Latch Register (Channel 2)"
|
|
hexmask.long.word 0x14 0.--15. 1. "FCAPDAT,Capture Falling Latch Register. In Capture mode this register is latched with the value of the PWM counter on a falling edge of the input signal."
|
|
line.long 0x18 "PWM_RCAPDAT3,Capture Rising Latch Register (Channel 3)"
|
|
hexmask.long.word 0x18 0.--15. 1. "RCAPDAT,Capture Rising Latch Register. In Capture mode this register is latched with the value of the PWM counter on a rising edge of the input signal."
|
|
line.long 0x1C "PWM_FCAPDAT3,Capture Falling Latch Register (Channel 3)"
|
|
hexmask.long.word 0x1C 0.--15. 1. "FCAPDAT,Capture Falling Latch Register. In Capture mode this register is latched with the value of the PWM counter on a falling edge of the input signal."
|
|
group.long 0x78++0x7
|
|
line.long 0x0 "PWM_CAPINEN,Capture Input Enable Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CAPINEN,Capture Input Enable Register. 0 : OFF (GPA[13:12] GPB[15:14] pin input disconnected from Capture block). 1 : ON (GPA[13:12] GPB[15:14] pin if in PWM alternative function will be configured as an input and fed to capture function)."
|
|
line.long 0x4 "PWM_POEN,PWM0 Output Enable Register for CH0~CH3"
|
|
bitfld.long 0x4 3. "POEN3,PWM0CH3 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)" "0: Disable PWM0CH3 output to pin,1: Enable PWM0CH3 output to pin"
|
|
bitfld.long 0x4 2. "POEN2,PWM0CH2 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)" "0: Disable PWM0CH2 output to pin,1: Enable PWM0CH2 output to pin"
|
|
newline
|
|
bitfld.long 0x4 1. "POEN1,PWM0CH1 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)" "0: Disable PWM0CH1 output to pin,1: Enable PWM0CH1 output to pin"
|
|
bitfld.long 0x4 0. "POEN0,PWM0CH0 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)" "0: Disable PWM0CH0 output to pin,1: Enable PWM0CH 0 output to pin"
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "RTC_INIT,RTC Initialization Register"
|
|
hexmask.long 0x0 1.--31. 1. "INIT,RTC Initialization. After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIT. This will force a hardware reset then release all logic and counters."
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|
rbitfld.long 0x0 0. "ATVSTS,RTC Active Status (Read Only). 0: RTC is in reset state. 1: RTC is in normal active state." "0: RTC is in reset state,1: RTC is in normal active state"
|
|
line.long 0x4 "RTC_RWEN,RTC Access Enable Register"
|
|
rbitfld.long 0x4 16. "RWENF,RTC Register Access Enable Flag (Read Only). RTC_INIT : R/W : R/W. RTC_FREQADJ : R/W : -. RTC_TIME : R/W : R. RTC_CAL.." "0: RTC register read/write disable,1: RTC register read/write enable"
|
|
hexmask.long.word 0x4 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only)."
|
|
line.long 0x8 "RTC_FREQADJ,RTC Frequency Compensation Register"
|
|
hexmask.long.byte 0x8 8.--11. 1. "INTEGER,Integer Part. Register should contain the value (INT(Factual) - 32761). The range between 32761 and 32776"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FRACTION,Fractional Part. Refer to Table 576 RTC Frequency Compensation Example for the examples."
|
|
line.long 0xC "RTC_TIME,Time Load Register"
|
|
bitfld.long 0xC 20.--21. "TENHR,10 Hour Time Digit (0~3)" "0,1,2,3"
|
|
hexmask.long.byte 0xC 16.--19. 1. "HR,1 Hour Time Digit (0~9)"
|
|
bitfld.long 0xC 12.--14. "TENMIN,10 Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 8.--11. 1. "MIN,1 Min Time Digit (0~9)"
|
|
newline
|
|
bitfld.long 0xC 4.--6. "TENSEC,10 Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEC,1 Sec Time Digit (0~9)"
|
|
line.long 0x10 "RTC_CAL,Calendar Load Register"
|
|
hexmask.long.byte 0x10 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)"
|
|
hexmask.long.byte 0x10 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)"
|
|
bitfld.long 0x10 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
|
|
hexmask.long.byte 0x10 8.--11. 1. "MON,1-Month Calendar Digit (0~9)"
|
|
newline
|
|
bitfld.long 0x10 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)"
|
|
line.long 0x14 "RTC_CLKFMT,Time Scale Selection Register"
|
|
bitfld.long 0x14 0. "_24HEN,24-hour / 12-hour Mode Selection. Determines whether RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode. . The range of 24-hour time scale is between 0 and 23.. 12-hour time scale:. 01(AM01) 02(AM02) 03(AM03) 04(AM04) 05(AM05) .." "0: select 12-hour time scale with AM and PM..,1: select 24-hour time scale"
|
|
line.long 0x18 "RTC_WEEKDAY,Day of the Week Register"
|
|
bitfld.long 0x18 0.--2. "WEEKDAY,Day of the Week Register . 0 (Sunday) 1 (Monday) 2 (Tuesday) 3 (Wednesday). 4 (Thursday) 5 (Friday) 6 (Saturday)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "RTC_TALM,Time Alarm Register"
|
|
bitfld.long 0x1C 20.--21. "TENHR,10 Hour Time Digit of Alarm Setting (0~3)2" "0,1,2,3"
|
|
hexmask.long.byte 0x1C 16.--19. 1. "HR,1 Hour Time Digit of Alarm Setting (0~9)"
|
|
bitfld.long 0x1C 12.--14. "TENMIN,10 Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "MIN,1 Min Time Digit of Alarm Setting (0~9)"
|
|
newline
|
|
bitfld.long 0x1C 4.--6. "TENSEC,10 Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "SEC,1 Sec Time Digit of Alarm Setting (0~9)"
|
|
line.long 0x20 "RTC_CALM,Calendar Alarm Register"
|
|
hexmask.long.byte 0x20 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)"
|
|
hexmask.long.byte 0x20 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)"
|
|
bitfld.long 0x20 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
hexmask.long.byte 0x20 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)"
|
|
newline
|
|
bitfld.long 0x20 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
|
|
hexmask.long.byte 0x20 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_LEAPYEAR,Leap Year Indicator Register"
|
|
bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication Register (Read Only)." "0: Current year is not a leap year,1: Current year is leap year"
|
|
group.long 0x28++0xB
|
|
line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "TICKIEN,Time-tick Interrupt and Wakeup-by-tick Enable." "0: RTC Time-Tick Interrupt is disabled,1: RTC Time-Tick Interrupt is enabled"
|
|
bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable." "0: RTC Alarm Interrupt is disabled,1: RTC Alarm Interrupt is enabled"
|
|
line.long 0x4 "RTC_INTSTS,RTC Interrupt Indicator Register"
|
|
bitfld.long 0x4 1. "TICKIF,RTC Time-tick Interrupt Flag." "0: Indicates no Time-Tick Interrupt condition,1: Indicates RTC Time-Tick Interrupt generated"
|
|
bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag." "0: Indicates no Alarm Interrupt condition,1: Indicates RTC Alarm Interrupt generated"
|
|
line.long 0x8 "RTC_TICK,RTC Time Tick Register"
|
|
bitfld.long 0x8 3. "TWKEN,RTC Timer Wakeup CPU Function Enable Bit. If TWKE is set before CPU is in power-down mode when a RTC Time-Tick or Alarm Match occurs CPU will wake up.." "0: Disable Wakeup CPU function,1: Enable the Wakeup function"
|
|
bitfld.long 0x8 0.--2. "TICKSEL,Time Tick Period Select. The RTC time tick period for Periodic Time-Tick Interrupt request.. Time Tick (second) : 1 / (2^TTR). Note: This register can be read back after the RTC is active." "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "SARADC (Successive Approximation Analog-to-Digital Converter)"
|
|
base ad:0x40060000
|
|
rgroup.long 0x0++0x2F
|
|
line.long 0x0 "SARADC_DAT0,SAR ADC Data Register 0"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
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|
|
bitfld.long 0x0 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
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|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x4 "SARADC_DAT1,SAR ADC Data Register 1"
|
|
bitfld.long 0x4 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
newline
|
|
bitfld.long 0x4 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
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|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x8 "SARADC_DAT2,SAR ADC Data Register 2"
|
|
bitfld.long 0x8 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
newline
|
|
bitfld.long 0x8 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
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|
newline
|
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hexmask.long.word 0x8 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0xC "SARADC_DAT3,SAR ADC Data Register 3"
|
|
bitfld.long 0xC 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
newline
|
|
bitfld.long 0xC 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
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|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x10 "SARADC_DAT4,SAR ADC Data Register 4"
|
|
bitfld.long 0x10 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
newline
|
|
bitfld.long 0x10 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
|
|
newline
|
|
hexmask.long.word 0x10 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x14 "SARADC_DAT5,SAR ADC Data Register 5"
|
|
bitfld.long 0x14 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
newline
|
|
bitfld.long 0x14 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
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|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x18 "SARADC_DAT6,SAR ADC Data Register 6"
|
|
bitfld.long 0x18 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
newline
|
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bitfld.long 0x18 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
|
|
newline
|
|
hexmask.long.word 0x18 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x1C "SARADC_DAT7,SAR ADC Data Register 7"
|
|
bitfld.long 0x1C 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
newline
|
|
bitfld.long 0x1C 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x20 "SARADC_DAT8,SAR ADC Data Register 8"
|
|
bitfld.long 0x20 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
newline
|
|
bitfld.long 0x20 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
|
|
newline
|
|
hexmask.long.word 0x20 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x24 "SARADC_DAT9,SAR ADC Data Register 9"
|
|
bitfld.long 0x24 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
newline
|
|
bitfld.long 0x24 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
|
|
newline
|
|
hexmask.long.word 0x24 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x28 "SARADC_DAT10,SAR ADC Data Register 10"
|
|
bitfld.long 0x28 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
newline
|
|
bitfld.long 0x28 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
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|
newline
|
|
hexmask.long.word 0x28 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
line.long 0x2C "SARADC_DAT11,SAR ADC Data Register 11"
|
|
bitfld.long 0x2C 17. "VALID,Valid Flag (Read Only). Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
newline
|
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bitfld.long 0x2C 16. "OV,Overrun Flag (Read Only). Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwritten"
|
|
newline
|
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hexmask.long.word 0x2C 0.--11. 1. "RESULT,A/D Conversion Result. This field contains conversion result of SARADC.. 12-bit SARADC conversion result with unsigned format."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SARADC_STATUS,SAR ADC Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "VALID,Data Valid Flag (Read Only). It is a mirror of VALID bit in DATx."
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "CHANNEL,Current Conversion Channel (Read Only)."
|
|
newline
|
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rbitfld.long 0x0 3. "BUSY,BUSY/IDLE (Read Only). This bit is mirror of as SWTRG bit in CTL." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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|
newline
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bitfld.long 0x0 2. "ADCMPF1,Compare Flag. When the selected channel A/D conversion result meets setting condition in SARADC_CMP1 then this bit is set to 1. And it is cleared by writing 1 to self.." "0: Conversion result in DAT register does not meet..,1: Conversion result in DAT register meets CMP1.."
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newline
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bitfld.long 0x0 1. "ADCMPF0,Compare Flag. When the selected channel A/D conversion result meets setting condition in SARADC_CMP0 then this bit is set to 1. And it is cleared by writing 1 to self.." "0: Conversion result in DAT register does not meet..,1: Conversion result in DAT register meets CMP0.."
|
|
newline
|
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bitfld.long 0x0 0. "ADEF,A/D Conversion End Flag. A status flag that indicates the end of A/D conversion.. ADEF is set to 1 at these two conditions:. 1. When A/D conversion ends in Single mode.. 2. When A/D conversion ends on all specified channels in Scan mode.. Note: This.." "0,1"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "SARADC_PDMADAT,SAR ADC PDMA Current Transfer Data"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "DATA,SAR ADC PDMA Current Transfer Data Register (Read Only). When PDMA transferring read this register can monitor current PDMA transfer data.. Current PDMA transfer data is the content of DAT0 ~ DAT11.."
|
|
group.long 0x5C++0x13
|
|
line.long 0x0 "SARADC_ACTL,SAR ADC Analog Control Register"
|
|
bitfld.long 0x0 18. "SAR_VREF,VREF selection. 0 -- select VCCA as VREF. 1 -- select MICBIAS as VREF" "0: select VCCA as VREF,1: select MICBIAS as VREF"
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|
newline
|
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bitfld.long 0x0 17. "ReservedSAR_cur,ReservedSAR current . 0 --- low bias current for comparator. 1 --- high bias current for comparator" "0: low bias current for comparator,1: high bias current for comparator"
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|
newline
|
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bitfld.long 0x0 16. "ReservedSAR_VCMsel,ReservedSAR VCM voltage. 0---- select internal VCM. 1 --- select external VCM" "0: select internal VCM,1: select external VCM"
|
|
newline
|
|
bitfld.long 0x0 0. "SAR_SE_MODE,SE mode selection." "?,1: SARADC in single ended mode"
|
|
line.long 0x4 "SARADC_CTL,SAR ADC Control Register"
|
|
bitfld.long 0x4 11. "SWTRG,A/D Conversion Start. SWTRG bit can be set to 1 from three sources: software external pin STADC. SWTRG will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode A/D conversion.." "0: Conversion stops and A/D converter enter idle..,1: Conversion starts"
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|
newline
|
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bitfld.long 0x4 9. "PDMAEN,PDMA Transfer Enable Bit." "0: PDMA data transfer Disabled,1: PDMA data transfer in DAT 0~11 Enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "HWTRGEN,Hardware Trigger Enable Bit. Enable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).. SARADC hardware trigger function is only supported in single-cycle scan mode.. If hardware trigger mode .." "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x4 6.--7. "HWTRGCOND,External Trigger Condition. These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.." "0: Low level,1: High level,?,?"
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newline
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bitfld.long 0x4 4.--5. "HWTRGSEL,Hardware Trigger Source Selection. Software should disable TRGEN and SWTRG before change HWTRGSEL." "0: A/D conversion is started by external STADC pin,?,?,?"
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|
newline
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bitfld.long 0x4 2.--3. "OPMODE,A/D Converter Operation Mode. When changing the operation mode software should disable SWTRG bit firstly." "0: Single conversion,1: Reserved,?,?"
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|
newline
|
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bitfld.long 0x4 1. "ADCIE,A/D Interrupt Enable Bit. A/D conversion end interrupt request is generated if ADCIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
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newline
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bitfld.long 0x4 0. "ADCEN,A/D Converter Enable Bit. Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption." "0: Disabled,1: Enabled"
|
|
line.long 0x8 "SARADC_CHEN,SAR ADC Channel Enable Register"
|
|
hexmask.long.byte 0x8 20.--23. 1. "ReservedDIFFCHEN,ReservedDifferencial channel mask enable."
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|
newline
|
|
bitfld.long 0x8 16. "ReservedSAR_Vref_sel,ReservedAnalog reference voltage . 0 --- use input [15] Note: no MUX selection to input[15] for user. 1 ---- measure voltage on vref_bandgap instead of voltage on input [15]" "0: use input [15] Note: no MUX selection to..,1: measure voltage on vref_bandgap instead of.."
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|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "CHEN,Analog Input Channel Enable Bit. Set CHEN[11:0] to enable the corresponding analog input channel 11 ~ 0.. Note: Keep 0 for [15:12]"
|
|
line.long 0xC "SARADC_CMP0,SAR ADC Compare Register 0"
|
|
hexmask.long.word 0xC 16.--27. 1. "CMPDAT,Comparison Data. The 12-bit data is used to compare with conversion result of specified channel.. When ADCFMbit is set to 0 SARADC comparator compares CMPDAT with conversion result with unsigned format. CMPDAT should be filled in unsigned.."
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|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count. When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx.."
|
|
newline
|
|
hexmask.long.byte 0xC 3.--6. 1. "CMPCH,Compare Channel Selection."
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|
newline
|
|
bitfld.long 0xC 2. "CMPCOND,Compare Condition. Note: When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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|
newline
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|
bitfld.long 0xC 1. "ADCMPIE,Compare Interrupt Enable Bit. Note: If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT ADCMPF bit will be asserted in the meanwhile if ADCMPIE is set to 1 a compare interrupt request is.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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|
newline
|
|
bitfld.long 0xC 0. "ADCMPEN,Compare Enable Bit. Note: Set this bit to 1 to enable SARADC controller to compare CMPDAT[11:0] with specified channel conversion result when converted data is loaded into DAT register." "0: Compare function Disabled,1: Compare function Enabled"
|
|
line.long 0x10 "SARADC_CMP1,SAR ADC Compare Register 1"
|
|
hexmask.long.word 0x10 16.--27. 1. "CMPDAT,Comparison Data. The 12-bit data is used to compare with conversion result of specified channel.. When ADCFMbit is set to 0 SARADC comparator compares CMPDAT with conversion result with unsigned format. CMPDAT should be filled in unsigned.."
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|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "CMPMCNT,Compare Match Count. When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx.."
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|
newline
|
|
hexmask.long.byte 0x10 3.--6. 1. "CMPCH,Compare Channel Selection."
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|
newline
|
|
bitfld.long 0x10 2. "CMPCOND,Compare Condition. Note: When the internal counter reaches the value to (CMPMCNT +1) the ADCMPFx bit will be set." "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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|
newline
|
|
bitfld.long 0x10 1. "ADCMPIE,Compare Interrupt Enable Bit. Note: If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT ADCMPF bit will be asserted in the meanwhile if ADCMPIE is set to 1 a compare interrupt request is.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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|
newline
|
|
bitfld.long 0x10 0. "ADCMPEN,Compare Enable Bit. Note: Set this bit to 1 to enable SARADC controller to compare CMPDAT[11:0] with specified channel conversion result when converted data is loaded into DAT register." "0: Compare function Disabled,1: Compare function Enabled"
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|
tree.end
|
|
tree "SCS (External Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Set-enable Control. Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). . Writing 1 will enable the associated interrupt.. Writing 0 has no effect.. The.."
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|
group.long 0x80++0x3
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|
line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CLRENA,Clear-enable Control. Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). . Writing 1 will disable the associated interrupt.. Writing 0 has no effect.. The.."
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|
group.long 0x100++0x3
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|
line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
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|
hexmask.long 0x0 0.--31. 1. "SETPEND,Set-pending Control. Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).. Writing 0 has no effect.. The register reads.."
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|
group.long 0x180++0x3
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|
line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear-pending Control. Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).. Writing 0 has no effect.. The register.."
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|
group.long 0x300++0x1F
|
|
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
|
|
bitfld.long 0x0 30.--31. "PRI_3,Priority of IRQ3. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
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|
bitfld.long 0x0 22.--23. "PRI_2,Priority of IRQ2. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
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|
bitfld.long 0x0 14.--15. "PRI_1,Priority of IRQ1. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
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|
bitfld.long 0x0 6.--7. "PRI_0,Priority of IRQ0. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
|
|
bitfld.long 0x4 30.--31. "PRI_7,Priority of IRQ7. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
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|
bitfld.long 0x4 22.--23. "PRI_6,Priority of IRQ6. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
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|
bitfld.long 0x4 14.--15. "PRI_5,Priority of IRQ5. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PRI_4,Priority of IRQ4. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
|
|
bitfld.long 0x8 30.--31. "PRI_11,Priority of IRQ11. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PRI_10,Priority of IRQ10. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PRI_9,Priority of IRQ9. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
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|
bitfld.long 0x8 6.--7. "PRI_8,Priority of IRQ8. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
|
|
bitfld.long 0xC 30.--31. "PRI_15,Priority of IRQ15. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PRI_14,Priority of IRQ14. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PRI_13,Priority of IRQ13. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PRI_12,Priority of IRQ12. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Priority Control Register"
|
|
bitfld.long 0x10 30.--31. "PRI_19,Priority of IRQ19. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. "PRI_18,Priority of IRQ18. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. "PRI_17,Priority of IRQ17. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "PRI_16,Priority of IRQ16. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Priority Control Register"
|
|
bitfld.long 0x14 30.--31. "PRI_23,Priority of IRQ23. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. "PRI_22,Priority of IRQ22. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. "PRI_21,Priority of IRQ21. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "PRI_20,Priority of IRQ20. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Priority Control Register"
|
|
bitfld.long 0x18 30.--31. "PRI_27,Priority of IRQ27. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. "PRI_26,Priority of IRQ26. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. "PRI_25,Priority of IRQ25. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. "PRI_24,Priority of IRQ24. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Priority Control Register"
|
|
bitfld.long 0x1C 30.--31. "PRI_31,Priority of IRQ31. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. "PRI_30,Priority of IRQ30. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. "PRI_29,Priority of IRQ29. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. "PRI_28,Priority of IRQ28. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
tree.end
|
|
tree "SDADC (Sigma-Delta Analog-to-Digital Converter)"
|
|
base ad:0x400E0000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SDADC_DAT,SD ADC FIFO Data Read Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,Delta-Sigma ADC DATA FIFO Read. A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with SDADC_FIFOSTS.THIF to determine if valid data is present in.."
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|
group.long 0x4++0x1F
|
|
line.long 0x0 "SDADC_EN,SD ADC Enable Register"
|
|
bitfld.long 0x0 2. "DINBYPS,ADC data input bypass (internal debug)." "0: normal mode,1: analog 5bits to FIFO for testing"
|
|
bitfld.long 0x0 1. "DINEDGE,ADC data input clock edge selection." "0: ADC clock negetive edge latch,1: ADC clock positive edge latch"
|
|
newline
|
|
bitfld.long 0x0 0. "SDADCEN,SDADC Enable ." "0: Conversion stopped and ADC is reset including..,1: ADC Conversion enabled"
|
|
line.long 0x4 "SDADC_CLKDIV,SD ADC Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,SD_CLK Clock Divider . SDADC internal clock divider. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. (Refer to 7.1.4.2.). CLKDIV must be greater than and equal 2. ."
|
|
line.long 0x8 "SDADC_CTL,SD ADC Control Register"
|
|
bitfld.long 0x8 11. "RATESEL,Sample Rate Selection." "0: choose DSRATE for SDADC,1: choose BSRATE for BS"
|
|
bitfld.long 0x8 9.--10. "ReservedBSRATE,Down Sampling for BS." "0: down sample 2000 for SPS384,1: down sampel 4000(reserved),?,?"
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|
newline
|
|
bitfld.long 0x8 8. "DMICEN,Digital MIC Enable." "0: keep SDADC function,1: turn digital MIC function input from GPIO"
|
|
bitfld.long 0x8 7. "FIFOTHIE,FIFO Threshold Interrupt Enable." "0: disable interrupt whenever FIFO level exceeds..,1: enable interrupt whenever FIFO level exceeds.."
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|
newline
|
|
bitfld.long 0x8 4.--6. "FIFOTH,FIFO Threshold:. Determines at what level the ADC FIFO will generate a interrupt.. Interrupt will be generated when number of words present in ADC FIFO is > . FIFOTH." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. "FIFOBITS,FIFO Data Bits Selection." "0: 32 bits,1: 16 bits,2: 8 bits,3: 24 bits"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "DSRATE,Down Sampling Ratio." "0: reserved,1: down sample X 16,2: down sample X 32,3: down sample X 64"
|
|
line.long 0xC "SDADC_FIFOSTS,SD ADC FIFO Status Register"
|
|
bitfld.long 0xC 31. "BISTEN,BIST Enable. Internal use" "0: Disable SDADC FIFO BIST testing,1: Enable SDADC FIFO BIST testing SDADC FIFO can be.."
|
|
hexmask.long.byte 0xC 4.--7. 1. "POINTER,SDADC FIFO Pointer (Read Only). The FULL bit and POINTER[3:0] indicates the field that the valid data count within the SDADC FIFO buffer.. The Maximum value shown in POINTER is 15. When the using level of SDADC FIFO Buffer equal to 16 The FULL.."
|
|
newline
|
|
rbitfld.long 0xC 2. "THIF,ADC FIFO Threshold Interrupt Status (Read Only)." "0: The valid data count within the transmit FIFO..,1: The valid data count within the SDADC FIFO.."
|
|
bitfld.long 0xC 1. "EMPTY,FIFO Empty." "0: FIFO is not empty,1: FIFO is empty"
|
|
newline
|
|
bitfld.long 0xC 0. "FULL,FIFO Full." "0: FIFO is not full,1: FIFO is full"
|
|
line.long 0x10 "SDADC_PDMACTL,SD ADC PDMA Control Register"
|
|
bitfld.long 0x10 0. "PDMAEN,Enable SDADC PDMA Receive Channel." "0: Disable SDADC PDMA,1: Enable SDADC PDMA"
|
|
line.long 0x14 "SDADC_CMPR0,SD ADC Comparator 0 Control Register"
|
|
bitfld.long 0x14 31. "CMPOEN,Compare Match output FIFO zero." "0: FIFO data keep original one,1: compare match then FIFO out zero"
|
|
hexmask.long.tbyte 0x14 8.--30. 1. "CMPD,Comparison Data. 23 bit value to compare to FIFO output word."
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "CMPMATCNT,Compare Match Count. When the A/D FIFO result matches the compare condition defined by CMPCOND the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1) the CMPF bit will be set."
|
|
bitfld.long 0x14 3. "CMPF,Compare Flag. When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "CMPCOND,Compare Condition. Note: When the internal counter reaches the value (CMPMATCNT +1) the CMPF bit will be set." "0: Set the compare condition that result is less..,1: Set the compare condition that result is greater.."
|
|
bitfld.long 0x14 1. "CMPIE,Compare Interrupt Enable. If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF bit will be asserted if CMPIE is set to 1 a compare interrupt request is generated." "0: Disable compare function interrupt,1: Enable compare function interrupt"
|
|
line.long 0x18 "SDADC_CMPR1,SD ADC Comparator 1 Control Register"
|
|
bitfld.long 0x18 31. "CMPOEN,Compare Match output FIFO zero." "0: FIFO data keep original one,1: compare match then FIFO out zero"
|
|
hexmask.long.tbyte 0x18 8.--30. 1. "CMPD,Comparison Data. 23 bit value to compare to FIFO output word."
|
|
newline
|
|
hexmask.long.byte 0x18 4.--7. 1. "CMPMATCNT,Compare Match Count. When the A/D FIFO result matches the compare condition defined by CMPCOND the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1) the CMPF bit will be set."
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|
bitfld.long 0x18 3. "CMPF,Compare Flag. When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "CMPCOND,Compare Condition. Note: When the internal counter reaches the value (CMPMATCNT +1) the CMPF bit will be set." "0: Set the compare condition that result is less..,1: Set the compare condition that result is greater.."
|
|
bitfld.long 0x18 1. "CMPIE,Compare Interrupt Enable. If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPF bit will be asserted if CMPIE is set to 1 a compare interrupt request is generated." "0: Disable compare function interrupt,1: Enable compare function interrupt"
|
|
line.long 0x1C "SDADC_SDCHOP,Sigma Delta Analog Block Control Register"
|
|
bitfld.long 0x1C 30.--31. "AUDIOPATHSEL,Audio Path Selection Connect SDADC input to." "0: PGA (default),1: MICN and MICP pins (bypass PGA),?,?"
|
|
bitfld.long 0x1C 29. "CHOPEN,SDADC chopper enable." "0: disable (default),1: enable"
|
|
newline
|
|
bitfld.long 0x1C 28. "CHOPPH,SDADC chopper phase. When chopper is off:." "0: chopper switches in default state,1: invert chopper switches"
|
|
bitfld.long 0x1C 27. "CHOPORD,SDADC Chopper Order." "0: 1st order dithering of chopper frequency (default),1: 2nd order dithering of chopper frequency"
|
|
newline
|
|
bitfld.long 0x1C 26. "CHOPFIX,SDADC Chopper Fixed Frequency." "0: dither chopper frequency (default),1: choose fixed frequency"
|
|
bitfld.long 0x1C 25. "CHOPCLKPH,SDADC Chopper Clock phase selection." "0: chopper transition after falling edge of ADC_CLK..,1: chopper transition after rising edge of ADC_CLK"
|
|
newline
|
|
bitfld.long 0x1C 23.--24. "CHOPF,SDADC Chopper Frequency in fixed chop mode." "0: Fs/2 (default),1: Fs/4,?,?"
|
|
bitfld.long 0x1C 21.--22. "PGA_ADCDC," "0: Default,?,?,?"
|
|
newline
|
|
bitfld.long 0x1C 20. "PGA_HZMODE,Select input impedance." "0: 12k Ohm input impedance,1: 500k Ohm input impedance (default)"
|
|
bitfld.long 0x1C 19. "PGA_TRIMOBC,Trim current in output driver." "0: disable,1: enable (default)"
|
|
newline
|
|
bitfld.long 0x1C 18. "PGA_CLASSA,Enable Class A mode of operation ." "0: Class AB,1: Class A (default)"
|
|
bitfld.long 0x1C 16.--17. "PGA_CMLCKADJ," "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 15. "PGA_CMLCK,Common mode Threshold lock adjust enable." "0: Enable,1: Disable"
|
|
bitfld.long 0x1C 14. "PGA_DISCH,Charge inputs selected by PGA_ACDC[1:0] to VREF." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x1C 13. "PGA_GAIN," "0,1"
|
|
bitfld.long 0x1C 12. "PGA_IBLOOP,Trim PGA current." "?,1: default"
|
|
newline
|
|
bitfld.long 0x1C 9.--11. "PGA_IBCTR,Trim PGA Current." "0: default,?,?,?,?,?,?,?"
|
|
bitfld.long 0x1C 6.--8. "PGA_MODE,PGA mode selection;." "0: Disable,1: Enable,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x1C 5. "PGA_MUTE,Mute control signal 0-disable 1-enable" "0: disable 1-enable,?"
|
|
bitfld.long 0x1C 4. "PGA_PU,Power up PGA 0-disable 1-enable" "0: disable 1-enable,?"
|
|
newline
|
|
bitfld.long 0x1C 3. "VREF,SDADC Chopper in Reference Buffer." "0: chopper off,1: chopper on"
|
|
bitfld.long 0x1C 1.--2. "BIAS,SDADC Bias Current Selection." "0: 1,1: 0.75,?,?"
|
|
newline
|
|
bitfld.long 0x1C 0. "PD,SDADC Power Down." "0: SDADC power on,1: SDADC power off"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI0"
|
|
base ad:0x40030000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "SPI_CTL,Control and Status Register"
|
|
bitfld.long 0x0 24. "RXMODEEN,FIFO Receive Mode Enable." "0: Disable function,1: Enable FIFO receive mode. In this mode SPI.."
|
|
bitfld.long 0x0 23. "RXTCNTEN,DMA Receive Transaction Count Enable." "0: Disable function,1: Enable transaction counter for DMA receive only.."
|
|
newline
|
|
bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable." "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
|
|
bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable." "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "QDIODIR,Quad or Dual I/O Mode Direction Control." "0: Quad or Dual Input mode,1: Quad or Dual Output mode"
|
|
bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable. Note:. Byte reorder function is only available if DWIDTH is defined as 16 24 and 32 bits.. REORDER is only available for Receive mode in DUAL and QUAD transactions.. For DUAL and QUAD transactions with REORDER .." "0: Byte reorder function Disabled,1: Byte reorder function Enabled. A byte suspend.."
|
|
newline
|
|
bitfld.long 0x0 18. "SLAVE,Master Slave Mode Control." "0: Master mode,1: Slave mode"
|
|
bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable." "0: Disable SPI Unit Transfer Interrupt,1: Enable SPI Unit Transfer Interrupt to CPU"
|
|
newline
|
|
bitfld.long 0x0 16. "TWOBIT,Two Bits Transfer Mode . When 2-bit mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function the.." "0: Disable two-bit transfer mode,1: Enable two-bit transfer mode"
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bitfld.long 0x0 13. "LSB,LSB First. Note:. For DUAL and QUAD transactions with LSB must be set to 0." "0: The MSB is transmitted/received first (which bit..,1: The LSB is sent first on the line (bit 0 of TX.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,DWIDTH - Data Word Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only). The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity." "0: SCLK idle low,1: SCLK idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit at Negative Edge." "0: The transmitted data output signal is changed at..,1: The transmitted data output signal is changed at.."
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bitfld.long 0x0 1. "RXNEG,Receive at Negative Edge." "0: The received data input signal is latched at the..,1: The received data input signal is latched at the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Enable. In Master mode the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode the device is ready to receive data when this bit is set to 1. . Note:. All configuration should be set before.." "0: Disable SPI Transfer,1: Enable SPI Transfer"
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line.long 0x4 "SPI_CLKDIV,Clock Divider Register (Master Only)"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register . The value in this field is the frequency divider for generating the SPI engine clock Fspi_sclk and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. . where ."
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line.long 0x8 "SPI_SSCTL,Slave Select Register"
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hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period . In Slave mode these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0 it indicates the.."
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable ." "0: Slave select inactive interrupt Disable,1: Slave select inactive interrupt Enable"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable ." "0: Slave select active interrupt Disable,1: Slave select active interrupt Enable"
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bitfld.long 0x8 9. "SLVUDRIEN,Slave Mode Error 1 Interrupt Enable ." "0: Slave mode error 1 interrupt Disable,1: Slave mode error 1 interrupt Enable"
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bitfld.long 0x8 8. "SLVBCEIEN,Slave Mode Error 0 Interrupt Enable ." "0: Slave mode error 0 interrupt Disable,1: Slave mode error 0 interrupt Enable"
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bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out FIFO Clear." "0: Function disabled,1: Both the FIFO clear function TXRST and RXRST are.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable." "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable. This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK SPI_MISO and SPI_MOSI.." "0: 4-wire bi-directional interface,1: 3-wire bi-directional interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)." "0: If this bit is cleared slave select signals will..,1: If this bit is set SPI_SS0/1 signals will be.."
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bitfld.long 0x8 2. "SSACTPOL,Slave Select Active Level. This bit defines the active status of slave select signal (SPI_SS0/1).." "0: The slave select signal SPI_SS0/1 is active on..,1: The slave select signal SPI_SS0/1 is active on.."
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bitfld.long 0x8 0.--1. "SS,Slave Select Control Bits (Master Only). If AUTOSS bit is cleared writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.. If the AUTOSS bit is set writing 0 to any bit.." "0,1,2,3"
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line.long 0xC "SPI_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset." "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable. Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit DMA Enable. Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done." "0,1"
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line.long 0x10 "SPI_FIFOCTL,FIFO Control/Status Register"
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bitfld.long 0x10 28.--29. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0.. 00: 1 word will transmit. 01: 2 word will transmit." "0,1,2,3"
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bitfld.long 0x10 24.--25. "RXTH,Receive FIFO Threshold. If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0.. 00: 1 word will transmit. 01: 2 word will transmit. 10: 3 word.." "0,1,2,3"
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bitfld.long 0x10 7. "TXUDFIEN,Slave Transmit Under Run Interrupt Enable." "0: Slave Transmit FIFO under-run interrupt Disabled,1: Slave Transmit FIFO under-run interrupt Enabled"
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bitfld.long 0x10 6. "TXUDFPOL,Transmit Under-run Data Out. Note: The under run event is active after the serial clock input and the hardware synchronous so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last.." "0: The SPI data out is 0 if there is transmit..,1: The SPI data out is 1 if there is transmit.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable." "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable." "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable." "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Clear Transmit FIFO Buffer. Note: If there is slave receive time out event the TXRST will be set 1 when the SPI_SSCTL.SLVTORST is enabled." "0: No effect,1: Clear transmit FIFO buffer. The TXFULL bit will.."
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bitfld.long 0x10 0. "RXRST,Clear Receive FIFO Buffer. Note: If there is slave receive time out event the RXRST will be set 1 when the SPI_SSCTL.SLVTORST is enabled." "0: No effect,1: Clear receive FIFO buffer. The RXFULL bit will.."
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line.long 0x14 "SPI_STATUS,Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,FIFO CLR Status (Read Only). Note: Both the TXRST RXRST need 3 system clock + 3 engine clocks the status of this bit allows the user to monitor whether the clear function is busy or done." "0: Done the FIFO buffer clear function of TXRST and..,1: Doing the FIFO buffer clear function of TXRST or.."
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rbitfld.long 0x14 19. "TXUFIF,Slave Transmit FIFO Under-run Interrupt Status (Read Only). When the transmit FIFO buffer is empty and further serial clock pulses occur data transmitted will be the value of the last transmitted bit and this under-run bit will be set.. Note:.." "0,1"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Status (Read Only)." "0: The valid data count of the transmit FIFO buffer..,1: The valid data count of the transmit FIFO buffer.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Bit Status (Read Only). Note: The clock source of SPI controller logic is engine clock it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic this bit indicates the real.." "0: Indicate the transmit control bit is disabled,1: Indicate the transfer control bit is active"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Status. Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Status. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to itself." "0,1"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Status (Read Only)." "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)." "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x14 7. "SLVURIF,Slave Mode Error 1 Interrupt Status (Read Only). In Slave mode transmit under-run occurs when the slave select line goes to inactive state.." "0: No Slave mode error 1 event,1: Slave mode error 1 occurs"
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rbitfld.long 0x14 6. "SLVBEIF,Slave Mode Error 0 Interrupt Status (Read Only). In Slave mode there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.. Note: If the slave select active but there is no any serial clock input the SLVBEIF.." "0: No Slave mode error 0 event,1: Slave mode error 0 occurs"
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rbitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Status (Read Only). When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input the slave time-out counter in SPI controller logic will be start. When the value of time-out counter.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only). Note: If SPI_SSCTL.SSACTPOL is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: Indicates the slave select line bus status is 0,1: Indicates the slave select line bus status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Status. Note: This bit will be cleared by writing 1 to itself." "0: Slave select inactive interrupt is clear or not..,1: Slave select inactive interrupt event has occur"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Status. Note: This bit will be cleared by writing 1 to itself." "0: Slave select active interrupt is clear or not..,1: Slave select active interrupt event has occur"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Status. Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,SPI Unit Bus Status (Read Only)." "0: No transaction in the SPI bus,1: SPI controller unit is in busy state"
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line.long 0x18 "SPI_RXTSNCNT,Receive Transaction Count Register"
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hexmask.long.tbyte 0x18 0.--16. 1. "RXTSNCNT,DMA Receive Transaction Count. When using DMA to receive SPI data without transmitting data this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of transactions to perform. Without this the SPI interface.."
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wgroup.long 0x20++0x3
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line.long 0x0 "SPI_TX,FIFO Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.. For example if DWIDTH is set.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPI_RX,FIFO Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS. RXEMPTY bit is not set to 1. This is a read-only register."
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rgroup.long 0x50++0x3
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line.long 0x0 "SPI_VERNUM,IP Version Number Register"
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tree.end
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tree "SPI1"
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base ad:0x40038000
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group.long 0x0++0xB
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line.long 0x0 "SPI1_CTL,Control and Status Register"
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bitfld.long 0x0 28. "DMABURST,Enable DMA Automatic SS function.. When enabled interface will automatically generate a SS signal for an entire PDMA access transaction." "0,1"
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bitfld.long 0x0 27. "TXFULL,Transmit FIFO FULL STATUS." "0: The transmit data FIFO is not full,1: The transmit data FIFO is full"
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bitfld.long 0x0 26. "TXEMPTY,Transmit FIFO EMPTY STATUS." "0: The transmit data FIFO is not empty,1: The transmit data FIFO is empty"
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bitfld.long 0x0 25. "RXFULL,Receive FIFO FULL STATUS." "0: The receive data FIFO is not full,1: The receive data FIFO is full"
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bitfld.long 0x0 24. "RXEMPTY,Receive FIFO EMPTY STATUS." "0: The receive data FIFO is not empty,1: The receive data FIFO is empty"
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bitfld.long 0x0 23. "VARCLKEN,Variable Clock Enable (Master Only). Note that when enabled the setting of TXBITLEN must be programmed as 0x10 (16 bits mode)" "0: The serial clock output frequency is fixed and..,1: SCLK output frequency is variable. The output.."
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bitfld.long 0x0 22. "TWOB,Two Bits Transfer Mode . Note that when enabled in master mode MOSI data comes from SPI1_TX0 and MOSI data from SPI1_TX1. Likewise SPI1_RX0 receives bit stream from MISO0 and SPI1_RX1 from MISO1. Note that when enabled the setting of TXNUM must.." "0: Disable two-bit transfer mode,1: Enable two-bit transfer mode"
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bitfld.long 0x0 21. "FIFO,FIFO Mode." "0: No FIFO present on transmit and receive buffer,1: Enable FIFO on transmit and receive buffer"
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bitfld.long 0x0 20. "BYTEENDIAN,Byte Endian Reorder Function. This function changes the order of bytes sent/received to be least significant physical byte first." "0,1"
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bitfld.long 0x0 19. "BYTESLEEP,Insert Sleep interval between Bytes." "0,1"
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bitfld.long 0x0 18. "SLAVE,Master Slave Mode Control." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "IE,Interrupt Enable." "0: Disable SPI Interrupt,1: Enable SPI Interrupt to CPU"
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bitfld.long 0x0 16. "IF,Interrupt Flag. NOTE: This bit is cleared by writing 1 to itself." "0: Indicates the transfer is not finished yet,1: Indicates that the transfer is complete."
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hexmask.long.byte 0x0 12.--15. 1. "SLEEP,Suspend Interval (Master Only). (SLEEP[3:0] + 2) * period of SCLK"
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bitfld.long 0x0 11. "CLKP,Clock Polarity." "0: SCLK idle low,1: SCLK idle high"
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bitfld.long 0x0 10. "LSB,LSB First." "0: The MSB is transmitted/received first (which bit..,1: The LSB is sent first on the line (bit 0 of.."
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bitfld.long 0x0 8.--9. "TXNUM,Transmit/Receive Word Numbers. This field specifies how many transmit/receive word numbers should be executed in one transfer.." "0: Only one transmit/receive word will be executed..,1: Two successive transmit/receive word will be..,?,?"
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hexmask.long.byte 0x0 3.--7. 1. "TXBITLEN,Transmit Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.."
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bitfld.long 0x0 2. "TXNEG,Transmit At Negative Edge." "0: The transmitted data output signal is changed at..,1: The transmitted data output signal is changed at.."
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bitfld.long 0x0 1. "RXNEG,Receive At Negative Edge." "0: The received data input signal is latched at the..,1: The received data input signal is latched at the.."
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bitfld.long 0x0 0. "EN,Go and Busy Status. NOTE: All registers should be set before writing 1 to this EN bit. When a transfer is in progress writing to any register of the SPI master/slave core has no effect." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit starts the transfer. This.."
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line.long 0x4 "SPI1_CLKDIV,Clock Divider Register (Master Only)"
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hexmask.long.word 0x4 16.--31. 1. "CLKDIV1,Clock Divider 2 Register (master only). The value in this field is the 2nd frequency divider of the system clock PCLK to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:"
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hexmask.long.word 0x4 0.--15. 1. "CLKDIV0,Clock Divider Register (master only). The value in this field is the frequency division of the system clock PCLK to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:. . In slave.."
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line.long 0x8 "SPI1_SSCTL,Slave Select Register"
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bitfld.long 0x8 5. "LTRIGFLAG,Level Trigger Flag. When the SSLTRIG bit is set in slave mode this bit can be read to indicate the received bit number is met the requirement or not.. Note: This bit is READ only" "0: One of the received number and the received bit..,1: The received number and received bits met the.."
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bitfld.long 0x8 4. "SSLTRIG,Slave Select Level Trigger (Slave only)." "0: The input slave select signal is edge-trigger.,1: The slave select signal will be level-trigger."
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bitfld.long 0x8 3. "ASS,Automatic Slave Select (Master only)." "0: If this bit is cleared slave select signals are..,1: If this bit is set SPISS signals are generated.."
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bitfld.long 0x8 2. "SSLVL,Slave Select Active Level . It defines the active level of device/slave select signal (SPISSx0/1).." "0: The slave select signal SPISSx0/1 is active at..,1: The slave select signal SPISSx0/1 is active at.."
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bitfld.long 0x8 0. "SSR,Slave Select Register (Master only). If ASS bit is cleared writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.. If ASS bit is set writing 1 to any bit.." "0,1"
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rgroup.long 0x10++0x7
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line.long 0x0 "SPI1_RX0,Data Receive Register 0"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example if TXBITLEN is set to 0x08 and TXNUM is set to.."
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line.long 0x4 "SPI1_RX1,Data Receive Register 1"
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hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register. The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example if TXBITLEN is set to 0x08 and TXNUM is set to.."
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wgroup.long 0x20++0x7
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line.long 0x0 "SPI1_TX0,Data Transmit Register 0"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example if TXBITLEN is set to 0x08 and the TXNUM is set to 0x0 .."
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line.long 0x4 "SPI1_TX1,Data Transmit Register 1"
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hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register. The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example if TXBITLEN is set to 0x08 and the TXNUM is set to 0x0 .."
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group.long 0x34++0x7
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line.long 0x0 "SPI1_VARCLK,Variable Clock Pattern Register"
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hexmask.long 0x0 0.--31. 1. "VARCLK,Variable Clock Pattern. The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0' the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1' the output frequency of.."
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line.long 0x4 "SPI1_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x4 1. "RXMDAEN,Receive DMA Start. Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically." "0: Disable,1: Enable"
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bitfld.long 0x4 0. "TXMDAEN,Transmit DMA Start. Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically. . If using DMA mode to transfer data remember not to set EN bit of SPI_CTL register. The DMA controller inside.." "0: Disable,1: Enable"
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tree.end
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tree.end
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tree "SYS (System Global Control)"
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base ad:0x50000000
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rgroup.long 0x0++0x3
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line.long 0x0 "SYS_PDID,Product ID"
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hexmask.long 0x0 0.--31. 1. "PDID,Product Identifier. Chip identifier for I91200 series."
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group.long 0x4++0xB
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line.long 0x0 "SYS_RSTSTS,System Reset Source Register"
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bitfld.long 0x0 10. "PORF,Power on Reset Flag. The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down.. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF DPDRSTF and WKRSTF" "0: No detected,1: A power on Reset has occurred"
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bitfld.long 0x0 9. "DPDRSTF,Deep Power Down Reset Flag. The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function. . This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF DPDRSTF and WKRSTF" "0: No detected,1: A power on was triggered by DPD timer"
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bitfld.long 0x0 8. "WKRSTF,Wakeup Pin Reset Flag. The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin. . This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF DPDRSTF and.." "0: No detected,1: A power on was triggered by WAKEUP pin"
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bitfld.long 0x0 7. "CPURF,Reset Source From CPU. The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a '1' to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).. This bit is cleared by writing 1 to itself." "0: No reset from CPU,1: The Cortex-M0 CPU kernel and FMC has been reset.."
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bitfld.long 0x0 6. "PMURSTF,Reset Source From PMU. The PMURSTF flag is set if the PMU.. This bit is cleared by writing 1 to itself." "0: No reset from PMU,1: PMU reset the system from a power down/standby.."
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bitfld.long 0x0 5. "SYSRF,Reset Source From MCU. The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel.. This bit is cleared by writing 1 to itself." "0: No reset from MCU,1: The Cortex_M0 MCU issued a reset signal to reset.."
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bitfld.long 0x0 3. "LVRF,Low Voltage Reset Flag. The LVRF flag is set if pervious reset source originates from the LVR module.. This bit is cleared by writing 1 to itself." "0: No reset from LVR,1: The LVR module issued the reset signal to reset.."
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bitfld.long 0x0 2. "WDTRF,Reset Source From WDT. The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.. This bit is cleared by writing 1 to itself." "0: No reset from Watch-Dog,1: The Watch-Dog module issued the reset signal to.."
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bitfld.long 0x0 1. "PADRF,The RSTS_PAD Flag Is If Pervious Reset Source Originates From the /RESET Pin . This bit is cleared by writing 1 to itself." "0: No reset from Pin /RESET,1: Pin /RESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "CORERSTF,Reset Source From CORE. The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR) RESETn Pin Reset or PMU reset. . This bit is cleared by writing 1 to itself." "0: No reset from CORE,1: Core was reset by hardware block"
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|
line.long 0x4 "SYS_IPRST0,IP Reset Control Resister0"
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|
bitfld.long 0x4 2. "PDMARST,PDMA Controller Reset. Set '1' will generate a reset signal to the PDMA Block. User needs to set this bit to '0' to release from the reset state." "0: Normal operation,1: PDMA IP reset"
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|
bitfld.long 0x4 1. "CPURST,CPU Kernel One Shot Reset. Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC) this bit will automatically return to '0' after the 2 clock cycles. This bit is a protected bit to program first issue the unlock sequence ." "0: Normal,1: Reset CPU"
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bitfld.long 0x4 0. "CHIPRST,CHIP One Shot Reset. Set this bit will reset the whole chip this bit will automatically return to '0' after the 2 clock cycles.. CHIPRST has same behavior as POR reset all the chip modules are reset and the chip configuration settings from.." "0: Normal,1: Reset CHIP"
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|
line.long 0x8 "SYS_IPRST1,IP Reset Control Resister1"
|
|
bitfld.long 0x8 30. "ANARST,Analog Block Control Reset." "0: Normal Operation,1: Reset"
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|
bitfld.long 0x8 29. "I2S0RST,I2S Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 28. "SDADCRST,SDADC Controller Reset ." "0: Normal Operation,1: Reset"
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|
bitfld.long 0x8 27. "SARADCRST,SAR ADC Controller Reset ." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 20. "PWM0RST,PWM0 Controller Reset." "0: Normal Operation,1: Reset"
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|
bitfld.long 0x8 18. "BIQRST,Biquad Filter Block Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 13. "DPWMRST,DPWM Speaker Driver Reset." "0: Normal Operation,1: Reset"
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|
bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 11. "SPI1RST,SPI1 Controller Reset." "0: Normal Operation,1: Reset"
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|
bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 7. "TMR1RST,Timer1 Controller Reset." "0: Normal Operation,1: Reset"
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|
bitfld.long 0x8 6. "TMR0RST,Timer0 Controller Reset." "0: Normal Operation,1: Reset"
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|
group.long 0x30++0x3
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|
line.long 0x0 "SYS_GPSMTEN,GPIOA/B Input Type Control Register"
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|
bitfld.long 0x0 31. "HSSGPBG3,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 15/14/13/12 Output low slew rate,1: GPIOB 15/14/13/12 Output high slew rate"
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bitfld.long 0x0 30. "SSGPBG3,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 15/14/13/12 input CMOS enabled,1: GPIOB 15/14/13/12 input Schmitt Trigger enabled"
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bitfld.long 0x0 29. "HSSGPBG2,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 11/10/9/8 Output low slew rate,1: GPIOB 11/10/9/8 Output high slew rate"
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bitfld.long 0x0 28. "SSGPBG2,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 11/10/9/8 input CMOS enabled,1: GPIOB 11/10/9/8 input Schmitt Trigger enabled"
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bitfld.long 0x0 27. "HSSGPBG1,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 7/6/5/4 Output low slew rate,1: GPIOB 7/6/5/4 Output high slew rate"
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bitfld.long 0x0 26. "SSGPBG1,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 7/6/5/4 input CMOS enabled,1: GPIOB 7/6/5/4 input Schmitt Trigger enabled"
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bitfld.long 0x0 25. "HSSGPBG0,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 3/2/1/0 Output low slew rate,1: GPIOB 3/2/1/0 Output high slew rate"
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bitfld.long 0x0 24. "SSGPBG0,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOB 3/2/1/0 input CMOS enabled,1: GPIOB 3/2/1/0 input Schmitt Trigger enabled"
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bitfld.long 0x0 23. "HSSGPAG3,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 15/14/13/12 Output low slew rate,1: GPIOA 15/14/13/12 Output high slew rate"
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bitfld.long 0x0 22. "SSGPAG3,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 15/14/13/12 input CMOS enabled,1: GPIOA 15/14/13/12 input Schmitt Trigger enabled"
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bitfld.long 0x0 21. "HSSGPAG2,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 11/10/9/8 Output low slew rate,1: GPIOA 11/10/9/8 Output high slew rate"
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bitfld.long 0x0 20. "SSGPAG2,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 11/10/9/8 input CMOS enabled,1: GPIOA 11/10/9/8 input Schmitt Trigger enabled"
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bitfld.long 0x0 19. "HSSGPAG1,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 7/6/5/4 Output low slew rate,1: GPIOA 7/6/5/4 Output high slew rate"
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bitfld.long 0x0 18. "SSGPAG1,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 7/6/5/4 input CMOS enabled,1: GPIOA 7/6/5/4 input Schmitt Trigger enabled"
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bitfld.long 0x0 17. "HSSGPAG0,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 3/2/1/0 Output low slew rate,1: GPIOA 3/2/1/0 Output high slew rate"
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bitfld.long 0x0 16. "SSGPAG0,this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.. Each bit controls a group of four GPIO pins." "0: GPIOA 3/2/1/0 input CMOS enabled,1: GPIOA 3/2/1/0 input Schmitt Trigger enabled"
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group.long 0x38++0x7
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line.long 0x0 "SYS_GPA_MFP,GPIOA Multiple Alternate Functions Control Register"
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bitfld.long 0x0 30.--31. "PA15MFP,Alternate Function Setting for PA15MFP." "0: GPIO,1: UART1_RX,?,?"
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bitfld.long 0x0 28.--29. "PA14MFP,Alternate Function Setting for PA14MFP." "0: GPIO,1: UART1_TX,?,?"
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bitfld.long 0x0 26.--27. "PA13MFP,Alternate Function Setting for PA13MFP." "0: GPIO,1: PWM0CH3,?,?"
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bitfld.long 0x0 24.--25. "PA12MFP,Alternate Function Setting for PA12MFP." "0: GPIO,1: PWM0CH2,?,?"
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bitfld.long 0x0 22.--23. "PA11MFP,Alternate Function Setting for PA11MFP." "0: GPIO,1: PWM0CH1,?,?"
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bitfld.long 0x0 20.--21. "PA10MFP,Alternate Function Setting for PA10MFP." "0: GPIO,1: PWM0CH0,?,?"
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bitfld.long 0x0 18.--19. "PA9MFP,Alternate Function Setting for PA9MFP." "0: GPIO,1: I2C0_SCL,?,?"
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bitfld.long 0x0 16.--17. "PA8MFP,Alternate Function Setting for PA8MFP." "0: GPIO,1: I2C0_SDA,?,?"
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bitfld.long 0x0 14.--15. "PA7MFP,Alternate Function Setting for PA7MFP." "0: GPIO,1: UART0_RX,?,?"
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bitfld.long 0x0 12.--13. "PA6MFP,Alternate Function Setting for PA6MFP." "0: GPIO,1: UART0_TX,?,?"
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bitfld.long 0x0 10.--11. "PA5MFP,Alternate Function Setting for PA5MFP." "0: GPIO,1: SPI0_MOSI1,?,?"
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bitfld.long 0x0 8.--9. "PA4MFP,Alternate Function Setting for PA4MFP." "0: GPIO,1: SPI0_MISO0,?,?"
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bitfld.long 0x0 6.--7. "PA3MFP,Alternate Function Setting for PA3MFP." "0: GPIO,1: SPI0_SSB0,?,?"
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bitfld.long 0x0 4.--5. "PA2MFP,Alternate Function Setting for PA2MFP." "0: GPIO,1: SPI0_SCLK0,?,?"
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bitfld.long 0x0 2.--3. "PA1MFP,Alternate Function Setting for PA1MFP." "0: GPIO,1: SPI0_MOSI0,?,?"
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bitfld.long 0x0 0.--1. "PA0MFP,Alternate Function Setting for PA0MFP." "0: GPIO,1: SPI0_MISO1,?,?"
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line.long 0x4 "SYS_GPB_MFP,GPIOB Multiple Alternate Functions Control Register"
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bitfld.long 0x4 30.--31. "PB15MFP,Alternate Function Setting for PB15MFP." "0: GPIO,1: SPI0_SSB0,?,?"
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bitfld.long 0x4 28.--29. "PB14MFP,Alternate Function Setting for PB14MFP." "0: GPIO,1: SPI0_SCLK0,?,?"
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bitfld.long 0x4 26.--27. "PB13MFP,Alternate Function Setting for PB13MFP." "0: GPIO,1: SPI0_MOSI0,?,?"
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bitfld.long 0x4 24.--25. "PB12MFP,Alternate Function Setting for PB12MFP." "0: GPIO,1: SP0_MISO1,?,?"
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bitfld.long 0x4 22.--23. "PB11MFP,Alternate Function Setting for PB11MFP." "0: GPIO,?,?,?"
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bitfld.long 0x4 20.--21. "PB10MFP,Alternate Function Setting for PB10MFP." "0: GPIO,?,?,?"
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bitfld.long 0x4 18.--19. "PB9MFP,Alternate Function Setting for PB9MFP." "0: GPIO,1: I2C0_SCL,?,?"
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bitfld.long 0x4 16.--17. "PB8MFP,Alternate Function Setting for PB8MFP." "0: GPIO,1: I2C0_SDA,?,?"
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bitfld.long 0x4 14.--15. "PB7MFP,Alternate Function Setting for PB7MFP." "0: GPIO,1: I2S0_SDO,?,?"
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bitfld.long 0x4 12.--13. "PB6MFP,Alternate Function Setting for PB6MFP." "0: GPIO,1: I2S0_SDI,?,?"
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bitfld.long 0x4 10.--11. "PB5MFP,Alternate Function Setting for PB5MFP." "0: GPIO,1: I2S0_BCLK,?,?"
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bitfld.long 0x4 8.--9. "PB4MFP,Alternate Function Setting for PB4MFP." "0: GPIO,1: I2S0_FS,?,?"
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bitfld.long 0x4 6.--7. "PB3MFP,Alternate Function Setting for PB3MFP." "0: GPIO,1: SPI1_MISO,?,?"
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bitfld.long 0x4 4.--5. "PB2MFP,Alternate Function Setting for PB2MFP." "0: GPIO,1: SPI1_SSB,?,?"
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bitfld.long 0x4 2.--3. "PB1MFP,Alternate Function Setting for PB1MFP." "0: GPIO,1: SPI1_SCLK,?,?"
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bitfld.long 0x4 0.--1. "PB0MFP,Alternate Function Setting for PB0MFP." "0: GPIO,1: SPI1_MOSI,?,?"
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group.long 0x54++0x3
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line.long 0x0 "SYS_WKCTL,WAKEUP pin control register"
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group.long 0x100++0x3
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line.long 0x0 "SYS_REGLCTL,Register Lock Control"
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bitfld.long 0x0 0. "REGLCTL,Protected Register Unlock Register." "0: Protected registers are locked. Any write to the..,1: Protected registers are unlocked"
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group.long 0x110++0x1B
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line.long 0x0 "SYS_IRCTCTL,Oscillator Frequency Adjustment Control Register"
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bitfld.long 0x0 15. "RANGE,1: Low Frequency mode of oscillator active (2MHz).. 0: High frequency mode (20-50MHz)" "0: High frequency mode,1: Low Frequency mode of oscillator active"
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hexmask.long.word 0x0 0.--9. 1. "FREQ,Current oscillator frequency trim value. (based on CLK_CLKSEL0.HIRCFSEL)"
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line.long 0x4 "SYS_OSC10KTRIM,10kHz Oscillator (LIRC) Trim Register"
|
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bitfld.long 0x4 31. "TRMCLK," "0,1"
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hexmask.long.tbyte 0x4 0.--22. 1. "TRIM,23bit trim for LIRC."
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line.long 0x8 "SYS_OSCTRIM0,Internal Oscillator Trim Register 0"
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bitfld.long 0x8 31. "EN2MHZ,1: Low Frequency mode of oscillator active (2MHz).. 0: High frequency mode (20-50MHz)" "0: High frequency mode,1: Low Frequency mode of oscillator active"
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hexmask.long.word 0x8 0.--15. 1. "TRIM,16bit sign extended representation of 10bit trim."
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line.long 0xC "SYS_OSCTRIM1,Internal Oscillator Trim Register 1"
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bitfld.long 0xC 31. "EN2MHZ,1: Low Frequency mode of oscillator active (2MHz).. 0: High frequency mode (20-50MHz)" "0: High frequency mode,1: Low Frequency mode of oscillator active"
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hexmask.long.word 0xC 0.--15. 1. "TRIM,16bit sign extended representation of 10bit trim."
|
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line.long 0x10 "SYS_OSCTRIM2,Internal Oscillator Trim Register 2"
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bitfld.long 0x10 31. "EN2MHZ,1: Low Frequency mode of oscillator active (2MHz).. 0: High frequency mode (20-50MHz)" "0: High frequency mode,1: Low Frequency mode of oscillator active"
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hexmask.long.word 0x10 0.--15. 1. "TRIM,16bit sign extended representation of 10bit trim."
|
|
line.long 0x14 "SYS_XTALTRIM,External Crystal Oscillator Trim Register"
|
|
bitfld.long 0x14 24.--25. "XGS,HXT Gain Select" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SELXT,HXT select external clock. 0: Disable. 1: Enable" "0: Disable,1: Enable"
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|
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|
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bitfld.long 0x14 9. "LOWPWR,1: low power mode. 0: normal mode." "0: normal mode,1: low power mode"
|
|
line.long 0x18 "Reserved,System Reserved. Keep POR Value"
|
|
tree.end
|
|
tree "SYSINFO (System Control Registers)"
|
|
base ad:0xE000ED00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SYSINFO_CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IMPCODE,Implementer Code Assigned by ARM."
|
|
hexmask.long.byte 0x0 16.--19. 1. "PART,ARMv6-m Parts. Reads as 0xC for ARMv6-M parts"
|
|
hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number. Reads as 0xC20."
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|
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hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision. Reads as 0x0"
|
|
group.long 0x4++0x3
|
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line.long 0x0 "SYSINFO_ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x0 31. "NMIPNSET,NMI Pending Set Control. Setting this bit will activate an NMI. Since NMI is the highest priority exception it will activate as soon as it is registered. Reads back with current state (1 if Pending 0 if not)." "0,1"
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|
bitfld.long 0x0 28. "PPSVISET,Set a Pending PendSV Interrupt. This is normally used to request a context switch. Reads back with current state (1 if Pending 0 if not)." "0,1"
|
|
bitfld.long 0x0 27. "PPSVICLR,Clear a Pending PendSV Interrupt. Write 1 to clear a pending PendSV interrupt." "0,1"
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|
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|
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bitfld.long 0x0 26. "PSTKISET,Set a Pending SYST. Reads back with current state (1 if Pending 0 if not)." "0,1"
|
|
bitfld.long 0x0 25. "PSTKICLR,Clear a Pending SYST. Write 1 to clear a pending SYST." "0,1"
|
|
bitfld.long 0x0 23. "ISRPREEM,ISR Preemptive. If set a pending exception will be serviced on exit from the debug halt state." "0,1"
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|
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bitfld.long 0x0 22. "ISRPEND,ISR Pending. Indicates if an external configurable (NVIC generated) interrupt is pending." "0,1"
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|
hexmask.long.word 0x0 12.--20. 1. "VTPEND,Vector Pending. Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A.."
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|
hexmask.long.word 0x0 0.--8. 1. "VTACT,Vector Active. 0: Thread mode. Value > 1: the exception number for the current executing exception."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "SYSINFO_AIRCTL,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VTKEY,Vector Key. The value 0x05FA must be written to this register otherwise. a write to register is UNPREDICTABLE."
|
|
bitfld.long 0x0 15. "ENDIANES,Endianness. Read Only. Reads 0 indicating little endian machine." "0,1"
|
|
bitfld.long 0x0 2. "SRSTREQ,System Reset Request. Writing 1 to this bit asserts a signal to request a reset by the external system." "0: do not request a reset,1: request reset"
|
|
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|
bitfld.long 0x0 1. "CLRACTVT,Clear All Active Vector. Clears all active state information for fixed and configurable exceptions.. The effect of writing a 1 to this bit if the processor is not halted in Debug is UNPREDICTABLE." "0: do not clear state information,1: clear state information"
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|
line.long 0x4 "SYSINFO_SCR,System Control Register"
|
|
bitfld.long 0x4 4. "SEVNONPN,Send Event on Pending Bit. When enabled interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.. When an event or interrupt enters pending state the event signal wakes up the processor.." "0: only enabled interrupts or events can wake-up..,1: enabled events and all interrupts including.."
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|
bitfld.long 0x4 2. "SLPDEEP,Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode. The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states." "0: sleep,1: deep sleep"
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|
bitfld.long 0x4 1. "SLPONEXC,Sleep on Exception. When set to 1 the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset the base level of execution. Setting this bit to 1 enables an interrupt driven.." "0,1"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "SYSINFO_SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x0 30.--31. "PRI11,Priority of System Handler 11 - SVCall. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x4 "SYSINFO_SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x4 30.--31. "PRI15,Priority of System Handler 15 - SYST. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PRI14,Priority of System Handler 14 - PendSV. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
tree.end
|
|
tree "SYSTICK (SysTick Timer)"
|
|
base ad:0xE000E000
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SYSTICK_CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,Count Flag. Returns 1 if timer counted to 0 since last time this register was read.." "0: Cleared on read or by a write to the Current..,1: Set by a count transition from 1 to 0"
|
|
bitfld.long 0x0 2. "CLKSRC,Clock Source." "0: Core clock unused,1: Core clock used for SysTick this bit will read.."
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|
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bitfld.long 0x0 1. "TICKINT,Enables SysTick Exception Request." "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause SysTick exception.."
|
|
bitfld.long 0x0 0. "ENABLE,ENABLE." "0: The counter is disabled,1: The counter will operate in a multi-shot manner"
|
|
line.long 0x4 "SYSTICK_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,SysTick Reload. Value to load into the Current Value register when the counter reaches 0.. To generate a multi-shot timer with a period of N processor clock cycles use a RELOAD value of N-1. For example if the SysTick interrupt is required every.."
|
|
line.long 0x8 "SYSTICK_CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current Counter Value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear.."
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|
tree.end
|
|
tree "TMR (Timer Controller)"
|
|
base ad:0x0
|
|
tree "TMR0"
|
|
base ad:0x40010000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TMRn_CTL,Timer Control and Status Register"
|
|
bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stops/Suspends counting,1: Starts counting"
|
|
bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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|
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The timer is operating in the one-shot mode. The..,1: The timer is operating in the periodic mode. The..,2: Reserved,3: The timer is operating in continuous counting.."
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bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of timer.." "0: Timer is not active,1: Timer is active"
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bitfld.long 0x0 16. "CNTDATEN,Data Latch Enable. When CNTDATEN is set TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting. ." "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Pre-scale Counter."
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line.long 0x4 "TMRn_CMP,Timer Compare Register"
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hexmask.long 0x4 0.--24. 1. "CMPDAT,Timer Comparison Value. NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. NOTE2: Regardless of CEN state whenever a new value is written to this register TIMER will restart counting using this new value and abort.."
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line.long 0x8 "TMRn_INTSTS,Timer Interrupt Status Register"
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1." "0,1"
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line.long 0xC "TMRn_CNT,Timer Data Register"
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register. When TIMERx_CTL.CNTDATEN is set to 1 the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value."
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tree.end
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tree "TMR1"
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base ad:0x40010020
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group.long 0x0++0xF
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line.long 0x0 "TMRn_CTL,Timer Control and Status Register"
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bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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newline
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The timer is operating in the one-shot mode. The..,1: The timer is operating in the periodic mode. The..,2: Reserved,3: The timer is operating in continuous counting.."
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bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of timer.." "0: Timer is not active,1: Timer is active"
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bitfld.long 0x0 16. "CNTDATEN,Data Latch Enable. When CNTDATEN is set TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting. ." "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Pre-scale Counter."
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line.long 0x4 "TMRn_CMP,Timer Compare Register"
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hexmask.long 0x4 0.--24. 1. "CMPDAT,Timer Comparison Value. NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. NOTE2: Regardless of CEN state whenever a new value is written to this register TIMER will restart counting using this new value and abort.."
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line.long 0x8 "TMRn_INTSTS,Timer Interrupt Status Register"
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1." "0,1"
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line.long 0xC "TMRn_CNT,Timer Data Register"
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hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register. When TIMERx_CTL.CNTDATEN is set to 1 the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value."
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tree.end
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tree.end
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tree "UART (Universal Asynchronous Receiver/Transmitter)"
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base ad:0x0
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tree "UART0"
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base ad:0x40050000
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group.long 0x0++0x33
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line.long 0x0 "UARTn_DAT,UART Receive/Transfer FIFO Register."
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive FIFO Register. Reading this register will return data from the receive data FIFO. By reading this register the UART will return the 8-bit data received from Rx pin (LSB first)."
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line.long 0x4 "UARTn_INTEN,UART Interrupt Enable Register."
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bitfld.long 0x4 15. "DMARXEN,Receive DMA Enable. If enabled the UART will request DMA service when data is available in receive FIFO." "0,1"
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bitfld.long 0x4 14. "DMATXEN,Transmit DMA Enable . If enabled the UART will request DMA service when space is available in transmit FIFO." "0,1"
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bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable . When CTS auto-flow is enabled the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted)." "0: Disable CTS auto flow control,1: Enable"
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bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable. When RTS auto-flow is enabled if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV the UART will de-assert the RTS signal." "0: Disable RTS auto flow control,1: Enable"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable." "0: Disable Time-out counter,1: Enable"
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bitfld.long 0x4 8. "LINIEN,LIN RX Break Field Detected Interrupt Enable." "0: Mask off Lin bus Rx break field interrupt,1: Enable Lin bus Rx break field interrupt"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable." "0: Mask off BUFERRINT,1: Enable IBUFERRINT"
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bitfld.long 0x4 4. "RXTOIEN,Receive Time Out Interrupt Enable." "0: Mask off RXTOINT,1: Enable RXTOINT"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable." "0: Mask off MODEMINT,1: Enable MODEMINT"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable ." "0: Mask off RLSINT,1: Enable RLSINT"
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bitfld.long 0x4 1. "THREIEN,Transmit FIFO Register Empty Interrupt Enable." "0: Mask off THERINT,1: Enable THERINT"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable." "0: Mask off RDAINT,1: Enable RDAINT"
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line.long 0x8 "UARTn_FIFO,UART FIFO Control Register."
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level for Auto-flow Control. Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).. Value : Trigger Level (Bytes). 0 :.."
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,Receive FIFO Interrupt (RDAINT) Trigger Level . When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and if enabled an RDAINT interrupt will generated.. Value : INTR_RDA Trigger Level.."
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bitfld.long 0x8 2. "TXRST,Transmit FIFO Reset. When TXRST is set all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.. Note: This bit will auto-clear after 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the transmit.."
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bitfld.long 0x8 1. "RXRST,Receive FIFO Reset. When RXRST is set all the bytes in the receive FIFO are cleared and receive internal state machine is reset.. Note: This bit will auto-clear after 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the receiving.."
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line.long 0xC "UARTn_LINE,UART Line Control Register."
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bitfld.long 0xC 6. "BCB,Break Control Bit . When this bit is set to logic 1 the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic." "0,1"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable ." "0: Disable stick parity,1: When bits PBE and SPE are set 'Stick Parity' is.."
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bitfld.long 0xC 4. "EPE,Even Parity Enable. This bit has effect only when PBE (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or..,1: Even number of logic 1's are transmitted or.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable." "0: Parity bit is not generated (transmit data) or..,1: Parity bit is generated or checked between the.."
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bitfld.long 0xC 2. "NSB,Number of STOP Bits." "0: One 'STOP bit' is generated after the..,1: Two 'STOP bits' are generated when 6- 7- and.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Select. 0 (5bits) 1(6bits) 2(7bits) 3(8bits)" "0,1,2,3"
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line.long 0x10 "UARTn_MODEM,UART Modem Control Register."
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rbitfld.long 0x10 13. "RTSSTS,RTS Pin State (Read Only). This bit is the pin status of RTS." "0,1"
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bitfld.long 0x10 9. "RTSACTLV,Request-to-send (RTS) Active Trigger Level. This bit can change the RTS trigger level.." "0: RTS is active low level,1: RTS is active high level"
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bitfld.long 0x10 4. "LBMEN,Loopback Mode Enable." "0: Disable,1: Enable"
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bitfld.long 0x10 1. "RTS,RTS (Request-to-send) Signal ." "0: Drive RTS inactive ( = ~RTSACTLV),1: Drive RTS active ( = RTSACTLV)"
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line.long 0x14 "UARTn_MODEMSTS,UART Modem Status Register."
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bitfld.long 0x14 8. "CTSACTLV,Clear-to-send (CTS) Active Trigger Level. This bit can change the CTS trigger level.." "0: CTS is active low level,1: CTS is active high level"
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rbitfld.long 0x14 4. "CTSSTS,CTS Pin Status (Read Only). This bit is the pin status of CTS." "0,1"
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newline
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bitfld.long 0x14 0. "CTSDETF,Detect CTS State Change Flag. NOTE: This bit is cleared by writing 1 to itself." "0,1"
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line.long 0x18 "UARTn_FIFOSTS,UART FIFO Status Register."
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty (Read Only). Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.. NOTE:.." "0,1"
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bitfld.long 0x18 24. "TXOVIF,Tx Overflow Error Interrupt Flag . If the Tx FIFO (UART_DAT) is full an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.. NOTE: This bit is.." "0,1"
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rbitfld.long 0x18 23. "TXFULL,Transmit FIFO Full (Read Only). This bit indicates whether the Tx FIFO is full or not.." "0,1"
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rbitfld.long 0x18 22. "TXEMPTY,Transmit FIFO Empty (Read Only). This bit indicates whether the Tx FIFO is empty or not.. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared after writing data to FIFO.." "0,1"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,Tx FIFO Pointer (Read Only). This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register TXPTR is decremented."
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rbitfld.long 0x18 15. "RXFULL,Receive FIFO Full (Read Only). This bit indicates whether the Rx FIFO is full or not.. This bit is set when Rx FIFO is full; otherwise it is cleared by hardware." "0,1"
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rbitfld.long 0x18 14. "RXEMPTY,Receive FIFO Empty (Read Only). This bit indicates whether the Rx FIFO is empty or not.. When the last byte of Rx FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,Rx FIFO Pointer (Read Only). This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device RXPTR is incremented. When one byte of Rx FIFO is read by.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag. This bit is set to a logic 1 whenever the receive data input (Rx) is held in the 'space' state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop bits). It.." "0,1"
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bitfld.long 0x18 5. "FEF,Framing Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic 0) and is reset whenever the CPU writes 1 to this.." "0,1"
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bitfld.long 0x18 4. "PEF,Parity Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit." "0,1"
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bitfld.long 0x18 0. "RXOVIF,Rx Overflow Error Interrupt Flag . If the Rx FIFO (UART_DAT) is full and an additional byte is received by the UART an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.." "0,1"
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line.long 0x1C "UARTn_INTSTS,UART Interrupt Status Register."
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bitfld.long 0x1C 31. "DLININT,DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF." "0,1"
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bitfld.long 0x1C 29. "DBERRINT,DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF." "0,1"
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bitfld.long 0x1C 28. "DRXTOINT,DMA MODE Time Out Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF." "0,1"
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bitfld.long 0x1C 27. "DMODEMI,DMA MODE MODEM Status Interrupt Indicator to Interrupt. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF." "0,1"
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bitfld.long 0x1C 26. "DRLSINT,DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF." "0,1"
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bitfld.long 0x1C 23. "DLINIF,DMA MODE LIN Bus Rx Break Field Detected Flag. This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1." "0,1"
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newline
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rbitfld.long 0x1C 21. "DBERRIF,DMA MODE Buffer Error Interrupt Flag (Read Only). This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is.." "0,1"
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rbitfld.long 0x1C 20. "DRXTOIF,DMA MODE Time Out Interrupt Flag (Read Only). This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be.." "0,1"
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rbitfld.long 0x1C 19. "DMODEMIF,DMA MODE MODEM Interrupt Flag (Read Only). NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1." "0,1"
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rbitfld.long 0x1C 18. "DRLSIF,DMA MODE Receive Line Status Interrupt Flag (Read Only). This bit is set when the Rx receive data has a parity framing or break error (at least one of UART_FIFOSTS.BIF UART_FIFOSTS.FEF and UART_FIFOSTS.PEF is set). If UART_INTEN.RLSIEN is.." "0,1"
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bitfld.long 0x1C 15. "LININT,LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.LINIEN and LINIF." "0,1"
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bitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator to Interrupt Controller . Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF." "0,1"
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newline
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bitfld.long 0x1C 12. "RXTOINT,Time Out Interrupt Indicator to Interrupt Controller . Logical AND of UART_INTEN.RXTOIEN and RXTOIF." "0,1"
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bitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator to Interrupt . Logical AND of UART_INTEN.MODEMIEN and MODENIF." "0,1"
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newline
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bitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator to Interrupt Controller . Logical AND of UART_INTEN.RLSIEN and RLSIF." "0,1"
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bitfld.long 0x1C 9. "THERINT,Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.THREIEN and THREIF." "0,1"
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newline
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bitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.RDAIEN and RDAIF." "0,1"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Rx Break Field Detected Flag. This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1." "0,1"
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newline
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled.." "0,1"
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rbitfld.long 0x1C 4. "RXTOIF,Time Out Interrupt Flag (Read Only). This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.. NOTE:.." "0,1"
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rbitfld.long 0x1C 3. "MODENIF,MODEM Interrupt Flag (Read Only). NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1." "0,1"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Status Interrupt Flag (Read Only). This bit is set when the Rx receive data has a parity framing or break error (at least one of UART_FIFOSTS.BIF UART_FIFOSTS.FEF and UART_FIFOSTS.PEF is set). If UART_INTEN.RLSIEN is enabled the.." "0,1"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled the THRE interrupt will be generated.. NOTE: This bit is read.." "0,1"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled the RDA interrupt will be generated. . NOTE: This bit is read only and it.." "0,1"
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line.long 0x20 "UARTn_TOUT,UART Time Out Register"
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hexmask.long.byte 0x20 0.--6. 1. "TOIC,Time Out Interrupt Comparator. The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC) a receiver time out.."
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line.long 0x24 "UARTn_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x24 29. "BAUDM1,Divider X Enable. Refer to Table 5116 UART Baud Rate Setting Table for more information.. NOTE: When in IrDA mode this bit must disabled." "0: Disable divider X ( M = 16),1: Enable divider X (M = EDIVM1+1 with EDIVM1 >= 8)"
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bitfld.long 0x24 28. "BAUDM0,Divider X Equal 1. Refer to Table 5116 UART Baud Rate Setting Table for more information." "0,1"
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newline
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Divider x."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider. Refer to Table 5116 UART Baud Rate Setting Table for more information."
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line.long 0x28 "UARTn_IRDA,UART IrDA Control Register."
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bitfld.long 0x28 6. "RXINV,Receive Inversion Enable." "0: No inversion,1: Invert Rx input signal"
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bitfld.long 0x28 5. "TXINV,Transmit Inversion Enable." "0: No inversion,1: Invert Tx output signal"
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newline
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bitfld.long 0x28 2. "LOOPBACK,IrDA Loopback Test Mode. Loopback Tx to Rx." "0,1"
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bitfld.long 0x28 1. "TXEN,Transmit/Receive Selection." "0: Enable IrDA receiver,1: Enable IrDA transmitter"
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line.long 0x2C "UARTn_ALTCTL,UART LIN Control Register."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable. NOTE: When Tx break field transfer operation finished this bit will be cleared automatically." "0: Disable LIN Tx Break Mode,1: Enable LIN Tx Break Mode"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable." "0: Disable LIN Rx mode,1: Enable LIN Rx mode"
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newline
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length Count. This field indicates a 4-bit LIN Tx break field count.. NOTE: This break field length is BRKFL + 2"
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line.long 0x30 "UARTn_FUNCSEL,UART Function Select Register."
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bitfld.long 0x30 1. "IRDAEN,Enable IrDA Function." "0: UART Function,1: Enable IrDA Function"
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bitfld.long 0x30 0. "LINEN,Enable LIN Function. Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time." "0: UART Function,1: Enable LIN Function"
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tree.end
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tree "UART1"
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base ad:0x40058000
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group.long 0x0++0x33
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line.long 0x0 "UARTn_DAT,UART Receive/Transfer FIFO Register."
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive FIFO Register. Reading this register will return data from the receive data FIFO. By reading this register the UART will return the 8-bit data received from Rx pin (LSB first)."
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line.long 0x4 "UARTn_INTEN,UART Interrupt Enable Register."
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bitfld.long 0x4 15. "DMARXEN,Receive DMA Enable. If enabled the UART will request DMA service when data is available in receive FIFO." "0,1"
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bitfld.long 0x4 14. "DMATXEN,Transmit DMA Enable . If enabled the UART will request DMA service when space is available in transmit FIFO." "0,1"
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newline
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bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable . When CTS auto-flow is enabled the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted)." "0: Disable CTS auto flow control,1: Enable"
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bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable. When RTS auto-flow is enabled if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV the UART will de-assert the RTS signal." "0: Disable RTS auto flow control,1: Enable"
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newline
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable." "0: Disable Time-out counter,1: Enable"
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bitfld.long 0x4 8. "LINIEN,LIN RX Break Field Detected Interrupt Enable." "0: Mask off Lin bus Rx break field interrupt,1: Enable Lin bus Rx break field interrupt"
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newline
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable." "0: Mask off BUFERRINT,1: Enable IBUFERRINT"
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bitfld.long 0x4 4. "RXTOIEN,Receive Time Out Interrupt Enable." "0: Mask off RXTOINT,1: Enable RXTOINT"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable." "0: Mask off MODEMINT,1: Enable MODEMINT"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable ." "0: Mask off RLSINT,1: Enable RLSINT"
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bitfld.long 0x4 1. "THREIEN,Transmit FIFO Register Empty Interrupt Enable." "0: Mask off THERINT,1: Enable THERINT"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable." "0: Mask off RDAINT,1: Enable RDAINT"
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line.long 0x8 "UARTn_FIFO,UART FIFO Control Register."
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level for Auto-flow Control. Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).. Value : Trigger Level (Bytes). 0 :.."
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,Receive FIFO Interrupt (RDAINT) Trigger Level . When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and if enabled an RDAINT interrupt will generated.. Value : INTR_RDA Trigger Level.."
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bitfld.long 0x8 2. "TXRST,Transmit FIFO Reset. When TXRST is set all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.. Note: This bit will auto-clear after 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the transmit.."
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bitfld.long 0x8 1. "RXRST,Receive FIFO Reset. When RXRST is set all the bytes in the receive FIFO are cleared and receive internal state machine is reset.. Note: This bit will auto-clear after 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the receiving.."
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line.long 0xC "UARTn_LINE,UART Line Control Register."
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bitfld.long 0xC 6. "BCB,Break Control Bit . When this bit is set to logic 1 the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic." "0,1"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable ." "0: Disable stick parity,1: When bits PBE and SPE are set 'Stick Parity' is.."
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bitfld.long 0xC 4. "EPE,Even Parity Enable. This bit has effect only when PBE (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or..,1: Even number of logic 1's are transmitted or.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable." "0: Parity bit is not generated (transmit data) or..,1: Parity bit is generated or checked between the.."
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bitfld.long 0xC 2. "NSB,Number of STOP Bits." "0: One 'STOP bit' is generated after the..,1: Two 'STOP bits' are generated when 6- 7- and.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Select. 0 (5bits) 1(6bits) 2(7bits) 3(8bits)" "0,1,2,3"
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line.long 0x10 "UARTn_MODEM,UART Modem Control Register."
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rbitfld.long 0x10 13. "RTSSTS,RTS Pin State (Read Only). This bit is the pin status of RTS." "0,1"
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bitfld.long 0x10 9. "RTSACTLV,Request-to-send (RTS) Active Trigger Level. This bit can change the RTS trigger level.." "0: RTS is active low level,1: RTS is active high level"
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bitfld.long 0x10 4. "LBMEN,Loopback Mode Enable." "0: Disable,1: Enable"
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bitfld.long 0x10 1. "RTS,RTS (Request-to-send) Signal ." "0: Drive RTS inactive ( = ~RTSACTLV),1: Drive RTS active ( = RTSACTLV)"
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line.long 0x14 "UARTn_MODEMSTS,UART Modem Status Register."
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bitfld.long 0x14 8. "CTSACTLV,Clear-to-send (CTS) Active Trigger Level. This bit can change the CTS trigger level.." "0: CTS is active low level,1: CTS is active high level"
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rbitfld.long 0x14 4. "CTSSTS,CTS Pin Status (Read Only). This bit is the pin status of CTS." "0,1"
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bitfld.long 0x14 0. "CTSDETF,Detect CTS State Change Flag. NOTE: This bit is cleared by writing 1 to itself." "0,1"
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line.long 0x18 "UARTn_FIFOSTS,UART FIFO Status Register."
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty (Read Only). Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.. NOTE:.." "0,1"
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bitfld.long 0x18 24. "TXOVIF,Tx Overflow Error Interrupt Flag . If the Tx FIFO (UART_DAT) is full an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.. NOTE: This bit is.." "0,1"
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rbitfld.long 0x18 23. "TXFULL,Transmit FIFO Full (Read Only). This bit indicates whether the Tx FIFO is full or not.." "0,1"
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rbitfld.long 0x18 22. "TXEMPTY,Transmit FIFO Empty (Read Only). This bit indicates whether the Tx FIFO is empty or not.. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared after writing data to FIFO.." "0,1"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,Tx FIFO Pointer (Read Only). This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register TXPTR is decremented."
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rbitfld.long 0x18 15. "RXFULL,Receive FIFO Full (Read Only). This bit indicates whether the Rx FIFO is full or not.. This bit is set when Rx FIFO is full; otherwise it is cleared by hardware." "0,1"
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rbitfld.long 0x18 14. "RXEMPTY,Receive FIFO Empty (Read Only). This bit indicates whether the Rx FIFO is empty or not.. When the last byte of Rx FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,Rx FIFO Pointer (Read Only). This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device RXPTR is incremented. When one byte of Rx FIFO is read by.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag. This bit is set to a logic 1 whenever the receive data input (Rx) is held in the 'space' state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop bits). It.." "0,1"
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bitfld.long 0x18 5. "FEF,Framing Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as a logic 0) and is reset whenever the CPU writes 1 to this.." "0,1"
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bitfld.long 0x18 4. "PEF,Parity Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit." "0,1"
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bitfld.long 0x18 0. "RXOVIF,Rx Overflow Error Interrupt Flag . If the Rx FIFO (UART_DAT) is full and an additional byte is received by the UART an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.." "0,1"
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line.long 0x1C "UARTn_INTSTS,UART Interrupt Status Register."
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bitfld.long 0x1C 31. "DLININT,DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF." "0,1"
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bitfld.long 0x1C 29. "DBERRINT,DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF." "0,1"
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bitfld.long 0x1C 28. "DRXTOINT,DMA MODE Time Out Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF." "0,1"
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bitfld.long 0x1C 27. "DMODEMI,DMA MODE MODEM Status Interrupt Indicator to Interrupt. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF." "0,1"
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bitfld.long 0x1C 26. "DRLSINT,DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF." "0,1"
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bitfld.long 0x1C 23. "DLINIF,DMA MODE LIN Bus Rx Break Field Detected Flag. This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1." "0,1"
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rbitfld.long 0x1C 21. "DBERRIF,DMA MODE Buffer Error Interrupt Flag (Read Only). This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is.." "0,1"
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rbitfld.long 0x1C 20. "DRXTOIF,DMA MODE Time Out Interrupt Flag (Read Only). This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be.." "0,1"
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rbitfld.long 0x1C 19. "DMODEMIF,DMA MODE MODEM Interrupt Flag (Read Only). NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1." "0,1"
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rbitfld.long 0x1C 18. "DRLSIF,DMA MODE Receive Line Status Interrupt Flag (Read Only). This bit is set when the Rx receive data has a parity framing or break error (at least one of UART_FIFOSTS.BIF UART_FIFOSTS.FEF and UART_FIFOSTS.PEF is set). If UART_INTEN.RLSIEN is.." "0,1"
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bitfld.long 0x1C 15. "LININT,LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.LINIEN and LINIF." "0,1"
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bitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator to Interrupt Controller . Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF." "0,1"
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bitfld.long 0x1C 12. "RXTOINT,Time Out Interrupt Indicator to Interrupt Controller . Logical AND of UART_INTEN.RXTOIEN and RXTOIF." "0,1"
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bitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator to Interrupt . Logical AND of UART_INTEN.MODEMIEN and MODENIF." "0,1"
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bitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator to Interrupt Controller . Logical AND of UART_INTEN.RLSIEN and RLSIF." "0,1"
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bitfld.long 0x1C 9. "THERINT,Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.THREIEN and THREIF." "0,1"
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bitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator to Interrupt Controller. Logical AND of UART_INTEN.RDAIEN and RDAIF." "0,1"
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bitfld.long 0x1C 7. "LINIF,LIN Bus Rx Break Field Detected Flag. This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1." "0,1"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled.." "0,1"
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rbitfld.long 0x1C 4. "RXTOIF,Time Out Interrupt Flag (Read Only). This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.. NOTE:.." "0,1"
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rbitfld.long 0x1C 3. "MODENIF,MODEM Interrupt Flag (Read Only). NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1." "0,1"
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rbitfld.long 0x1C 2. "RLSIF,Receive Line Status Interrupt Flag (Read Only). This bit is set when the Rx receive data has a parity framing or break error (at least one of UART_FIFOSTS.BIF UART_FIFOSTS.FEF and UART_FIFOSTS.PEF is set). If UART_INTEN.RLSIEN is enabled the.." "0,1"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled the THRE interrupt will be generated.. NOTE: This bit is read.." "0,1"
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rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled the RDA interrupt will be generated. . NOTE: This bit is read only and it.." "0,1"
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line.long 0x20 "UARTn_TOUT,UART Time Out Register"
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hexmask.long.byte 0x20 0.--6. 1. "TOIC,Time Out Interrupt Comparator. The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC) a receiver time out.."
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line.long 0x24 "UARTn_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x24 29. "BAUDM1,Divider X Enable. Refer to Table 5116 UART Baud Rate Setting Table for more information.. NOTE: When in IrDA mode this bit must disabled." "0: Disable divider X ( M = 16),1: Enable divider X (M = EDIVM1+1 with EDIVM1 >= 8)"
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bitfld.long 0x24 28. "BAUDM0,Divider X Equal 1. Refer to Table 5116 UART Baud Rate Setting Table for more information." "0,1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Divider x."
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hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider. Refer to Table 5116 UART Baud Rate Setting Table for more information."
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line.long 0x28 "UARTn_IRDA,UART IrDA Control Register."
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bitfld.long 0x28 6. "RXINV,Receive Inversion Enable." "0: No inversion,1: Invert Rx input signal"
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bitfld.long 0x28 5. "TXINV,Transmit Inversion Enable." "0: No inversion,1: Invert Tx output signal"
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bitfld.long 0x28 2. "LOOPBACK,IrDA Loopback Test Mode. Loopback Tx to Rx." "0,1"
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bitfld.long 0x28 1. "TXEN,Transmit/Receive Selection." "0: Enable IrDA receiver,1: Enable IrDA transmitter"
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line.long 0x2C "UARTn_ALTCTL,UART LIN Control Register."
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bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable. NOTE: When Tx break field transfer operation finished this bit will be cleared automatically." "0: Disable LIN Tx Break Mode,1: Enable LIN Tx Break Mode"
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bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable." "0: Disable LIN Rx mode,1: Enable LIN Rx mode"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length Count. This field indicates a 4-bit LIN Tx break field count.. NOTE: This break field length is BRKFL + 2"
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line.long 0x30 "UARTn_FUNCSEL,UART Function Select Register."
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bitfld.long 0x30 1. "IRDAEN,Enable IrDA Function." "0: UART Function,1: Enable IrDA Function"
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bitfld.long 0x30 0. "LINEN,Enable LIN Function. Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time." "0: UART Function,1: Enable LIN Function"
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tree.end
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tree.end
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tree "VOLCTRL (Volume Control)"
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base ad:0x400B00A0
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group.long 0x0++0xB
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line.long 0x0 "VOLCTRL_EN,Volume Control Enable Register"
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bitfld.long 0x0 3. "DPWMZCEN,DPWM Audio Signal Volume Zero Crossing Enable." "0: disable zero crossing update gain,1: enable Zero crossing update gain"
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bitfld.long 0x0 2. "SDADCZCEN,Delta-Sigma ADC Signal Volume Zero Crossing Enable." "0: disable zero crossing update gain,1: enable Zero crossing update gain"
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bitfld.long 0x0 1. "DPWMVOLEN,DPWM Audio Signal Volume Control Enable." "0: bypass the volume control function,1: enable the volume control function"
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bitfld.long 0x0 0. "SDADCVOLEN,Delta-Sigma ADC Signal Volume Control Enable." "0: bypass the volume control function,1: enable the volume control function"
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line.long 0x4 "VOLCTRL_ADCVAL,ADC Volume Control Value"
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hexmask.long.tbyte 0x4 0.--23. 1. "VALUE,Delta-Sigma ADC Signal Volume Control Value."
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line.long 0x8 "VOLCTRL_DPWMVAL,DPWM Volume Control Value"
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hexmask.long.tbyte 0x8 0.--23. 1. "VALUE,DPWM Audio Signal Volume Control Value."
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tree.end
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tree "WDT (Watchdog Timer)"
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base ad:0x40004000
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group.long 0x0++0x3
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line.long 0x0 "WDT_CTL,Watchdog Timer Control Register"
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bitfld.long 0x0 8.--10. "TOUTSEL,Watchdog Timer Interval Select. These three bits select the timeout interval for the Watchdog timer a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by:. Where WDT_CLK is the period of the Watchdog Timer.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 7. "WDTEN,Watchdog Timer Enable." "0: Disable the Watchdog timer (This action will..,1: Enable the Watchdog timer"
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bitfld.long 0x0 6. "INTEN,Watchdog Timer Interrupt Enable." "0: Disable the Watchdog timer interrupt,1: Enable the Watchdog timer interrupt"
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bitfld.long 0x0 3. "IF,Watchdog Timer Interrupt Flag. If the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled then this bit indicates that a.." "0: Watchdog timer interrupt has not occurred,1: Watchdog timer interrupt has occurred"
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bitfld.long 0x0 2. "RSTF,Watchdog Timer Reset Flag. When the Watchdog timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is.." "0: Watchdog timer reset has not occurred,1: Watchdog timer reset has occurred"
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bitfld.long 0x0 1. "RSTEN,Watchdog Timer Reset Enable. Setting this bit will enable the Watchdog timer reset function.." "0: Disable Watchdog timer reset function,1: Enable Watchdog timer reset function"
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bitfld.long 0x0 0. "RSTCNT,Clear Watchdog Timer . Set this bit will clear the Watchdog timer. . NOTE: This bit will auto clear after few clock cycle" "0: Writing 0 to this bit has no effect,1: Reset the contents of the Watchdog timer"
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tree.end
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AUTOINDENT.OFF
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