1925 lines
116 KiB
Plaintext
1925 lines
116 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: XSCALE IXP421 on chip peripherals
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; @Props:
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; @Author: -
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; @Changelog:
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; @Manufacturer:
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; @Doc:
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; @Core:
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; @Chip:
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; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peri421.per 16518 2023-08-17 13:49:43Z kwisniewski $
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config 16. 8.
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width 8.
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;begin include file xscale/cp15.ph
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;parameters:
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; --------------------------------------------------------------------------------
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; 80200, 80321, IXP2400, IXP2800, PXA210, PXA250, PXA800F
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; not impl.: IXP425, IXP2850, IXC1100, Bulverde
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tree "CP15"
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; State: ok
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; --------------------------------------------------------------------------------
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; --------------------------------------------------------------------------------
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; *** Intel 80200 ***
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; --------------------------------------------------------------------------------
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if (d.l(c15:0x0)&0xffffe3f0)==0x69052000
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80200,80200"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,A-1,B-0,C-0,D-0,res,res,res,res,res,res,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel 80321 or IOP321 (Verde) ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80321 (400MHz),80321 (600MHz)"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,B-0,B-1,res,res,res,res,res,res,res,res,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel 80331 or IOP331 (Dobson) ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x69054090
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80331,80331"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-1,res,res,res,B-0,res,C-0,C-1,res,res,D-0,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel 80332 or IOP332 ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x69054010
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80332,80332"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-1/A-2,res,res,res,B-0,res,C-0,C-1,res,res,D-0,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel PXA210 (Sabinal), PXA250 (Cotulla) ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "PXA250,PXA210"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,A-1,B-0,B-1,B-2,C-0,res,res,res,res,res,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel PXA27x (Bulverde) ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x69054110
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "PXA27x,PXA27x"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,A-1,B-0,B-1,C-0,res,res,C-5,res,res,res,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel IXP2400 (Sausolito), IXP2800 (Castine) ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffffe3f0)==0x690541a0
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 12.--15. "CoreGen ,Core Generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 8.--11. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
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textline " "
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bitfld.long 0x0 4.--7. "ProdNum ,Product Number" "res,res,res,res,res,res,res,res,res,IXP2400,IXP2800,res,res,res,res,res"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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; --------------------------------------------------------------------------------
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; *** Intel PXA800F (Manitoba) ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "PXA800F,PXA800F"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** Intel IXP4xx, IXC1100 ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe3f0)==0x690541f0
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res"
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "IXP4xx/IXC1100,IXP4xx/IXC1100"
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bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res"
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; --------------------------------------------------------------------------------
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; *** other Intel XScale V5TE ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe000)==0x69052000
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--23. " Arch ,Architecture Version" ",V4,V4T,V5,V5T,V5TE,?..."
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textline " "
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bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8"
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textline " "
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hexmask.long 0x0 4.--9. 1. "ProdNum ,Product Number"
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hexmask.long 0x0 0.--3. 1. " ProdRev ,Product Revision"
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; --------------------------------------------------------------------------------
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; *** other Intel XScale V5TE ***
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; --------------------------------------------------------------------------------
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elif (d.l(c15:0x0)&0xffffe000)==0x69054000
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel"
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bitfld.long 0x0 16.--23. " Arch ,Architecture Version" ",V4,V4T,V5,V5T,V5TE,?..."
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textline " "
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bitfld.long 0x0 12.--12. "CoreGen ,Core Generation" "XScale,XScale"
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bitfld.long 0x0 8.--11. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
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textline " "
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hexmask.long 0x0 4.--7. 1. "ProdNum ,Product Number"
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hexmask.long 0x0 0.--3. 1. " ProdRev ,Product Revision"
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; --------------------------------------------------------------------------------
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; *** any else ***
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; --------------------------------------------------------------------------------
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else
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group c15:0x0--0x0
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line.long 0x0 "ID,ID Register (read only)"
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; 0x41 = ARM, 0x44 = Digital, 0x69 = Intel
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hexmask.long 0x0 24.--31. 1. "Implementor ,Implementation Trademark"
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hexmask.long 0x0 20.--23. 1. " Variant ,Implementation defined variant number"
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textline " "
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hexmask.long 0x0 16.--19. 1. "Architecture ,Architecture Version Code"
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hexmask.long 0x0 13.--15. 1. " Primary part number ,Core Generation"
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textline " "
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hexmask.long 0x0 0.--3. 1. "Revision ,Product Revision"
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endif
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; --------------------------------------------------------------------------------
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group c15:0x100--0x100
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line.long 0x0 "CTYPE,Cache Type Register (read only)"
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bitfld.long 0x0 25.--28. "CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--20. "DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k"
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--8. "ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k"
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x1--0x1
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 13. "V ,Exception Vector Relocation" "0x00000000,0xffff0000"
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bitfld.long 0x0 12. " I ,Instruction Cache" "disable,enable"
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bitfld.long 0x0 11. " Z ,Branch Target Buffer" "disable,enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "off,on"
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bitfld.long 0x0 8. " S ,System Protection" "off,on"
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textline " "
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bitfld.long 0x0 7. "B ,Endianism" "little,big"
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bitfld.long 0x0 2. " C ,Data Cache" "disable,enable"
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bitfld.long 0x0 1. " A ,Alignment Fault" "disable,enable"
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bitfld.long 0x0 0. " M ,Memory Management Unit" "disable,enable"
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group c15:0x101--0x101
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line.long 0x0 "AuxCR,Auxiliary Control Register"
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bitfld.long 0x0 4.--5. "MD ,Mini Data Cache Attributes" "write back - read allocate,write back - read/write allocate,write through - read allocate,unpredictable"
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bitfld.long 0x0 1. " P ,Page Table Memory Attribute" "0,1"
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bitfld.long 0x0 0. " K ,Write Buffer Coalescing Disable" "enable,disable"
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group c15:0x2--0x2
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line.long 0x0 "TTB,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 "TTBA ,Translation Table Base Address"
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group c15:0x3--0x3
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line.long 0x0 "DAC,Domain Access Control Register"
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bitfld.long 0x0 30.--31. "D15 ,Domain Access 15" "no access,client,reserved,manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "no access,client,reserved,manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "no access,client,reserved,manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "no access,client,reserved,manager"
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textline " "
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bitfld.long 0x0 22.--23. "D11 ,Domain Access 11" "no access,client,reserved,manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "no access,client,reserved,manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "no access,client,reserved,manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "no access,client,reserved,manager"
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textline " "
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bitfld.long 0x0 14.--15. "D7 ,Domain Access 7" "no access,client,reserved,manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "no access,client,reserved,manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "no access,client,reserved,manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "no access,client,reserved,manager"
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textline " "
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bitfld.long 0x0 6.--7. "D3 ,Domain Access 3" "no access,client,reserved,manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "no access,client,reserved,manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "no access,client,reserved,manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "no access,client,reserved,manager"
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group c15:0x5--0x5
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line.long 0x0 "FSR,Fault Status Register"
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bitfld.long 0x0 10. "X ,Status Field Extension" "0,1"
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bitfld.long 0x0 9. " D ,Debug event" "no,yes"
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bitfld.long 0x0 4.--7. " Domain ,Domain for Data Abort" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " Status ,Status X=0/X=1" "reserved/IMMU Exception,alignment/reserved,reserved,alignment/reserved,reserved/lock abort,transl_sect/reserved,reserved/external,transl_page,reserved/cache parity,domain_sect/reserved,reserved,domain_page,trans_lev_1/reserved,permission_sect/reserved,trans_lev_2/reserved,permission_page"
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group c15:0x6--0x6
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line.long 0x0 "FAR,Fault Address Registerr"
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group c15:0x29--0x29
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line.long 0x0 "DCLR, Data Cache Lock Register"
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bitfld.long 0x0 0. "L ,Data Cache Lock Register" "no locking,fill with lock"
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group c15:0xd--0xd
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line.long 0x0 "PID,Process Identifier"
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hexmask.long 0x0 25.--31. 0x2000000 "PID ,Process Identifier"
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group c15:0x8e--0x8e
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line.long 0x0 "IBCR0,Inctruction Breakpoint Register 0"
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hexmask.long 0x0 1.--31. 2. "MVA ,Instruction Breakpoint MVA"
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bitfld.long 0x0 0. " E ,Breakpoint Enable" "disable,enable"
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group c15:0x9e--0x9e
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line.long 0x0 "IBCR1,Inctruction Breakpoint Register 1"
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hexmask.long 0x0 1.--31. 2. "MVA ,Instruction Breakpoint MVA"
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bitfld.long 0x0 0. " E ,Breakpoint Enable" "disable,enable"
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group c15:0x0e--0x0e
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line.long 0x0 "DBR0,Data Breakpoint Register 0"
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group c15:0x3e--0x3e
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line.long 0x0 "DBR1,Data Breakpoint Register 1"
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group c15:0x4e--0x4e
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line.long 0x0 "DBCON,Data Breakpoint Configuration Register"
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bitfld.long 0x0 8. "M ,DBR1 Mode" "Data Breakpoint Address,Data Address Mask"
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bitfld.long 0x0 2.--3. " E1 ,DBR1 Breakpoint Enable" "disable,enable store,enable load/store,enable load"
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bitfld.long 0x0 0.--1. " E0 ,DBR0 Enable" "disable,enable store,enable load/store,enable load"
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; --------------------------------------------------------------------------------
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; *** Intel 80200 ***
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; --------------------------------------------------------------------------------
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if (d.l(c15:0x0)&0xffffe3f0)==0x69052000
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group c15:0x1f--0x1f
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line.long 0x0 "CPAR,Coprocessor Access Register"
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bitfld.long 0x0 13. "CP13 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel 80321 (IOP321) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 13. "CP13 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 7. " CP7 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 6. " CP6 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel PXA210, PXA250 (Sabinal, Cotulla) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 7. "CP7 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel PXA27x (Bulverde) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69054110
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 1. "CP1 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel (Manitoba) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel IXP2400, IXP2800 (Sausolito, Castine) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffff41a0)==0x69052120
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 7. "CP7 ,Coprocessor Access Rights" "denied,allowed"
|
|
bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** other Intel XScale V5TE ***
|
|
; *** includes XScale IXP425, because no product ID is available now ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe000)==0x69054000
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** other Intel XScale V5TE ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe000)==0x69052000
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
; *** any else ***
|
|
; --------------------------------------------------------------------------------
|
|
else
|
|
group c15:0x1f--0x1f
|
|
line.long 0x0 "CPAR,Coprocessor Access Register"
|
|
bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed"
|
|
; --------------------------------------------------------------------------------
|
|
endif
|
|
tree.end
|
|
;end include file xscale/cp15.ph
|
|
;begin include file xscale/cp14.ph
|
|
;parameters:
|
|
; --------------------------------------------------------------------------------
|
|
; 80200, PXA210, PXA250
|
|
; not impl.: 80321, IXP425, IXP2400, IXP2800, Bulverde, Manitoba
|
|
tree "CP14"
|
|
; State: preliminary
|
|
; --------------------------------------------------------------------------------
|
|
group c14:0x00--0x03 "Performance Monitoring"
|
|
line.long 4*0x00 "PMNC, Performance Monitor control Register"
|
|
bitfld.long 4*0x00 20.--27. "EvtCnt1 ,Source of Events that PMN1 counts" "IC miss ext,IC no inst,Data stall,ITLB miss,DTLB miss,Branch,Branch mispr,Inst exec,DC full every,DC full once,DC acc,DC miss,DC wback,SW changed PC,res,res,BCU requ,BCU que full,BCU que drain,res,unlogged ECC,BCU 1-bit err,RMW,?..."
|
|
bitfld.long 4*0x00 12.--19. " EvtCnt0 ,Source of Events that PMN0 counts" "IC miss ext,IC no inst,Data stall,ITLB miss,DTLB miss,Branch,Branch mispr,Inst exec,DC full every,DC full once,DC acc,DC miss,DC wback,SW changed PC,res,res,BCU requ,BCU que full,BCU que drain,res,unlogged ECC,BCU 1-bit err,RMW,?..."
|
|
textline " "
|
|
bitfld.long 4*0x00 10. "CCNT-OV ,Clock Counter Overflow Flag" "no,yes"
|
|
bitfld.long 4*0x00 9. " PMN1-OV ,Performace Counter 1 Overflow Flag" "no,yes"
|
|
bitfld.long 4*0x00 8. " PMN0-OV ,Performace Counter 0 Overflow Flag" "no,yes"
|
|
textline " "
|
|
bitfld.long 4*0x00 6. "CCNT-IE ,Clock Counter Interrupt" "disable,enable"
|
|
bitfld.long 4*0x00 5. " PMN1-IE ,Performace Counter 1 Interrupt" "disable,enable"
|
|
bitfld.long 4*0x00 4. " PMN0-IE ,Performace Counter 0 Interrupt" "disable,enable"
|
|
textline " "
|
|
bitfld.long 4*0x00 3. "D ,Clock Count Divider" "1,64"
|
|
bitfld.long 4*0x00 2. " C ,Clock Counter Reset" "no action,reset to 0"
|
|
bitfld.long 4*0x00 1. " P ,Performace Counter Reset (both)" "no action,reset to 0"
|
|
bitfld.long 4*0x00 0. " E ,Enable all 3 Counters" "disable,enable"
|
|
line.long 4*0x01 "CCNT, 32-bit clock counter"
|
|
line.long 4*0x02 "PMN0, 32-bit event counter"
|
|
line.long 4*0x03 "PMN1, 32-bit event counter"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel 80200 ***
|
|
; --------------------------------------------------------------------------------
|
|
if (d.l(c15:0x0)&0xffffe3f0)==0x69052000
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
bitfld.long 4*0x00 0.--3. "CCLKCFG ,Core Clock Configuration" "res,3,4,5,6,7,8,9,res,res,res,res,res,res,res,res"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,IDLE,res,SLEEP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel 80321 or IOP321 (Verde) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel PXA210, PXA250 (Sabinal, Cotulla) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
bitfld.long 4*0x00 1.--1. "FCS ,Frequency Change Sequence" "do not enter,enter"
|
|
bitfld.long 4*0x00 0.--0. " TURBO ,Turbo Mode" "exit,enter"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "Run/Turbo,Idle,res,Sleep/Deep Sleep"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel (Bulverde) ***
|
|
; --------------------------------------------------------------------------------
|
|
; wrong Product ID in developer's manual revision 0.1 (ID of PXA250!!!)
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel IXP2400, IXP2800 (Sausolito, Castine) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffffe3f0)==0x690541a0
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** Intel (Manitoba) ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** other Intel XScale V5TE ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe000)==0x69052000
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** other Intel XScale V5TE ***
|
|
; *** includes XScale IXP425 ***
|
|
; --------------------------------------------------------------------------------
|
|
elif (d.l(c15:0x0)&0xffffe000)==0x69054000
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
; --------------------------------------------------------------------------------
|
|
; *** any other XScale ***
|
|
; --------------------------------------------------------------------------------
|
|
else
|
|
group c14:0x06--0x07 "Clock and Power Management"
|
|
line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register"
|
|
line.long 4*0x01 "PWRMODE,Power Management Register"
|
|
bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP"
|
|
endif
|
|
group c14:0x08--0x0d "Software Debug"
|
|
line.long 4*0x02 "DCSR,Debug Control and Status Register"
|
|
bitfld.long 4*0x02 31. "GE ,Global Enable" "disable,enable"
|
|
bitfld.long 4*0x02 30. " H ,Halt Mode" "Monitor Mode,Halt Mode"
|
|
textline " "
|
|
bitfld.long 4*0x02 23. "TF ,Trap FIQ" "disable,enable"
|
|
bitfld.long 4*0x02 22. " TI ,Trap IRQ" "disable,enable"
|
|
bitfld.long 4*0x02 20. " TD ,Trap Data Abort" "disable,enable"
|
|
textline " "
|
|
bitfld.long 4*0x02 19. "TA ,Trap Prefetch Abort" "disable,enable"
|
|
bitfld.long 4*0x02 18. " TS ,Trap Software Interrupt" "disable,enable"
|
|
bitfld.long 4*0x02 17. " TU ,Trap Undefined Instruction" "disable,enable"
|
|
bitfld.long 4*0x02 16. " TR ,Trap Reset" "disable,enable"
|
|
textline " "
|
|
bitfld.long 4*0x02 5. "SA ,Sticky Abort" "no,yes"
|
|
bitfld.long 4*0x02 2.--4. " MOE ,Method of Entry" "Reset,Inst Bkpt, Data Bkpt, BKPT Inst, Ext Debug Event, Vector Trap, Trace Buffer full, reserved"
|
|
bitfld.long 4*0x02 1. " M ,Trace Buffer Mode" "wrap around,fill-once"
|
|
bitfld.long 4*0x02 0. " E ,Trace Buffer Enable" "no,yes"
|
|
line.long 4*0x04 "CHKPT0,Checkpoint 0 Register"
|
|
line.long 4*0x05 "CHKPT1,Checkpoint 1 Register"
|
|
tree.end
|
|
;end include file xscale/cp14.ph
|
|
width 22.
|
|
;begin include file xscale/ixp4xx-pci.ph
|
|
;parameters:
|
|
tree "PCI_CONF_STA (PCI Controller Configuration and Status Registers)"
|
|
base ASD:0xC0000000
|
|
group 0x00++0x3
|
|
line.long 0x00 " pci_np_ad,PCI non-pre-fetch address register"
|
|
group 0x04++0x3
|
|
line.long 0x00 " pci_np_cbe,PCI non-pre-fetch command/byte enables register"
|
|
bitfld.long 0x00 4.--7. " NP_BE ,Byte enables driven onto C/BE[3:0] lines of PCI bus during data phase of non-pre-fetch PCI access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " NP_CMD ,PCI command driven onto C/BE[3:0] lines of PCI bus during address phase of non-prefetch PCI access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group 0x08++0x3
|
|
line.long 0x00 " pci_np_wdata,PCI non-pre-fetch write data register"
|
|
rgroup 0x0C++0x3
|
|
line.long 0x00 " pci_np_rdata,PCI non-pre-fetch read data register"
|
|
group 0x10++0x3
|
|
line.long 0x00 " pci_crp_ad_cbe,PCI configuration port address/cmd/byte enables register"
|
|
bitfld.long 0x00 20.--23. " CRP_BE ,Active-low byte enables for a PCI configuration port write access" "Bit[7:0],Bit[15:8],Bit[ 23:16],Bit[31:24],?..."
|
|
bitfld.long 0x00 16.--19. " CRP_CMD ,Command for the PCI configuration port access" "Read,Write,Read,Write,Read,Write,Read,Write,Read,Write,Read,Write,Read,Write,Read,Write"
|
|
hexmask.long 0x00 0.--10. 1. " CRP_AD ,Byte address for the PCI configuration port access"
|
|
group 0x14++0x3
|
|
line.long 0x00 " pci_crp_wdata,PCI configuration port write data register"
|
|
group 0x18++0x3
|
|
line.long 0x00 " pci_crp_rdata,PCI configuration port read data register"
|
|
group 0x1c++0x3
|
|
line.long 0x00 " pci_csr,PCI Controller Control and Status register"
|
|
bitfld.long 0x00 16. " PRST ,PCI Reset to initializes the PCI controller flip flops clocked by the PCI clock" "Normal,Reset"
|
|
bitfld.long 0x00 15. " IC ,Initialization Complete" "Retry,Compl"
|
|
bitfld.long 0x00 8. " ASE ,Assert System Error" "Normal,Assert"
|
|
bitfld.long 0x00 5. " DBT ,Doorbell Test mode enable" "Dis,Ena"
|
|
bitfld.long 0x00 4. " ABE ,AHB big-endian addressing" "Little,Big"
|
|
bitfld.long 0x00 3. " PBS ,PCI byte swap" "NoSwap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ABS ,AHB byte swap" "NoSwap,Swap"
|
|
bitfld.long 0x00 1. " ARBEN ,Arbiter enable status" "0,1"
|
|
bitfld.long 0x00 0. " HOST ,Host status" "0,1"
|
|
group 0x20++0x3
|
|
line.long 0x00 " pci_isr,PCI Controller Interrupt Status register"
|
|
bitfld.long 0x00 7. " PDB ,PCI Doorbell interrupt" "No,Yes"
|
|
bitfld.long 0x00 6. " ADB ,AHB Doorbell interrupt" "No,Yes"
|
|
bitfld.long 0x00 5. " PADC ,PCI to AHB DMA Complete" "No,Yes"
|
|
bitfld.long 0x00 4. " APDC ,AHB to PCI DMA Complete" "No,Yes"
|
|
bitfld.long 0x00 3. " AHBE ,AHB Error indication" "No-Err,Error"
|
|
bitfld.long 0x00 2. " PPE ,PCI Parity Error" "No-Err,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PFE ,PCI Fatal Error" "No-Err,Error"
|
|
bitfld.long 0x00 0. " PSE ,PCI System Error" "No-Err,Error"
|
|
group 0x24++0x3
|
|
line.long 0x00 " pci_inten,PCI Controller Interrupt Enable register"
|
|
bitfld.long 0x00 7. " PDB ,PCI Doorbell interrupt enable" "-,Ena"
|
|
bitfld.long 0x00 6. " ADB ,AHB Doorbell interrupt enable" "-,Ena"
|
|
bitfld.long 0x00 5. " PADC ,PCI to AHB DMA Complete interrupt enable" "-,Ena"
|
|
bitfld.long 0x00 4. " APDC ,AHB to PCI DMA Complete interrupt enable" "-,Ena"
|
|
bitfld.long 0x00 3. " AHBE ,AHB Error indication interrupt enable" "-,Ena"
|
|
bitfld.long 0x00 2. " PPE ,PCI Parity Error interrupt enable" "-,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PFE ,PCI Fatal Error interrupt enable" "-,Ena"
|
|
bitfld.long 0x00 0. " PSE ,PCI System Error interrupt enable" "-,Ena"
|
|
group 0x28++0x3
|
|
line.long 0x00 " pci_dmactrl,DMA control register"
|
|
bitfld.long 0x00 15. " PADE1 ,PCI to AHB DMA error for buffer 1" "Clr,Set"
|
|
bitfld.long 0x00 14. " PADC1 ,PCI to AHB DMA complete for buffer 1" "No,Yes"
|
|
bitfld.long 0x00 13. " PADE0 ,PCI to AHB DMA error for buffer 0" "Clr,Set"
|
|
bitfld.long 0x00 12. " PADC0 ,PCI to AHB DMA complete for buffer 0" "No,Yes"
|
|
bitfld.long 0x00 8. " PADCEN ,PCI to AHB DMA Complete interrupt enable " "-,Ena"
|
|
bitfld.long 0x00 7. " APDE1 ,AHB to PCI DMA error for buffer 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " APDC1 ,AHB to PCI DMA complete for buffer 1" "No,Yes"
|
|
bitfld.long 0x00 5. " APDE0 ,AHB to PCI DMA error for buffer 0" "No,Yes"
|
|
bitfld.long 0x00 4. " APDC0 ,AHB to PCI DMA complete for buffer 0" "No,Yes"
|
|
bitfld.long 0x00 0. " APDCEN ,AHB to PCI DMA Complete interrupt enable" "-,Ena"
|
|
textline ""
|
|
group 0x2c++0x3
|
|
line.long 0x00 " pci_ahbmembase,AHB Memory Base Address Register"
|
|
hexmask.long 0x00 24.--31. 1. " AHBbase0 ,Upper 8 AHB address bits for PCI accesses that target pci_bar0"
|
|
hexmask.long 0x00 16.--23. 1. " AHBbase1 ,Upper 8 AHB address bits for PCI accesses that target pci_bar1"
|
|
hexmask.long 0x00 8.--15. 1. " AHBbase2 ,Upper 8 AHB address bits for PCI accesses that target pci_bar2"
|
|
hexmask.long 0x00 0.--7. 1. " AHBbase3 ,Upper 8 AHB address bits for PCI accesses that target pci_bar3"
|
|
group 0x30++0x3
|
|
line.long 0x00 " pci_ahbiobase,AHB I/O Base Address Register"
|
|
hexmask.long 0x00 0.--23. 1. " Iobase ,Upper 24 AHB address bits for PCI accesses that target pci_bar5"
|
|
group 0x34++0x3
|
|
line.long 0x00 " pci_pcimembase,PCI Memory Base Address Register"
|
|
hexmask.long 0x00 24.--31. 1. " PCIbase0 ,Upper 8 PCI address bits for AHB accesses that target the first 16Mbyte PCI memory partition"
|
|
hexmask.long 0x00 16.--23. 1. " PCIbase1 ,Upper 8 PCI address bits for AHB accesses that target the second 16Mbyte PCI memory partition"
|
|
hexmask.long 0x00 8.--15. 1. " PCIbase2 ,Upper 8 PCI address bits for AHB accesses that target the third 16Mbyte PCI memory partition"
|
|
hexmask.long 0x00 0.--7. 1. " PCIbase3 ,Upper 8 PCI address bits for AHB accesses that target the fourth 16Mbyte PCI memory partition"
|
|
group 0x38++0x3
|
|
line.long 0x00 " pci_ahbdoorbell,AHB Doorbell Register"
|
|
group 0x3c++0x3
|
|
line.long 0x00 " pci_pcidoorbell,PCI Doorbell Register"
|
|
group 0x40++0x3
|
|
line.long 0x00 " pci_atpdma0_ahbaddr,AHB to PCI DMA AHB Address Register 0"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,AHB word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower AHB address bits hard-wired to zero" "00,?..."
|
|
group 0x44++0x3
|
|
line.long 0x00 " pci_atpdma0_pciaddr,AHB to PCI DMA PCI Address Register 0"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,PCI word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower PCI address bits hard-wired to zero" "00,?..."
|
|
group 0x48++0x3
|
|
line.long 0x00 " pci_atpdma0_length,AHB to PCI DMA Length Register 0"
|
|
bitfld.long 0x00 31. " EN ,Channel enable" "Dis,Ena"
|
|
bitfld.long 0x00 28. " DS ,Data Swap indicator" "NoSwap,Swap"
|
|
hexmask.long 0x00 0.--15. 1. " Wordcount ,Number of words to transfer"
|
|
group 0x4c++0x3
|
|
line.long 0x00 " pci_atpdma1_ahbaddr,AHB to PCI DMA AHB Address Register 1"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,AHB word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower AHB address bits hard-wired to zero" "00,?..."
|
|
group 0x50++0x3
|
|
line.long 0x00 " pci_atpdma1_pciaddr,AHB to PCI DMA PCI Address Register 1"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,PCI word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower PCI address bits hard-wired to zero" "00,?..."
|
|
group 0x54++0x3
|
|
line.long 0x00 " pci_atpdma1_length,AHB to PCI DMA Length Register 1"
|
|
bitfld.long 0x00 31. " EN ,Channel enable" "Dis,Ena"
|
|
bitfld.long 0x00 28. " DS ,Data Swap indicator" "NoSwap,Swap"
|
|
hexmask.long 0x00 0.--15. 1. " Wordcount ,Number of words to transfer"
|
|
group 0x58++0x3
|
|
line.long 0x00 " pci_ptadma0_ahbaddr,PCI to AHB DMA AHB Address Register 0"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,AHB word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower AHB address bits hard-wired to zero" "00,?..."
|
|
group 0x5c++0x3
|
|
line.long 0x00 " pci_ptadma0_pciaddr,PCI to AHB DMA PCI Address Register 0"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,PCI word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower PCI address bits hard-wired to zero" "00,?..."
|
|
group 0x60++0x3
|
|
line.long 0x00 " pci_ptadma0_length, PCI to AHB DMA Length Register 0"
|
|
bitfld.long 0x00 31. " EN ,Channel enable" "Dis,Ena"
|
|
bitfld.long 0x00 28. " DS ,Data Swap indicator" "NoSwap,Swap"
|
|
hexmask.long 0x00 0.--15. 1. " Wordcount ,Number of words to transfer"
|
|
group 0x64++0x3
|
|
line.long 0x00 " pci_ptadma1_ahbaddr, PCI to AHB DMA AHB Address Register 1"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,AHB word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower AHB address bits hard-wired to zero" "00,?..."
|
|
group 0x68++0x3
|
|
line.long 0x00 " pci_ptadma1_pciaddr,PCI to AHB DMA PCI Address Register 1"
|
|
hexmask.long 0x00 2.--31. 1. " Addr ,PCI word address"
|
|
bitfld.long 0x00 0.--1. " ZERO ,Lower PCI address bits hard-wired to zero" "00,?..."
|
|
group 0x6c++0x3
|
|
line.long 0x00 " pci_ptadma1_length,PCI to AHB DMA Length Register 1"
|
|
bitfld.long 0x00 31. " EN ,Channel enable" "Dis,Ena"
|
|
bitfld.long 0x00 28. " DS ,Data Swap indicator" "NoSwap,Swap"
|
|
hexmask.long 0x00 0.--15. 1. " Wordcount ,Number of words to transfer"
|
|
tree.end
|
|
;end include file xscale/ixp4xx-pci.ph
|
|
;begin include file xscale/ixp4xx-sdram.ph
|
|
;parameters:
|
|
tree "SDRAM (SDRAM Controller Registers)"
|
|
base ASD:0xCC000000
|
|
group 0x00++0x3
|
|
line.long 0x00 " sdr_config,SDRAM Configuration Register"
|
|
bitfld.long 0x0 5. " 64M_en ,Enable 64Mbit" "128/256/512 Mbit chips,64Mbit"
|
|
bitfld.long 0x0 4. " RAS_Lat ,RAS Latency" " -,Three-cycle latency"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CAS_Lat ,CAS Latency" "Two-cycle latency,Three-cycle latency"
|
|
bitfld.long 0x0 0.--2. " Mem_conf ,Memory Config" "0,1,2,3,4,5,6,7"
|
|
group 0x04++0x3
|
|
line.long 0x00 " sdr_refresh,SDRAM Refresh Register"
|
|
hexmask.long 0x0 0.--15. 1. " Ref_time ,Refresh time"
|
|
group 0x08++0x3
|
|
line.long 0x00 " sdr_ir,SDRAM Instruction Register"
|
|
bitfld.long 0x0 0.--2. " Instruction ,Commands to be sent out to the SDRAM" "Mode-Register-Set Command where CAS# Latency 2,Mode-Register-Set Command where CAS# Latency 3,Precharge-All Command,NOP Command,Auto-Refresh Command,Burst Terminate Command,res,res"
|
|
tree.end
|
|
;end include file xscale/ixp4xx-sdram.ph
|
|
;begin include file xscale/ixp4xx-ebc.ph
|
|
;parameters:
|
|
tree "EBC (Expansion Bus Controller Registers)"
|
|
base ASD:0xC4000000
|
|
group 0x00++0x3
|
|
line.long 0x00 " EXP_TIMING_CS0, Timing and Control Register for Chip Select 0"
|
|
bitfld.long 0x0 31. " CS0_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x04++0x3
|
|
line.long 0x00 " EXP_TIMING_CS1,Timing and Control Register for Chip Select 1"
|
|
bitfld.long 0x0 31. " CS1_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x08++0x3
|
|
line.long 0x00 " EXP_TIMING_CS2,Timing and Control Register for Chip Select 2"
|
|
bitfld.long 0x0 31. " CS2_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x0c++0x3
|
|
line.long 0x00 " EXP_TIMING_CS3,Timing and Control Register for Chip Select 3"
|
|
bitfld.long 0x0 31. " CS3_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x10++0x3
|
|
line.long 0x00 " EXP_TIMING_CS4,Timing and Control Register for Chip Select 4"
|
|
bitfld.long 0x0 31. " CS4_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x14++0x3
|
|
line.long 0x00 " EXP_TIMING_CS5,Timing and Control Register for Chip Select 5"
|
|
bitfld.long 0x0 31. " CS5_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x18++0x3
|
|
line.long 0x00 " EXP_TIMING_CS6 ,iming and Control Register for Chip Select 6"
|
|
bitfld.long 0x0 31. " CS6_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x1c++0x3
|
|
line.long 0x00 " EXP_TIMING_CS7,Timing and Control Register for Chip Select 7"
|
|
bitfld.long 0x0 31. " CS7_EN ,Chip selection enable" "dis,ena"
|
|
bitfld.long 0x0 28.--29. " T1 ,Address timing" "normal,Ext_by_1 clocks,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 26.--27. " T2 ,Setup / Chip Select Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 22.--25. " T3 ,Strobe Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
bitfld.long 0x0 20.--21. " T4 ,Hold Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks"
|
|
bitfld.long 0x0 16.--19. " T5 ,Recovery Timing" "normal,Ext_by_1 clock,Ext_by_2 clocks,Ext_by_3 clocks,Ext_by-4 clocks,Ext_by_5 clocks,Ext_by_6 clocks,Ext_by_7 clocks,Ext_by_8 clocks,Ext_by_9 clocks,Ext_by_10 clocks,Ext_by_11 clocks,Ext_by_12 clocks,Ext_by_13 clocks,Ext_by_14 clocks,Ext_by_15 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CYC_TYPE ,Cycle type" "Intel cycles,Motorola cycles,HPI cycles,res"
|
|
bitfld.long 0x0 10.--13. " CNFG[3:0] ,Device Configuration Size=2 power of (9+CNFG[3:0])" "512 Bytes,1 Kbytes,2 Kbytes,4 Kbytes,8 Kbytes,16 Kbytes,32 Kbytes,64 Kbytes,128 Kbytes,256 Kbytes,512 Kbytes,1 Mbytes,2 Mbytes,4 Mbytes,8 Mbytes,16 Mbytes"
|
|
bitfld.long 0x0 6. " BYTE_RD16 ,Byte read access to Half Word device" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HRDY_POL ,HPI HRDY polarity (reserved for exp_cs_n[7:4] only)" "Pol_low true,Pol_high true"
|
|
bitfld.long 0x0 4. " MUX_EN ,Multiplexed enable" "dis,ena"
|
|
bitfld.long 0x0 3. " SPLT_EN ,Split trandfers enable" "dis,ena"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WR_EN ,Write to CS region enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " BYTE_EN ,Expansion bus uses 8 bit enable" "16-bit-wide,only 8-bit"
|
|
group 0x20++0x3
|
|
line.long 0x00 " EXP_CNFG0,General Purpose Configuration Register 0"
|
|
bitfld.long 0x0 31. " MEM_MAP ,Location of EXPBus in memory map space" "normal mode,boot mode"
|
|
bitfld.long 0x0 21.--23. " CLK[2:0] ,Core clock set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4. " PCI_CLK ,Sets the clock speed of the PCI Interface" "33 MHz,66 MHz"
|
|
textline " "
|
|
bitfld.long 0x0 2. " PCI_ARB ,Enables the PCC Controller Arbiter" "dis,ena"
|
|
bitfld.long 0x0 1. " PCI_HOST ,Configures the PCC Controller as PCI Bus Host" "non-host,host"
|
|
bitfld.long 0x0 0. " 8/16 FLASH ,Specifies the data bus width of the FLASH memory device" "16-bit,8-bit"
|
|
group 0x24++0x3
|
|
line.long 0x00 " EXP_CNFG1,General Purpose Configuration Register 1"
|
|
bitfld.long 0x0 8. " BYTE_SWAP_EN ,Sets byte swapping at the Core Gasket" "dis,ena"
|
|
bitfld.long 0x0 1. " SW_INT1 ,Interrupt enabled" "dis,ena"
|
|
bitfld.long 0x0 0. " SW_INT0 ,Interrupt enabled" "dis,ena"
|
|
tree.end
|
|
;end include file xscale/ixp4xx-ebc.ph
|
|
;begin include file xscale/ixp4xx-hsuart.ph
|
|
;parameters:
|
|
tree "HS-UART (High Speed UART Registers)"
|
|
base ASD:0xC8000000
|
|
width 8.
|
|
;if (DLAB==1)
|
|
if (d.l(asd:0xc800000c)&0x80)==0x80
|
|
group 0x00++0x3
|
|
line.long 0x00 "DLL,Divisor Latch Low Register"
|
|
hexmask.long 0x0 0.--7. 1. " DLL ,Lower byte of compare-value used by the baud rate generator"
|
|
else
|
|
;if ( DLAB==0)
|
|
rgroup 0x00++0x3
|
|
hide.byte 0x0 "RBR , Receive Buffer Register"
|
|
in
|
|
;if( DLAB==0)
|
|
hide.byte 0x0 "THR ,Transmit Holding Register"
|
|
endif
|
|
;if( DLAB==1)
|
|
if (d.l(asd:0xc800000c)&0x80)==0x80
|
|
group 0x04++0x3
|
|
line.long 0x00 "DLH,Divisor Latch High Register"
|
|
hexmask.long 0x0 0.--7. 1. " DLH ,Upper byte of compare-value used by the baud-rate generator"
|
|
else
|
|
;if( DLAB==0)
|
|
group 0x04++0x3
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. " DMAE ,DMA Requests Enable" "dis,ena"
|
|
bitfld.long 0x0 6. " UUE ,UART Unit Enable" "dis,ena"
|
|
bitfld.long 0x0 5. " NRZE ,NRZ coding Enable" "dis,ena"
|
|
bitfld.long 0x0 4. " RTOIE ,Receiver Time Out Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 3. " RIE ,Modem Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 2. " RLSE ,Receiver Line Status Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 1. " TIE ,Transmit Data request Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 0. " RAVIE ,Receiver Data Available Interrupt Enable" "dis,ena"
|
|
endif
|
|
rgroup 0x08++0x3
|
|
line.long 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.long 0x0 6.--7. " FIFOES ,FIFO Mode Enable Status" "NonFIFO,Res,Res,FIFO"
|
|
bitfld.long 0x0 3. " TOD , Time Out Detected" "No,Yes"
|
|
bitfld.long 0x0 1.--2. " IID ,Interrupt Source Encoded" "ModemStat,TransFIFO,RecData,RecError"
|
|
bitfld.long 0x0 0. " IP_N ,Interrupt Pending" "Yes,No"
|
|
wgroup 0x08++0x3
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x0 6.--7. " ITL ,Interrupt Trigger Level" ">=1 byte,>=8 bytes,>=16 bytes,>=32 bytes"
|
|
bitfld.long 0x0 2. " RESETTF ,Reset Transmitter FIFO" "-, Reset"
|
|
bitfld.long 0x0 1. " RESETRF ,Reset Receiver FIFO" "-, Reset"
|
|
bitfld.long 0x0 0. " TRFIFOE ,Transmit and Receive FIFO Enable" "dis,ena"
|
|
group 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x0 7. " DLAB ,Divisor Latch Access Bit" "0,1"
|
|
bitfld.long 0x0 6. " SB ,Set break" "-,TXD=0"
|
|
bitfld.long 0x0 5. " STKYP ,Sticky Parity" "-,Yes"
|
|
bitfld.long 0x0 4. " EPS ,Even-Parity Select" "Odd,Even"
|
|
bitfld.long 0x0 3. " PEN ,Parity enable" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x0 2. " STB ,Stop bits" "1 bit,2 bits(1.5 bits for 5 bits char)"
|
|
bitfld.long 0x0 0.--1. " WLS ,Word-Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
group 0x10++0x3
|
|
line.long 0x00 "MCR,Modem Control Register"
|
|
bitfld.long 0x0 4. " LOOP ,Loop back test mode" "Normal,Test"
|
|
bitfld.long 0x0 3. " OUT2 ,Interrupt Mask" "Masked, NotMSK"
|
|
bitfld.long 0x0 2. " OUT1 ,Test bit" "0,1"
|
|
bitfld.long 0x0 1. " RTS ,Request to Send" "RTS_N pin=1,RTS_N pin=0"
|
|
bitfld.long 0x0 0. " DTR ,Data Terminal Ready" "DTR# pin=1,DTR# pin=0"
|
|
rgroup 0x14++0x3
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x0 7. " FIFOE ,FIFO Error Status" "NonFIFO/NoError,Error"
|
|
bitfld.long 0x0 6. " TEMT ,Transmitter Empty" "NotEmpty,Empty"
|
|
bitfld.long 0x0 5. " TDRQ ,Transmit Data Request" "0,1"
|
|
bitfld.long 0x0 4. " BI ,Break Interrupt" "No,Yes"
|
|
bitfld.long 0x0 3. " FE ,Framing Error" "No,Yes"
|
|
bitfld.long 0x0 2. " PE ,Parity Error" "No,Yes"
|
|
bitfld.long 0x0 1. " OE ,Overrun Error" "No,Yes"
|
|
bitfld.long 0x0 0. " DR ,Data Ready" "No,Yes"
|
|
rgroup 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x0 7. " DCD ,Data Carrier Detect" "DCD# pin=1,DCD# pin=0"
|
|
bitfld.long 0x0 6. " RI ,Ring Indicator" "RI# pin=1,RI# pin=0"
|
|
bitfld.long 0x0 5. " DSR ,Data Set Ready" "DSR# pin=1,DSR# pin=0"
|
|
bitfld.long 0x0 4. " CTS ,Clear to Send" "CTS# pin=1,CTS# pin=0"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DDCD ,Delta Data Carrier Detect" "NoChg,Changed"
|
|
bitfld.long 0x0 2. " TERI ,Trailing Edge Ring Indicator" "NoChg,Chg 0 to 1"
|
|
bitfld.long 0x0 1. "DDSR ,Delta Data Set Ready" "NoChg,Changed"
|
|
bitfld.long 0x0 0. " DCTS ,Delta Clear To Send" "NoChg,Changed"
|
|
group 0x1c++0x3
|
|
line.long 0x00 "SPR,Scratch Pad Register"
|
|
bitfld.long 0x0 7. " SCR ,No effect on UART functionality" "-,-"
|
|
if (d.l(asd:0xc800000c)&0x80)==0x00
|
|
group 0x20++0x3
|
|
line.long 0x00 "ISR,Slow Infrared Select Register"
|
|
bitfld.long 0x0 4. " RXPL ,Receive Data Polarity" "Pos-puls-as-0,Neg-puls-as-0"
|
|
bitfld.long 0x0 3. " TXPL ,Transmit Data Polarity" "Pos-puls-as-0,Neg-puls-as-0"
|
|
textline " "
|
|
bitfld.long 0x0 2. " XMODE ,Transmit Pulse Width Select" "3/16th bit time,1.6us"
|
|
bitfld.long 0x0 1. " RCVEIR ,Receiver SIR Enable" "Normal,Infrared"
|
|
bitfld.long 0x0 0. " XMITIR ,Transmitter SIR Enable" "Normal,Infrared"
|
|
endif
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-hsuart.ph
|
|
;begin include file xscale/ixp4xx-cuart.ph
|
|
;parameters:
|
|
tree "C-UART (Console UART Registers)"
|
|
base ASD:0xC8001000
|
|
width 8.
|
|
;if (DLAB==1)
|
|
if (d.l(asd:0xC800100C)&0x80)==0x80
|
|
group 0x00++0x3
|
|
line.long 0x00 "DLL,Divisor Latch Low Register"
|
|
hexmask.long 0x0 0.--7. 1. " DLL ,Lower byte of compare-value used by the baud rate generator"
|
|
else
|
|
;if ( DLAB==0)
|
|
rgroup 0x00++0x3
|
|
hide.byte 0x0 "RBR , Receive Buffer Register"
|
|
in
|
|
;if( DLAB==0)
|
|
hide.byte 0x0 "THR ,Transmit Holding Register"
|
|
endif
|
|
;if( DLAB==1)
|
|
if (d.l(asd:0xC800100C)&0x80)==0x80
|
|
group 0x04++0x3
|
|
line.long 0x00 "DLH,Divisor Latch High Register"
|
|
hexmask.long 0x0 0.--7. 1. " DLH ,Upper byte of compare-value used by the baud-rate generator"
|
|
else
|
|
;if( DLAB==0)
|
|
group 0x04++0x3
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. " DMAE ,DMA Requests Enable" "dis,ena"
|
|
bitfld.long 0x0 6. " UUE ,UART Unit Enable" "dis,ena"
|
|
bitfld.long 0x0 5. " NRZE ,NRZ coding Enable" "dis,ena"
|
|
bitfld.long 0x0 4. " RTOIE ,Receiver Time Out Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 3. " RIE ,Modem Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 2. " RLSE ,Receiver Line Status Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 1. " TIE ,Transmit Data request Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 0. " RAVIE ,Receiver Data Available Interrupt Enable" "dis,ena"
|
|
endif
|
|
rgroup 0x08++0x3
|
|
line.long 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.long 0x0 6.--7. " FIFOES ,FIFO Mode Enable Status" "NonFIFO,Res,Res,FIFO"
|
|
bitfld.long 0x0 3. " TOD , Time Out Detected" "No,Yes"
|
|
bitfld.long 0x0 1.--2. " IID ,Interrupt Source Encoded" "ModemStat,TransFIFO,RecData,RecError"
|
|
bitfld.long 0x0 0. " IP_N ,Interrupt Pending" "Yes,No"
|
|
wgroup 0x08++0x3
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x0 6.--7. " ITL ,Interrupt Trigger Level" ">=1 byte,>=8 bytes,>=16 bytes,>=32 bytes"
|
|
bitfld.long 0x0 2. " RESETTF ,Reset Transmitter FIFO" "-, Reset"
|
|
bitfld.long 0x0 1. " RESETRF ,Reset Receiver FIFO" "-, Reset"
|
|
bitfld.long 0x0 0. " TRFIFOE ,Transmit and Receive FIFO Enable" "dis,ena"
|
|
group 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x0 7. " DLAB ,Divisor Latch Access Bit" "0,1"
|
|
bitfld.long 0x0 6. " SB ,Set break" "-,TXD=0"
|
|
bitfld.long 0x0 5. " STKYP ,Sticky Parity" "-,Yes"
|
|
bitfld.long 0x0 4. " EPS ,Even-Parity Select" "Odd,Even"
|
|
bitfld.long 0x0 3. " PEN ,Parity enable" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x0 2. " STB ,Stop bits" "1 bit,2 bits(1.5 bits for 5 bits char)"
|
|
bitfld.long 0x0 0.--1. " WLS ,Word-Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
group 0x10++0x3
|
|
line.long 0x00 "MCR,Modem Control Register"
|
|
bitfld.long 0x0 4. " LOOP ,Loop back test mode" "Normal,Test"
|
|
bitfld.long 0x0 3. " OUT2 ,Interrupt Mask" "Masked, NotMSK"
|
|
bitfld.long 0x0 2. " OUT1 ,Test bit" "0,1"
|
|
bitfld.long 0x0 1. " RTS ,Request to Send" "RTS_N pin=1,RTS_N pin=0"
|
|
bitfld.long 0x0 0. " DTR ,Data Terminal Ready" "DTR# pin=1,DTR# pin=0"
|
|
rgroup 0x14++0x3
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x0 7. " FIFOE ,FIFO Error Status" "NonFIFO/NoError,Error"
|
|
bitfld.long 0x0 6. " TEMT ,Transmitter Empty" "NotEmpty,Empty"
|
|
bitfld.long 0x0 5. " TDRQ ,Transmit Data Request" "0,1"
|
|
bitfld.long 0x0 4. " BI ,Break Interrupt" "No,Yes"
|
|
bitfld.long 0x0 3. " FE ,Framing Error" "No,Yes"
|
|
bitfld.long 0x0 2. " PE ,Parity Error" "No,Yes"
|
|
bitfld.long 0x0 1. " OE ,Overrun Error" "No,Yes"
|
|
bitfld.long 0x0 0. " DR ,Data Ready" "No,Yes"
|
|
rgroup 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x0 7. " DCD ,Data Carrier Detect" "DCD# pin=1,DCD# pin=0"
|
|
bitfld.long 0x0 6. " RI ,Ring Indicator" "RI# pin=1,RI# pin=0"
|
|
bitfld.long 0x0 5. " DSR ,Data Set Ready" "DSR# pin=1,DSR# pin=0"
|
|
bitfld.long 0x0 4. " CTS ,Clear to Send" "CTS# pin=1,CTS# pin=0"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DDCD ,Delta Data Carrier Detect" "NoChg,Changed"
|
|
bitfld.long 0x0 2. " TERI ,Trailing Edge Ring Indicator" "NoChg,Chg 0 to 1"
|
|
bitfld.long 0x0 1. "DDSR ,Delta Data Set Ready" "NoChg,Changed"
|
|
bitfld.long 0x0 0. " DCTS ,Delta Clear To Send" "NoChg,Changed"
|
|
group 0x1c++0x3
|
|
line.long 0x00 "SPR,Scratch Pad Register"
|
|
bitfld.long 0x0 7. " SCR ,No effect on UART functionality" "-,-"
|
|
if (d.l(asd:0xc800000c)&0x80)==0x00
|
|
group 0x20++0x3
|
|
line.long 0x00 "ISR,Slow Infrared Select Register"
|
|
bitfld.long 0x0 4. " RXPL ,Receive Data Polarity" "Pos-puls-as-0,Neg-puls-as-0"
|
|
bitfld.long 0x0 3. " TXPL ,Transmit Data Polarity" "Pos-puls-as-0,Neg-puls-as-0"
|
|
textline " "
|
|
bitfld.long 0x0 2. " XMODE ,Transmit Pulse Width Select" "3/16th bit time,1.6us"
|
|
bitfld.long 0x0 1. " RCVEIR ,Receiver SIR Enable" "Normal,Infrared"
|
|
bitfld.long 0x0 0. " XMITIR ,Transmitter SIR Enable" "Normal,Infrared"
|
|
endif
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-cuart.ph
|
|
;begin include file xscale/ixp4xx-ibpmu.ph
|
|
;parameters:
|
|
tree "IBPMU (Internal Bus Performance Monitoring Unit)"
|
|
base ASD:0xC8002000
|
|
width 8.
|
|
group 0x00++0x3
|
|
line.long 0x0 " ESR,Event Select Register"
|
|
bitfld.long 0x0 20.--22. " PEC1CTRL ,Selects Enable conditions for counter PEC1" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
bitfld.long 0x0 17.--19. " PEC2CTRL ,Selects Enable conditions for counter PEC2" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
bitfld.long 0x0 14.--16. " PEC3CTRL ,Selects Enable conditions for counter PEC3" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
bitfld.long 0x0 11.--13. " PEC4CTRL ,Selects Enable conditions for counter PEC4" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
textline " "
|
|
bitfld.long 0x0 8.--10. " PEC5CTRL ,Selects Enable conditions for counter PEC5" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
bitfld.long 0x0 5.--7. " PEC6CTRL ,Selects Enable conditions for counter PEC6" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
bitfld.long 0x0 2.--4. " PEC7CTRL ,Selects Enable conditions for counter PEC7" "Occur/Hit,Occur/Hit,Occur/Hit,Occur/Hit,Duration/Miss,Duration/Miss,Duration/Miss,Duration/Miss"
|
|
bitfld.long 0x0 0.--1. " Mode ,Monitored interface mode" "Halt,AHB South,AHB North,SDRAM"
|
|
group 0x04++0x3
|
|
line.long 0x0 " PSR,PMU Status Register"
|
|
bitfld.long 0x0 6. " OFL7 ,PEC7 has overflowed" "No,Yes"
|
|
bitfld.long 0x0 5. " OFL6 ,PEC6 has overflowed" "No,Yes"
|
|
bitfld.long 0x0 4. " OFL5 ,PEC5 has overflowed" "No,Yes"
|
|
bitfld.long 0x0 3. " OFL4 ,PEC4 has overflowed" "No,Yes"
|
|
bitfld.long 0x0 2. " OFL3 ,PEC3 has overflowed" "No,Yes"
|
|
bitfld.long 0x0 1. " OFL2 ,PEC2 has overflowed" "No,Yes"
|
|
bitfld.long 0x0 0. " OFL1 ,PEC1 has overflowed" "No,Yes"
|
|
rgroup 0x08++0x3
|
|
line.long 0x0 " PEC1,Programmable Event Counter 1"
|
|
hexmask.long 0x0 0.--26. 1. " PEC1 ,Programmable Event Counter 1"
|
|
rgroup 0x0C++0x3
|
|
line.long 0x0 " PEC2,Programmable Event Counter 2"
|
|
hexmask.long 0x0 0.--26. 1. " PEC2 ,Programmable Event Counter 2"
|
|
rgroup 0x10++0x3
|
|
line.long 0x0 " PEC3,Programmable Event Counter 3"
|
|
hexmask.long 0x0 0.--26. 1. " PEC3 ,Programmable Event Counter 3"
|
|
rgroup 0x14++0x3
|
|
line.long 0x0 " PEC4,Programmable Event Counter 4"
|
|
hexmask.long 0x0 0.--26. 1. " PEC4 ,Programmable Event Counter 4"
|
|
rgroup 0x18++0x3
|
|
line.long 0x0 " PEC5,Programmable Event Counter 5"
|
|
hexmask.long 0x0 0.--26. 1. " PEC5 ,Programmable Event Counter 5"
|
|
rgroup 0x1C++0x3
|
|
line.long 0x0 " PEC6,Programmable Event Counter 6"
|
|
hexmask.long 0x0 0.--26. 1. " PEC6 ,Programmable Event Counter 6"
|
|
rgroup 0x20++0x3
|
|
line.long 0x0 " PEC7,Programmable Event Counter 7"
|
|
hexmask.long 0x0 0.--26. 1. " PEC7 ,Programmable Event Counter 7"
|
|
rgroup 0x24++0x3
|
|
line.long 0x0 " PMSR,Previous Master/Slave Register"
|
|
hexmask.long 0x0 12.--17. 1. " PSS ,Indicates which of the Slaves on South AHB was previously accessed by South AHB Masters"
|
|
hexmask.long 0x0 8.--11. 1. " PSN ,Indicates which of the Slaves on North AHB was previously accessed North AHB Masters"
|
|
hexmask.long 0x0 4.--7. 1. " PMS ,Indicates which of the Masters on South AHB was previously accessing the South AHB"
|
|
hexmask.long 0x0 0.--3. 1. " PMN ,Indicates which of the Master on North AHB was previously accessing the North AHB"
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-ibpmu.ph
|
|
;begin include file xscale/ixp4xx-gpio.ph
|
|
;parameters:
|
|
tree "GPIO (General-Purpose Input/Output Registers)"
|
|
base ASD:0xC8004000
|
|
width 8.
|
|
group 0x0++0x3
|
|
line.long 0x0 " GPOUTR,GPIO pin data output register"
|
|
bitfld.long 0x0 15. " DO15 ,Output 15" "0,1"
|
|
bitfld.long 0x0 14. " DO14 ,Output 14" "0,1"
|
|
bitfld.long 0x0 13. " DO13 ,Output 13" "0,1"
|
|
bitfld.long 0x0 12. " DO12 ,Output 12" "0,1"
|
|
bitfld.long 0x0 11. " DO11 ,Output 11" "0,1"
|
|
bitfld.long 0x0 10. " DO10 ,Output 10" "0,1"
|
|
bitfld.long 0x0 9. " DO9 ,Output 9" "0,1"
|
|
bitfld.long 0x0 8. " DO8 ,Output 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " DO7 ,Output 7" "0,1"
|
|
bitfld.long 0x0 6. " DO6 ,Output 6" "0,1"
|
|
bitfld.long 0x0 5. " DO5 ,Output 5" "0,1"
|
|
bitfld.long 0x0 4. " DO4 ,Output 4" "0,1"
|
|
bitfld.long 0x0 3. " DO3 ,Output 3" "0,1"
|
|
bitfld.long 0x0 2. " DO2 ,Output 2" "0,1"
|
|
bitfld.long 0x0 1. " DO1 ,Output 1" "0,1"
|
|
bitfld.long 0x0 0. " DO0 ,Output 0" "0,1"
|
|
group 0x4++0x3
|
|
line.long 0x0 " GPOER,GPIO pin out enable register"
|
|
bitfld.long 0x0 15. " OE15 ,Output pin 15 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 14. "OE14 ,Output pin 14 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 13. "OE13 ,Output pin 13 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 12. "OE12 ,Output pin 12 Enable" "Driven,Tri-stated/input"
|
|
textline " "
|
|
bitfld.long 0x0 11. "OE11 ,Output pin 11 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 10. "OE10 ,Output pin 10 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 9. "OE9 ,Output pin 9 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 8. "OE8 ,Output pin 8 Enable" "Driven,Tri-stated/input"
|
|
textline " "
|
|
bitfld.long 0x0 7. "OE7 ,Output pin 7 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 6. "OE6 ,Output pin 6 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 5. "OE5 ,Output pin 5 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 4. "OE4 ,Output pin 4 Enable" "Driven,Tri-stated/input"
|
|
textline " "
|
|
bitfld.long 0x0 3. "OE3 ,Output pin 3 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 2. "OE2 ,Output pin 2 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 1. "OE1 ,Output pin 1 Enable" "Driven,Tri-stated/input"
|
|
bitfld.long 0x0 0. "OE0 ,Output pin 0 Enable" "Driven,Tri-stated/input"
|
|
rgroup 0x8++0x3
|
|
line.long 0x0 " GPINR,GPIO pin status register"
|
|
bitfld.long 0x00 15. " IN_LEV15 ,Level of general purpose inputs 15" "0,1"
|
|
bitfld.long 0x00 14. " IN_LEV14 ,Level of general purpose inputs 14" "0,1"
|
|
bitfld.long 0x00 13. " IN_LEV13 ,Level of general purpose inputs 13" "0,1"
|
|
bitfld.long 0x00 12. " IN_LEV12 ,Level of general purpose inputs 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IN_LEV11 ,Level of general purpose inputs 11" "0,1"
|
|
bitfld.long 0x00 10. " IN_LEV10 ,Level of general purpose inputs 10" "0,1"
|
|
bitfld.long 0x00 9. " IN_LEV9 ,Level of general purpose inputs 9" "0,1"
|
|
bitfld.long 0x00 8. " IN_LEV8 ,Level of general purpose inputs 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IN_LEV7 ,Level of general purpose inputs 7" "0,1"
|
|
bitfld.long 0x00 6. " IN_LEV6 ,Level of general purpose inputs 6" "0,1"
|
|
bitfld.long 0x00 5. " IN_LEV5 ,Level of general purpose inputs 5" "0,1"
|
|
bitfld.long 0x00 4. " IN_LEV4 ,Level of general purpose inputs 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IN_LEV3 ,Level of general purpose inputs 3" "0,1"
|
|
bitfld.long 0x00 2. " IN_LEV2 ,Level of general purpose inputs 2" "0,1"
|
|
bitfld.long 0x00 1. " IN_LEV1 ,Level of general purpose inputs 1" "0,1"
|
|
bitfld.long 0x00 0. " IN_LEV0 ,Level of general purpose inputs 0" "0,1"
|
|
group 0xC++0x3
|
|
line.long 0x0 " GPISR,GPIO interrupt status register"
|
|
bitfld.long 0x00 15. " INT_STAT15 ,Interrupt status at Pin15" "NoInt,Int"
|
|
bitfld.long 0x00 14. " INT_STAT14 ,Interrupt status at Pin14" "NoInt,Int"
|
|
bitfld.long 0x00 13. " INT_STAT13 ,Interrupt status at Pin13" "NoInt,Int"
|
|
bitfld.long 0x00 12. " INT_STAT12 ,Interrupt status at Pin12" "NoInt,Int"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT_STAT11 ,Interrupt status at Pin11" "NoInt,Int"
|
|
bitfld.long 0x00 10. " INT_STAT10 ,Interrupt status at Pin10" "NoInt,Int"
|
|
bitfld.long 0x00 9. " INT_STAT9 ,Interrupt status at Pin9" "NoInt,Int"
|
|
bitfld.long 0x00 8. " INT_STAT8 ,Interrupt status at Pin8" "NoInt,Int"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INT_STAT7 ,Interrupt status at Pin7" "NoInt,Int"
|
|
bitfld.long 0x00 6. " INT_STAT6 ,Interrupt status at Pin6" "NoInt,Int"
|
|
bitfld.long 0x00 5. " INT_STAT5 ,Interrupt status at Pin5" "NoInt,Int"
|
|
bitfld.long 0x00 4. " INT_STAT4 ,Interrupt status at Pin4" "NoInt,Int"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_STAT3 ,Interrupt status at Pin3" "NoInt,Int"
|
|
bitfld.long 0x00 2. " INT_STAT2 ,Interrupt status at Pin2" "NoInt,Int"
|
|
bitfld.long 0x00 1. " INT_STAT1 ,Interrupt status at Pin1" "NoInt,Int"
|
|
bitfld.long 0x00 0. " INT_STAT0 ,Interrupt status at Pin0" "NoInt,Int"
|
|
group 0x10++0x3
|
|
line.long 0x0 " GPIT1R,GPIO interrupt type register"
|
|
bitfld.long 0x0 21.--23. " GPIO7 ,Input 7" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 18.--20. " GPIO6 ,Input 6" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 15.--17. " GPIO5 ,Input 5" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 12.--14. " GPIO4 ,Input 4" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
textline " "
|
|
bitfld.long 0x0 9.--11. " GPIO3 ,Input 3" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 6.--8. " GPIO2 ,Input 2" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 3.--5. " GPIO1 ,Input 1" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 0.--2. " GPIO0 ,Input 0" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
group 0x14++0x3
|
|
line.long 0x0 " GPIT2R,GPIO pin interrupt type register"
|
|
bitfld.long 0x0 21.--23. " GPIO15 ,Input 15" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 18.--20. " GPIO14 ,Input 14" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 15.--17. " GPIO13 ,Input 13" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 12.--14. " GPIO12 ,Input 12" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
textline " "
|
|
bitfld.long 0x0 9.--11. " GPIO11 ,Input 11" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 6.--8. " GPIO10 ,Input 10" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 3.--5. " GPIO9 ,Input 9" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
bitfld.long 0x0 0.--2. " GPIO8 ,Input 8" "Active High,Active Low,Rising Edge,Falling Edge,Transitional,Transitional,Transitional,Transitional"
|
|
group 0x18++0x3
|
|
line.long 0x0 " GPCLKR,GPIO Clock Control Register"
|
|
bitfld.long 0x0 24. " MUX15 ,Control the use of GPIO15" "From GPOUTR,Clock output"
|
|
hexmask.long 0x0 20.--23. 1. " CLK1TC ,Terminal count"
|
|
hexmask.long 0x0 16.--19. 1. " CLK1DC ,Represents the number of counts for which clock output should be low"
|
|
textline " "
|
|
bitfld.long 0x0 8. " MUX14 ,Control the use of GPIO15" "From GPOUTR,Clock output"
|
|
hexmask.long 0x0 4.--7. 1. " CLK1TC ,Terminal count"
|
|
hexmask.long 0x0 0.--3. 1. " CLK1DC ,Represents the number of counts for which clock output should be low"
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-gpio.ph
|
|
;begin include file xscale/ixp4xx-ic.ph
|
|
;parameters:
|
|
tree "IC (Interrupt Controller Registers)"
|
|
base ASD:0xC8003000
|
|
width 18.
|
|
rgroup 0x0++0x3
|
|
line.long 0x0 " INTR_ST,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " Int31 ,SW Interrupt 1 Status" "0 ,1 "
|
|
bitfld.long 0x00 30. " Int30 ,SW Interrupt 0 Status" "0 ,1 "
|
|
bitfld.long 0x00 29. " Int29 ,GPIO[12] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 28. " Int28 ,GPIO[11] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 27. " Int27 ,GPIO[10] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 26. " Int26 ,GPIO[9] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 25. " Int25 ,GPIO[8] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 24. " Int24 ,GPIO[7] Interrupt Status" "0 ,1 "
|
|
textline " "
|
|
bitfld.long 0x00 23. " Int23 ,GPIO[6] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 22. " Int22 ,GPIO[5] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 21. " Int21 ,GPIO[4] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 20. " Int20 ,GPIO[3] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 19. " Int19 ,GPIO[2] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 18. " Int18 ,XScale PMU counter rollover Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 17. " Int17 ,Performance Monitoring Unit counter rollover Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 16. " Int16 ,Watchdog Timer Interrupt Status" "0 ,1 "
|
|
textline " "
|
|
bitfld.long 0x00 15. " Int15 ,High-Speed UART Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 14. " Int14 ,Timestamp Timer Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 13. " Int13 ,Console UART Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 12. " Int12 ,USB Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 11. " Int11 ,General-Purpose Timer 1 Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 10. " Int10 ,PCI DMA Channel 2 Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 9. " Int9 ,PCI DMA Channel 1 Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 8. " Int8 ,PCI Interrupt Status" "0 ,1 "
|
|
textline " "
|
|
bitfld.long 0x00 7. " Int7 ,GPIO[1] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 6. " Int6 ,GPIO[0] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 5. " Int5 ,General-Purpose Timer 0 Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 4. " Int4 ,Queue[33-64] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 3. " Int3 ,Queue[1-32] Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 2. " Int2 ,Debug/Execution/MBox Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 1. " Int1 ,Debug/Execution/MBox Interrupt Status" "0 ,1 "
|
|
bitfld.long 0x00 0. " Int0 ,Debug/Execution/MBox Interrupt Status" "0 ,1 "
|
|
group 0x4++0x3
|
|
line.long 0x0 " INTR_EN,Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " Int31 ,SW Interrupt 1 Enable" "Dis,Ena"
|
|
bitfld.long 0x00 30. " Int30 ,SW Interrupt 0 Enable" "Dis,Ena"
|
|
bitfld.long 0x00 29. " Int29 ,GPIO[12] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 28. " Int28 ,GPIO[11] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 27. " Int27 ,GPIO[10] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 26. " Int26 ,GPIO[9] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 25. " Int25 ,GPIO[8] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 24. " Int24 ,GPIO[7] Interrupt Enable" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 23. " Int23 ,GPIO[6] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 22. " Int22 ,GPIO[5] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 21. " Int21 ,GPIO[4] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 20. " Int20 ,GPIO[3] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 19. " Int19 ,GPIO[2] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 18. " Int18 ,XScale PMU counter rollover Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 17. " Int17 ,Performance Monitoring Unit counter rollover Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 16. " Int16 ,Watchdog Timer Interrupt Enable" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 15. " Int15 ,High-Speed UART Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 14. " Int14 ,Timestamp Timer Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 13. " Int13 ,Console UART Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 12. " Int12 ,USB Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 11. " Int11 ,General-Purpose Timer 1 Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 10. " Int10 ,PCI DMA Channel 2 Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 9. " Int9 ,PCI DMA Channel 1 Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 8. " Int8 ,PCI Interrupt Enable" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 7. " Int7 ,GPIO[1] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 6. " Int6 ,GPIO[0] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 5. " Int5 ,General-Purpose Timer 0 Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 4. " Int4 ,Queue[33-64] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 3. " Int3 ,Queue[1-32] Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 2. " Int2 ,Debug/Execution/MBox Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 1. " Int1 ,Debug/Execution/MBox Interrupt Enable" "Dis,Ena"
|
|
bitfld.long 0x00 0. " Int0 ,Debug/Execution/MBox Interrupt Enable" "Dis,Ena"
|
|
group 0x8++0x3
|
|
line.long 0x0 " INTR_SEL,Interrupt Select Register"
|
|
bitfld.long 0x00 31. " Int31 ,SW Interrupt 1 Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " Int30 ,SW Interrupt 0 Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " Int29 ,GPIO[12] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " Int28 ,GPIO[11] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 27. " Int27 ,GPIO[10] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 26. " Int26 ,GPIO[9] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " Int25 ,GPIO[8] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " Int24 ,GPIO[7] Interrupt Select" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 23. " Int23 ,GPIO[6] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " Int22 ,GPIO[5] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " Int21 ,GPIO[4] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " Int20 ,GPIO[3] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 19. " Int19 ,GPIO[2] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " Int18 ,XScale PMU counter rollover Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " Int17 ,Performance Monitoring Unit counter rollover Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 16. " Int16 ,Watchdog Timer Interrupt Select" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 15. " Int15 ,High-Speed UART Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " Int14 ,Timestamp Timer Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " Int13 ,Console UART Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " Int12 ,USB Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 11. " Int11 ,General-Purpose Timer 1 Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " Int10 ,PCI DMA Channel 2 Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " Int9 ,PCI DMA Channel 1 Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " Int8 ,PCI Interrupt Select" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 7. " Int7 ,GPIO[1] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " Int6 ,GPIO[0] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " Int5 ,General-Purpose Timer 0 Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " Int4 ,Queue[33-64] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 3. " Int3 ,Queue[1-32] Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " Int2 ,Debug/Execution/MBox Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " Int1 ,Debug/Execution/MBox Interrupt Select" "IRQ,FIQ"
|
|
bitfld.long 0x00 0. " Int0 ,Debug/Execution/MBox Interrupt Select" "IRQ,FIQ"
|
|
rgroup 0xC++0x3
|
|
line.long 0x0 " INTR_IRQ_ST,IRQ Status register"
|
|
bitfld.long 0x00 31. " Int31 ,SW Interrupt 1 enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 30. " Int30 ,SW Interrupt 0 enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 29. " Int29 ,GPIO[12] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 28. " Int28 ,GPIO[11] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 27. " Int27 ,GPIO[10] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 26. " Int26 ,GPIO[9] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 25. " Int25 ,GPIO[8] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 24. " Int24 ,GPIO[7] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 23. " Int23 ,GPIO[6] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 22. " Int22 ,GPIO[5] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 21. " Int21 ,GPIO[4] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 20. " Int20 ,GPIO[3] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 19. " Int19 ,GPIO[2] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 18. " Int18 ,XScale PMU counter rollover Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 17. " Int17 ,Performance Monitoring Unit counter rollover Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 16. " Int16 ,Watchdog Timer Interrupt enabled as an IRQ" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 15. " Int15 ,High-Speed UART Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 14. " Int14 ,Timestamp Timer Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 13. " Int13 ,Console UART Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 12. " Int12 ,USB Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 11. " Int11 ,General-Purpose Timer 1 Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 10. " Int10 ,PCI DMA Channel 2 Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 9. " Int9 ,PCI DMA Channel 1 Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 8. " Int8 ,PCI Interrupt enabled as an IRQ" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 7. " Int7 ,GPIO[1] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 6. " Int6 ,GPIO[0] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 5. " Int5 ,General-Purpose Timer 0 Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 4. " Int4 ,Queue[33-64] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 3. " Int3 ,Queue[1-32] Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 2. " Int2 ,Debug/Execution/MBox Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 1. " Int1 ,Debug/Execution/MBox Interrupt enabled as an IRQ" "Dis,Ena"
|
|
bitfld.long 0x00 0. " Int0 ,Debug/Execution/MBox Interrupt enabled as an IRQ" "Dis,Ena"
|
|
rgroup 0x10++0x3
|
|
line.long 0x0 " INTR_FIQ_ST,FIQ status Register"
|
|
bitfld.long 0x00 31. " Int31 ,SW Interrupt 1 enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 30. " Int30 ,SW Interrupt 0 enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 29. " Int29 ,GPIO[12] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 28. " Int28 ,GPIO[11] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 27. " Int27 ,GPIO[10] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 26. " Int26 ,GPIO[9] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 25. " Int25 ,GPIO[8] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 24. " Int24 ,GPIO[7] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 23. " Int23 ,GPIO[6] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 22. " Int22 ,GPIO[5] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 21. " Int21 ,GPIO[4] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 20. " Int20 ,GPIO[3] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 19. " Int19 ,GPIO[2] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 18. " Int18 ,XScale PMU counter rollover Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 17. " Int17 ,Performance Monitoring Unit counter rollover Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 16. " Int16 ,Watchdog Timer Interrupt enabled as a FIQ" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 15. " Int15 ,High-Speed UART Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 14. " Int14 ,Timestamp Timer Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 13. " Int13 ,Console UART Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 12. " Int12 ,USB Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 11. " Int11 ,General-Purpose Timer 1 Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 10. " Int10 ,PCI DMA Channel 2 Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 9. " Int9 ,PCI DMA Channel 1 Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 8. " Int8 ,PCI Interrupt enabled as a FIQ" "Dis,Ena"
|
|
textline " "
|
|
bitfld.long 0x00 7. " Int7 ,GPIO[1] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 6. " Int6 ,GPIO[0] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 5. " Int5 ,General-Purpose Timer 0 Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 4. " Int4 ,Queue[33-64] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 3. " Int3 ,Queue[1-32] Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 2. " Int2 ,Debug/Execution/MBox Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 1. " Int1 ,Debug/Execution/MBox Interrupt enabled as a FIQ" "Dis,Ena"
|
|
bitfld.long 0x00 0. " Int0 ,Debug/Execution/MBox Interrupt enabled as a FIQ" "Dis,Ena"
|
|
group 0x14++0x3
|
|
line.long 0x0 " INTR_PRTY,Interrupt Priority Register"
|
|
bitfld.long 0x0 31. " Bit31 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 30. " Bit30 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 29. " Bit29 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 28. " Bit28 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 27. " Bit27 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 26. " Bit26 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 25. " Bit25 ,Read as undefined" "0,?..."
|
|
bitfld.long 0x0 24. " Bit24 ,Read as undefined" "0,?..."
|
|
textline " "
|
|
bitfld.long 0x0 21.--23. " Prior_Intbus7 ,Set the priority of the Intr_bus [7]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. " Prior_Intbus6 ,Set the priority of the Intr_bus [6]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15.--17. " Prior_Intbus5 ,Set the priority of the Intr_bus [5]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. " Prior_Intbus4 ,Set the priority of the Intr_bus [4]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 9.--11. " Prior_Intbus3 ,Set the priority of the Intr_bus [3]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. " Prior_Intbus2 ,Set the priority of the Intr_bus [2]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3.--5. " Prior_Intbus1 ,Set the priority of the Intr_bus [1]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. " Prior_Intbus0 ,Set the priority of the Intr_bus [0]" "0,1,2,3,4,5,6,7"
|
|
rgroup 0x18++0x3
|
|
line.long 0x0 " INTR_IRQ_ENC_ST,IRQ Highest Priority Register"
|
|
hexmask.long 0x0 2.--7. 1. " IRQ_ENC_ST ,Indicates the highest-priority;pending non-maskable interrupt"
|
|
bitfld.long 0x0 1. " RES ,Reserved as 0" "0,?..."
|
|
bitfld.long 0x0 0. " RES ,Reserved as 0" "0,?..."
|
|
rgroup 0x1C++0x3
|
|
line.long 0x0 " INTR_FIQ_ENC_ST,FIQ Highest Priority Register"
|
|
hexmask.long 0x0 2.--7. 1. " FIQ_ENC_ST ,Indicates the highest-priority;pending non-maskable interrupt"
|
|
bitfld.long 0x0 1. " RES ,Reserved as 0" "0,?..."
|
|
bitfld.long 0x0 0. " RES ,Reserved as 0" "0,?..."
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-ic.ph
|
|
;begin include file xscale/ixp4xx-timer.ph
|
|
;parameters:
|
|
tree "TIMER (Timer Registers)"
|
|
base ASD:0xC8005000
|
|
width 18.
|
|
group 0x0++0x3
|
|
line.long 0x0 " ost_ts,Time-Stamp Timer"
|
|
rgroup 0x4++0x3
|
|
line.long 0x0 " ost_tim0,General-Purpose Timer 0"
|
|
group 0x8++0x3
|
|
line.long 0x0 " ost_tim0_rl,General-Purpose Timer 0 Reload"
|
|
hexmask.long 0x0 2.--31. 1. " reload_val ,Value loaded into ost_tim0"
|
|
bitfld.long 0x0 1. " tim0_one_shot ,One shot control bit" "0,1"
|
|
bitfld.long 0x0 0. " tim0_enable ,Counter enabled" "dis,ena"
|
|
rgroup 0xC++0x3
|
|
line.long 0x0 " ost_tim1,General-Purpose Timer 1"
|
|
group 0x10++0x3
|
|
line.long 0x0 " ost_tim1_rl,General-Purpose Timer 1 Reload"
|
|
hexmask.long 0x0 2.--31. 1. " reload_val ,Value loaded into ost_tim1"
|
|
bitfld.long 0x0 1. " tim1_one_shot ,One shot control bit" "0,1"
|
|
bitfld.long 0x0 0. " tim1_enable ,Counter enabled" "dis,ena"
|
|
group 0x14++0x3
|
|
line.long 0x0 " ost_wdog,Watch-Dog Timer"
|
|
group 0x18++0x3
|
|
line.long 0x0 " ost_wdog_enab,Watch-Dog Enable Register"
|
|
bitfld.long 0x0 2. " wdog_cnt_ena ,Watch-dog count enable bit" "dis,ena"
|
|
bitfld.long 0x0 1. " wdog_int_ena ,Watch-dog Interrupt Enable" "dis,ena"
|
|
bitfld.long 0x0 0. " wdog_rst_ena ,Watch-dog Reset Enable" "dis,ena"
|
|
group 0x1C++0x3
|
|
line.long 0x0 " ost_wdog_key,Watch-Dog Key Register"
|
|
hexmask.long 0x0 0.--15. 1. " key_value ,Reset Key Value"
|
|
rgroup 0x20++0x3
|
|
line.long 0x0 " ost_sts,Timer Status"
|
|
bitfld.long 0x0 4. " warm_reset ,Warm reset occurred" "No,Yes"
|
|
bitfld.long 0x0 3. " Ost_wdog_int_val ,Watch-dog timer interrupt occurred" "No,Yes"
|
|
bitfld.long 0x0 2. " Ost_ts_int_val ,Time-stamp timer reaches the maximum count value" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Ost_tim1_int_val ,General-purpose timer down counter has reached a value of zero" "No,Yes"
|
|
bitfld.long 0x0 0. " Ost_tim0_int_val ,General-purpose timer down counter has reached a value of zero" "No,Yes"
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-timer.ph
|
|
;begin include file xscale/ixp4xx-emaca.ph
|
|
;parameters:
|
|
tree "EMACA (Ethernet MAC A Registers)"
|
|
base ASD:0xC8009000
|
|
width 8.
|
|
group 0x0++0x3
|
|
line.long 0x0 " TC1,Transmit Control 1"
|
|
group 0x04++0x3
|
|
line.long 0x0 " TC2,Transmit Control 2"
|
|
group 0x10++0x3
|
|
line.long 0x0 " RC1,Receive Control 1"
|
|
group 0x14++0x3
|
|
line.long 0x0 " RC2,Receive Control 2"
|
|
group 0x20++0x3
|
|
line.long 0x0 " RS,Random Seed"
|
|
group 0x30++0x3
|
|
line.long 0x0 " THPE,Threshold For Partial Empty"
|
|
group 0x38++0x3
|
|
line.long 0x0 " THPF,Threshold For Partial Full"
|
|
group 0x40++0x3
|
|
line.long 0x0 " BST,Buffer Size For Transmit"
|
|
group 0x50++0x3
|
|
line.long 0x0 " TSDP,Transmit Single Deferral Parameters"
|
|
group 0x54++0x3
|
|
line.long 0x0 " RDP,Receive Deferral Parameters"
|
|
group 0x60++0x3
|
|
line.long 0x0 " TTPDP1,Transmit Two Part Deferral Parameters 1"
|
|
group 0x64++0x3
|
|
line.long 0x0 " TTPDP2,Transmit Two Part Deferral Parameters 2"
|
|
group 0x70++0x3
|
|
line.long 0x0 " ST,Slot Time"
|
|
group 0x80++0x3
|
|
line.long 0x0 " MDIOC1,MDIO Command 1"
|
|
group 0x84++0x3
|
|
line.long 0x0 " MDIOC2,MDIO Command 2"
|
|
group 0x88++0x3
|
|
line.long 0x0 " MDIOC3,MDIO Command 3"
|
|
group 0x8C++0x3
|
|
line.long 0x0 " MDIOC4,MDIO Command 4"
|
|
group 0x90++0x3
|
|
line.long 0x0 " MDIOS1,MDIO Status 1"
|
|
group 0x94++0x3
|
|
line.long 0x0 " MDIOS2,MDIO Status 2"
|
|
group 0x98++0x3
|
|
line.long 0x0 " MDIOS3,MDIO Status 3"
|
|
group 0x9C++0x3
|
|
line.long 0x0 " MDIOS4,MDIO Status 4"
|
|
group 0xA0++0x3
|
|
line.long 0x0 " AM1,Address Mask 1"
|
|
group 0xA4++0x3
|
|
line.long 0x0 " AM2,Address Mask 2"
|
|
group 0xA8++0x3
|
|
line.long 0x0 " AM3,Address Mask 3"
|
|
group 0xAC++0x3
|
|
line.long 0x0 " AM4,Address Mask 4"
|
|
group 0xB0++0x3
|
|
line.long 0x0 " AM5,Address Mask 5"
|
|
group 0xB4++0x3
|
|
line.long 0x0 " AM6,Address Mask 6"
|
|
group 0xC0++0x3
|
|
line.long 0x0 " A1,Address 1"
|
|
group 0xC4++0x3
|
|
line.long 0x0 " A2,Address 2"
|
|
group 0xC8++0x3
|
|
line.long 0x0 " A3,Address 3"
|
|
group 0xCC++0x3
|
|
line.long 0x0 " A4,Address 4"
|
|
group 0xD0++0x3
|
|
line.long 0x0 " A5,Address 5"
|
|
group 0xD4++0x3
|
|
line.long 0x0 " A6,Address 6"
|
|
group 0xE0++0x3
|
|
line.long 0x0 " THIC,Threshold For Internal Clock"
|
|
group 0xF0++0x3
|
|
line.long 0x0 " UA1,Unicast Address 1"
|
|
group 0xF4++0x3
|
|
line.long 0x0 " UA2,Unicast Address 2"
|
|
group 0xF8++0x3
|
|
line.long 0x0 " UA3,Unicast Address 3"
|
|
group 0xFC++0x3
|
|
line.long 0x0 " UA4,Unicast Address 4"
|
|
group 0x100++0x3
|
|
line.long 0x0 " UA5,Unicast Address 5"
|
|
group 0x104++0x3
|
|
line.long 0x0 " UA6,Unicast Address 6"
|
|
group 0x1FC++0x3
|
|
line.long 0x0 " CC,Core Control"
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-emaca.ph
|
|
;begin include file xscale/ixp4xx-emacb.ph
|
|
;parameters:
|
|
tree "EMACB (Ethernet MAC B Registers)"
|
|
base ASD:0xC800A000
|
|
width 8.
|
|
group 0x0++0x3
|
|
line.long 0x0 " TC1,Transmit Control 1"
|
|
group 0x04++0x3
|
|
line.long 0x0 " TC2,Transmit Control 2"
|
|
group 0x10++0x3
|
|
line.long 0x0 " RC1,Receive Control 1"
|
|
group 0x14++0x3
|
|
line.long 0x0 " RC2,Receive Control 2"
|
|
group 0x20++0x3
|
|
line.long 0x0 " RS,Random Seed"
|
|
group 0x30++0x3
|
|
line.long 0x0 " THPE,Threshold For Partial Empty"
|
|
group 0x38++0x3
|
|
line.long 0x0 " THPF,Threshold For Partial Full"
|
|
group 0x40++0x3
|
|
line.long 0x0 " BST,Buffer Size For Transmit"
|
|
group 0x50++0x3
|
|
line.long 0x0 " TSDP,Transmit Single Deferral Parameters"
|
|
group 0x54++0x3
|
|
line.long 0x0 " RDP,Receive Deferral Parameters"
|
|
group 0x60++0x3
|
|
line.long 0x0 " TTPDP1,Transmit Two Part Deferral Parameters 1"
|
|
group 0x64++0x3
|
|
line.long 0x0 " TTPDP2,Transmit Two Part Deferral Parameters 2"
|
|
group 0x70++0x3
|
|
line.long 0x0 " ST,Slot Time"
|
|
group 0x80++0x3
|
|
line.long 0x0 " MDIOC1,MDIO Command 1"
|
|
group 0x84++0x3
|
|
line.long 0x0 " MDIOC2,MDIO Command 2"
|
|
group 0x88++0x3
|
|
line.long 0x0 " MDIOC3,MDIO Command 3"
|
|
group 0x8C++0x3
|
|
line.long 0x0 " MDIOC4,MDIO Command 4"
|
|
group 0x90++0x3
|
|
line.long 0x0 " MDIOS1,MDIO Status 1"
|
|
group 0x94++0x3
|
|
line.long 0x0 " MDIOS2,MDIO Status 2"
|
|
group 0x98++0x3
|
|
line.long 0x0 " MDIOS3,MDIO Status 3"
|
|
group 0x9C++0x3
|
|
line.long 0x0 " MDIOS4,MDIO Status 4"
|
|
group 0xA0++0x3
|
|
line.long 0x0 " AM1,Address Mask 1"
|
|
group 0xA4++0x3
|
|
line.long 0x0 " AM2,Address Mask 2"
|
|
group 0xA8++0x3
|
|
line.long 0x0 " AM3,Address Mask 3"
|
|
group 0xAC++0x3
|
|
line.long 0x0 " AM4,Address Mask 4"
|
|
group 0xB0++0x3
|
|
line.long 0x0 " AM5,Address Mask 5"
|
|
group 0xB4++0x3
|
|
line.long 0x0 " AM6,Address Mask 6"
|
|
group 0xC0++0x3
|
|
line.long 0x0 " A1,Address 1"
|
|
group 0xC4++0x3
|
|
line.long 0x0 " A2,Address 2"
|
|
group 0xC8++0x3
|
|
line.long 0x0 " A3,Address 3"
|
|
group 0xCC++0x3
|
|
line.long 0x0 " A4,Address 4"
|
|
group 0xD0++0x3
|
|
line.long 0x0 " A5,Address 5"
|
|
group 0xD4++0x3
|
|
line.long 0x0 " A6,Address 6"
|
|
group 0xE0++0x3
|
|
line.long 0x0 " THIC,Threshold For Internal Clock"
|
|
group 0xF0++0x3
|
|
line.long 0x0 " UA1,Unicast Address 1"
|
|
group 0xF4++0x3
|
|
line.long 0x0 " UA2,Unicast Address 2"
|
|
group 0xF8++0x3
|
|
line.long 0x0 " UA3,Unicast Address 3"
|
|
group 0xFC++0x3
|
|
line.long 0x0 " UA4,Unicast Address 4"
|
|
group 0x100++0x3
|
|
line.long 0x0 " UA5,Unicast Address 5"
|
|
group 0x104++0x3
|
|
line.long 0x0 " UA6,Unicast Address 6"
|
|
group 0x1FC++0x3
|
|
line.long 0x0 " CC,Core Control"
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-emacb.ph
|
|
;begin include file xscale/ixp4xx-usb.ph
|
|
;parameters:
|
|
tree "USB (USB V 1.1 Device Controller Registers)"
|
|
base ASD:0xC800B000
|
|
width 8.
|
|
group 0x0++3
|
|
line.long 0x00 " UDCCR,UDC Control Register"
|
|
bitfld.long 0x0 7. " REM ,Reset interrupt mask(read/write)" "RintEna,RintDis"
|
|
bitfld.long 0x0 6. " RSTIR ,Reset interrupt request(read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 5. " SRM ,Suspend/resume interrupt mask(read/write)" "Ena,Dis"
|
|
bitfld.long 0x0 4. " SUSIR ,Suspend interrupt request(read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " RESIR ,Resume interrupt request(read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " RSM ,Device Resume(read/write 1 to set)" "No,Yes"
|
|
bitfld.long 0x0 1. " UDA ,UDC active (read-only)" "No,Yes"
|
|
bitfld.long 0x0 0. " UDE ,UDD enable.(read/write)" "Dis,Ena"
|
|
;group 0x04++3
|
|
;line.long 0x00 " RES,Reserved for Future Use"
|
|
;group 0x08++3
|
|
;line.long 0x00 " RES,Reserved for Future Use"
|
|
;group 0x0C++3
|
|
;line.long 0x00 " RES,Reserved for Future Use"
|
|
group 0x10++3
|
|
line.long 0x00 " UDCCS0,UDC Endpoint 0 Control/Status Register"
|
|
bitfld.long 0x0 7. " SA ,Setup Active (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 5. " FST ,Force stall (read/write 1 to set)" "No,Yes"
|
|
bitfld.long 0x0 4 " SST ,Sent stall (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " DRWF ,Device remote wake-up feature (read-only)" "Dis,Ena"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/write 1 to set)" "No,Yes"
|
|
bitfld.long 0x0 1. " IPR ,IN packet ready (always read 0/write 1 to set)" "No,Yes"
|
|
bitfld.long 0x0 0. " OPR ,OUT packet ready (read/write 1 to clear)" "No,Yes"
|
|
group 0x14++3
|
|
line.long 0x00 " UDCCS1,UDC Endpoint 1 (IN) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 5. " FST ,Force STALL (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent STALL (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "NoRoom,Room>=1 Packet"
|
|
group 0x18++3
|
|
line.long 0x00 " UDCCS2,UDC Endpoint 2 (OUT) Control/Status Register"
|
|
bitfld.long 0x0 7. " RSP ,Receive short packet (read only)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 5. " FST ,Force stall (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent stall (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " RPC ,Receive packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " RFS ,Receive FIFO service (read-only)" "< 1 packet,>= 1 packet"
|
|
group 0x1C++3
|
|
line.long 0x00 " UDCCS3,UDC Endpoint 3 (IN) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room>=1 Packet"
|
|
group 0x20++3
|
|
line.long 0x00 " UDCCS4,UDC Endpoint 4 (OUT) Control/Status Register"
|
|
bitfld.long 0x0 7. " RSP ,Receive short packet (read only)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 2. " ROF ,Receive overflow (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " RPC ,Receive packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " RFS ,Receive FIFO service (read-only)" "< 1 packet,>= 1 packet"
|
|
group 0x24++3
|
|
line.long 0x00 " UDCCS5,UDC Endpoint 5 (Interrupt) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 5. " FST ,Force STALL (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent STALL (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room >= 1 packet"
|
|
group 0x28++3
|
|
line.long 0x00 " UDCCS6,UDC Endpoint 6 (IN) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 5. " FST ,Force STALL (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent STALL (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room >= 1 packet"
|
|
group 0x2C++3
|
|
line.long 0x00 " UDCCS7,UDC Endpoint 7 (OUT) Control/Status Register"
|
|
bitfld.long 0x0 7. " RSP ,Receive short packet (read only)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 5. " FST ,Force stall (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent stall (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " RPC ,Receive packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " RFS ,Receive FIFO service (read-only)" "< 1 packet,>= 1 packet"
|
|
group 0x30++3
|
|
line.long 0x00 " UDCCS8,UDC Endpoint 8 (IN) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room>=1 Packet"
|
|
group 0x34++3
|
|
line.long 0x00 " UDCCS9,UDC Endpoint 9 (OUT) Control/Status Register"
|
|
bitfld.long 0x0 7. " RSP ,Receive short packet (read only)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 2. " ROF ,Receive overflow (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " RPC ,Receive packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " RFS ,Receive FIFO service (read-only)" "< 1 packet,>= 1 packet"
|
|
group 0x38++3
|
|
line.long 0x00 " UDCCS10,UDC Endpoint 10 (Interrupt) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 5. " FST ,Force STALL (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent STALL (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room>=1 Packet"
|
|
group 0x3C++3
|
|
line.long 0x00 " UDCCS11,UDC Endpoint 11 (IN) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 5. " FST ,Force STALL (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent STALL (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room>=1 Packet"
|
|
group 0x40++3
|
|
line.long 0x00 " UDCCS12,UDC Endpoint 12 (OUT) Control/Status Register"
|
|
bitfld.long 0x0 7. " RSP ,Receive short packet (read only)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 5. " FST ,Force stall (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent stall (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " RPC ,Receive packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " RFS ,Receive FIFO service (read-only)" "< 1 packet,>= 1 packet"
|
|
group 0x44++3
|
|
line.long 0x00 " UDCCS13,UDC Endpoint 13 (IN) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room>=1 Packet"
|
|
group 0x48++3
|
|
line.long 0x00 " UDCCS14,UDC Endpoint 14 (OUT) Control/Status Register"
|
|
bitfld.long 0x0 7. " RSP ,Receive short packet (read only)" "No,Yes"
|
|
bitfld.long 0x0 6. " RNE ,Receive FIFO NotEmpt (read-only)" "Empty,NotEmpt"
|
|
bitfld.long 0x0 2. " ROF ,Receive overflow (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " RPC ,Receive packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " RFS ,Receive FIFO service (read-only)" "< 1 packet,>= 1 packet"
|
|
group 0x4C++3
|
|
line.long 0x00 " UDCCS15,UDC Endpoint 15 (Interrupt) Control/Status Register"
|
|
bitfld.long 0x0 7. " TSP ,Transmit short packet (read/write 1 to set)" "NotRdy,Ready"
|
|
bitfld.long 0x0 5. " FST ,Force STALL (read/write)" "No,Yes"
|
|
bitfld.long 0x0 4. " SST ,Sent STALL (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " TUR ,Transmit FIFO underrun (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " FTF ,Flush Tx FIFO (always read 0/ write a 1 to set)" "-,Flush"
|
|
bitfld.long 0x0 1. " TPC ,Transmit packet complete (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " TFS ,Transmit FIFO service (read-only)" "No room,Room>=1 Packet"
|
|
textline ""
|
|
group 0x50++3
|
|
line.long 0x00 " UICR0,UDC Interrupt Control Register 0"
|
|
bitfld.long 0x0 7. " IM7 ,Interrupt Mask for Endpoint 7" "RintEna,RintDis"
|
|
bitfld.long 0x0 6. " IM6 ,Interrupt Mask for Endpoint 6" "RintEna,RintDis"
|
|
bitfld.long 0x0 5. " IM5 ,Interrupt Mask for Endpoint 5" "RintEna,RintDis"
|
|
bitfld.long 0x0 4. " IM4 ,Interrupt Mask for Endpoint 4" "RintEna,RintDis"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IM3 ,Interrupt Mask for Endpoint 3" "RintEna,RintDis"
|
|
bitfld.long 0x0 2. " IM2 ,Interrupt Mask for Endpoint 2" "RintEna,RintDis"
|
|
bitfld.long 0x0 1. " IM1 ,Interrupt Mask for Endpoint 1" "RintEna,RintDis"
|
|
bitfld.long 0x0 0. " IM0 ,Interrupt Mask for Endpoint 0" "RintEna,RintDis"
|
|
group 0x54++3
|
|
line.long 0x00 " UICR1,UDC Interrupt Control Register 1"
|
|
bitfld.long 0x0 7. " IM15 ,Interrupt Mask for Endpoint 15" "RintEna,RintDis"
|
|
bitfld.long 0x0 6. " IM14 ,Interrupt Mask for Endpoint 14" "RintEna,RintDis"
|
|
bitfld.long 0x0 5. " IM13 ,Interrupt Mask for Endpoint 13" "RintEna,RintDis"
|
|
bitfld.long 0x0 4. " IM12 ,Interrupt Mask for Endpoint 12" "RintEna,RintDis"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IM11 ,Interrupt Mask for Endpoint 11" "RintEna,RintDis"
|
|
bitfld.long 0x0 2. " IM10 ,Interrupt Mask for Endpoint 10" "RintEna,RintDis"
|
|
bitfld.long 0x0 1. " IM9 ,Interrupt Mask for Endpoint 9" "RintEna,RintDis"
|
|
bitfld.long 0x0 0. " IM8 ,Interrupt Mask for Endpoint 8" "RintEna,RintDis"
|
|
group 0x58++3
|
|
line.long 0x00 " UISR0,UDC Status Interrupt Register 0"
|
|
bitfld.long 0x0 7. " IR7 ,Interrupt Request Endpoint 7 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 6. " IR6 ,Interrupt Request Endpoint 6 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 5. " IR5 ,Interrupt Request Endpoint 5 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 4. " IR4 ,Interrupt Request Endpoint 4 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " IR3 ,Interrupt Request Endpoint 3 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " IR2 ,Interrupt Request Endpoint 2 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " IR7 ,Interrupt Request Endpoint 1 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " IR0 ,Interrupt Request Endpoint 0 (read/write 1 to clear)" "No,Yes"
|
|
group 0x5C++3
|
|
line.long 0x00 " UISR1,UDC Status Interrupt Register 1"
|
|
bitfld.long 0x0 7. " IR15 ,Interrupt Request Endpoint 15 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 6. " IR14 ,Interrupt Request Endpoint 14 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 5. " IR13 ,Interrupt Request Endpoint 13 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 4. " IR12 ,Interrupt Request Endpoint 12 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 3. " IR11 ,Interrupt Request Endpoint 11 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 2. " IR10 ,Interrupt Request Endpoint 10 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 1. " IR9 ,Interrupt Request Endpoint 9 (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 0. " IR8 ,Interrupt Request Endpoint 8 (read/write 1 to clear)" "No,Yes"
|
|
textline ""
|
|
rgroup 0x60++3
|
|
line.long 0x00 " UFNHR,UDC Frame Number Register High"
|
|
bitfld.long 0x0 7. " SIR ,SOF Interrupt Request (read/write 1 to clear)" "No,Yes"
|
|
bitfld.long 0x0 6. " SIM ,SOF interrupt mask" "Ena,Dis"
|
|
bitfld.long 0x0 5. " IPE14 ,Isochronous Packet Error Endpoint 14 (read/write 1 to clear)" "NoErr,Corrupt"
|
|
bitfld.long 0x0 4. " IPE9 ,Isochronous Packet Error Endpoint 9 (read/write 1 to clear)" "NoErr,Corrupt"
|
|
bitfld.long 0x0 3. " IPE4 ,Isochronous Packet Error Endpoint 4 (read/write 1 to clear)" "NoErr,Corrupt"
|
|
bitfld.long 0x0 0.--2. " FNMSB ,Frame Number MSB" "0,1,2,3,4,5,6,7"
|
|
rgroup 0x64++3
|
|
line.long 0x00 " UFNLR,UDC Frame Number Register Low"
|
|
hexmask.long 0x0 0.--7. 1. " FNLSB ,Frame number LSB"
|
|
rgroup 0x68++3
|
|
line.long 0x00 " UBC2,UDC Byte Count Register 2"
|
|
hexmask.long 0x0 0.--7. 1. " BC ,Byte Count (read-only)"
|
|
group 0x6C++3
|
|
line.long 0x00 " UBC4,UDC Byte Count Register 4"
|
|
hexmask.long 0x0 0.--7. 1. " BC ,Byte Count (read-only)"
|
|
rgroup 0x70++3
|
|
line.long 0x00 " UBC7,UDC Byte Count Register 7"
|
|
hexmask.long 0x0 0.--7. 1. " BC ,Byte Count (read-only)"
|
|
rgroup 0x74++3
|
|
line.long 0x00 " UBC9,UDC Byte Count Register 9"
|
|
hexmask.long 0x0 0.--7. 1. " BC ,Byte Count (read-only)"
|
|
rgroup 0x78++3
|
|
line.long 0x00 " UBC12,UDC Byte Count Register 12"
|
|
hexmask.long 0x0 0.--7. 1. " BC ,Byte Count (read-only)"
|
|
rgroup 0x7C++3
|
|
line.long 0x00 " UBC14,UDC Byte Count Register 14"
|
|
hexmask.long 0x0 0.--7. 1. " BC ,Byte Count (read-only)"
|
|
wgroup 0x80++3
|
|
line.long 0x00 " UDDR0,UDC Endpoint 0 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top/bottom of endpoint 0 FIFO data (Read Bottom,Write Top)"
|
|
wgroup 0x100++3
|
|
line.long 0x00 " UDDR1,UDC Endpoint 1 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x180++3
|
|
line.long 0x00 " UDDR2,UDC Endpoint 2 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x200++3
|
|
line.long 0x00 " UDDR3,UDC Endpoint 3 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x400++3
|
|
line.long 0x00 " UDDR4,UDC Endpoint 4 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x008++3
|
|
line.long 0x00 " UDDR5,UDC Endpoint 5 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x600++3
|
|
line.long 0x00 " UDDR6,UDC Endpoint 6 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x680++3
|
|
line.long 0x00 " UDDR7,UDC Endpoint 7 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x700++3
|
|
line.long 0x00 " UDDR8,UDC Endpoint 8 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x900++3
|
|
line.long 0x00 " UDDR9,UDC Endpoint 9 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x0C0++3
|
|
line.long 0x00 " UDDR10,UDC Endpoint 10 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0xB00++3
|
|
line.long 0x00 " UDDR11,UDC Endpoint 11 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0xB80++3
|
|
line.long 0x00 " UDDR12,UDC Endpoint 12 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0xC00++3
|
|
line.long 0x00 " UDDR13,UDC Endpoint 13 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0xE00++3
|
|
line.long 0x00 " UDDR14,UDC Endpoint 14 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
wgroup 0x0E0++3
|
|
line.long 0x00 " UDDR15,UDC Endpoint 15 Data Register"
|
|
hexmask.long 0x0 0.--7. 1. " DATA ,Top of endpoint data currently being loaded"
|
|
width 22.
|
|
tree.end
|
|
;end include file xscale/ixp4xx-usb.ph
|