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Gen4_R-Car_Trace32/2_Trunk/perht32f611xx.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: HT32F611xx On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2023-12-22 NEJ
; @Manufacturer: HOLTEK - HOLTEK Semiconductor Inc.
; @Doc: Generated (TRACE32, build: 165719.), based on:
; HT32F61141.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: HT32F61141
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perht32f611xx.per 17330 2024-01-15 13:06:35Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "NVIC (Nested Vectored Interrupt Controller)"
base ad:0xE000E000
group.long 0x4++0x7
line.long 0x0 "ICTR,ICTR"
hexmask.long.byte 0x0 0.--4. 1. "INTLINESNUM,INTLINESNUM"
line.long 0x4 "ACTLR,ACTLR"
bitfld.long 0x4 2. "DISFOLD,DISFOLD" "0,1"
bitfld.long 0x4 1. "DISDEFWBUF,DISDEFWBUF" "0,1"
bitfld.long 0x4 0. "DISMCYCINT,DISMCYCINT" "0,1"
group.long 0x100++0xB
line.long 0x0 "ISER0,ISER0"
bitfld.long 0x0 31. "SETENA31,SETENA31" "0,1"
bitfld.long 0x0 30. "SETENA30,SETENA30" "0,1"
bitfld.long 0x0 29. "SETENA29,SETENA29" "0,1"
bitfld.long 0x0 28. "SETENA28,SETENA28" "0,1"
bitfld.long 0x0 27. "SETENA27,SETENA27" "0,1"
bitfld.long 0x0 26. "SETENA26,SETENA26" "0,1"
newline
bitfld.long 0x0 25. "SETENA25,SETENA25" "0,1"
bitfld.long 0x0 24. "SETENA24,SETENA24" "0,1"
bitfld.long 0x0 23. "SETENA23,SETENA23" "0,1"
bitfld.long 0x0 22. "SETENA22,SETENA22" "0,1"
bitfld.long 0x0 21. "SETENA21,SETENA21" "0,1"
bitfld.long 0x0 20. "SETENA20,SETENA20" "0,1"
newline
bitfld.long 0x0 19. "SETENA19,SETENA19" "0,1"
bitfld.long 0x0 18. "SETENA18,SETENA18" "0,1"
bitfld.long 0x0 17. "SETENA17,SETENA17" "0,1"
bitfld.long 0x0 16. "SETENA16,SETENA16" "0,1"
bitfld.long 0x0 15. "SETENA15,SETENA15" "0,1"
bitfld.long 0x0 14. "SETENA14,SETENA14" "0,1"
newline
bitfld.long 0x0 13. "SETENA13,SETENA13" "0,1"
bitfld.long 0x0 12. "SETENA12,SETENA12" "0,1"
bitfld.long 0x0 11. "SETENA11,SETENA11" "0,1"
bitfld.long 0x0 10. "SETENA10,SETENA10" "0,1"
bitfld.long 0x0 9. "SETENA9,SETENA9" "0,1"
bitfld.long 0x0 8. "SETENA8,SETENA8" "0,1"
newline
bitfld.long 0x0 7. "SETENA7,SETENA7" "0,1"
bitfld.long 0x0 6. "SETENA6,SETENA6" "0,1"
bitfld.long 0x0 5. "SETENA5,SETENA5" "0,1"
bitfld.long 0x0 4. "SETENA4,SETENA4" "0,1"
bitfld.long 0x0 3. "SETENA3,SETENA3" "0,1"
bitfld.long 0x0 2. "SETENA2,SETENA2" "0,1"
newline
bitfld.long 0x0 1. "SETENA1,SETENA1" "0,1"
bitfld.long 0x0 0. "SETENA0,SETENA0" "0,1"
line.long 0x4 "ISER1,ISER1"
bitfld.long 0x4 31. "SETENA63,SETENA63" "0,1"
bitfld.long 0x4 30. "SETENA62,SETENA62" "0,1"
bitfld.long 0x4 29. "SETENA61,SETENA61" "0,1"
bitfld.long 0x4 28. "SETENA60,SETENA60" "0,1"
bitfld.long 0x4 27. "SETENA59,SETENA59" "0,1"
bitfld.long 0x4 26. "SETENA58,SETENA58" "0,1"
newline
bitfld.long 0x4 25. "SETENA57,SETENA57" "0,1"
bitfld.long 0x4 24. "SETENA56,SETENA56" "0,1"
bitfld.long 0x4 23. "SETENA55,SETENA55" "0,1"
bitfld.long 0x4 22. "SETENA54,SETENA54" "0,1"
bitfld.long 0x4 21. "SETENA53,SETENA53" "0,1"
bitfld.long 0x4 20. "SETENA52,SETENA52" "0,1"
newline
bitfld.long 0x4 19. "SETENA51,SETENA51" "0,1"
bitfld.long 0x4 18. "SETENA50,SETENA50" "0,1"
bitfld.long 0x4 17. "SETENA49,SETENA49" "0,1"
bitfld.long 0x4 16. "SETENA48,SETENA48" "0,1"
bitfld.long 0x4 15. "SETENA47,SETENA47" "0,1"
bitfld.long 0x4 14. "SETENA46,SETENA46" "0,1"
newline
bitfld.long 0x4 13. "SETENA45,SETENA45" "0,1"
bitfld.long 0x4 12. "SETENA44,SETENA44" "0,1"
bitfld.long 0x4 11. "SETENA43,SETENA43" "0,1"
bitfld.long 0x4 10. "SETENA42,SETENA42" "0,1"
bitfld.long 0x4 9. "SETENA41,SETENA41" "0,1"
bitfld.long 0x4 8. "SETENA40,SETENA40" "0,1"
newline
bitfld.long 0x4 7. "SETENA39,SETENA39" "0,1"
bitfld.long 0x4 6. "SETENA38,SETENA38" "0,1"
bitfld.long 0x4 5. "SETENA37,SETENA37" "0,1"
bitfld.long 0x4 4. "SETENA36,SETENA36" "0,1"
bitfld.long 0x4 3. "SETENA35,SETENA35" "0,1"
bitfld.long 0x4 2. "SETENA34,SETENA34" "0,1"
newline
bitfld.long 0x4 1. "SETENA33,SETENA33" "0,1"
bitfld.long 0x4 0. "SETENA32,SETENA32" "0,1"
line.long 0x8 "ISER2,ISER2"
bitfld.long 0x8 4. "SETENA68,SETENA68" "0,1"
bitfld.long 0x8 3. "SETENA67,SETENA67" "0,1"
bitfld.long 0x8 2. "SETENA66,SETENA66" "0,1"
bitfld.long 0x8 1. "SETENA65,SETENA65" "0,1"
bitfld.long 0x8 0. "SETENA64,SETENA64" "0,1"
group.long 0x180++0xB
line.long 0x0 "ICER0,ICER0"
bitfld.long 0x0 31. "CLRENA31,CLRENA31" "0,1"
bitfld.long 0x0 30. "CLRENA30,CLRENA30" "0,1"
bitfld.long 0x0 29. "CLRENA29,CLRENA29" "0,1"
bitfld.long 0x0 28. "CLRENA28,CLRENA28" "0,1"
bitfld.long 0x0 27. "CLRENA27,CLRENA27" "0,1"
bitfld.long 0x0 26. "CLRENA26,CLRENA26" "0,1"
newline
bitfld.long 0x0 25. "CLRENA25,CLRENA25" "0,1"
bitfld.long 0x0 24. "CLRENA24,CLRENA24" "0,1"
bitfld.long 0x0 23. "CLRENA23,CLRENA23" "0,1"
bitfld.long 0x0 22. "CLRENA22,CLRENA22" "0,1"
bitfld.long 0x0 21. "CLRENA21,CLRENA21" "0,1"
bitfld.long 0x0 20. "CLRENA20,CLRENA20" "0,1"
newline
bitfld.long 0x0 19. "CLRENA19,CLRENA19" "0,1"
bitfld.long 0x0 18. "CLRENA18,CLRENA18" "0,1"
bitfld.long 0x0 17. "CLRENA17,CLRENA17" "0,1"
bitfld.long 0x0 16. "CLRENA16,CLRENA16" "0,1"
bitfld.long 0x0 15. "CLRENA15,CLRENA15" "0,1"
bitfld.long 0x0 14. "CLRENA14,CLRENA14" "0,1"
newline
bitfld.long 0x0 13. "CLRENA13,CLRENA13" "0,1"
bitfld.long 0x0 12. "CLRENA12,CLRENA12" "0,1"
bitfld.long 0x0 11. "CLRENA11,CLRENA11" "0,1"
bitfld.long 0x0 10. "CLRENA10,CLRENA10" "0,1"
bitfld.long 0x0 9. "CLRENA9,CLRENA9" "0,1"
bitfld.long 0x0 8. "CLRENA8,CLRENA8" "0,1"
newline
bitfld.long 0x0 7. "CLRENA7,CLRENA7" "0,1"
bitfld.long 0x0 6. "CLRENA6,CLRENA6" "0,1"
bitfld.long 0x0 5. "CLRENA5,CLRENA5" "0,1"
bitfld.long 0x0 4. "CLRENA4,CLRENA4" "0,1"
bitfld.long 0x0 3. "CLRENA3,CLRENA3" "0,1"
bitfld.long 0x0 2. "CLRENA2,CLRENA2" "0,1"
newline
bitfld.long 0x0 1. "CLRENA1,CLRENA1" "0,1"
bitfld.long 0x0 0. "CLRENA0,CLRENA0" "0,1"
line.long 0x4 "ICER1,ICER1"
bitfld.long 0x4 31. "CLRENA63,CLRENA63" "0,1"
bitfld.long 0x4 30. "CLRENA62,CLRENA62" "0,1"
bitfld.long 0x4 29. "CLRENA61,CLRENA61" "0,1"
bitfld.long 0x4 28. "CLRENA60,CLRENA60" "0,1"
bitfld.long 0x4 27. "CLRENA59,CLRENA59" "0,1"
bitfld.long 0x4 26. "CLRENA58,CLRENA58" "0,1"
newline
bitfld.long 0x4 25. "CLRENA57,CLRENA57" "0,1"
bitfld.long 0x4 24. "CLRENA56,CLRENA56" "0,1"
bitfld.long 0x4 23. "CLRENA55,CLRENA55" "0,1"
bitfld.long 0x4 22. "CLRENA54,CLRENA54" "0,1"
bitfld.long 0x4 21. "CLRENA53,CLRENA53" "0,1"
bitfld.long 0x4 20. "CLRENA52,CLRENA52" "0,1"
newline
bitfld.long 0x4 19. "CLRENA51,CLRENA51" "0,1"
bitfld.long 0x4 18. "CLRENA50,CLRENA50" "0,1"
bitfld.long 0x4 17. "CLRENA49,CLRENA49" "0,1"
bitfld.long 0x4 16. "CLRENA48,CLRENA48" "0,1"
bitfld.long 0x4 15. "CLRENA47,CLRENA47" "0,1"
bitfld.long 0x4 14. "CLRENA46,CLRENA46" "0,1"
newline
bitfld.long 0x4 13. "CLRENA45,CLRENA45" "0,1"
bitfld.long 0x4 12. "CLRENA44,CLRENA44" "0,1"
bitfld.long 0x4 11. "CLRENA43,CLRENA43" "0,1"
bitfld.long 0x4 10. "CLRENA42,CLRENA42" "0,1"
bitfld.long 0x4 9. "CLRENA41,CLRENA41" "0,1"
bitfld.long 0x4 8. "CLRENA40,CLRENA40" "0,1"
newline
bitfld.long 0x4 7. "CLRENA39,CLRENA39" "0,1"
bitfld.long 0x4 6. "CLRENA38,CLRENA38" "0,1"
bitfld.long 0x4 5. "CLRENA37,CLRENA37" "0,1"
bitfld.long 0x4 4. "CLRENA36,CLRENA36" "0,1"
bitfld.long 0x4 3. "CLRENA35,CLRENA35" "0,1"
bitfld.long 0x4 2. "CLRENA34,CLRENA34" "0,1"
newline
bitfld.long 0x4 1. "CLRENA33,CLRENA33" "0,1"
bitfld.long 0x4 0. "CLRENA32,CLRENA32" "0,1"
line.long 0x8 "ICER2,ICER2"
bitfld.long 0x8 4. "CLRENA68,CLRENA68" "0,1"
bitfld.long 0x8 3. "CLRENA67,CLRENA67" "0,1"
bitfld.long 0x8 2. "CLRENA66,CLRENA66" "0,1"
bitfld.long 0x8 1. "CLRENA65,CLRENA65" "0,1"
bitfld.long 0x8 0. "CLRENA64,CLRENA64" "0,1"
group.long 0x200++0xB
line.long 0x0 "ISPR0,ISPR0"
bitfld.long 0x0 31. "SETPEND31,SETPEND31" "0,1"
bitfld.long 0x0 30. "SETPEND30,SETPEND30" "0,1"
bitfld.long 0x0 29. "SETPEND29,SETPEND29" "0,1"
bitfld.long 0x0 28. "SETPEND28,SETPEND28" "0,1"
bitfld.long 0x0 27. "SETPEND27,SETPEND27" "0,1"
bitfld.long 0x0 26. "SETPEND26,SETPEND26" "0,1"
newline
bitfld.long 0x0 25. "SETPEND25,SETPEND25" "0,1"
bitfld.long 0x0 24. "SETPEND24,SETPEND24" "0,1"
bitfld.long 0x0 23. "SETPEND23,SETPEND23" "0,1"
bitfld.long 0x0 22. "SETPEND22,SETPEND22" "0,1"
bitfld.long 0x0 21. "SETPEND21,SETPEND21" "0,1"
bitfld.long 0x0 20. "SETPEND20,SETPEND20" "0,1"
newline
bitfld.long 0x0 19. "SETPEND19,SETPEND19" "0,1"
bitfld.long 0x0 18. "SETPEND18,SETPEND18" "0,1"
bitfld.long 0x0 17. "SETPEND17,SETPEND17" "0,1"
bitfld.long 0x0 16. "SETPEND16,SETPEND16" "0,1"
bitfld.long 0x0 15. "SETPEND15,SETPEND15" "0,1"
bitfld.long 0x0 14. "SETPEND14,SETPEND14" "0,1"
newline
bitfld.long 0x0 13. "SETPEND13,SETPEND13" "0,1"
bitfld.long 0x0 12. "SETPEND12,SETPEND12" "0,1"
bitfld.long 0x0 11. "SETPEND11,SETPEND11" "0,1"
bitfld.long 0x0 10. "SETPEND10,SETPEND10" "0,1"
bitfld.long 0x0 9. "SETPEND9,SETPEND9" "0,1"
bitfld.long 0x0 8. "SETPEND8,SETPEND8" "0,1"
newline
bitfld.long 0x0 7. "SETPEND7,SETPEND7" "0,1"
bitfld.long 0x0 6. "SETPEND6,SETPEND6" "0,1"
bitfld.long 0x0 5. "SETPEND5,SETPEND5" "0,1"
bitfld.long 0x0 4. "SETPEND4,SETPEND4" "0,1"
bitfld.long 0x0 3. "SETPEND3,SETPEND3" "0,1"
bitfld.long 0x0 2. "SETPEND2,SETPEND2" "0,1"
newline
bitfld.long 0x0 1. "SETPEND1,SETPEND1" "0,1"
bitfld.long 0x0 0. "SETPEND0,SETPEND0" "0,1"
line.long 0x4 "ISPR1,ISPR1"
bitfld.long 0x4 31. "SETPEND63,SETPEND63" "0,1"
bitfld.long 0x4 30. "SETPEND62,SETPEND62" "0,1"
bitfld.long 0x4 29. "SETPEND61,SETPEND61" "0,1"
bitfld.long 0x4 28. "SETPEND60,SETPEND60" "0,1"
bitfld.long 0x4 27. "SETPEND59,SETPEND59" "0,1"
bitfld.long 0x4 26. "SETPEND58,SETPEND58" "0,1"
newline
bitfld.long 0x4 25. "SETPEND57,SETPEND57" "0,1"
bitfld.long 0x4 24. "SETPEND56,SETPEND56" "0,1"
bitfld.long 0x4 23. "SETPEND55,SETPEND55" "0,1"
bitfld.long 0x4 22. "SETPEND54,SETPEND54" "0,1"
bitfld.long 0x4 21. "SETPEND53,SETPEND53" "0,1"
bitfld.long 0x4 20. "SETPEND52,SETPEND52" "0,1"
newline
bitfld.long 0x4 19. "SETPEND51,SETPEND51" "0,1"
bitfld.long 0x4 18. "SETPEND50,SETPEND50" "0,1"
bitfld.long 0x4 17. "SETPEND49,SETPEND49" "0,1"
bitfld.long 0x4 16. "SETPEND48,SETPEND48" "0,1"
bitfld.long 0x4 15. "SETPEND47,SETPEND47" "0,1"
bitfld.long 0x4 14. "SETPEND46,SETPEND46" "0,1"
newline
bitfld.long 0x4 13. "SETPEND45,SETPEND45" "0,1"
bitfld.long 0x4 12. "SETPEND44,SETPEND44" "0,1"
bitfld.long 0x4 11. "SETPEND43,SETPEND43" "0,1"
bitfld.long 0x4 10. "SETPEND42,SETPEND42" "0,1"
bitfld.long 0x4 9. "SETPEND41,SETPEND41" "0,1"
bitfld.long 0x4 8. "SETPEND40,SETPEND40" "0,1"
newline
bitfld.long 0x4 7. "SETPEND39,SETPEND39" "0,1"
bitfld.long 0x4 6. "SETPEND38,SETPEND38" "0,1"
bitfld.long 0x4 5. "SETPEND37,SETPEND37" "0,1"
bitfld.long 0x4 4. "SETPEND36,SETPEND36" "0,1"
bitfld.long 0x4 3. "SETPEND35,SETPEND35" "0,1"
bitfld.long 0x4 2. "SETPEND34,SETPEND34" "0,1"
newline
bitfld.long 0x4 1. "SETPEND33,SETPEND33" "0,1"
bitfld.long 0x4 0. "SETPEND32,SETPEND32" "0,1"
line.long 0x8 "ISPR2,ISPR2"
bitfld.long 0x8 4. "SETPEND68,SETPEND68" "0,1"
bitfld.long 0x8 3. "SETPEND67,SETPEND67" "0,1"
bitfld.long 0x8 2. "SETPEND66,SETPEND66" "0,1"
bitfld.long 0x8 1. "SETPEND65,SETPEND65" "0,1"
bitfld.long 0x8 0. "SETPEND64,SETPEND64" "0,1"
group.long 0x280++0xB
line.long 0x0 "ICPR0,ICPR0"
bitfld.long 0x0 31. "CLRPEND31,CLRPEND31" "0,1"
bitfld.long 0x0 30. "CLRPEND30,CLRPEND30" "0,1"
bitfld.long 0x0 29. "CLRPEND29,CLRPEND29" "0,1"
bitfld.long 0x0 28. "CLRPEND28,CLRPEND28" "0,1"
bitfld.long 0x0 27. "CLRPEND27,CLRPEND27" "0,1"
bitfld.long 0x0 26. "CLRPEND26,CLRPEND26" "0,1"
newline
bitfld.long 0x0 25. "CLRPEND25,CLRPEND25" "0,1"
bitfld.long 0x0 24. "CLRPEND24,CLRPEND24" "0,1"
bitfld.long 0x0 23. "CLRPEND23,CLRPEND23" "0,1"
bitfld.long 0x0 22. "CLRPEND22,CLRPEND22" "0,1"
bitfld.long 0x0 21. "CLRPEND21,CLRPEND21" "0,1"
bitfld.long 0x0 20. "CLRPEND20,CLRPEND20" "0,1"
newline
bitfld.long 0x0 19. "CLRPEND19,CLRPEND19" "0,1"
bitfld.long 0x0 18. "CLRPEND18,CLRPEND18" "0,1"
bitfld.long 0x0 17. "CLRPEND17,CLRPEND17" "0,1"
bitfld.long 0x0 16. "CLRPEND16,CLRPEND16" "0,1"
bitfld.long 0x0 15. "CLRPEND15,CLRPEND15" "0,1"
bitfld.long 0x0 14. "CLRPEND14,CLRPEND14" "0,1"
newline
bitfld.long 0x0 13. "CLRPEND13,CLRPEND13" "0,1"
bitfld.long 0x0 12. "CLRPEND12,CLRPEND12" "0,1"
bitfld.long 0x0 11. "CLRPEND11,CLRPEND11" "0,1"
bitfld.long 0x0 10. "CLRPEND10,CLRPEND10" "0,1"
bitfld.long 0x0 9. "CLRPEND9,CLRPEND9" "0,1"
bitfld.long 0x0 8. "CLRPEND8,CLRPEND8" "0,1"
newline
bitfld.long 0x0 7. "CLRPEND7,CLRPEND7" "0,1"
bitfld.long 0x0 6. "CLRPEND6,CLRPEND6" "0,1"
bitfld.long 0x0 5. "CLRPEND5,CLRPEND5" "0,1"
bitfld.long 0x0 4. "CLRPEND4,CLRPEND4" "0,1"
bitfld.long 0x0 3. "CLRPEND3,CLRPEND3" "0,1"
bitfld.long 0x0 2. "CLRPEND2,CLRPEND2" "0,1"
newline
bitfld.long 0x0 1. "CLRPEND1,CLRPEND1" "0,1"
bitfld.long 0x0 0. "CLRPEND0,CLRPEND0" "0,1"
line.long 0x4 "ICPR1,ICPR1"
bitfld.long 0x4 31. "CLRPEND63,CLRPEND63" "0,1"
bitfld.long 0x4 30. "CLRPEND62,CLRPEND62" "0,1"
bitfld.long 0x4 29. "CLRPEND61,CLRPEND61" "0,1"
bitfld.long 0x4 28. "CLRPEND60,CLRPEND60" "0,1"
bitfld.long 0x4 27. "CLRPEND59,CLRPEND59" "0,1"
bitfld.long 0x4 26. "CLRPEND58,CLRPEND58" "0,1"
newline
bitfld.long 0x4 25. "CLRPEND57,CLRPEND57" "0,1"
bitfld.long 0x4 24. "CLRPEND56,CLRPEND56" "0,1"
bitfld.long 0x4 23. "CLRPEND55,CLRPEND55" "0,1"
bitfld.long 0x4 22. "CLRPEND54,CLRPEND54" "0,1"
bitfld.long 0x4 21. "CLRPEND53,CLRPEND53" "0,1"
bitfld.long 0x4 20. "CLRPEND52,CLRPEND52" "0,1"
newline
bitfld.long 0x4 19. "CLRPEND51,CLRPEND51" "0,1"
bitfld.long 0x4 18. "CLRPEND50,CLRPEND50" "0,1"
bitfld.long 0x4 17. "CLRPEND49,CLRPEND49" "0,1"
bitfld.long 0x4 16. "CLRPEND48,CLRPEND48" "0,1"
bitfld.long 0x4 15. "CLRPEND47,CLRPEND47" "0,1"
bitfld.long 0x4 14. "CLRPEND46,CLRPEND46" "0,1"
newline
bitfld.long 0x4 13. "CLRPEND45,CLRPEND45" "0,1"
bitfld.long 0x4 12. "CLRPEND44,CLRPEND44" "0,1"
bitfld.long 0x4 11. "CLRPEND43,CLRPEND43" "0,1"
bitfld.long 0x4 10. "CLRPEND42,CLRPEND42" "0,1"
bitfld.long 0x4 9. "CLRPEND41,CLRPEND41" "0,1"
bitfld.long 0x4 8. "CLRPEND40,CLRPEND40" "0,1"
newline
bitfld.long 0x4 7. "CLRPEND39,CLRPEND39" "0,1"
bitfld.long 0x4 6. "CLRPEND38,CLRPEND38" "0,1"
bitfld.long 0x4 5. "CLRPEND37,CLRPEND37" "0,1"
bitfld.long 0x4 4. "CLRPEND36,CLRPEND36" "0,1"
bitfld.long 0x4 3. "CLRPEND35,CLRPEND35" "0,1"
bitfld.long 0x4 2. "CLRPEND34,CLRPEND34" "0,1"
newline
bitfld.long 0x4 1. "CLRPEND33,CLRPEND33" "0,1"
bitfld.long 0x4 0. "CLRPEND32,CLRPEND32" "0,1"
line.long 0x8 "ICPR2,ICPR2"
bitfld.long 0x8 4. "CLRPEND68,CLRPEND68" "0,1"
bitfld.long 0x8 3. "CLRPEND67,CLRPEND67" "0,1"
bitfld.long 0x8 2. "CLRPEND66,CLRPEND66" "0,1"
bitfld.long 0x8 1. "CLRPEND65,CLRPEND65" "0,1"
bitfld.long 0x8 0. "CLRPEND64,CLRPEND64" "0,1"
group.long 0x300++0xB
line.long 0x0 "IABR0,IABR0"
bitfld.long 0x0 31. "ACTIVE31,ACTIVE31" "0,1"
bitfld.long 0x0 30. "ACTIVE30,ACTIVE30" "0,1"
bitfld.long 0x0 29. "ACTIVE29,ACTIVE29" "0,1"
bitfld.long 0x0 28. "ACTIVE28,ACTIVE28" "0,1"
bitfld.long 0x0 27. "ACTIVE27,ACTIVE27" "0,1"
bitfld.long 0x0 26. "ACTIVE26,ACTIVE26" "0,1"
newline
bitfld.long 0x0 25. "ACTIVE25,ACTIVE25" "0,1"
bitfld.long 0x0 24. "ACTIVE24,ACTIVE24" "0,1"
bitfld.long 0x0 23. "ACTIVE23,ACTIVE23" "0,1"
bitfld.long 0x0 22. "ACTIVE22,ACTIVE22" "0,1"
bitfld.long 0x0 21. "ACTIVE21,ACTIVE21" "0,1"
bitfld.long 0x0 20. "ACTIVE20,ACTIVE20" "0,1"
newline
bitfld.long 0x0 19. "ACTIVE19,ACTIVE19" "0,1"
bitfld.long 0x0 18. "ACTIVE18,ACTIVE18" "0,1"
bitfld.long 0x0 17. "ACTIVE17,ACTIVE17" "0,1"
bitfld.long 0x0 16. "ACTIVE16,ACTIVE16" "0,1"
bitfld.long 0x0 15. "ACTIVE15,ACTIVE15" "0,1"
bitfld.long 0x0 14. "ACTIVE14,ACTIVE14" "0,1"
newline
bitfld.long 0x0 13. "ACTIVE13,ACTIVE13" "0,1"
bitfld.long 0x0 12. "ACTIVE12,ACTIVE12" "0,1"
bitfld.long 0x0 11. "ACTIVE11,ACTIVE11" "0,1"
bitfld.long 0x0 10. "ACTIVE10,ACTIVE10" "0,1"
bitfld.long 0x0 9. "ACTIVE9,ACTIVE9" "0,1"
bitfld.long 0x0 8. "ACTIVE8,ACTIVE8" "0,1"
newline
bitfld.long 0x0 7. "ACTIVE7,ACTIVE7" "0,1"
bitfld.long 0x0 6. "ACTIVE6,ACTIVE6" "0,1"
bitfld.long 0x0 5. "ACTIVE5,ACTIVE5" "0,1"
bitfld.long 0x0 4. "ACTIVE4,ACTIVE4" "0,1"
bitfld.long 0x0 3. "ACTIVE3,ACTIVE3" "0,1"
bitfld.long 0x0 2. "ACTIVE2,ACTIVE2" "0,1"
newline
bitfld.long 0x0 1. "ACTIVE1,ACTIVE1" "0,1"
bitfld.long 0x0 0. "ACTIVE0,ACTIVE0" "0,1"
line.long 0x4 "IABR1,IABR1"
bitfld.long 0x4 31. "ACTIVE63,ACTIVE63" "0,1"
bitfld.long 0x4 30. "ACTIVE62,ACTIVE62" "0,1"
bitfld.long 0x4 29. "ACTIVE61,ACTIVE61" "0,1"
bitfld.long 0x4 28. "ACTIVE60,ACTIVE60" "0,1"
bitfld.long 0x4 27. "ACTIVE59,ACTIVE59" "0,1"
bitfld.long 0x4 26. "ACTIVE58,ACTIVE58" "0,1"
newline
bitfld.long 0x4 25. "ACTIVE57,ACTIVE57" "0,1"
bitfld.long 0x4 24. "ACTIVE56,ACTIVE56" "0,1"
bitfld.long 0x4 23. "ACTIVE55,ACTIVE55" "0,1"
bitfld.long 0x4 22. "ACTIVE54,ACTIVE54" "0,1"
bitfld.long 0x4 21. "ACTIVE53,ACTIVE53" "0,1"
bitfld.long 0x4 20. "ACTIVE52,ACTIVE52" "0,1"
newline
bitfld.long 0x4 19. "ACTIVE51,ACTIVE51" "0,1"
bitfld.long 0x4 18. "ACTIVE50,ACTIVE50" "0,1"
bitfld.long 0x4 17. "ACTIVE49,ACTIVE49" "0,1"
bitfld.long 0x4 16. "ACTIVE48,ACTIVE48" "0,1"
bitfld.long 0x4 15. "ACTIVE47,ACTIVE47" "0,1"
bitfld.long 0x4 14. "ACTIVE46,ACTIVE46" "0,1"
newline
bitfld.long 0x4 13. "ACTIVE45,ACTIVE45" "0,1"
bitfld.long 0x4 12. "ACTIVE44,ACTIVE44" "0,1"
bitfld.long 0x4 11. "ACTIVE43,ACTIVE43" "0,1"
bitfld.long 0x4 10. "ACTIVE42,ACTIVE42" "0,1"
bitfld.long 0x4 9. "ACTIVE41,ACTIVE41" "0,1"
bitfld.long 0x4 8. "ACTIVE40,ACTIVE40" "0,1"
newline
bitfld.long 0x4 7. "ACTIVE39,ACTIVE39" "0,1"
bitfld.long 0x4 6. "ACTIVE38,ACTIVE38" "0,1"
bitfld.long 0x4 5. "ACTIVE37,ACTIVE37" "0,1"
bitfld.long 0x4 4. "ACTIVE36,ACTIVE36" "0,1"
bitfld.long 0x4 3. "ACTIVE35,ACTIVE35" "0,1"
bitfld.long 0x4 2. "ACTIVE34,ACTIVE34" "0,1"
newline
bitfld.long 0x4 1. "ACTIVE33,ACTIVE33" "0,1"
bitfld.long 0x4 0. "ACTIVE32,ACTIVE32" "0,1"
line.long 0x8 "IABR2,IABR2"
bitfld.long 0x8 4. "ACTIVE68,ACTIVE68" "0,1"
bitfld.long 0x8 3. "ACTIVE67,ACTIVE67" "0,1"
bitfld.long 0x8 2. "ACTIVE66,ACTIVE66" "0,1"
bitfld.long 0x8 1. "ACTIVE65,ACTIVE65" "0,1"
bitfld.long 0x8 0. "ACTIVE64,ACTIVE64" "0,1"
group.long 0x400++0x47
line.long 0x0 "IP0,IP0"
hexmask.long.byte 0x0 24.--31. 1. "PRI_3,PRI_3"
hexmask.long.byte 0x0 16.--23. 1. "PRI_2,PRI_2"
hexmask.long.byte 0x0 8.--15. 1. "PRI_1,PRI_1"
hexmask.long.byte 0x0 0.--7. 1. "PRI_0,PRI_0"
line.long 0x4 "IP1,IP1"
hexmask.long.byte 0x4 24.--31. 1. "PRI_7,PRI_7"
hexmask.long.byte 0x4 16.--23. 1. "PRI_6,PRI_6"
hexmask.long.byte 0x4 8.--15. 1. "PRI_5,PRI_5"
hexmask.long.byte 0x4 0.--7. 1. "PRI_4,PRI_4"
line.long 0x8 "IP2,IP2"
hexmask.long.byte 0x8 24.--31. 1. "PRI_11,PRI_11"
hexmask.long.byte 0x8 16.--23. 1. "PRI_10,PRI_10"
hexmask.long.byte 0x8 8.--15. 1. "PRI_9,PRI_9"
hexmask.long.byte 0x8 0.--7. 1. "PRI_8,PRI_8"
line.long 0xC "IP3,IP3"
hexmask.long.byte 0xC 24.--31. 1. "PRI_15,PRI_15"
hexmask.long.byte 0xC 16.--23. 1. "PRI_14,PRI_14"
hexmask.long.byte 0xC 8.--15. 1. "PRI_13,PRI_13"
hexmask.long.byte 0xC 0.--7. 1. "PRI_12,PRI_12"
line.long 0x10 "IP4,IP4"
hexmask.long.byte 0x10 24.--31. 1. "PRI_19,PRI_19"
hexmask.long.byte 0x10 16.--23. 1. "PRI_18,PRI_18"
hexmask.long.byte 0x10 8.--15. 1. "PRI_17,PRI_17"
hexmask.long.byte 0x10 0.--7. 1. "PRI_16,PRI_16"
line.long 0x14 "IP5,IP5"
hexmask.long.byte 0x14 24.--31. 1. "PRI_23,PRI_23"
hexmask.long.byte 0x14 16.--23. 1. "PRI_22,PRI_22"
hexmask.long.byte 0x14 8.--15. 1. "PRI_21,PRI_21"
hexmask.long.byte 0x14 0.--7. 1. "PRI_20,PRI_20"
line.long 0x18 "IP6,IP6"
hexmask.long.byte 0x18 24.--31. 1. "PRI_27,PRI_27"
hexmask.long.byte 0x18 16.--23. 1. "PRI_26,PRI_26"
hexmask.long.byte 0x18 8.--15. 1. "PRI_25,PRI_25"
hexmask.long.byte 0x18 0.--7. 1. "PRI_24,PRI_24"
line.long 0x1C "IP7,IP7"
hexmask.long.byte 0x1C 24.--31. 1. "PRI_31,PRI_31"
hexmask.long.byte 0x1C 16.--23. 1. "PRI_30,PRI_30"
hexmask.long.byte 0x1C 8.--15. 1. "PRI_29,PRI_29"
hexmask.long.byte 0x1C 0.--7. 1. "PRI_28,PRI_28"
line.long 0x20 "IP8,IP8"
hexmask.long.byte 0x20 24.--31. 1. "PRI_35,PRI_35"
hexmask.long.byte 0x20 16.--23. 1. "PRI_34,PRI_34"
hexmask.long.byte 0x20 8.--15. 1. "PRI_33,PRI_33"
hexmask.long.byte 0x20 0.--7. 1. "PRI_32,PRI_32"
line.long 0x24 "IP9,IP9"
hexmask.long.byte 0x24 24.--31. 1. "PRI_39,PRI_39"
hexmask.long.byte 0x24 16.--23. 1. "PRI_38,PRI_38"
hexmask.long.byte 0x24 8.--15. 1. "PRI_37,PRI_37"
hexmask.long.byte 0x24 0.--7. 1. "PRI_36,PRI_36"
line.long 0x28 "IP10,IP10"
hexmask.long.byte 0x28 24.--31. 1. "PRI_43,PRI_43"
hexmask.long.byte 0x28 16.--23. 1. "PRI_42,PRI_42"
hexmask.long.byte 0x28 8.--15. 1. "PRI_41,PRI_41"
hexmask.long.byte 0x28 0.--7. 1. "PRI_40,PRI_40"
line.long 0x2C "IP11,IP11"
hexmask.long.byte 0x2C 24.--31. 1. "PRI_47,PRI_47"
hexmask.long.byte 0x2C 16.--23. 1. "PRI_46,PRI_46"
hexmask.long.byte 0x2C 8.--15. 1. "PRI_45,PRI_45"
hexmask.long.byte 0x2C 0.--7. 1. "PRI_44,PRI_44"
line.long 0x30 "IP12,IP12"
hexmask.long.byte 0x30 24.--31. 1. "PRI_51,PRI_51"
hexmask.long.byte 0x30 16.--23. 1. "PRI_50,PRI_50"
hexmask.long.byte 0x30 8.--15. 1. "PRI_49,PRI_49"
hexmask.long.byte 0x30 0.--7. 1. "PRI_48,PRI_48"
line.long 0x34 "IP13,IP13"
hexmask.long.byte 0x34 24.--31. 1. "PRI_55,PRI_55"
hexmask.long.byte 0x34 16.--23. 1. "PRI_54,PRI_54"
hexmask.long.byte 0x34 8.--15. 1. "PRI_53,PRI_53"
hexmask.long.byte 0x34 0.--7. 1. "PRI_52,PRI_52"
line.long 0x38 "IP14,IP14"
hexmask.long.byte 0x38 24.--31. 1. "PRI_59,PRI_59"
hexmask.long.byte 0x38 16.--23. 1. "PRI_58,PRI_58"
hexmask.long.byte 0x38 8.--15. 1. "PRI_57,PRI_57"
hexmask.long.byte 0x38 0.--7. 1. "PRI_56,PRI_56"
line.long 0x3C "IP15,IP15"
hexmask.long.byte 0x3C 24.--31. 1. "PRI_63,PRI_63"
hexmask.long.byte 0x3C 16.--23. 1. "PRI_62,PRI_62"
hexmask.long.byte 0x3C 8.--15. 1. "PRI_61,PRI_61"
hexmask.long.byte 0x3C 0.--7. 1. "PRI_60,PRI_60"
line.long 0x40 "IP16,IP16"
hexmask.long.byte 0x40 24.--31. 1. "PRI_67,PRI_67"
hexmask.long.byte 0x40 16.--23. 1. "PRI_66,PRI_66"
hexmask.long.byte 0x40 8.--15. 1. "PRI_65,PRI_65"
hexmask.long.byte 0x40 0.--7. 1. "PRI_64,PRI_64"
line.long 0x44 "IP17,IP17"
hexmask.long.byte 0x44 0.--7. 1. "PRI_68,PRI_68"
group.long 0xD00++0xF
line.long 0x0 "CPUID,CPUID"
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,IMPLEMENTER"
hexmask.long.byte 0x0 20.--23. 1. "VARIANT,VARIANT"
hexmask.long.word 0x0 4.--15. 1. "PARTNO,PARTNO"
hexmask.long.byte 0x0 0.--3. 1. "REVISION,REVISION"
line.long 0x4 "ICSR,ICSR"
bitfld.long 0x4 31. "NMIPENDSET,NMIPENDSET" "0,1"
bitfld.long 0x4 28. "PENDSVSET,PENDSVSET" "0,1"
bitfld.long 0x4 27. "PENDSVCLR,PENDSVCLR" "0,1"
bitfld.long 0x4 26. "PENDSTSET,PENDSTSET" "0,1"
bitfld.long 0x4 25. "PENDSTCLR,PENDSTCLR" "0,1"
bitfld.long 0x4 23. "ISRPREEMPT,ISRPREEMPT" "0,1"
newline
bitfld.long 0x4 22. "ISRPENDING,ISRPENDING" "0,1"
hexmask.long.word 0x4 12.--21. 1. "VECTPENDING,VECTPENDING"
bitfld.long 0x4 11. "RETTOBASE,RETTOBASE" "0,1"
hexmask.long.word 0x4 0.--8. 1. "VECTACTIVE,VECTACTIVE"
line.long 0x8 "VTOR,VTOR"
bitfld.long 0x8 29. "TBLBASE,TBLBASE" "0,1"
hexmask.long.tbyte 0x8 7.--28. 1. "TBLOFF,TBLOFF"
line.long 0xC "AIRCR,AIRCR"
hexmask.long.word 0xC 16.--31. 1. "VECTKEY,VECTKEY"
bitfld.long 0xC 15. "ENDIANESS,ENDIANESS" "0,1"
bitfld.long 0xC 8.--10. "PRIGROUP,PRIGROUP" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 2. "SYSRESETREQ,SYSRESETREQ" "0,1"
bitfld.long 0xC 1. "VECTCLRACTIVE,VECTCLRACTIVE" "0,1"
bitfld.long 0xC 0. "VECTRESET,VECTRESET" "0,1"
group.long 0xD18++0xF
line.long 0x0 "SHP0,SHP0"
hexmask.long.byte 0x0 24.--31. 1. "PRI_7,PRI_7"
hexmask.long.byte 0x0 16.--23. 1. "PRI_6,PRI_6"
hexmask.long.byte 0x0 8.--15. 1. "PRI_5,PRI_5"
hexmask.long.byte 0x0 0.--7. 1. "PRI_4,PRI_4"
line.long 0x4 "SHP1,SHP1"
hexmask.long.byte 0x4 24.--31. 1. "PRI_11,PRI_11"
hexmask.long.byte 0x4 16.--23. 1. "PRI_10,PRI_10"
hexmask.long.byte 0x4 8.--15. 1. "PRI_9,PRI_9"
hexmask.long.byte 0x4 0.--7. 1. "PRI_8,PRI_8"
line.long 0x8 "SHP2,SHP2"
hexmask.long.byte 0x8 24.--31. 1. "PRI_15,PRI_15"
hexmask.long.byte 0x8 16.--23. 1. "PRI_14,PRI_14"
hexmask.long.byte 0x8 8.--15. 1. "PRI_13,PRI_13"
hexmask.long.byte 0x8 0.--7. 1. "PRI_12,PRI_12"
line.long 0xC "SHCSR,SHCSR"
bitfld.long 0xC 18. "USGFAULTENA,USGFAULTENA" "0,1"
bitfld.long 0xC 17. "BUSFAULTENA,BUSFAULTENA" "0,1"
bitfld.long 0xC 16. "MEMFAULTENA,MEMFAULTENA" "0,1"
bitfld.long 0xC 15. "SVCALLPENDED,SVCALLPENDED" "0,1"
bitfld.long 0xC 14. "BUSFAULTPENDED,BUSFAULTPENDED" "0,1"
bitfld.long 0xC 13. "MEMFAULTPENDED,MEMFAULTPENDED" "0,1"
newline
bitfld.long 0xC 12. "USGFAULTPENDED,USGFAULTPENDED" "0,1"
bitfld.long 0xC 11. "SYSTICKACT,SYSTICKACT" "0,1"
bitfld.long 0xC 10. "PENDSVACT,PENDSVACT" "0,1"
bitfld.long 0xC 8. "MONITORACT,MONITORACT" "0,1"
bitfld.long 0xC 7. "SVCALLACT,SVCALLACT" "0,1"
bitfld.long 0xC 3. "USGFAULTACT,USGFAULTACT" "0,1"
newline
bitfld.long 0xC 1. "BUSFAULTACT,BUSFAULTACT" "0,1"
bitfld.long 0xC 0. "MEMFAULTACT,MEMFAULTACT" "0,1"
group.long 0xF00++0x3
line.long 0x0 "STIR,STIR"
hexmask.long.word 0x0 0.--8. 1. "INTID,INTID"
tree.end
AUTOINDENT.OFF
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