146 lines
8.7 KiB
Plaintext
146 lines
8.7 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: CoreSight GPR (Granular Power Requestor) On-Chip Peripherals
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; @Props: Released
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; @Author: BES
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; @Changelog: 2020-08-03 BES
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; @Manufacturer: ARM - ARM Ltd.
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; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pergpr.per 13417 2021-07-02 08:14:51Z jboch $
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config 16. 8.
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width 12.
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base edap:per.arg()
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group 0x0--0x7 "Power"
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line.long 0x0 "CPWRUPREQ,Power Up Request"
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bitfld.long 0x0 0. " REQ0 ,Set cpwrupreq[0] output port" "off,on"
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bitfld.long 0x0 1. " REQ1 ,Set cpwrupreq[1] output port" "off,on"
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bitfld.long 0x0 2. " REQ2 ,Set cpwrupreq[2] output port" "off,on"
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bitfld.long 0x0 3. " REQ3 ,Set cpwrupreq[3] output port" "off,on"
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bitfld.long 0x0 4. " REQ4 ,Set cpwrupreq[4] output port" "off,on"
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bitfld.long 0x0 5. " REQ5 ,Set cpwrupreq[5] output port" "off,on"
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bitfld.long 0x0 6. " REQ6 ,Set cpwrupreq[6] output port" "off,on"
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bitfld.long 0x0 7. " REQ7 ,Set cpwrupreq[7] output port" "off,on"
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textline " "
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bitfld.long 0x0 8. " REQ8 ,Set cpwrupreq[8] output port" "off,on"
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bitfld.long 0x0 9. " REQ9 ,Set cpwrupreq[9] output port" "off,on"
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bitfld.long 0x0 10. " REQ10 ,Set cpwrupreq[10] output port" "off,on"
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bitfld.long 0x0 11. " REQ11 ,Set cpwrupreq[11] output port" "off,on"
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bitfld.long 0x0 12. " REQ12 ,Set cpwrupreq[12] output port" "off,on"
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bitfld.long 0x0 13. " REQ13 ,Set cpwrupreq[13] output port" "off,on"
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bitfld.long 0x0 14. " REQ14 ,Set cpwrupreq[14] output port" "off,on"
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bitfld.long 0x0 15. " REQ15 ,Set cpwrupreq[15] output port" "off,on"
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textline " "
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bitfld.long 0x0 16. " REQ16 ,Set cpwrupreq[16] output port" "off,on"
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bitfld.long 0x0 17. " REQ17 ,Set cpwrupreq[17] output port" "off,on"
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bitfld.long 0x0 18. " REQ18 ,Set cpwrupreq[18] output port" "off,on"
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bitfld.long 0x0 19. " REQ19 ,Set cpwrupreq[19] output port" "off,on"
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bitfld.long 0x0 20. " REQ20 ,Set cpwrupreq[20] output port" "off,on"
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bitfld.long 0x0 21. " REQ21 ,Set cpwrupreq[21] output port" "off,on"
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bitfld.long 0x0 22. " REQ22 ,Set cpwrupreq[22] output port" "off,on"
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bitfld.long 0x0 23. " REQ23 ,Set cpwrupreq[23] output port" "off,on"
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textline " "
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bitfld.long 0x0 24. " REQ24 ,Set cpwrupreq[24] output port" "off,on"
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bitfld.long 0x0 25. " REQ25 ,Set cpwrupreq[25] output port" "off,on"
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bitfld.long 0x0 26. " REQ26 ,Set cpwrupreq[26] output port" "off,on"
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bitfld.long 0x0 27. " REQ27 ,Set cpwrupreq[27] output port" "off,on"
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bitfld.long 0x0 28. " REQ28 ,Set cpwrupreq[28] output port" "off,on"
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bitfld.long 0x0 29. " REQ29 ,Set cpwrupreq[29] output port" "off,on"
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bitfld.long 0x0 30. " REQ30 ,Set cpwrupreq[30] output port" "off,on"
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bitfld.long 0x0 31. " REQ31 ,Set cpwrupreq[31] output port" "off,on"
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textline ""
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line.long 0x4 "CPWRUPACK,Power Up Acknowledge"
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bitfld.long 0x4 0. " ACK0 ,Set cpwrupACK[0] output port" "low,high"
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bitfld.long 0x4 1. " ACK1 ,Set cpwrupACK[1] output port" "low,high"
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bitfld.long 0x4 2. " ACK2 ,Set cpwrupACK[2] output port" "low,high"
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bitfld.long 0x4 3. " ACK3 ,Set cpwrupACK[3] output port" "low,high"
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bitfld.long 0x4 4. " ACK4 ,Set cpwrupACK[4] output port" "low,high"
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bitfld.long 0x4 5. " ACK5 ,Set cpwrupACK[5] output port" "low,high"
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bitfld.long 0x4 6. " ACK6 ,Set cpwrupACK[6] output port" "low,high"
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bitfld.long 0x4 7. " ACK7 ,Set cpwrupACK[7] output port" "low,high"
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textline " "
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bitfld.long 0x4 8. " ACK8 ,Set cpwrupACK[8] output port" "low,high"
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bitfld.long 0x4 9. " ACK9 ,Set cpwrupACK[9] output port" "low,high"
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bitfld.long 0x4 10. " ACK10 ,Set cpwrupACK[10] output port" "low,high"
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bitfld.long 0x4 11. " ACK11 ,Set cpwrupACK[11] output port" "low,high"
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bitfld.long 0x4 12. " ACK12 ,Set cpwrupACK[12] output port" "low,high"
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bitfld.long 0x4 13. " ACK13 ,Set cpwrupACK[13] output port" "low,high"
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bitfld.long 0x4 14. " ACK14 ,Set cpwrupACK[14] output port" "low,high"
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bitfld.long 0x4 15. " ACK15 ,Set cpwrupACK[15] output port" "low,high"
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textline " "
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bitfld.long 0x4 16. " ACK16 ,Set cpwrupACK[16] output port" "low,high"
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bitfld.long 0x4 17. " ACK17 ,Set cpwrupACK[17] output port" "low,high"
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bitfld.long 0x4 18. " ACK18 ,Set cpwrupACK[18] output port" "low,high"
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bitfld.long 0x4 19. " ACK19 ,Set cpwrupACK[19] output port" "low,high"
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bitfld.long 0x4 20. " ACK20 ,Set cpwrupACK[20] output port" "low,high"
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bitfld.long 0x4 21. " ACK21 ,Set cpwrupACK[21] output port" "low,high"
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bitfld.long 0x4 22. " ACK22 ,Set cpwrupACK[22] output port" "low,high"
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bitfld.long 0x4 23. " ACK23 ,Set cpwrupACK[23] output port" "low,high"
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textline " "
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bitfld.long 0x4 24. " ACK24 ,Set cpwrupACK[24] output port" "low,high"
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bitfld.long 0x4 25. " ACK25 ,Set cpwrupACK[25] output port" "low,high"
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bitfld.long 0x4 26. " ACK26 ,Set cpwrupACK[26] output port" "low,high"
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bitfld.long 0x4 27. " ACK27 ,Set cpwrupACK[27] output port" "low,high"
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bitfld.long 0x4 28. " ACK28 ,Set cpwrupACK[28] output port" "low,high"
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bitfld.long 0x4 29. " ACK29 ,Set cpwrupACK[29] output port" "low,high"
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bitfld.long 0x4 30. " ACK30 ,Set cpwrupACK[30] output port" "low,high"
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bitfld.long 0x4 31. " ACK31 ,Set cpwrupACK[31] output port" "low,high"
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group 0xF00--0xF03 "Integration"
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line.long 0x0 "ITCTRL,Integration Mode Control register"
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bitfld.long 0x0 0. " IME0 ,Integration mode enable on port 0" "dis,en"
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bitfld.long 0x0 1. " IME1 ,Integration mode enable on port 1" "dis,en"
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bitfld.long 0x0 2. " IME2 ,Integration mode enable on port 2" "dis,en"
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bitfld.long 0x0 3. " IME3 ,Integration mode enable on port 3" "dis,en"
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bitfld.long 0x0 4. " IME4 ,Integration mode enable on port 4" "dis,en"
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bitfld.long 0x0 5. " IME5 ,Integration mode enable on port 5" "dis,en"
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bitfld.long 0x0 6. " IME6 ,Integration mode enable on port 6" "dis,en"
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bitfld.long 0x0 7. " IME7 ,Integration mode enable on port 7" "dis,en"
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textline " "
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bitfld.long 0x0 8. " IME8 ,Integration mode enable on port 8" "dis,en"
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bitfld.long 0x0 9. " IME9 ,Integration mode enable on port 9" "dis,en"
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bitfld.long 0x0 10. " IME10 ,Integration mode enable on port 10" "dis,en"
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bitfld.long 0x0 11. " IME11 ,Integration mode enable on port 11" "dis,en"
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bitfld.long 0x0 12. " IME12 ,Integration mode enable on port 12" "dis,en"
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bitfld.long 0x0 13. " IME13 ,Integration mode enable on port 13" "dis,en"
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bitfld.long 0x0 14. " IME14 ,Integration mode enable on port 14" "dis,en"
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bitfld.long 0x0 15. " IME15 ,Integration mode enable on port 15" "dis,en"
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textline " "
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bitfld.long 0x0 16. " IME16 ,Integration mode enable on port 16" "dis,en"
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bitfld.long 0x0 17. " IME17 ,Integration mode enable on port 17" "dis,en"
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bitfld.long 0x0 18. " IME18 ,Integration mode enable on port 18" "dis,en"
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bitfld.long 0x0 19. " IME19 ,Integration mode enable on port 19" "dis,en"
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bitfld.long 0x0 20. " IME20 ,Integration mode enable on port 20" "dis,en"
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bitfld.long 0x0 21. " IME21 ,Integration mode enable on port 21" "dis,en"
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bitfld.long 0x0 22. " IME22 ,Integration mode enable on port 22" "dis,en"
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bitfld.long 0x0 23. " IME23 ,Integration mode enable on port 23" "dis,en"
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textline " "
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bitfld.long 0x0 24. " IME24 ,Integration mode enable on port 24" "dis,en"
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bitfld.long 0x0 25. " IME25 ,Integration mode enable on port 25" "dis,en"
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bitfld.long 0x0 26. " IME26 ,Integration mode enable on port 26" "dis,en"
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bitfld.long 0x0 27. " IME27 ,Integration mode enable on port 27" "dis,en"
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bitfld.long 0x0 28. " IME28 ,Integration mode enable on port 28" "dis,en"
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bitfld.long 0x0 29. " IME29 ,Integration mode enable on port 29" "dis,en"
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bitfld.long 0x0 30. " IME30 ,Integration mode enable on port 30" "dis,en"
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bitfld.long 0x0 31. " IME31 ,Integration mode enable on port 31" "dis,en"
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group 0xFA0--0xFA7 "Debug Claim"
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line.long 0x0 "CLAIMSET,Claim Set Register"
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line.long 0x4 "CLAIMCLR,Claim Clear Register"
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group 0xFB0--0xFBB "Access permission"
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line.long 0x0 "LAR,Lock Access Register"
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line.long 0x4 "LSR,Lock Status Register"
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line.long 0x8 "AUTHSTATUS,Authentication Status Register"
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rgroup 0xFBC--0xFFF "ID Registers"
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line.long 0x0 "DEVARCH,Device Architecture register,"
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line.long 0xC "DEVID,Device Configuration register"
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line.long 0x10 "DEVTYPE,Device Type Identifier register"
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line.long 0x24 "PIDR0,Peripheral ID0 Register"
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line.long 0x28 "PIDR1,Peripheral ID1 Register"
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line.long 0x2C "PIDR2,Peripheral ID2 Register"
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line.long 0x30 "PIDR3,Peripheral ID3 Register"
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line.long 0x14 "PIDR4,Peripheral ID4 Register"
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line.long 0x34 "CIDR0,Component ID0 Register"
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line.long 0x38 "CIDR1,Component ID1 Register"
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line.long 0x3C "CIDR2,Component ID2 Register"
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line.long 0x40 "CIDR3,Component ID3 Register"
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textline ""
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