2094 lines
146 KiB
Plaintext
2094 lines
146 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: ERTEC200, ERTEC400 On-Chip Peripherals
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; @Props: Released
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; @Author: MAL, ZEN
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; @Changelog: 2007-02-20 MAL
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Doc: UserManual.pdf (2006.05) Doc No. A17988EE1V0UM00
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; UserManual.pdf (2006.02) Doc No. A17812EE1V0UM00
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; @Core: ARM946E-S
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; @Chip: ERTEC200, ERTEC400
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perertecxxx.per 15961 2023-04-12 15:09:02Z bschroefel $
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config 16. 8.
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width 0xb
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tree "ARM Core Registers"
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width 8.
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tree "ID Registers"
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rgroup c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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rgroup c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMCFG ,Tightly coupled memory size configuraton"
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bitfld.long 0x0 18.--21. " DTCM , Data TCM size" "0,res,res,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,res,res,res,res"
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bitfld.long 0x0 14. " DTCM , Data TCM exists" "yes,no"
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textline " "
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bitfld.long 0x0 6.--9. " ITCM , Instruction TCM size" "0,res,res,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,res,res,res,res"
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bitfld.long 0x0 2. " ITCM , Instruction TCM exists" "yes,no"
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tree.end
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tree "System Configuration and Control"
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width 8.
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group c15:0x1--0x1
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 19. " ILOAD ,Instruction RAM Load Mode" "Disable,Enable"
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bitfld.long 0x0 18. " IRAM ,Instruction RAM Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 17. " DLOAD ,Data RAM Load Mode" "Disable,Enable"
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bitfld.long 0x0 16. " DRAM ,Data RAM Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MPU" "Disable,Enable"
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textline " "
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group c15:0x2--0x2
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line.long 0x0 "DCACHE,Data-Cacheable Register"
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bitfld.long 0x0 0x7 " No.7 ,Memory Area No.7 cacheable" "no,yes"
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bitfld.long 0x0 0x6 " No.6 ,Memory Area No.6 cacheable" "no,yes"
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bitfld.long 0x0 0x5 " No.5 ,Memory Area No.5 cacheable" "no,yes"
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bitfld.long 0x0 0x4 " No.4 ,Memory Area No.4 cacheable" "no,yes"
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bitfld.long 0x0 0x3 " No.3 ,Memory Area No.3 cacheable" "no,yes"
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bitfld.long 0x0 0x2 " No.2 ,Memory Area No.2 cacheable" "no,yes"
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bitfld.long 0x0 0x1 " No.1 ,Memory Area No.1 cacheable" "no,yes"
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bitfld.long 0x0 0x0 " No.0 ,Memory Area No.0 cacheable" "no,yes"
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group c15:0x102--0x102
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line.long 0x0 "ICACHE,Instruction-Cacheable Register"
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bitfld.long 0x0 0x7 " No.7 ,Memory Area No.7 cacheable" "no,yes"
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bitfld.long 0x0 0x6 " No.6 ,Memory Area No.6 cacheable" "no,yes"
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bitfld.long 0x0 0x5 " No.5 ,Memory Area No.5 cacheable" "no,yes"
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bitfld.long 0x0 0x4 " No.4 ,Memory Area No.4 cacheable" "no,yes"
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bitfld.long 0x0 0x3 " No.3 ,Memory Area No.3 cacheable" "no,yes"
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bitfld.long 0x0 0x2 " No.2 ,Memory Area No.2 cacheable" "no,yes"
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bitfld.long 0x0 0x1 " No.1 ,Memory Area No.1 cacheable" "no,yes"
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bitfld.long 0x0 0x0 " No.0 ,Memory Area No.0 cacheable" "no,yes"
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group c15:0x3--0x3
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line.long 0x0 "WRBUF,Write Buffer Control"
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bitfld.long 0x0 0x7 " No.7 ,Memory Area No.7 bufferable" "no,yes"
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bitfld.long 0x0 0x6 " No.6 ,Memory Area No.6 bufferable" "no,yes"
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bitfld.long 0x0 0x5 " No.5 ,Memory Area No.5 bufferable" "no,yes"
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bitfld.long 0x0 0x4 " No.4 ,Memory Area No.4 bufferable" "no,yes"
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bitfld.long 0x0 0x3 " No.3 ,Memory Area No.3 bufferable" "no,yes"
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bitfld.long 0x0 0x2 " No.2 ,Memory Area No.2 bufferable" "no,yes"
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bitfld.long 0x0 0x1 " No.1 ,Memory Area No.1 bufferable" "no,yes"
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bitfld.long 0x0 0x0 " No.0 ,Memory Area No.0 bufferable" "no,yes"
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textline " "
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group c15:0x05--0x05
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line.long 0x0 "DACCESS,Data Space Protection Register - Standard"
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bitfld.long 0x0 14.--15. " No.7 ,Memory Area No.7 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 12.--13. " No.6 ,Memory Area No.6 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 10.--11. " No.5 ,Memory Area No.5 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x8--0x9 " No.4 ,Memory Area No.4 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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textline " "
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bitfld.long 0x0 0x6--0x7 " No.3 ,Memory Area No.3 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x4--0x5 " No.2 ,Memory Area No.2 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x2--0x3 " No.1 ,Memory Area No.1 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x0--0x1 " No.0 ,Memory Area No.0 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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group c15:0x205--0x205
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line.long 0x0 "DACCESE,Data Space Protection Register - Extended"
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bitfld.long 0x0 28.--31. " No.7 ,Memory Area No.7 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 24.--27. " No.6 ,Memory Area No.6 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 20.--23. " No.5 ,Memory Area No.5 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 16.--19. " No.4 ,Memory Area No.4 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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textline " "
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bitfld.long 0x0 12.--15. " No.3 ,Memory Area No.3 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 8.--11. " No.2 ,Memory Area No.2 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 4.--7. " No.1 ,Memory Area No.1 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 0.--3. " No.0 ,Memory Area No.0 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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group c15:0x105--0x105
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line.long 0x0 "IACCESS,Instruction Space Protection Register - Standard"
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bitfld.long 0x0 14.--15. " No.7 ,Memory Area No.7 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 12.--13. " No.6 ,Memory Area No.6 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 10.--11. " No.5 ,Memory Area No.5 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x8--0x9 " No.4 ,Memory Area No.4 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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textline " "
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bitfld.long 0x0 0x6--0x7 " No.3 ,Memory Area No.3 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x4--0x5 " No.2 ,Memory Area No.2 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x2--0x3 " No.1 ,Memory Area No.1 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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bitfld.long 0x0 0x0--0x1 " No.0 ,Memory Area No.0 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w"
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group c15:0x305--0x305
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line.long 0x0 "IACCESE,Instruction Space Protection Register - Extended"
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bitfld.long 0x0 28.--31. " No.7 ,Memory Area No.7 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 24.--27. " No.6 ,Memory Area No.6 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 20.--23. " No.5 ,Memory Area No.5 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 16.--19. " No.4 ,Memory Area No.4 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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textline " "
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bitfld.long 0x0 12.--15. " No.3 ,Memory Area No.3 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 8.--11. " No.2 ,Memory Area No.2 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 4.--7. " No.1 ,Memory Area No.1 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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bitfld.long 0x0 0.--3. " No.0 ,Memory Area No.0 Access Permission" "S:no U:no ,S:r/w U:no ,S:r/w U:r ,S:r/w U:r/w ,S:UNP U:UNP,S:r U:no,S:r U:r,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP,S:UNP U:UNP"
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textline " "
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group c15:0x6--0x6
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line.long 0x0 "REG0,Protection region/size 0"
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hexmask.long 0x0 12.--31. 4096. " Base ,Region 0 base"
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bitfld.long 0x0 1.--5. " Size ,Region 0 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
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bitfld.long 0x0 0. " Enable:,Protection Enable 0" "no,yes"
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group c15:0x16--0x16
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line.long 0x0 "REG1,Protection region/size 1"
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hexmask.long 0x0 12.--31. 4096. " Base ,Region 1 base"
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bitfld.long 0x0 1.--5. " Size ,Region 1 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
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bitfld.long 0x0 0. " Enable:,Protection Enable 1" "no,yes"
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group c15:0x26--0x26
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line.long 0x0 "REG2,Protection region/size 2"
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hexmask.long 0x0 12.--31. 4096. " Base ,Region 2 base"
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bitfld.long 0x0 1.--5. " Size ,Region 2 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
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bitfld.long 0x0 0. " Enable:,Protection Enable 2" "no,yes"
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group c15:0x36--0x36
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line.long 0x0 "REG3,Protection region/size 3"
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hexmask.long 0x0 12.--31. 4096. " Base ,Region 3 base"
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bitfld.long 0x0 1.--5. " Size ,Region 3 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
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bitfld.long 0x0 0. " Enable:,Protection Enable 3" "no,yes"
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group c15:0x46--0x46
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line.long 0x0 "REG4,Protection region/size 4"
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hexmask.long 0x0 12.--31. 4096. " Base ,Region 4 base"
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bitfld.long 0x0 1.--5. " Size ,Region 4 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x0 0. " Enable:,Protection Enable 4" "no,yes"
|
|
group c15:0x56--0x56
|
|
line.long 0x0 "REG5,Protection region/size 5"
|
|
hexmask.long 0x0 12.--31. 4096. " Base ,Region 5 base"
|
|
bitfld.long 0x0 1.--5. " Size ,Region 5 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x0 0. " Enable:,Protection Enable 5" "no,yes"
|
|
group c15:0x66--0x66
|
|
line.long 0x0 "REG6,Protection region/size 6"
|
|
hexmask.long 0x0 12.--31. 4096. " Base ,Region 6 base"
|
|
bitfld.long 0x0 1.--5. " Size ,Region 6 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x0 0. " Enable:,Protection Enable 6" "no,yes"
|
|
group c15:0x76--0x76
|
|
line.long 0x0 "REG7,Protection region/size 7"
|
|
hexmask.long 0x0 12.--31. 4096. " Base ,Region 7 base"
|
|
bitfld.long 0x0 1.--5. " Size ,Region 7 size" "UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,UNP,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x0 0. " Enable:,Protection Enable 7" "no,yes"
|
|
group c15:0x19--0x19
|
|
line.long 0x0 "DTCM,Tightly-Coupled Data Memory Region"
|
|
hexmask.long 0x0 12.--31. 0x1000 " BASE ,Region Base"
|
|
bitfld.long 0x0 1.--5. " SIZE ,Area Size" "-,-,-,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,-,-,-,-,-,?..."
|
|
group c15:0x119--0x119
|
|
line.long 0x0 "ITCM,Tightly-Coupled Instruction Memory Region"
|
|
hexmask.long 0x0 12.--31. 0x1000 " BASE ,Region Base"
|
|
bitfld.long 0x0 1.--5. " SIZE ,Area Size" "-,-,-,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,-,-,-,-,-,?..."
|
|
textline " "
|
|
group c15:0x010d--0x010d
|
|
line.long 0x0 "CONTEXT,Context ID"
|
|
textline " "
|
|
group c15:0xf--0xf
|
|
line.long 0x0 "TSR,Test State Register"
|
|
bitfld.long 0x0 12. " DCSD ,Disable DCache Streaming" "ena,dis"
|
|
bitfld.long 0x0 11. " ICSD ,Disable ICache Streaming" "ena,dis"
|
|
bitfld.long 0x0 10. " DCLD ,Disable DCache Linefill" "ena,dis"
|
|
bitfld.long 0x0 9. " ICLD ,Disable ICache Linefill" "ena,dis"
|
|
tree.end
|
|
tree "ICEbreaker"
|
|
width 8.
|
|
group ice:0x0--0x5 "Debug Control"
|
|
line.long 0x0 "DBGCTRL,Debug Control Register"
|
|
bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
|
|
bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
|
|
bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
|
|
bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
|
|
bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
|
|
line.long 0x4 "DBGSTAT,Debug Status Register"
|
|
bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
|
|
bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
|
|
bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
|
|
bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
|
|
bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
|
|
bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
|
|
bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
|
|
line.long 0x8 "VECTOR,Vector Catch Register"
|
|
bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
|
|
bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
|
|
bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
|
|
bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
|
|
bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
|
|
bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
|
|
bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
|
|
line.long 0x10 "COMCTRL,Debug Communication Control Register"
|
|
bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
|
|
bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
|
|
line.long 0x14 "COMDATA,Debug Communication Data Register"
|
|
group ice:0x8--0x0d "Watchpoint 0"
|
|
line.long 0x0 "AV,Address Value"
|
|
line.long 0x4 "AM,Address Mask"
|
|
line.long 0x8 "DV,Data Value"
|
|
line.long 0x0c "DM,Data Mask"
|
|
line.long 0x10 "CV,Control Value"
|
|
bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
|
|
bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
|
|
bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
|
|
bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
|
|
bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
|
|
bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
|
|
bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
|
|
bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
|
|
line.long 0x14 "CM,Control Mask"
|
|
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
|
|
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
|
|
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
|
|
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
|
|
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
|
|
group ice:0x10--0x15 "Watchpoint 1"
|
|
line.long 0x0 "AV,Address Value"
|
|
line.long 0x4 "AM,Address Mask"
|
|
line.long 0x8 "DV,Data Value"
|
|
line.long 0x0c "DM,Data Mask"
|
|
line.long 0x10 "CV,Control Value"
|
|
bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
|
|
bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
|
|
bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
|
|
bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
|
|
bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
|
|
bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
|
|
bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
|
|
bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
|
|
line.long 0x14 "CM,Control Mask"
|
|
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
|
|
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
|
|
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
|
|
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
|
|
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "EMIF (External Memory Interface)"
|
|
base ad:0x70000000
|
|
sif (cpu()=="ERTEC200")
|
|
width 26.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "Revision_Code_and_Status,Revision Code and Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " MAJOR_REVISION ,Major revision code"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MINOR_REVISION ,Minor revision code"
|
|
group.long 0x4++0x1f
|
|
line.long 0x0 "Async_Wait_Cycle_Config,Async Wait Cycle Config Register"
|
|
bitfld.long 0x0 30. " WP , Wait polarity" "Low,High"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MAX_EXT_WAIT ,Number of AHB cycles before termination of an asynchronous memory or peripheral access with an IRQ"
|
|
line.long 0x4 "SDRAM_Bank_Config,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x4 13. " CL ,CAS latency" "2,3"
|
|
bitfld.long 0x4 8.--10. " ROWS ,Number of used row address lines" "8,9,10,11,12,13,?..."
|
|
textline " "
|
|
bitfld.long 0x4 4.--6. " IBANK ,Number of internal SDRAM banks" "1 bank,2 banks,4 banks,?..."
|
|
bitfld.long 0x4 0.--2. " PAGESIZE ,Number of column address lines" "8,9,10,11,?..."
|
|
line.long 0x8 "SDRAM_Refresh_Control,SDRAM Refresh Control Register"
|
|
bitfld.long 0x8 30. " AT ,Asynchronous timeout" "Not elapsed,Elapsed"
|
|
textline " "
|
|
bitfld.long 0x8 29. " INIT_DONE ,SDRAM initialization done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--12. 1. " REFRESH_RATE ,Number of AHB clock cycles between 2 SDRAM refresh cycles"
|
|
line.long 0xc "Async_BANK0_Config,Async Bank Configuration Register"
|
|
bitfld.long 0xc 31. " EWS_XAS ,Extended wait timing mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0xc 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0xc 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0xc 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0xc 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0xc 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0xc 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0xc 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0xc 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x10 "Async_BANK1_Config,Async Bank Configuration Register"
|
|
bitfld.long 0x10 31. " EWS_XAS ,Extended wait timing mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x10 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x10 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x10 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0x10 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x10 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x10 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0x10 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x14 "Async_BANK2_Config,Async Bank Configuration Register"
|
|
bitfld.long 0x14 31. " EWS_XAS ,Extended wait timing mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x14 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x14 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x14 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x14 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0x14 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x18 "Async_BANK3_Config,Async Bank Configuration Register"
|
|
bitfld.long 0x18 31. " EWS_XAS ,Extended wait timing mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x18 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
textline " "
|
|
bitfld.long 0x18 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x18 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0x18 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x18 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x18 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0x18 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x18 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x1c "Extended_Config,Extended Configuration Register"
|
|
bitfld.long 0x1c 30. " TEST_1 ,Test mode 1" "200us delay,Immediately"
|
|
textline " "
|
|
bitfld.long 0x1c 29. " TEST_2 ,Test mode 2" "Normal,SDRAM missed"
|
|
textline " "
|
|
bitfld.long 0x1c 25. " ADS ,Active data bus (for SDRAM)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 24. " ASDB ,Active data bus (for asynchronous)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " TEST_3 ,Test mode 3" "Normal,DTR_N test output"
|
|
textline " "
|
|
bitfld.long 0x1c 16.--17. " BURST_LENGTH ,SDRAM burst length" "1,2,4,8"
|
|
textline " "
|
|
bitfld.long 0x1c 14. " TRCD/TCD ,Time between the SDRAM commands" "2 clocks,1 clock"
|
|
textline " "
|
|
bitfld.long 0x1c 8. " SDSIZE ,SDRAM bank size" "32-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " ATIRQ ,Asynchronous access timeout enable" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
sif (cpu()=="ERTEC400")
|
|
width 26.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "Revision_Code_and_Status,Revision Code and Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " MAJOR_REVISION ,Major revision code"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MINOR_REVISION ,Minor revision code"
|
|
group.long 0x4++0x1f
|
|
line.long 0x0 "Async_Wait_Cycle_Config,Async Wait Cycle Config Register"
|
|
bitfld.long 0x0 30. " WP , Wait polarity" "Low,High"
|
|
hexmask.long.byte 0x0 0.--7. 1. " MAX_EXT_WAIT ,Number of AHB cycles before termination of an asynchronous memory or peripheral access with an IRQ"
|
|
line.long 0x4 "SDRAM_Bank_Config,SDRAM Bank Configuration Register"
|
|
bitfld.long 0x4 14. " WB ,Write burst type" "Burst,Single"
|
|
bitfld.long 0x4 13. " CL ,CAS latency" "2,3"
|
|
textline " "
|
|
bitfld.long 0x4 8.--10. " ROWS ,Number of used row address lines" "8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--6. " IBANK ,Number of internal SDRAM banks" "1 bank,2 banks,4 banks,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " PAGESIZE ,Number of column address lines" "8,9,10,11,?..."
|
|
line.long 0x8 "SDRAM_Refresh_Control,SDRAM Refresh Control Register"
|
|
bitfld.long 0x8 30. " AT ,Asynchronous timeout" "Not elapsed,Elapsed"
|
|
textline " "
|
|
bitfld.long 0x8 29. " INIT_DONE ,SDRAM initialization done" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--12. 1. " REFRESH_RATE ,Number of AHB clock cycles between 2 SDRAM refresh cycles"
|
|
line.long 0xc "Async_BANK0_Config,Async Bank Configuration Register"
|
|
bitfld.long 0xc 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
bitfld.long 0xc 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0xc 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0xc 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0xc 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0xc 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0xc 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0xc 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x10 "Async_BANK1_Config,Async Bank Configuration Register"
|
|
bitfld.long 0x10 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
bitfld.long 0x10 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x10 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0x10 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x10 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x10 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0x10 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x10 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x14 "Async_BANK2_Config,Async Bank Configuration Register"
|
|
bitfld.long 0x14 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
bitfld.long 0x14 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0x14 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x14 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x14 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x18 "Async_BANK3_Config,Async Bank Configuration Register"
|
|
bitfld.long 0x18 30. " EW ,Extended wait mode" "Ignored,Not ignored"
|
|
bitfld.long 0x18 26.--29. " W_SU ,Write strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x18 20.--25. " W_STROBE ,Write strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
bitfld.long 0x18 17.--19. " W_HOLD ,Write strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x18 13.--16. " R_SU ,Read strobe setup cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x18 7.--12. " R_STROBE ,Read strobe duration cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles,64 cycles"
|
|
textline " "
|
|
bitfld.long 0x18 4.--6. " R_HOLD ,Read strobe hold cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x18 0.--1. " ASIZE ,Data bus width" "8-bit,16-bit,32-bit,32-bit"
|
|
line.long 0x1c "Extended_Config,Extended Configuration Register"
|
|
bitfld.long 0x1c 30. " TEST_1 ,Test mode 1" "200us delay,Immediately"
|
|
bitfld.long 0x1c 29. " TEST_2 ,Test mode 2" "Normal,SDRAM missed"
|
|
textline " "
|
|
bitfld.long 0x1c 25. " ADB ,Active data bus (for SDRAM)" "Not active,Active"
|
|
bitfld.long 0x1c 24. " ASDB ,Active data bus (for asynchronous)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " TEST_3 ,Test mode 3" "Normal,DTR_N test output"
|
|
bitfld.long 0x1c 16.--17. " BURST_LENGTH ,SDRAM burst length" "1,2,4,8"
|
|
textline " "
|
|
bitfld.long 0x1c 14. " TRCD/TCD ,Time between the SDRAM commands" "2 clocks,1 clock"
|
|
bitfld.long 0x1c 8. " SDSIZE ,SDRAM bank size" "32-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x1c 7. " ATIRQ ,Asynchronous access timeout enable" "Disabled,Enabled"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="ERTEC200")
|
|
tree "DMA Controller"
|
|
base ad:0x80000000
|
|
width 21.
|
|
group.long 0x0++0xf
|
|
line.long 0x0 "DMAC0_SRC_ADDR_REG,DMA Source Address Register"
|
|
line.long 0x4 "DMAC0_DEST_ADDR_REG,DMA Destination Address Register"
|
|
line.long 0x8 "DMAC0_CONTR_REG,DMA Control Register"
|
|
bitfld.long 0x8 21.--23. " D_DELAY_EXTENSION ,D_DELAY extension in 50MHz clocks" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 16.--20. " S_DELAY_EXTENSION ,S_DELAY extension in 50MHz clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.long.word 0x8 0.--15. 1. " BYTE_COUNT ,Byte count"
|
|
line.long 0xc "DMAC0_CONF_REG,DMA Configuration Register"
|
|
bitfld.long 0xc 31. " START/ABORT ,DMA transfer start/abort" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0xc 29. " INTR_ENABLE ,DMA interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 27.--28. " SYNCHRONIZATION ,DMA synchronization scheme" "No synchronization,To destination,To source,To source and destination"
|
|
textline " "
|
|
bitfld.long 0xc 22.--23. " S_ADDR_MODE ,DMA source address modification" "Increment,Decrement,Hold,?..."
|
|
textline " "
|
|
bitfld.long 0xc 19.--21. " S_DMA_REQ ,DMA synchronization scheme" "SPI1_SPI1RXDMA,SPI1_SPI1TXDMA,UART_UARTRXINTR,UART_UARTTXINTR,?..."
|
|
textline " "
|
|
bitfld.long 0xc 16.--18. " S_WIDTH ,DMA data element width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xc 14.--15. " D_ADDR_MODE ,DMA destination address modification" "Increment,Decrement,Hold,?..."
|
|
textline " "
|
|
bitfld.long 0xc 11.--13. " D_DMA_REQ ,DMA synchronization scheme" "SPI1_SPI1RXDMA,SPI1_SPI1TXDMA,UART_UARTRXINTR,UART_UARTTXINTR,?..."
|
|
textline " "
|
|
bitfld.long 0xc 8.--10. " D_WIDTH ,DMA data element width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xc 4.--7. " D_DELAY ,Write inactive delay counter" "No delay,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks"
|
|
textline " "
|
|
bitfld.long 0xc 0.--3. " S_DELAY ,Read inactive delay counter" "No delay,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "Interrupt Controller"
|
|
base ad:0x50000000
|
|
width 13.
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IRVEC,IRQ Interrupt Vector Register"
|
|
hexmask.long 0x0 4.--31. 1. " Vector_ID ,Valid IRQ interrupt vectors from the default IRQ vector"
|
|
bitfld.long 0x0 0.--3. " IRVEC ,Number of the currently pending, valid IRQ interrupt vector with the highest priority" "IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,IRQ14,IRQ15"
|
|
line.long 0x4 "FIVEC,FIQ Interrupt Vector Register"
|
|
hexmask.long 0x4 3.--31. 1. " Vector_ID ,Valid FIQ interrupt vectors from the default FIQ vector"
|
|
bitfld.long 0x4 0.--2. " FIVEC ,Number of the currently pending valid FIQ interrupt vector with the highest priority" "FIQ0,FIQ1,FIQ2,FIQ3,FIQ4,FIQ5,FIQ6,FIQ7"
|
|
group.long 0x8++0xb
|
|
line.long 0x0 "LOCKREG,IRQ Interrupt Priority Lock Register"
|
|
bitfld.long 0x0 7. " LOCKENABLE ,Enable interrupt lock mechanism" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--3. " LOCKPRIO ,Blocked interrupt priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "FIQ1SREG,Interrupt Select Register"
|
|
bitfld.long 0x4 7. " FIQ1SENABLE ,Enable the re-routing of an IRQ interrupt to FIQ6" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--3. " FIQ1SREG ,Declaration of an IRQ interrupt as FIQ" "IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,IRQ14,IRQ15"
|
|
line.long 0x8 "FIQ2SREG,Interrupt Select Register"
|
|
bitfld.long 0x8 7. " FIQ2SENABLE ,Enable the re-routing of an IRQ interrupt to FIQ7" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--3. " FIQ2SREG ,Declaration of an IRQ interrupt as FIQ" "IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,IRQ14,IRQ15"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "IRQACK,IRQ Interrupt Acknowledge Register"
|
|
hexmask.long 0x0 4.--31. 1. " Vector_ID ,Valid IRQ interrupt vectors from the default IRQ vector"
|
|
bitfld.long 0x0 0.--3. " IRVEC ,Acknowledge of highest-priority pending interrupt request" "IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,IRQ14,IRQ15"
|
|
line.long 0x4 "FIQACK,FIQ Interrupt Acknowledge Register"
|
|
hexmask.long 0x4 3.--31. 1. " Vector_ID ,Valid FIQ interrupt vectors from the default FIQ vector"
|
|
bitfld.long 0x4 0.--2. " FIVEC ,Acknowledge of highest-priority pending interrupt request" "IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7"
|
|
wgroup.long 0x1c++0x3
|
|
line.long 0x0 "IRCLVEC,IRQ Interrupt Request Clear Register"
|
|
bitfld.long 0x0 0.--3. " IRCLVEC ,Clear the respective request the interrupt request register" "IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,IRQ8,IRQ9,IRQ10,IRQ11,IRQ12,IRQ13,IRQ14,IRQ15"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MASKALL,Mask All IRQ Interrupt Request Register"
|
|
bitfld.long 0x0 0. " MASKALL ,Mask all pending IRQ interrupt requests" "Enabled,Masked"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IRQEND,End of IRQ Interrupt Signaling Register"
|
|
line.long 0x4 "FIQEND,End of FIQ Interrupt Signaling Register"
|
|
group.long 0x2c++0x1f
|
|
line.long 0x0 "FIQPR0,Interrupt Priority Register"
|
|
bitfld.long 0x0 0.--2. " FIQPR0 ,FIQ0 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x4 "FIQPR1,Interrupt Priority Register"
|
|
bitfld.long 0x4 0.--2. " FIQPR1 ,FIQ1 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x8 "FIQPR2,Interrupt Priority Register"
|
|
bitfld.long 0x8 0.--2. " FIQPR2 ,FIQ2 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0xc "FIQPR3,Interrupt Priority Register"
|
|
bitfld.long 0xc 0.--2. " FIQPR3 ,FIQ3 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x10 "FIQPR4,Interrupt Priority Register"
|
|
bitfld.long 0x10 0.--2. " FIQPR4 ,FIQ4 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x14 "FIQPR5,Interrupt Priority Register"
|
|
bitfld.long 0x14 0.--2. " FIQPR5 ,FIQ5 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x18 "FIQPR6,Interrupt Priority Register"
|
|
bitfld.long 0x18 0.--2. " FIQPR6 ,FIQ6 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x1c "FIQPR7,Interrupt Priority Register"
|
|
bitfld.long 0x1c 0.--2. " FIQPR7 ,FIQ7 interrupt request priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x4c++0x7
|
|
line.long 0x0 "FIQISR,FIQ Interrupt In-Service Register"
|
|
bitfld.long 0x0 7. " FIQISR7 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 6. " FIQISR6 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FIQISR5 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 4. " FIQISR4 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 3. " FIQISR3 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 2. " FIQISR2 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 1. " FIQISR1 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 0. " FIQISR0 ,Confirmation of FIQ interrupt request" "Not confirmed,Confirmed"
|
|
line.long 0x4 "FIQIRR,Request Register"
|
|
bitfld.long 0x4 7. " FIQIRR7 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x4 6. " FIQIRR6 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x4 5. " FIQIRR5 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x4 4. " FIQIRR4 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x4 3. " FIQIRR3 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x4 2. " FIQIRR2 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x4 1. " FIQIRR1 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x4 0. " FIQIRR0 ,Recognition of FIQ interrupt request" "Not recognized,Recognized"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "FIQ_MASKREG,FIQ Interrupt Mask Register"
|
|
bitfld.long 0x0 7. " FIQ_MASKREG7 ,FIQ7 mask" "Enabled,Masked"
|
|
bitfld.long 0x0 6. " FIQ_MASKREG6 ,FIQ6 mask" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FIQ_MASKREG5 ,FIQ5 mask" "Enabled,Masked"
|
|
bitfld.long 0x0 4. " FIQ_MASKREG4 ,FIQ4 mask" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 3. " FIQ_MASKREG3 ,FIQ3 mask" "Enabled,Masked"
|
|
bitfld.long 0x0 2. " FIQ_MASKREG2 ,FIQ2 mask" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " FIQ_MASKREG1 ,FIQ1 mask" "Enabled,Masked"
|
|
bitfld.long 0x0 0. " FIQ_MASKREG0 ,FIQ0 mask" "Enabled,Masked"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "IRREG,IRQ Interrupt Request Register"
|
|
bitfld.long 0x0 15. " IRREG15 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 14. " IRREG14 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 13. " IRREG13 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 12. " IRREG12 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 11. " IRREG11 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 10. " IRREG10 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 9. " IRREG9 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 8. " IRREG8 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IRREG7 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 6. " IRREG6 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IRREG5 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 4. " IRREG4 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IRREG3 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 2. " IRREG2 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IRREG1 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
bitfld.long 0x0 0. " IRREG0 ,Recognition of IRQ interrupt request" "Not recognized,Recognized"
|
|
group.long 0x5c++0x3
|
|
line.long 0x0 "MASKREG,IRQ Interrupt Mask Register"
|
|
bitfld.long 0x0 15. " MASKREG15 ,Individual masking of IRQ interrupt input 15" "Enabled,Masked"
|
|
bitfld.long 0x0 14. " MASKREG14 ,Individual masking of IRQ interrupt input 14" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 13. " MASKREG13 ,Individual masking of IRQ interrupt input 13" "Enabled,Masked"
|
|
bitfld.long 0x0 12. " MASKREG12 ,Individual masking of IRQ interrupt input 12" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 11. " MASKREG11 ,Individual masking of IRQ interrupt input 11" "Enabled,Masked"
|
|
bitfld.long 0x0 10. " MASKREG10 ,Individual masking of IRQ interrupt input 10" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 9. " MASKREG9 ,Individual masking of IRQ interrupt input 9" "Enabled,Masked"
|
|
bitfld.long 0x0 8. " MASKREG8 ,Individual masking of IRQ interrupt input 8" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 7. " MASKREG7 ,Individual masking of IRQ interrupt input 7" "Enabled,Masked"
|
|
bitfld.long 0x0 6. " MASKREG6 ,Individual masking of IRQ interrupt input 6" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 5. " MASKREG5 ,Individual masking of IRQ interrupt input 5" "Enabled,Masked"
|
|
bitfld.long 0x0 4. " MASKREG4 ,Individual masking of IRQ interrupt input 4" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 3. " MASKREG3 ,Individual masking of IRQ interrupt input 3" "Enabled,Masked"
|
|
bitfld.long 0x0 2. " MASKREG2 ,Individual masking of IRQ interrupt input 2" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " MASKREG1 ,Individual masking of IRQ interrupt input 1" "Enabled,Masked"
|
|
bitfld.long 0x0 0. " MASKREG0 ,Individual masking of IRQ interrupt input 0" "Enabled,Masked"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "ISREG,IRQ Interrupt In-Service Register"
|
|
bitfld.long 0x0 15. " ISREG15 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 14. " ISREG14 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 13. " ISREG13 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 12. " ISREG12 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 11. " ISREG11 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 10. " ISREG10 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 9. " ISREG9 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 8. " ISREG8 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ISREG7 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 6. " ISREG6 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 5. " ISREG5 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 4. " ISREG4 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 3. " ISREG3 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 2. " ISREG2 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ISREG1 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
bitfld.long 0x0 0. " ISREG0 ,Confirmation of IRQ interrupt request" "Not confirmed,Confirmed"
|
|
group.long 0x64++0x4b
|
|
line.long 0x0 "TRIGREG,IRQ Trigger Mode Select Register"
|
|
bitfld.long 0x0 15. " TRIGREG15 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 14. " TRIGREG14 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 13. " TRIGREG13 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 12. " TRIGREG12 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 11. " TRIGREG11 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 10. " TRIGREG10 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 9. " TRIGREG9 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 8. " TRIGREG8 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 7. " TRIGREG7 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 6. " TRIGREG6 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 5. " TRIGREG5 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 4. " TRIGREG4 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TRIGREG3 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 2. " TRIGREG2 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGREG1 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
bitfld.long 0x0 0. " TRIGREG0 ,Selection of IRQ trigger mode" "Edge,Level"
|
|
line.long 0x4 "EDGEREG,IRQ Trigger Edge Select Register"
|
|
bitfld.long 0x4 15. " EDGEREG15 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 14. " EDGEREG14 ,Selection of IRQ trigger mode" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 13. " EDGEREG13 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 12. " EDGEREG12 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 11. " EDGEREG11 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 10. " EDGEREG10 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 9. " EDGEREG9 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 8. " EDGEREG8 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 7. " EDGEREG7 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 6. " EDGEREG6 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 5. " EDGEREG5 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 4. " EDGEREG4 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 3. " EDGEREG3 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 2. " EDGEREG2 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x4 1. " EDGEREG1 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
bitfld.long 0x4 0. " EDGEREG0 ,Selection of IRQ trigger edge" "Positive,Negative"
|
|
line.long 0x8 "SWIRREG,Software IRQ Interrupt Register"
|
|
bitfld.long 0x8 15. " SWIRREG15 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 14. " SWIRREG14 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 13. " SWIRREG13 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 12. " SWIRREG12 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 11. " SWIRREG11 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 10. " SWIRREG10 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 9. " SWIRREG9 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 8. " SWIRREG8 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 7. " SWIRREG7 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 6. " SWIRREG6 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 5. " SWIRREG5 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 4. " SWIRREG4 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 3. " SWIRREG3 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 2. " SWIRREG2 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x8 1. " SWIRREG1 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
bitfld.long 0x8 0. " SWIRREG0 ,Generation of IRQ interrupt" "Not generated,Generated"
|
|
line.long 0xC "PRIOREG0,IRQ Interrupt Priority Register"
|
|
bitfld.long 0xC 0.--3. " PRIOREG0 ,IRQ0 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x10 "PRIOREG1,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x10 0.--3. " PRIOREG1 ,IRQ1 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x14 "PRIOREG2,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x14 0.--3. " PRIOREG2 ,IRQ2 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x18 "PRIOREG3,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x18 0.--3. " PRIOREG3 ,IRQ3 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x1C "PRIOREG4,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x1C 0.--3. " PRIOREG4 ,IRQ4 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x20 "PRIOREG5,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x20 0.--3. " PRIOREG5 ,IRQ5 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x24 "PRIOREG6,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x24 0.--3. " PRIOREG6 ,IRQ6 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x28 "PRIOREG7,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x28 0.--3. " PRIOREG7 ,IRQ7 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x2C "PRIOREG8,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x2C 0.--3. " PRIOREG8 ,IRQ8 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x30 "PRIOREG9,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x30 0.--3. " PRIOREG9 ,IRQ9 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x34 "PRIOREG10,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x34 0.--3. " PRIOREG10 ,IRQ10 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x38 "PRIOREG11,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x38 0.--3. " PRIOREG11 ,IRQ11 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x3C "PRIOREG12,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x3C 0.--3. " PRIOREG12 ,IRQ12 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x40 "PRIOREG13,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x40 0.--3. " PRIOREG13 ,IRQ13 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x44 "PRIOREG14,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x44 0.--3. " PRIOREG14 ,IRQ14 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
line.long 0x48 "PRIOREG15,IRQ Interrupt Priority Register"
|
|
bitfld.long 0x48 0.--3. " PRIOREG15 ,IRQ15 interrupt request priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest"
|
|
textline " "
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="ERTEC400")
|
|
tree "PCI Interface"
|
|
base ad:0x80000000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PCI_ID,ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " Device_ID ,Device ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " Vendor_ID ,Vendor ID"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCI_STAT_COM,Status and Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " Status ,Status"
|
|
hexmask.long.word 0x00 0.--15. 1. " Command ,Command"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "REV_ID,Revision ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " Class_Code ,Class Code"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Revision_ID ,Revision ID"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCI_BIST,BIST Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIST ,BIST"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Header_Type ,Header Type"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " Latency_Timer ,Latency Timer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Cache_Line_Size ,Cache Line Size"
|
|
width 33.
|
|
group.long 0x10--0x27
|
|
line.long 0x00 "PCI_Base_Address_Register0,PCI Base Address Register 0"
|
|
line.long 0x04 "PCI_Base_Address_Register1,PCI Base Address Register 1"
|
|
line.long 0x08 "PCI_Base_Address_Register2,PCI Base Address Register 2"
|
|
line.long 0x0C "PCI_Base_Address_Register3,PCI Base Address Register 3"
|
|
line.long 0x10 "PCI_Base_Address_Register4,PCI Base Address Register 4"
|
|
line.long 0x14 "PCI_Base_Address_Register5,PCI Base Address Register 5"
|
|
rgroup.long 0x28--0x2F
|
|
line.long 0x00 "Cardbus_CIS_Pointer,Cardbus CIS Pointer Register"
|
|
line.long 0x04 "SUBSYS_ID,Subsystem ID Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " Subsystem_ID ,Subsystem ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " Subsystem_Vendor_ID ,Subsystem Vendor ID"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "Capability_Pointer,Capability Pointer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Capability_Pointer ,Capability Pointer Value"
|
|
group.long 0x3C--0x47
|
|
line.long 0x00 "PCI_INT,Interrupt Line Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Max_Lat ,Max Latency"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Min_Lat ,Min Latency"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " Interrupt_Pin ,Interrupt Pin"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Interrupt_Line ,Interrupt Line"
|
|
line.long 0x04 "DEV_ID,Device ID Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " Device_ID ,Device ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " Vendor_ID ,Vendor ID"
|
|
line.long 0x08 "SUBSYS_ID,Subsystem and Vendor ID Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " Subsystem_ID , Subsystem ID"
|
|
hexmask.long.word 0x08 0.--15. 1. " Subsystem_Vendor_ID ,Subsystem Vendor ID"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PCI_PM,PM Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PM_Capability ,PM Capability"
|
|
hexmask.long.word 0x00 8.--15. 1. " PM_next_item_ptr ,PM Next Item Pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--7. 1. " PM_Capability_id ,PM Capability ID"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCI_PM_CON,PM Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PM_Data ,PM Data"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PM_CSR_BSE ,PM_CSR_BSE"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " PM_Control_Status ,PM Control Status"
|
|
group.long 0x50--0x67
|
|
line.long 0x00 "PCI_Base_Address_Mask_Register0,PCI Base Address Mask Register 0"
|
|
line.long 0x04 "PCI_Base_Address_Mask_Register1,PCI Base Address Mask Register 1"
|
|
line.long 0x08 "PCI_Base_Address_Mask_Register2,PCI Base Address Mask Register 2"
|
|
line.long 0x0C "PCI_Base_Address_Mask_Register3,PCI Base Address Mask Register 3"
|
|
line.long 0x10 "PCI_Base_Address_Mask_Register4,PCI Base Address Mask Register 4"
|
|
line.long 0x14 "PCI_Base_Address_Mask_Register5,PCI Base Address Mask Register 6"
|
|
width 40.
|
|
group.long 0x68--0x7F
|
|
line.long 0x00 "PCI_Base_Address_Translation_Register0,PCI Base Address Translation Register 0"
|
|
line.long 0x04 "PCI_Base_Address_Translation_Register1,PCI Base Address Translation Register 1"
|
|
line.long 0x08 "PCI_Base_Address_Translation_Register2,PCI Base Address Translation Register 2"
|
|
line.long 0x0C "PCI_Base_Address_Translation_Register3,PCI Base Address Translation Register 3"
|
|
line.long 0x10 "PCI_Base_Address_Translation_Register4,PCI Base Address Translation Register 4"
|
|
line.long 0x14 "PCI_Base_Address_Translation_Register0,PCI Base Address Translation Register 4"
|
|
width 33.
|
|
group.long 0x80--0x8F
|
|
line.long 0x00 "PCI_Arbiter_Config,PCI Arbiter Config Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PCI_Arbiter_Config_Register ,PCI Arbiter ConfigRegister"
|
|
line.long 0x04 "INT_Pin,INT Pin Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " Max_Lat ,Max Latency"
|
|
hexmask.long.byte 0x04 16.--23. 1. " Min_Gnt ,Min Gnt"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " INT_Pin ,INT Pin"
|
|
line.long 0x08 "PCI_PM_Capability,PM Capability Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " PM_Capability ,PM Capability"
|
|
line.long 0x0C "PCI_Class_Code,Class Code Register"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. " Class_Code ,Class Code"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " Revision_ID ,Revision ID"
|
|
group.long 0x90--0xA3
|
|
line.long 0x00 "AHB_Base_Address_Register0,AHB Base Address Register 0"
|
|
line.long 0x04 "AHB_Base_Address_Register1,AHB Base Address Register 1"
|
|
line.long 0x08 "AHB_Base_Address_Register2,AHB Base Address Register 2"
|
|
line.long 0x0C "AHB_Base_Address_Register3,AHB Base Address Register 3"
|
|
line.long 0x10 "AHB_Base_Address_Register4,AHB Base Address Register 4"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "AHB_Base_Address_Mask_Register0,AHB Base Address Mask Register 0"
|
|
group.long 0xA8--0xB7
|
|
line.long 0x00 "AHB_Base_Address_Mask_Register1,AHB Base Address Mask Register 1"
|
|
line.long 0x04 "AHB_Base_Address_Mask_Register2,AHB Base Address Mask Register 2"
|
|
line.long 0x08 "AHB_Base_Address_Mask_Register3,AHB Base Address Mask Register 3"
|
|
line.long 0x0C "AHB_Base_Address_Mask_Register4,AHB Base Address Mask Register 4"
|
|
width 40.
|
|
group.long 0xC0--0xCB
|
|
line.long 0x00 "AHB_Base_Address_Translation_Register2,AHB Base Address Translation Register 2"
|
|
line.long 0x04 "AHB_Base_Address_Translation_Register3,AHB Base Address Translation Register 3"
|
|
line.long 0x08 "AHB_Base_Address_Translation_Register4,AHB Base Address Translation Register 4"
|
|
width 33.
|
|
group.long 0xCC++0x07
|
|
line.long 0x00 "AHB_Status,AHB Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " AHB_Status_Register ,AHB Status Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_Function_Register ,AHB Function Register"
|
|
line.long 0x04 "WAIT_STATE,Wait State Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " Wait_States_Bridge_as_PCII_Target ,Wait States Bridge as PCII Target"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " Wait_States_Bridge_PCI_Master ,Wait States Bridge PCI Master"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " Wait_States_Bridge_as_AHB_Slave ,Wait States Bridge as AHB Slave"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " Wait_States_Bridge_AHB_Master ,Wait States Bridge AHB Master"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "Bridge_Interrupt_Status_Register,Bridge Interrupt Status Register"
|
|
group.long 0xD8++0x07
|
|
line.long 0x00 "AHB_Interrupt_Enable_Register,AHB Interrupt Enable Register"
|
|
line.long 0x04 "PCI_Interrupt_Enable_Register,PCI Interrupt Enable Register"
|
|
wgroup.long 0xF8++0x03
|
|
line.long 0x00 "SERR_Generation_By_Software,SERR Generation By Software"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "Enable_Configuration_From_PCI,Enable Configuration From PCI"
|
|
tree.end
|
|
endif
|
|
tree "LBU (Local Bus Unit)"
|
|
base ad:0x000000
|
|
width 13.
|
|
group.word 0x0++0x9 "Page 0"
|
|
line.word 0x0 "LBU_P0_RG_L,LBU Page 0 Range Register Low"
|
|
hexmask.word.byte 0x0 8.--15. 1. " LBU_P0_RG_L ,Bit (15:8) of the LBU page 0 size setting"
|
|
line.word 0x2 "LBU_P0_RG_H,LBU Page 0 Range Register High"
|
|
hexmask.word.byte 0x2 0.--5. 1. " LBU_P0_RG_H ,Bit (21:16) of the LBU page 0 size setting"
|
|
line.word 0x4 "LBU_P0_OF_L,LBU Page 0 Offset Register Low"
|
|
hexmask.word.byte 0x4 8.--15. 1. " LBU_P0_OF_L ,Bit (15:8) of the LBU page 0 offset setting"
|
|
line.word 0x6 "LBU_P0_OF_H,LBU Page 0 Offset Register High"
|
|
line.word 0x8 "LBU_P0_CFG,LBU Page Configuration Register"
|
|
bitfld.word 0x8 0. " Page_0_32 ,Page width configuration" "16-bit,32-bit"
|
|
group.word 0x10++0x9 "Page 1"
|
|
line.word 0x0 "LBU_P1_RG_L,LBU Page 1 Range Register Low"
|
|
hexmask.word.byte 0x0 8.--15. 1. " LBU_P1_RG_L ,Bit (15:8) of the LBU page 1 size setting"
|
|
line.word 0x2 "LBU_P1_RG_H,LBU Page 1 Range Register High"
|
|
hexmask.word.byte 0x2 0.--5. 1. " LBU_P1_RG_H ,Bit (21:16) of the LBU page 1 size setting"
|
|
line.word 0x4 "LBU_P1_OF_L,LBU Page 1 Offset Register Low"
|
|
hexmask.word.byte 0x4 8.--15. 1. " LBU_P1_OF_L ,Bit (15:8) of the LBU page 1 offset setting"
|
|
line.word 0x6 "LBU_P1_OF_H,LBU Page 1 Offset Register High"
|
|
line.word 0x8 "LBU_P1_CFG,LBU Page Configuration Register"
|
|
bitfld.word 0x8 0. " Page_1_32 ,Page width configuration" "16-bit,32-bit"
|
|
group.word 0x20++0x9 "Page 2"
|
|
line.word 0x0 "LBU_P2_RG_L,LBU Page 2 Range Register Low"
|
|
hexmask.word.byte 0x0 8.--15. 1. " LBU_P2_RG_L ,Bit (15:8) of the LBU page 2 size setting"
|
|
line.word 0x2 "LBU_P2_RG_H,LBU Page 2 Range Register High"
|
|
hexmask.word.byte 0x2 0.--5. 1. " LBU_P2_RG_H ,Bit (21:16) of the LBU page 2 size setting"
|
|
line.word 0x4 "LBU_P2_OF_L,LBU Page 2 Offset Register Low"
|
|
hexmask.word.byte 0x4 8.--15. 1. " LBU_P2_OF_L ,Bit (15:8) of the LBU page 2 offset setting"
|
|
line.word 0x6 "LBU_P2_OF_H,LBU Page 2 Offset Register High"
|
|
line.word 0x8 "LBU_P2_CFG,LBU Page Configuration Register"
|
|
bitfld.word 0x8 0. " Page_2_32 ,Page width configuration" "16-bit,32-bit"
|
|
group.word 0x30++0x9 "Page 3"
|
|
line.word 0x0 "LBU_P3_RG_L,LBU Page 3 Range Register Low"
|
|
hexmask.word.byte 0x0 8.--15. 1. " LBU_P3_RG_L ,Bit (15:8) of the LBU page 3 size setting"
|
|
line.word 0x2 "LBU_P3_RG_H,LBU Page 3 Range Register High"
|
|
hexmask.word.byte 0x2 0.--5. 1. " LBU_P3_RG_H ,Bit (21:16) of the LBU page 3 size setting"
|
|
line.word 0x4 "LBU_P3_OF_L,LBU Page 3 Offset Register Low"
|
|
hexmask.word.byte 0x4 8.--15. 1. " LBU_P3_OF_L ,Bit (15:8) of the LBU page 3 offset setting"
|
|
line.word 0x6 "LBU_P3_OF_H,LBU Page 3 Offset Register High"
|
|
line.word 0x8 "LBU_P3_CFG,LBU Page Configuration Register"
|
|
bitfld.word 0x8 0. " Page_3_32 ,Page width configuration" "16-bit,32-bit"
|
|
width 0xb
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O)"
|
|
base ad:0x40002500
|
|
sif (cpu()=="ERTEC200")
|
|
width 18.
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "GPIO_IOCTRL,GPIO Configuration Register"
|
|
bitfld.long 0x0 31. " GPIO_IOCTRL31 ,GPIO pin 31 direction" "Output,Input"
|
|
bitfld.long 0x0 30. " GPIO_IOCTRL30 ,GPIO pin 30 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 29. " GPIO_IOCTRL29 ,GPIO pin 29 direction" "Output,Input"
|
|
bitfld.long 0x0 28. " GPIO_IOCTRL28 ,GPIO pin 28 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPIO_IOCTRL27 ,GPIO pin 27 direction" "Output,Input"
|
|
bitfld.long 0x0 26. " GPIO_IOCTRL26 ,GPIO pin 26 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPIO_IOCTRL25 ,GPIO pin 25 direction" "Output,Input"
|
|
bitfld.long 0x0 24. " GPIO_IOCTRL24 ,GPIO pin 24 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPIO_IOCTRL23 ,GPIO pin 23 direction" "Output,Input"
|
|
bitfld.long 0x0 22. " GPIO_IOCTRL22 ,GPIO pin 22 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 21. " GPIO_IOCTRL21 ,GPIO pin 21 direction" "Output,Input"
|
|
bitfld.long 0x0 20. " GPIO_IOCTRL20 ,GPIO pin 20 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 19. " GPIO_IOCTRL19 ,GPIO pin 19 direction" "Output,Input"
|
|
bitfld.long 0x0 18. " GPIO_IOCTRL18 ,GPIO pin 18 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 17. " GPIO_IOCTRL17 ,GPIO pin 17 direction" "Output,Input"
|
|
bitfld.long 0x0 16. " GPIO_IOCTRL16 ,GPIO pin 16 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPIO_IOCTRL15 ,GPIO pin 15 direction" "Output,Input"
|
|
bitfld.long 0x0 14. " GPIO_IOCTRL14 ,GPIO pin 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPIO_IOCTRL13 ,GPIO pin 13 direction" "Output,Input"
|
|
bitfld.long 0x0 12. " GPIO_IOCTRL12 ,GPIO pin 12 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPIO_IOCTRL11 ,GPIO pin 11 direction" "Output,Input"
|
|
bitfld.long 0x0 10. " GPIO_IOCTRL10 ,GPIO pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 9. " GPIO_IOCTRL9 ,GPIO pin 9 direction" "Output,Input"
|
|
bitfld.long 0x0 8. " GPIO_IOCTRL8 ,GPIO pin 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPIO_IOCTRL7 ,GPIO pin 7 direction" "Output,Input"
|
|
bitfld.long 0x0 6. " GPIO_IOCTRL6 ,GPIO pin 6 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_IOCTRL5 ,GPIO pin 5 direction" "Output,Input"
|
|
bitfld.long 0x0 4. " GPIO_IOCTRL4 ,GPIO pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_IOCTRL3 ,GPIO pin 3 direction" "Output,Input"
|
|
bitfld.long 0x0 2. " GPIO_IOCTRL2 ,GPIO pin 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_IOCTRL1 ,GPIO pin 1 direction" "Output,Input"
|
|
bitfld.long 0x0 0. " GPIO_IOCTRL0 ,GPIO pin 0 direction" "Output,Input"
|
|
line.long 0x4 "GPIO_OUT,GPIO Data Output Register"
|
|
bitfld.long 0x4 31. " GPIO_OUT31 ,GPIO pin 31 output data" "Low,High"
|
|
bitfld.long 0x4 30. " GPIO_OUT30 ,GPIO pin 30 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 29. " GPIO_OUT29 ,GPIO pin 29 output data" "Low,High"
|
|
bitfld.long 0x4 28. " GPIO_OUT28 ,GPIO pin 28 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 27. " GPIO_OUT27 ,GPIO pin 27 output data" "Low,High"
|
|
bitfld.long 0x4 26. " GPIO_OUT26 ,GPIO pin 26 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 25. " GPIO_OUT25 ,GPIO pin 25 output data" "Low,High"
|
|
bitfld.long 0x4 24. " GPIO_OUT24 ,GPIO pin 24 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 23. " GPIO_OUT23 ,GPIO pin 23 output data" "Low,High"
|
|
bitfld.long 0x4 22. " GPIO_OUT22 ,GPIO pin 22 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 21. " GPIO_OUT21 ,GPIO pin 21 output data" "Low,High"
|
|
bitfld.long 0x4 20. " GPIO_OUT20 ,GPIO pin 20 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 19. " GPIO_OUT19 ,GPIO pin 19 output data" "Low,High"
|
|
bitfld.long 0x4 18. " GPIO_OUT18 ,GPIO pin 18 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 17. " GPIO_OUT17 ,GPIO pin 17 output data" "Low,High"
|
|
bitfld.long 0x4 16. " GPIO_OUT16 ,GPIO pin 16 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 15. " GPIO_OUT15 ,GPIO pin 15 output data" "Low,High"
|
|
bitfld.long 0x4 14. " GPIO_OUT14 ,GPIO pin 14 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 13. " GPIO_OUT13 ,GPIO pin 13 output data" "Low,High"
|
|
bitfld.long 0x4 12. " GPIO_OUT12 ,GPIO pin 12 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 11. " GPIO_OUT11 ,GPIO pin 11 output data" "Low,High"
|
|
bitfld.long 0x4 10. " GPIO_OUT10 ,GPIO pin 10 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 9. " GPIO_OUT9 ,GPIO pin 9 output data" "Low,High"
|
|
bitfld.long 0x4 8. " GPIO_OUT8 ,GPIO pin 8 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 7. " GPIO_OUT7 ,GPIO pin 7 output data" "Low,High"
|
|
bitfld.long 0x4 6. " GPIO_OUT6 ,GPIO pin 6 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 5. " GPIO_OUT5 ,GPIO pin 5 output data" "Low,High"
|
|
bitfld.long 0x4 4. " GPIO_OUT4 ,GPIO pin 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 3. " GPIO_OUT3 ,GPIO pin 3 output data" "Low,High"
|
|
bitfld.long 0x4 2. " GPIO_OUT2 ,GPIO pin 2 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 1. " GPIO_OUT1 ,GPIO pin 1 output data" "Low,High"
|
|
bitfld.long 0x4 0. " GPIO_OUT0 ,GPIO pin 0 output data" "Low,High"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "GPIO_IN,GPIO Data Input Register"
|
|
bitfld.long 0x0 31. " GPIO_IN31 ,GPIO pin 31 input data" "Low,High"
|
|
bitfld.long 0x0 30. " GPIO_IN30 ,GPIO pin 30 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " GPIO_IN29 ,GPIO pin 29 input data" "Low,High"
|
|
bitfld.long 0x0 28. " GPIO_IN28 ,GPIO pin 28 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPIO_IN27 ,GPIO pin 27 input data" "Low,High"
|
|
bitfld.long 0x0 26. " GPIO_IN26 ,GPIO pin 26 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPIO_IN25 ,GPIO pin 25 input data" "Low,High"
|
|
bitfld.long 0x0 24. " GPIO_IN24 ,GPIO pin 24 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPIO_IN23 ,GPIO pin 23 input data" "Low,High"
|
|
bitfld.long 0x0 22. " GPIO_IN22 ,GPIO pin 22 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " GPIO_IN21 ,GPIO pin 21 input data" "Low,High"
|
|
bitfld.long 0x0 20. " GPIO_IN20 ,GPIO pin 20 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " GPIO_IN19 ,GPIO pin 19 input data" "Low,High"
|
|
bitfld.long 0x0 18. " GPIO_IN18 ,GPIO pin 18 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " GPIO_IN17 ,GPIO pin 17 input data" "Low,High"
|
|
bitfld.long 0x0 16. " GPIO_IN16 ,GPIO pin 16 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPIO_IN15 ,GPIO pin 15 input data" "Low,High"
|
|
bitfld.long 0x0 14. " GPIO_IN14 ,GPIO pin 14 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPIO_IN13 ,GPIO pin 13 input data" "Low,High"
|
|
bitfld.long 0x0 12. " GPIO_IN12 ,GPIO pin 12 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPIO_IN11 ,GPIO pin 11 input data" "Low,High"
|
|
bitfld.long 0x0 10. " GPIO_IN10 ,GPIO pin 10 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " GPIO_IN9 ,GPIO pin 9 input data" "Low,High"
|
|
bitfld.long 0x0 8. " GPIO_IN8 ,GPIO pin 8 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPIO_IN7 ,GPIO pin 7 input data" "Low,High"
|
|
bitfld.long 0x0 6. " GPIO_IN6 ,GPIO pin 6 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_IN5 ,GPIO pin 5 input data" "Low,High"
|
|
bitfld.long 0x0 4. " GPIO_IN4 ,GPIO pin 4 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_IN3 ,GPIO pin 3 input data" "Low,High"
|
|
bitfld.long 0x0 2. " GPIO_IN2 ,GPIO pin 2 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_IN1 ,GPIO pin 1 input data" "Low,High"
|
|
bitfld.long 0x0 0. " GPIO_IN0 ,GPIO pin 0 input data" "Low,High"
|
|
group.long 0xc++0x0b
|
|
line.long 0x0 "GPIO_PORT_MODE_L,GPIO Function Selection Register"
|
|
bitfld.long 0x0 30.--31. " GPIO15_PORT_MODE ,Switch functions of pin GPIO15" "GPIO15,WD_WDOUT_N,?..."
|
|
bitfld.long 0x0 28.--29. " GPIO14_PORT_MODE ,Switch functions of pin GPIO14" "GPIO14,DBGACK,?..."
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " GPIO13_PORT_MODE ,Switch functions of pin GPIO13" "GPIO13,?..."
|
|
bitfld.long 0x0 24.--25. " GPIO12_PORT_MODE ,Switch functions of pin GPIO12" "GPIO12,UART-CTS_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " GPIO11_PORT_MODE ,Switch functions of pin GPIO11" "GPIO11,UART-DSR_N,?..."
|
|
bitfld.long 0x0 20.--21. " GPIO10_PORT_MODE ,Switch functions of pin GPIO10" "GPIO10,UART-DCD_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " GPIO9_PORT_MODE ,Switch functions of pin GPIO9" "GPIO9,UART-RXD,?..."
|
|
bitfld.long 0x0 16.--17. " GPIO8_PORT_MODE ,Switch functions of pin GPIO8" "GPIO8,UART-TXD,?..."
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " GPIO7_PORT_MODE ,Switch functions of pin GPIO7" "GPIO7,P2-RX-LED_N,P2-TX-LED_N,P2-ACTIVE-LED_N"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " GPIO6_PORT_MODE ,Switch functions of pin GPIO6" "GPIO6,P1-RX-LED_N,P1-TX-LED_N,P1-ACTIVE-LED_N"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " GPIO5_PORT_MODE ,Switch functions of pin GPIO5" "GPIO5,P2-LINK-LED_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8.--9. " GPIO4_PORT_MODE ,Switch functions of pin GPIO4" "GPIO4,P1-LINK-LED_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " GPIO3_PORT_MODE ,Switch functions of pin GPIO3" "GPIO3,P2-SPEED-100LED_N (TX/FX),P2-SPEED-10LED_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 4.--5. " GPIO2_PORT_MODE ,Switch functions of pin GPIO2" "GPIO2,P1-SPEED-100LED_N (TX/FX),P1-SPEED-10LED_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " GPIO1_PORT_MODE ,Switch functions of pin GPIO1" "GPIO1,P2-DUPLEX-LED_N,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " GPIO0_PORT_MODE ,Switch functions of pin GPIO0" "GPIO0,P1-DUPLEX-LED_N,?..."
|
|
line.long 0x4 "GPIO_PORT_MODE_H,GPIO Function Selection Register"
|
|
bitfld.long 0x4 30.--31. " GPIO31_PORT_MODE ,Switch functions of pin GPIO31" "GPIO31,DBGREQ,?..."
|
|
bitfld.long 0x4 28.--29. " GPIO30_PORT_MODE ,Switch functions of pin GPIO30" "GPIO30,?..."
|
|
textline " "
|
|
bitfld.long 0x4 26.--27. " GPIO29_PORT_MODE ,Switch functions of pin GPIO29" "GPIO29,?..."
|
|
bitfld.long 0x4 24.--25. " GPIO28_PORT_MODE ,Switch functions of pin GPIO28" "GPIO28,?..."
|
|
textline " "
|
|
bitfld.long 0x4 22.--23. " GPIO27_PORT_MODE ,Switch functions of pin GPIO27" "GPIO27,?..."
|
|
bitfld.long 0x4 20.--21. " GPIO26_PORT_MODE ,Switch functions of pin GPIO26" "GPIO26,?..."
|
|
textline " "
|
|
bitfld.long 0x4 18.--19. " GPIO25_PORT_MODE ,Switch functions of pin GPIO25" "GPIO25,?..."
|
|
bitfld.long 0x4 16.--17. " GPIO24_PORT_MODE ,Switch functions of pin GPIO24" "GPIO24,?..."
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " GPIO23_PORT_MODE ,Switch functions of pin GPIO23" "GPIO23,SPI1_SCLKIN,?..."
|
|
bitfld.long 0x4 12.--13. " GPIO22_PORT_MODE ,Switch functions of pin GPIO22" "GPIO22,SPI1_SFRMIN,DBGACK,?..."
|
|
textline " "
|
|
bitfld.long 0x4 10.--11. " GPIO21_PORT_MODE ,Switch functions of pin GPIO21" "GPIO21,SPI1_SFRMOUT,?..."
|
|
bitfld.long 0x4 8.--9. " GPIO20_PORT_MODE ,Switch functions of pin GPIO20" "GPIO20,SPI1_SCLKOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x4 6.--7. " GPIO19_PORT_MODE ,Switch functions of pin GPIO19" "GPIO19,SPI1_SSPTXD,?..."
|
|
bitfld.long 0x4 4.--5. " GPIO18_PORT_MODE ,Switch functions of pin GPIO18" "GPIO18,SPI1_SSPRXD,?..."
|
|
textline " "
|
|
bitfld.long 0x4 2.--3. " GPIO17_PORT_MODE ,Switch functions of pin GPIO17" "GPIO17,SPI1_SSPOE,?..."
|
|
bitfld.long 0x4 0.--1. " GPIO16_PORT_MODE ,Switch functions of pin GPIO16" "GPIO16,SPI1_SSPCTLOE,?..."
|
|
line.long 0x8 "GPIO_POLSEL,GPIO Polarity Selection Register"
|
|
bitfld.long 0x8 3. " POLSEL_GPIO31 ,Control GPIO31 input signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x8 2. " POLSEL_GPIO30 ,Control GPIO30 input signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x8 1. " POLSEL_GPIO1 ,Control GPIO1 input signal" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x8 0. " POLSEL_GPIO0 ,Control GPIO0 input signal" "Not inverted,Inverted"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "GPIO2_IOCTRL,GPIO2 Configuration Register"
|
|
bitfld.long 0x0 12. " GPIO_IOCTRL12 ,GPIO2 pin 12 direction" "Output,Input"
|
|
bitfld.long 0x0 11. " GPIO_IOCTRL11 ,GPIO2 pin 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 10. " GPIO_IOCTRL10 ,GPIO2 pin 10 direction" "Output,Input"
|
|
bitfld.long 0x0 9. " GPIO_IOCTRL9 ,GPIO2 pin 9 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 8. " GPIO_IOCTRL8 ,GPIO2 pin 8 direction" "Output,Input"
|
|
bitfld.long 0x0 7. " GPIO_IOCTRL7 ,GPIO2 pin 7 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 6. " GPIO_IOCTRL6 ,GPIO2 pin 6 direction" "Output,Input"
|
|
bitfld.long 0x0 5. " GPIO_IOCTRL5 ,GPIO2 pin 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPIO_IOCTRL4 ,GPIO2 pin 4 direction" "Output,Input"
|
|
bitfld.long 0x0 3. " GPIO_IOCTRL3 ,GPIO2 pin 3 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 2. " GPIO_IOCTRL2 ,GPIO2 pin 2 direction" "Output,Input"
|
|
bitfld.long 0x0 1. " GPIO_IOCTRL1 ,GPIO2 pin 1 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 0. " GPIO_IOCTRL0 ,GPIO2 pin 0 direction" "Output,Input"
|
|
line.long 0x4 "GPIO2_OUT,GPIO2 Data Output Register"
|
|
bitfld.long 0x4 12. " GPIO2_OUT12 ,Output of GPIO2 pin 12" "Low,High"
|
|
bitfld.long 0x4 11. " GPIO2_OUT11 ,Output of GPIO2 pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " GPIO2_OUT10 ,Output of GPIO2 pin 10" "Low,High"
|
|
bitfld.long 0x4 9. " GPIO2_OUT9 ,Output of GPIO2 pin 9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 8. " GPIO2_OUT8 ,Output of GPIO2 pin 8" "Low,High"
|
|
bitfld.long 0x4 7. " GPIO2_OUT7 ,Output of GPIO2 pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 6. " GPIO2_OUT6 ,Output of GPIO2 pin 6" "Low,High"
|
|
bitfld.long 0x4 5. " GPIO2_OUT5 ,Output of GPIO2 pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 4. " GPIO2_OUT4 ,Output of GPIO2 pin 4" "Low,High"
|
|
bitfld.long 0x4 3. " GPIO2_OUT3 ,Output of GPIO2 pin 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 2. " GPIO2_OUT2 ,Output of GPIO2 pin 2" "Low,High"
|
|
bitfld.long 0x4 1. " GPIO2_OUT1 ,Output of GPIO2 pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 0. " GPIO2_OUT0 ,Output of GPIO2 pin 0" "Low,High"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIO2_IN,GPIO2 Data Input Register"
|
|
bitfld.long 0x0 12. " GPIO2_IN12 ,Logical level at the GPIO2 pin 12 " "Low,High"
|
|
bitfld.long 0x0 11. " GPIO2_IN11 ,Logical level at the GPIO2 pin 11 " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " GPIO2_IN10 ,Logical level at the GPIO2 pin 10 " "Low,High"
|
|
bitfld.long 0x0 9. " GPIO2_IN9 ,Logical level at the GPIO2 pin 9 " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 8. " GPIO2_IN8 ,Logical level at the GPIO2 pin 8 " "Low,High"
|
|
bitfld.long 0x0 7. " GPIO2_IN7 ,Logical level at the GPIO2 pin 7 " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " GPIO2_IN6 ,Logical level at the GPIO2 pin 6 " "Low,High"
|
|
bitfld.long 0x0 5. " GPIO2_IN5 ,Logical level at the GPIO2 pin 5 " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPIO2_IN4 ,Logical level at the GPIO2 pin 4 " "Low,High"
|
|
bitfld.long 0x0 3. " GPIO2_IN3 ,Logical level at the GPIO2 pin 3 " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 2. " GPIO2_IN2 ,Logical level at the GPIO2 pin 2 " "Low,High"
|
|
bitfld.long 0x0 1. " GPIO2_IN1 ,Logical level at the GPIO2 pin 1 " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 0. " GPIO2_IN0 ,Logical level at the GPIO2 pin 0 " "Low,High"
|
|
width 0xb
|
|
endif
|
|
sif (cpu()=="ERTEC400")
|
|
width 18.
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "GPIO_IOCTRL,GPIO Configuration Register"
|
|
bitfld.long 0x0 31. " GPIO_IOCTRL31 ,GPIO pin 31 direction" "Output,Input"
|
|
bitfld.long 0x0 30. " GPIO_IOCTRL30 ,GPIO pin 30 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 29. " GPIO_IOCTRL29 ,GPIO pin 29 direction" "Output,Input"
|
|
bitfld.long 0x0 28. " GPIO_IOCTRL28 ,GPIO pin 28 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPIO_IOCTRL27 ,GPIO pin 27 direction" "Output,Input"
|
|
bitfld.long 0x0 26. " GPIO_IOCTRL26 ,GPIO pin 26 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPIO_IOCTRL25 ,GPIO pin 25 direction" "Output,Input"
|
|
bitfld.long 0x0 24. " GPIO_IOCTRL24 ,GPIO pin 24 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPIO_IOCTRL23 ,GPIO pin 23 direction" "Output,Input"
|
|
bitfld.long 0x0 22. " GPIO_IOCTRL22 ,GPIO pin 22 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 21. " GPIO_IOCTRL21 ,GPIO pin 21 direction" "Output,Input"
|
|
bitfld.long 0x0 20. " GPIO_IOCTRL20 ,GPIO pin 20 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 19. " GPIO_IOCTRL19 ,GPIO pin 19 direction" "Output,Input"
|
|
bitfld.long 0x0 18. " GPIO_IOCTRL18 ,GPIO pin 18 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 17. " GPIO_IOCTRL17 ,GPIO pin 17 direction" "Output,Input"
|
|
bitfld.long 0x0 16. " GPIO_IOCTRL16 ,GPIO pin 16 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPIO_IOCTRL15 ,GPIO pin 15 direction" "Output,Input"
|
|
bitfld.long 0x0 14. " GPIO_IOCTRL14 ,GPIO pin 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPIO_IOCTRL13 ,GPIO pin 13 direction" "Output,Input"
|
|
bitfld.long 0x0 12. " GPIO_IOCTRL12 ,GPIO pin 12 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPIO_IOCTRL11 ,GPIO pin 11 direction" "Output,Input"
|
|
bitfld.long 0x0 10. " GPIO_IOCTRL10 ,GPIO pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 9. " GPIO_IOCTRL9 ,GPIO pin 9 direction" "Output,Input"
|
|
bitfld.long 0x0 8. " GPIO_IOCTRL8 ,GPIO pin 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPIO_IOCTRL7 ,GPIO pin 7 direction" "Output,Input"
|
|
bitfld.long 0x0 6. " GPIO_IOCTRL6 ,GPIO pin 6 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_IOCTRL5 ,GPIO pin 5 direction" "Output,Input"
|
|
bitfld.long 0x0 4. " GPIO_IOCTRL4 ,GPIO pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_IOCTRL3 ,GPIO pin 3 direction" "Output,Input"
|
|
bitfld.long 0x0 2. " GPIO_IOCTRL2 ,GPIO pin 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_IOCTRL1 ,GPIO pin 1 direction" "Output,Input"
|
|
bitfld.long 0x0 0. " GPIO_IOCTRL0 ,GPIO pin 0 direction" "Output,Input"
|
|
line.long 0x4 "GPIO_OUT,GPIO Data Output Register"
|
|
bitfld.long 0x4 31. " GPIO_OUT31 ,GPIO pin 31 output data" "Low,High"
|
|
bitfld.long 0x4 30. " GPIO_OUT30 ,GPIO pin 30 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 29. " GPIO_OUT29 ,GPIO pin 29 output data" "Low,High"
|
|
bitfld.long 0x4 28. " GPIO_OUT28 ,GPIO pin 28 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 27. " GPIO_OUT27 ,GPIO pin 27 output data" "Low,High"
|
|
bitfld.long 0x4 26. " GPIO_OUT26 ,GPIO pin 26 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 25. " GPIO_OUT25 ,GPIO pin 25 output data" "Low,High"
|
|
bitfld.long 0x4 24. " GPIO_OUT24 ,GPIO pin 24 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 23. " GPIO_OUT23 ,GPIO pin 23 output data" "Low,High"
|
|
bitfld.long 0x4 22. " GPIO_OUT22 ,GPIO pin 22 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 21. " GPIO_OUT21 ,GPIO pin 21 output data" "Low,High"
|
|
bitfld.long 0x4 20. " GPIO_OUT20 ,GPIO pin 20 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 19. " GPIO_OUT19 ,GPIO pin 19 output data" "Low,High"
|
|
bitfld.long 0x4 18. " GPIO_OUT18 ,GPIO pin 18 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 17. " GPIO_OUT17 ,GPIO pin 17 output data" "Low,High"
|
|
bitfld.long 0x4 16. " GPIO_OUT16 ,GPIO pin 16 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 15. " GPIO_OUT15 ,GPIO pin 15 output data" "Low,High"
|
|
bitfld.long 0x4 14. " GPIO_OUT14 ,GPIO pin 14 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 13. " GPIO_OUT13 ,GPIO pin 13 output data" "Low,High"
|
|
bitfld.long 0x4 12. " GPIO_OUT12 ,GPIO pin 12 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 11. " GPIO_OUT11 ,GPIO pin 11 output data" "Low,High"
|
|
bitfld.long 0x4 10. " GPIO_OUT10 ,GPIO pin 10 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 9. " GPIO_OUT9 ,GPIO pin 9 output data" "Low,High"
|
|
bitfld.long 0x4 8. " GPIO_OUT8 ,GPIO pin 8 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 7. " GPIO_OUT7 ,GPIO pin 7 output data" "Low,High"
|
|
bitfld.long 0x4 6. " GPIO_OUT6 ,GPIO pin 6 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 5. " GPIO_OUT5 ,GPIO pin 5 output data" "Low,High"
|
|
bitfld.long 0x4 4. " GPIO_OUT4 ,GPIO pin 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 3. " GPIO_OUT3 ,GPIO pin 3 output data" "Low,High"
|
|
bitfld.long 0x4 2. " GPIO_OUT2 ,GPIO pin 2 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 1. " GPIO_OUT1 ,GPIO pin 1 output data" "Low,High"
|
|
bitfld.long 0x4 0. " GPIO_OUT0 ,GPIO pin 0 output data" "Low,High"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "GPIO_IN,GPIO Data Input Register"
|
|
bitfld.long 0x0 31. " GPIO_IN31 ,GPIO pin 31 input data" "Low,High"
|
|
bitfld.long 0x0 30. " GPIO_IN30 ,GPIO pin 30 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " GPIO_IN29 ,GPIO pin 29 input data" "Low,High"
|
|
bitfld.long 0x0 28. " GPIO_IN28 ,GPIO pin 28 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPIO_IN27 ,GPIO pin 27 input data" "Low,High"
|
|
bitfld.long 0x0 26. " GPIO_IN26 ,GPIO pin 26 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPIO_IN25 ,GPIO pin 25 input data" "Low,High"
|
|
bitfld.long 0x0 24. " GPIO_IN24 ,GPIO pin 24 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPIO_IN23 ,GPIO pin 23 input data" "Low,High"
|
|
bitfld.long 0x0 22. " GPIO_IN22 ,GPIO pin 22 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 21. " GPIO_IN21 ,GPIO pin 21 input data" "Low,High"
|
|
bitfld.long 0x0 20. " GPIO_IN20 ,GPIO pin 20 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " GPIO_IN19 ,GPIO pin 19 input data" "Low,High"
|
|
bitfld.long 0x0 18. " GPIO_IN18 ,GPIO pin 18 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 17. " GPIO_IN17 ,GPIO pin 17 input data" "Low,High"
|
|
bitfld.long 0x0 16. " GPIO_IN16 ,GPIO pin 16 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPIO_IN15 ,GPIO pin 15 input data" "Low,High"
|
|
bitfld.long 0x0 14. " GPIO_IN14 ,GPIO pin 14 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPIO_IN13 ,GPIO pin 13 input data" "Low,High"
|
|
bitfld.long 0x0 12. " GPIO_IN12 ,GPIO pin 12 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPIO_IN11 ,GPIO pin 11 input data" "Low,High"
|
|
bitfld.long 0x0 10. " GPIO_IN10 ,GPIO pin 10 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 9. " GPIO_IN9 ,GPIO pin 9 input data" "Low,High"
|
|
bitfld.long 0x0 8. " GPIO_IN8 ,GPIO pin 8 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPIO_IN7 ,GPIO pin 7 input data" "Low,High"
|
|
bitfld.long 0x0 6. " GPIO_IN6 ,GPIO pin 6 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_IN5 ,GPIO pin 5 input data" "Low,High"
|
|
bitfld.long 0x0 4. " GPIO_IN4 ,GPIO pin 4 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_IN3 ,GPIO pin 3 input data" "Low,High"
|
|
bitfld.long 0x0 2. " GPIO_IN2 ,GPIO pin 2 input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_IN1 ,GPIO pin 1 input data" "Low,High"
|
|
bitfld.long 0x0 0. " GPIO_IN0 ,GPIO pin 0 input data" "Low,High"
|
|
group.long 0xc++0x0b
|
|
line.long 0x0 "GPIO_PORT_MODE_L,GPIO Function Selection Register"
|
|
bitfld.long 0x0 30.--31. " GPIO15_PORT_MO ,Switch functions of pin GPIO15" "GPIO15,DCD2_N,WDOUT0_N,?..."
|
|
bitfld.long 0x0 28.--29. " GPIO14_PORT_MO ,Switch functions of pin GPIO14" "GPIO14,RXD2,?..."
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " GPIO13_PORT_MO ,Switch functions of pin GPIO13" "GPIO13,TXD2,?..."
|
|
bitfld.long 0x0 24.--25. " GPIO12_PORT_MO ,Switch functions of pin GPIO12" "GPIO12,CTS1_N,Reserved,ETMEXTOUT"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " GPIO11_PORT_MO ,Switch functions of pin GPIO11" "GPIO11,DSR1_N,Reserved,TRACEPKT3"
|
|
bitfld.long 0x0 20.--21. " GPIO10_PORT_MO ,Switch functions of pin GPIO10" "GPIO10,DCD1_N,Reserved,TRACEPKT2"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " GPIO9_PORT_MO ,Switch functions of pin GPIO9" "GPIO9,RXD1,Reserved,TRACEPKT1"
|
|
bitfld.long 0x0 16.--17. " GPIO8_PORT_MO ,Switch functions of pin GPIO8" "GPIO8,TXD1,Reserved,TRACEPKT0"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " GPIO7_PORT_MO ,Switch functions of pin GPIO7" "GPIO7,?..."
|
|
bitfld.long 0x0 12.--13. " GPIO6_PORT_MO ,Switch functions of pin GPIO6" "GPIO6,?..."
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " GPIO5_PORT_MO ,Switch functions of pin GPIO5" "GPIO5,?..."
|
|
bitfld.long 0x0 8.--9. " GPIO4_PORT_MO ,Switch functions of pin GPIO4" "GPIO4,?..."
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " GPIO3_PORT_MO ,Switch functions of pin GPIO3" "GPIO3,?..."
|
|
bitfld.long 0x0 4.--5. " GPIO2_PORT_MO ,Switch functions of pin GPIO2" "GPIO2,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " GPIO1_PORT_MO ,Switch functions of pin GPIO1" "GPIO1,?..."
|
|
bitfld.long 0x0 0.--1. " GPIO0_PORT_MO ,Switch functions of pin GPIO0" "GPIO0,?..."
|
|
line.long 0x4 "GPIO_PORT_MODE_H,GPIO Function Selection Register"
|
|
bitfld.long 0x4 30.--31. " GPIO31_PORT_MO ,Switch functions of pin GPIO31" "GPIO31,?..."
|
|
bitfld.long 0x4 28.--29. " GPIO30_PORT_MO ,Switch functions of pin GPIO30" "GPIO30,?..."
|
|
textline " "
|
|
bitfld.long 0x4 26.--27. " GPIO29_PORT_MO ,Switch functions of pin GPIO29" "GPIO29,?..."
|
|
bitfld.long 0x4 24.--25. " GPIO28_PORT_MO ,Switch functions of pin GPIO28" "GPIO28,?..."
|
|
textline " "
|
|
bitfld.long 0x4 22.--23. " GPIO27_PORT_MO ,Switch functions of pin GPIO27" "GPIO27,?..."
|
|
bitfld.long 0x4 20.--21. " GPIO26_PORT_MO ,Switch functions of pin GPIO26" "GPIO26,?..."
|
|
textline " "
|
|
bitfld.long 0x4 18.--19. " GPIO25_PORT_MO ,Switch functions of pin GPIO25" "GPIO25,?..."
|
|
bitfld.long 0x4 16.--17. " GPIO24_PORT_MO ,Switch functions of pin GPIO24" "GPIO24,?..."
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " GPIO23_PORT_MO ,Switch functions of pin GPIO23" "GPIO23,SCLKIN,Reserved,DBGACK"
|
|
bitfld.long 0x4 12.--13. " GPIO22_PORT_MO ,Switch functions of pin GPIO22" "GPIO22,SFRMIN,Reserved,TRACEPKT7"
|
|
textline " "
|
|
bitfld.long 0x4 10.--11. " GPIO21_PORT_MO ,Switch functions of pin GPIO21" "GPIO21,SFRMOUT,Reserved,TRACEPKT6"
|
|
bitfld.long 0x4 8.--9. " GPIO20_PORT_MO ,Switch functions of pin GPIO20" "GPIO20,SCLKOUT,Reserved,TRACEPKT5"
|
|
textline " "
|
|
bitfld.long 0x4 6.--7. " GPIO19_PORT_MO ,Switch functions of pin GPIO19" "GPIO19,SSPTXD,Reserved,TRACEPKT4"
|
|
bitfld.long 0x4 4.--5. " GPIO18_PORT_MO ,Switch functions of pin GPIO18" "GPIO18,SSPRXD,?..."
|
|
textline " "
|
|
bitfld.long 0x4 2.--3. " GPIO17_PORT_MO ,Switch functions of pin GPIO17" "GPIO17,CTS2_N,SSPOE,?..."
|
|
bitfld.long 0x4 0.--1. " GPIO16_PORT_MO ,Switch functions of pin GPIO16" "GPIO16,DSR2_N,SSPCTLOE,ETMEXTIN1"
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="ERTEC200")
|
|
tree "UART (Asynchronous Serial Interface)"
|
|
base ad:0x40002300
|
|
width 17.
|
|
hgroup.byte 0x0++0x0
|
|
hide.byte 0x0 "UARTDR,Data Register"
|
|
in
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "UARTRSR/UARTECR,Receive Status Register (read) Error Clear Register (write)"
|
|
bitfld.byte 0x0 3. " OE ,Overrun error - FIFO overloaded" "Not detected,Detected"
|
|
bitfld.byte 0x0 2. " BE ,Break error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " PE ,Parity error" "Not detected,Detected"
|
|
bitfld.byte 0x0 0. " FE ,Framing error" "Not detected,Detected"
|
|
if (((data.byte(ad:(0x40002300+0x8)))&0x2)==0x2)
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "UARTLCR_H,Line Control Register (High Byte)"
|
|
bitfld.byte 0x0 5.--6. " WLEN ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
bitfld.byte 0x0 4. " FEN ,FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " STP2 ,Number of stop bits" "1-bit,2-bits"
|
|
bitfld.byte 0x0 1. " PEN ,Parity check and generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " EPS ,Even/Odd parity for check and generation" "Odd,Even"
|
|
bitfld.byte 0x0 0. " BRK ,Send low level at transmit output" "Not sent,Sent"
|
|
else
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "UARTLCR_H,Line Control Register (High Byte)"
|
|
bitfld.byte 0x0 5.--6. " WLEN ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
bitfld.byte 0x0 4. " FEN ,FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " STP2 ,Number of stop bits" "1-bit,2-bits"
|
|
bitfld.byte 0x0 1. " PEN ,Parity check and generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0. " BRK ,Send low level at transmit output" "Not sent,Sent"
|
|
endif
|
|
group.byte 0xc++0x0
|
|
line.byte 0x0 "UARTLCR_M,Line Control Register (Middle Byte)"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "UARTLCR_L,Line Control Register (Low Byte)"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "UARTCR,Control Register"
|
|
bitfld.byte 0x0 7. " LBE ,Loop back enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " UARTEN , UART enable" "Disabled,Enabled"
|
|
rgroup.byte 0x18++0x0
|
|
line.byte 0x0 "UARTFR,Flag Register"
|
|
bitfld.byte 0x0 7. " TXFE ,Transmit FIFO status" "Not empty,Empty"
|
|
bitfld.byte 0x0 6. " RXFF ,Receive FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " TXFF ,Transmit FIFO status" "Not full,Full"
|
|
bitfld.byte 0x0 4. " RXFE ,Receive FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " BUSY ,UART status" "Not busy,Busy"
|
|
bitfld.byte 0x0 2. " DCD ,Inverse logical level of UART-DCD_N input pin" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " DSR ,Inverse logical level of UART-DCD_N input pin" "High,Low"
|
|
bitfld.byte 0x0 0. " CTS ,Inverse logical level of UART-CTS_N input pin" "High,Low"
|
|
group.byte 0x1c++0x0
|
|
line.byte 0x0 "UARTIIR/UARTICR,Interrupt Identification Register (read) Interrupt Clear Register (write)"
|
|
bitfld.byte 0x0 3. " RTIS ,Receive timeout interrupt status" "Not occurred,Occurred"
|
|
bitfld.byte 0x0 2. " TIS ,Transmit interrupt status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " RIS ,Receive interrupt status" "Not occurred,Occurred"
|
|
bitfld.byte 0x0 0. " MIS ,Modem interrupt status" "Not occurred,Ocurred"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ERTEC400")
|
|
tree.open "UART (Asynchronous Serial Interface)"
|
|
tree "UART 1"
|
|
base ad:0x40002300
|
|
width 17.
|
|
hgroup.byte 0x0++0x0
|
|
hide.byte 0x0 "UARTDR,Data Register"
|
|
in
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "UARTRSR/UARTECR,Receive Status Register (read) Error Clear Register (write)"
|
|
bitfld.byte 0x0 3. " OE ,Overrun error - FIFO overloaded" "Not detected,Detected"
|
|
bitfld.byte 0x0 2. " BE ,Break error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " PE ,Parity error" "Not detected,Detected"
|
|
bitfld.byte 0x0 0. " FE ,Framing error" "Not detected,Detected"
|
|
if (((data.byte(ad:(0x40002300+0x8)))&0x2)==0x2)
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "UARTLCR_H,Line Control Register (High Byte)"
|
|
bitfld.byte 0x0 5.--6. " WLEN ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
bitfld.byte 0x0 4. " FEN ,FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " STP2 ,Number of stop bits" "1-bit,2-bits"
|
|
bitfld.byte 0x0 1. " PEN ,Parity check and generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " EPS ,Even/Odd parity for check and generation" "Odd,Even"
|
|
bitfld.byte 0x0 0. " BRK ,Send low level at transmit output" "Not sent,Sent"
|
|
else
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "UARTLCR_H,Line Control Register (High Byte)"
|
|
bitfld.byte 0x0 5.--6. " WLEN ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
bitfld.byte 0x0 4. " FEN ,FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " STP2 ,Number of stop bits" "1-bit,2-bits"
|
|
bitfld.byte 0x0 1. " PEN ,Parity check and generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0. " BRK ,Send low level at transmit output" "Not sent,Sent"
|
|
endif
|
|
group.byte 0xc++0x0
|
|
line.byte 0x0 "UARTLCR_M,Line Control Register (Middle Byte)"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "UARTLCR_L,Line Control Register (Low Byte)"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "UARTCR,Control Register"
|
|
bitfld.byte 0x0 7. " LBE ,Loop back enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " UARTEN , UART enable" "Disabled,Enabled"
|
|
rgroup.byte 0x18++0x0
|
|
line.byte 0x0 "UARTFR,Flag Register"
|
|
bitfld.byte 0x0 7. " TXFE ,Transmit FIFO status" "Not empty,Empty"
|
|
bitfld.byte 0x0 6. " RXFF ,Receive FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " TXFF ,Transmit FIFO status" "Not full,Full"
|
|
bitfld.byte 0x0 4. " RXFE ,Receive FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " BUSY ,UART status" "Not busy,Busy"
|
|
bitfld.byte 0x0 2. " DCD ,Inverse logical level of UART-DCD_N input pin" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " DSR ,Inverse logical level of UART-DCD_N input pin" "High,Low"
|
|
bitfld.byte 0x0 0. " CTS ,Inverse logical level of UART-CTS_N input pin" "High,Low"
|
|
group.byte 0x1c++0x0
|
|
line.byte 0x0 "UARTIIR/UARTICR,Interrupt Identification Register (read) Interrupt Clear Register (write)"
|
|
bitfld.byte 0x0 3. " RTIS ,Receive timeout interrupt status" "Not occurred,Occurred"
|
|
bitfld.byte 0x0 2. " TIS ,Transmit interrupt status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " RIS ,Receive interrupt status" "Not occurred,Occurred"
|
|
bitfld.byte 0x0 0. " MIS ,Modem interrupt status" "Not occurred,Ocurred"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 2"
|
|
base ad:0x40002400
|
|
width 17.
|
|
hgroup.byte 0x0++0x0
|
|
hide.byte 0x0 "UARTDR,Data Register"
|
|
in
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "UARTRSR/UARTECR,Receive Status Register (read) Error Clear Register (write)"
|
|
bitfld.byte 0x0 3. " OE ,Overrun error - FIFO overloaded" "Not detected,Detected"
|
|
bitfld.byte 0x0 2. " BE ,Break error" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " PE ,Parity error" "Not detected,Detected"
|
|
bitfld.byte 0x0 0. " FE ,Framing error" "Not detected,Detected"
|
|
if (((data.byte(ad:(0x40002400+0x8)))&0x2)==0x2)
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "UARTLCR_H,Line Control Register (High Byte)"
|
|
bitfld.byte 0x0 5.--6. " WLEN ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
bitfld.byte 0x0 4. " FEN ,FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " STP2 ,Number of stop bits" "1-bit,2-bits"
|
|
bitfld.byte 0x0 1. " PEN ,Parity check and generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " EPS ,Even/Odd parity for check and generation" "Odd,Even"
|
|
bitfld.byte 0x0 0. " BRK ,Send low level at transmit output" "Not sent,Sent"
|
|
else
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "UARTLCR_H,Line Control Register (High Byte)"
|
|
bitfld.byte 0x0 5.--6. " WLEN ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
bitfld.byte 0x0 4. " FEN ,FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " STP2 ,Number of stop bits" "1-bit,2-bits"
|
|
bitfld.byte 0x0 1. " PEN ,Parity check and generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0. " BRK ,Send low level at transmit output" "Not sent,Sent"
|
|
endif
|
|
group.byte 0xc++0x0
|
|
line.byte 0x0 "UARTLCR_M,Line Control Register (Middle Byte)"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "UARTLCR_L,Line Control Register (Low Byte)"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "UARTCR,Control Register"
|
|
bitfld.byte 0x0 7. " LBE ,Loop back enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " UARTEN , UART enable" "Disabled,Enabled"
|
|
rgroup.byte 0x18++0x0
|
|
line.byte 0x0 "UARTFR,Flag Register"
|
|
bitfld.byte 0x0 7. " TXFE ,Transmit FIFO status" "Not empty,Empty"
|
|
bitfld.byte 0x0 6. " RXFF ,Receive FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " TXFF ,Transmit FIFO status" "Not full,Full"
|
|
bitfld.byte 0x0 4. " RXFE ,Receive FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " BUSY ,UART status" "Not busy,Busy"
|
|
bitfld.byte 0x0 2. " DCD ,Inverse logical level of UART-DCD_N input pin" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " DSR ,Inverse logical level of UART-DCD_N input pin" "High,Low"
|
|
bitfld.byte 0x0 0. " CTS ,Inverse logical level of UART-CTS_N input pin" "High,Low"
|
|
group.byte 0x1c++0x0
|
|
line.byte 0x0 "UARTIIR/UARTICR,Interrupt Identification Register (read) Interrupt Clear Register (write)"
|
|
bitfld.byte 0x0 3. " RTIS ,Receive timeout interrupt status" "Not occurred,Occurred"
|
|
bitfld.byte 0x0 2. " TIS ,Transmit interrupt status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " RIS ,Receive interrupt status" "Not occurred,Occurred"
|
|
bitfld.byte 0x0 0. " MIS ,Modem interrupt status" "Not occurred,Ocurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "SPI1 (Synchronous Serial Interface)"
|
|
base ad:0x40002200
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SSPCR0,SPI1 Control Register 0"
|
|
hexmask.word.byte 0x0 8.--15. 1. " SCR ,Serial transmission speed for master mode"
|
|
bitfld.word 0x0 7. " SPH ,Select phase" "Immediately,Delayed"
|
|
bitfld.word 0x0 6. " SPO ,Select Serial clock output polarity(received/outgoing)" "Rising/falling edge,Falling/rising edge"
|
|
textline " "
|
|
bitfld.word 0x0 4.--5. " FRF ,Operation mode" "Motorola SPI,TI synchronous serial,National Microwire,?..."
|
|
bitfld.word 0x0 0.--3. " DSS ,Data size select" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SSPCR1,SPI1 Control Register 1"
|
|
bitfld.word 0x0 6. " SOD ,Slave mode output enable" "Enabled,Disabled"
|
|
bitfld.word 0x0 5. " MS ,Master/slave mode" "Master,Slave"
|
|
bitfld.word 0x0 4. " SSE ,Synchronous serial port enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 3. " LBM ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.word 0x0 2. " RORIE ,Receive FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 1. " TIE ,Transmit FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 0. " RIE ,Receive FIFO interrupt enable" "Disabled,Enabled"
|
|
hgroup.word 0x8++0x1
|
|
hide.word 0x0 "SSPDR,Rx/Tx FIFO Data Register"
|
|
in
|
|
rgroup.word 0x0c++0x1
|
|
line.word 0x0 "SSPSR,SPI1 Status Register"
|
|
bitfld.word 0x0 4. " BSY ,SPI1 busy status" "Not busy,Busy"
|
|
bitfld.word 0x0 3. " RFF ,Receive FIFO full indication" "Not full,Full"
|
|
bitfld.word 0x0 2. " RNE ,Receive FIFO not empty indication" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.word 0x0 1. " TNF ,Transmit FIFO not full indication" "Full,Not full"
|
|
bitfld.word 0x0 0. " TFE ,Transmit FIFO empty indication" "Not empty,Empty"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SSPCPSR,SPI1 Clock Prescale Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. " CPSDVSR ,Set the divisor for the SPI1 clock prescaler"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "SSPIIR/SSPICR,Interrupt Identification Register (read) Interrupt Clear Register (write)"
|
|
bitfld.word 0x0 2. " RORIS ,SPI1 receive FIFO overrun interrupt status" "Not active,Active"
|
|
bitfld.word 0x0 1. " TIS ,SPI1 transmit FIFO service request interrupt status" "Not active,Active"
|
|
bitfld.word 0x0 0. " RIS ,SPI1 receive FIFO service request interrupt status" "Not active,Active"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="ERTEC200")
|
|
tree "ERTEC 200 Timers"
|
|
base ad:0x40002000
|
|
width 15.
|
|
textline " "
|
|
tree "Timer0 and Timer 1"
|
|
group.long 0x10++0x7 "Timers 0 and 1"
|
|
line.long 0x0 "CTRL_PREDIV,Both Prescalers Control Register"
|
|
bitfld.long 0x0 3. " Load_V1 ,Load trigger for prescaler 1" "Not effect,Loaded"
|
|
bitfld.long 0x0 2. " Run/xStop_V1 ,Starts and stops prescaler 1 for timer 1" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Load_V0 , Load trigger for prescaler 0" "Not effect,Loaded"
|
|
bitfld.long 0x0 0. " Run/xStop_V0 ,Starts and stops prescaler 0 for timer 0" "Stopped,Running"
|
|
line.long 0x4 "RELD_PREDIV,Both Prescalers Reload Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. " Prediv_V1 ,Hold 8-bit reload value for prescaler 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " Prediv_V0 ,Hold 8-bit reload value for prescaler 0"
|
|
group.long 0x0++0x3 "Timer 0"
|
|
line.long 0x0 "CTRL_STAT0,Timer 0 Control/Status Register"
|
|
bitfld.long 0x0 5. " Status ,Timer 0 status indication" "Not expired,Expired"
|
|
bitfld.long 0x0 2. " Reload-Mode ,Timer 0 reload mode selection" "Stopped,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Load ,Load trigger for timer 0" "No effect,Loaded"
|
|
bitfld.long 0x0 0. " Run/xStop ,Start and stop the counter in timer 0" "Stopped,Running"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "RELD0,Timer 0 Reload Register"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "TIM0,Timer 0 Value Register"
|
|
group.long 0x4++0x3 "Timer 1"
|
|
line.long 0x0 "CTRL_STAT1,Timer 1 Control/Status Register "
|
|
bitfld.long 0x0 6. " Cascading ,Timers 0 and 1 cascaded" "Not cascaded,Cascaded"
|
|
bitfld.long 0x0 5. " Status ,Timer 1 status indication" "Not expired,Expired"
|
|
textline " "
|
|
bitfld.long 0x0 2. " Reload-Mode ,Timer 1 reload mode selection" "Stopped,Reloaded"
|
|
bitfld.long 0x0 1. " Load ,Load trigger for timer 1" "No effect,Loaded"
|
|
textline " "
|
|
bitfld.long 0x0 0. " Run/xStop ,Starts and stops the counter in timer 1" "Stopped,Running"
|
|
group.long 0xc++0x3
|
|
line.long 0x0 "RELD1,Timer 1 Reload Register"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x0 "TIM1,Timer 1 Value Register"
|
|
tree.end
|
|
tree "Timer 2"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "TIM2_CTRL,Timer 2 Control Register"
|
|
bitfld.long 0x0 18. " Timer_Mode ,Trigger mode for timer 2" "Free running,Re-triggered"
|
|
bitfld.long 0x0 17. " OneShot_Mode ,One-shot/Reload mode" "Reload,One shot"
|
|
textline " "
|
|
bitfld.long 0x0 16. " Run/xStop_T2 ,Start/stop timer 2" "Stopped,Started"
|
|
hexmask.long.word 0x0 0.--15. 1. " Reload ,16-bit reload value for timer 2"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "TIM2,Timer 2 Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " Timer ,Current counter value for timer 2"
|
|
tree.end
|
|
tree "F-Timer"
|
|
rgroup.long 0x700++0x3
|
|
line.long 0x0 "F-COUNTER-VAL,F-Timer Value Register"
|
|
wgroup.long 0x704++0x3
|
|
line.long 0x0 "F-COUNTER-RES,F-Timer Reset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " F-CNTRES ,Reset value for F-timer"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ERTEC400")
|
|
tree.open "ERTEC 400 Timers"
|
|
base ad:0x40002000
|
|
width 15.
|
|
tree "Timer0 and Timer 1"
|
|
group.long 0x10++0x7 "Timers 0 and 1"
|
|
line.long 0x0 "CTRL_PREDIV,Both Prescalers Control Register"
|
|
bitfld.long 0x0 3. " Load_V1 ,Load trigger for prescaler 1" "No effect,Loaded"
|
|
bitfld.long 0x0 2. " Run/xStop_V1 ,Starts and stops prescaler 1 for timer 1" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Load_V0 , Load trigger for prescaler 0" "No effect,Loaded"
|
|
bitfld.long 0x0 0. " Run/xStop_V0 ,Starts and stops prescaler 0 for timer 0" "Stopped,Running"
|
|
line.long 0x4 "RELD_PREDIV,Both Prescalers Reload Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. " Prediv_V1 ,Hold 8-bit reload value for prescaler 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " Prediv_V0 ,Hold 8-bit reload value for prescaler 0"
|
|
group.long 0x0++0x3 "Timer 0"
|
|
line.long 0x0 "CTRL_STAT0,Timer 0 Control/Status Register"
|
|
bitfld.long 0x0 5. " Status ,Timer 0 status indication" "Not expired,Expired"
|
|
bitfld.long 0x0 2. " Reload-Mode ,Timer 0 reload mode selection" "Stopped,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Load ,Load trigger for timer 0" "No effect,Loaded"
|
|
bitfld.long 0x0 0. " Run/xStop ,Start and stop the counter in timer 0" "Stopped,Running"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "RELD0,Timer 0 Reload Register"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "TIM0,Timer 0 Value Register"
|
|
group.long 0x4++0x3 "Timer 1"
|
|
line.long 0x0 "CTRL_STAT1,Timer 1 Control/Status Register "
|
|
bitfld.long 0x0 6. " Cascading ,Timers 0 and 1 cascaded" "Not cascaded,Cascaded"
|
|
bitfld.long 0x0 5. " Status ,Timer 1 status indication" "Not expired,Expired"
|
|
textline " "
|
|
bitfld.long 0x0 2. " Reload-Mode ,Timer 1 reload mode selection" "Stopped,Reloaded"
|
|
bitfld.long 0x0 1. " Load ,Load trigger for timer 1" "No effect,Loaded"
|
|
textline " "
|
|
bitfld.long 0x0 0. " Run/xStop ,Starts and stops the counter in timer 1" "Stopped,Running"
|
|
group.long 0xc++0x3
|
|
line.long 0x0 "RELD1,Timer 1 Reload Register"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x0 "TIM1,Timer 1 Value Register"
|
|
tree.end
|
|
tree "F-Timer"
|
|
rgroup.long 0x700++0x3
|
|
line.long 0x0 "F-COUNTER-VAL,F-Timer Value Register"
|
|
wgroup.long 0x704++0x3
|
|
line.long 0x0 "F-COUNTER-RES,F-Timer Reset Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " F-CNT-RES ,Reset value for F-timer"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "Watchdog Timer"
|
|
base ad:0x40002100
|
|
width 15.
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTRL/STATUS,Watchdog Control/Status Register "
|
|
hexmask.long.word 0x0 16.--31. 1. " KB ,Key bits"
|
|
textline " "
|
|
bitfld.long 0x0 4. " Status_Counter1 ,Watchdog counter 1 status" "Not expired,Expired"
|
|
textline " "
|
|
bitfld.long 0x0 3. " Status_Counter0 ,Watchdog counter 0 status" "Not expired,Expired"
|
|
textline " "
|
|
bitfld.long 0x0 2. " Load ,Reload for watchdog counters 0 and 1" "No effect,Loaded"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Run/xStop_Z1 ,Start/stop watchdog counter 1" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x0 0. " Run/xStop_Z0 ,Start/stop watchdog counter 0" "Stopped,Running"
|
|
line.long 0x4 "RELD0_LOW,Watchdog 0 Reload Register (Low)"
|
|
hexmask.long.word 0x4 16.--31. 1. " KB ,Key bits"
|
|
hexmask.long.word 0x4 0.--15. 1. " Reload0 ,Value for bits (15:0) of watchdog counter 0"
|
|
line.long 0x8 "RELD0_HIGH,Watchdog 0 Reload Register (High)"
|
|
hexmask.long.word 0x8 16.--31. 1. " KB ,Key bits"
|
|
hexmask.long.word 0x8 0.--15. 1. " Reload0 ,Value for bits (31:16) of watchdog counter 0"
|
|
line.long 0xc "RELD1_LOW,Watchdog 1 Reload Register (Low)"
|
|
hexmask.long.word 0xc 16.--31. 1. " KB ,Key bits"
|
|
hexmask.long.word 0xc 0.--15. 1. " Reload1 ,Value for bits (19:4) of watchdog counter 1"
|
|
line.long 0x10 "RELD1_HIGH,Watchdog 1 Reload Register (High)"
|
|
hexmask.long.word 0x10 16.--31. 1. " KB ,Key bits"
|
|
hexmask.long.word 0x10 0.--15. 1. " Reload1 ,Value for bits (35:20) of watchdog counter 1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "WDOG0,Watchdog Timer 0 Counter Register"
|
|
line.long 0x4 "WDOG1,Watchdog Timer 1 Counter Register"
|
|
textline " "
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="ERTEC200")
|
|
tree "SCR (System Control Registers)"
|
|
base ad:0x40002600
|
|
width 15.
|
|
rgroup.long 0x0++0xb
|
|
line.long 0x0 "ID_REG,Device Identification Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ERTEC200-ID ,Identification pattern"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " HW-RELEASE ,Number representing the HW release"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " METAL-FIX ,Number representing the metal fix step"
|
|
line.long 0x4 "BOOT_REG,Boot Mode Pin Register"
|
|
bitfld.long 0x4 0.--3. " BOOT ,Logical level of the BOOT[3:0] pins during the active reset phase" "ROM/NOR 8-bit,ROM/NOR 16-bit,ROM/NOR 32-bit,Reserved,Reserved,SPI,UART,LBU,Fast ROM/NOR 8-bit,Fast ROM/NOR 16-bit,Fast ROM/NOR 32-bit,?..."
|
|
line.long 0x8 "CONFIG_REG,Config Pin Register"
|
|
;textline " "
|
|
bitfld.long 0x8 2. 5.--6. " CONFIG[6/5/2] ,Logical level of the CONFIG[6:5] and CONFIG2 pins during the active reset phase" "LBU On/LBU_WR_N write/LBU_RD_N read/LBU_RDY_N low,Reserved,LBU On/LBU_WR_N read-write/LBU_RDY_N low,LBU Off/GPIO[44:32] active/Trace off/MII on,LBU On/LBU_WR_N write/LBU_RD_N read/LBU_RDY_N high,LBU Off/GPIO[44:32] active/Trace on/MII off,LBU On/LBU_WR_N read-write/LBU_RDY_N high,?..."
|
|
textline " "
|
|
bitfld.long 0x8 3.--4. " CONFIG[4:3] ,Logical level of the CONFIG[4:3] pins during the active reset phase" "50 MHz,100 MHz,150 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x8 1. " CONFIG1 ,Logical level of the CONFIG1 pin during the active reset phase" "Clock,Tri-state"
|
|
group.long 0xc++0x3
|
|
line.long 0x0 "RES_CTRL_REG,Reset Control Register"
|
|
hexmask.long.word 0x0 3.--12. 1. " PULSE_DUR ,Pulse duration"
|
|
textline " "
|
|
bitfld.long 0x0 2. " EN_WD_SOFT_RES_IRTE ,Software/watchdog reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 1. " XRES_SOFT ,Trigger a reset under software control" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WD_RES_FREI ,Enables reset triggered by watchdog timer 1" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "RES_STAT_REG,Reset Status Register"
|
|
bitfld.long 0x0 2. " HW_RESET ,Hardware reset status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SW_RESET ,Software reset status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WD_RESET ,Watchdog reset status" "No reset,Reset"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PLL_STAT_REG,PLL Status Register"
|
|
bitfld.long 0x0 17. " INT_MASK_LOSS ,Interrupt masking for INT_LOSS_STATE interrupt" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 16. " INT_MASK_LOCK ,Interrupt masking for INT_LOCK_STATE interrupt" "Enabled,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 5. " INT_QVZ_EMIF_STATE ,External memory interface timeout interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " INT_LOSS_STATE ,INT_LOSS_STATE interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 2. " INT_LOCK_STATE ,INT_LOCK_STATE interrupt status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PLL_INPUT_CLK_LOSS ,PLL input clock monitoring status" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PLL_LOCK ,PLL lock state" "Not locked,Locked"
|
|
rgroup.long 0x28++0x13
|
|
line.long 0x0 "QVZ_AHB_ADR,AHB Timeout Address Register"
|
|
line.long 0x4 "QVZ_AHB_CTRL,AHB Timeout Control Signal Register"
|
|
bitfld.long 0x4 4.--6. " HBURST ,Logical level of the HBURST[2:0] signals" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x4 1.--3. " HSIZE ,Logical level of the HSIZE[2:0] signals" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 0. " HWRITE ,Logical level of the HWRITE signal" "Read,Write"
|
|
line.long 0x8 "QVZ_AHB_M,AHB Timeout Master Register"
|
|
bitfld.long 0x8 3. " QVZ_AHB_DMA ,DMA controller state during incorrect multilayer AHB access" "Not master,Master"
|
|
textline " "
|
|
bitfld.long 0x8 2. " QVZ_AHB_IRT ,IRT switch state during incorrect multilayer AHB access" "Not master,Master"
|
|
textline " "
|
|
bitfld.long 0x8 1. " QVZ_AHB_LBU ,LBU Block state during incorrect multilayer AHB access" "Not master,Master"
|
|
textline " "
|
|
bitfld.long 0x8 0. " QVZ_AHB_ARM946 ,ARM946E-S CPU state during incorrect multilayer AHB access" "Not master,Master"
|
|
line.long 0xc "QVZ_APB_ADR,APB Timeout Address Register"
|
|
line.long 0x10 "QVZ_EMIF_ADR,EMIF Timeout Address Register"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "MEM_SWAP,Memory Swap Register"
|
|
bitfld.long 0x0 0.--1. " MEM_SWAP ,Alternative memories to the original internal ROM address location" "Int boot ROM,Ext SDRAM,Ext static Mem,No memory"
|
|
group.long 0x4c++0xb
|
|
line.long 0x0 "M_LOCK_CTRL,AHB Master Lock Control Register"
|
|
bitfld.long 0x0 2. " M_LOCK_CTRL2 ,AHB master bus locking for IRT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " M_LOCK_CTRL1 ,AHB master bus locking for LBU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M_LOCK_CTRL0 ,AHB master bus locking for ARM946E-S" "Disabled,Enabled"
|
|
line.long 0x4 "ARM9_CTRL,ARM9 Control Register"
|
|
bitfld.long 0x4 13. " BIGENDIAN ,Processor is running in little/big endian mode" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x4 12. " DISABLE_GATE_THE_CLK ,ARM9 CPU clock runs freely or not" "Paused,Free run"
|
|
textline " "
|
|
bitfld.long 0x4 11. " DBGEN ,Embedded ARM9 debugger" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 10. " MICEBYPASS ,Bypass TCK synchronisation to ARM9 clock" "Synchronized,Not synchronized"
|
|
textline " "
|
|
bitfld.long 0x4 9. " INITRAM ,TCMs are enabled/disabled to use" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x4 0.--8. 1. " SYSOPT ,ETM options"
|
|
line.long 0x8 "ARM9_WE,ARM9 Control Write Enable Register"
|
|
bitfld.long 0x8 0. " WE_ARM9_CTRL ,ARM9_CTRL register write enable" "Disabled,Enabled"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "ERTEC 200_TAG,ERTEC 200 TAG Identification Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. " REVISION_ID ,Revision ID of the current ERTEC switching state"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " VERSION_ID ,Version ID of the current ERTEC switching state"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " DEBUG_ID ,Debug ID of the current ERTEC switching state"
|
|
group.long 0x5c++0x3
|
|
line.long 0x0 "PHY_CONFIG,PHY1/2 Configuration Register"
|
|
bitfld.long 0x0 16. " PHY_RES_SEL ,Reset source for PHY1 and PHY2" "Device,IRT output"
|
|
textline " "
|
|
bitfld.long 0x0 13. " P2_AUTOMDIXEN ,Enable AutoMDIX state machine for PHY2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10.--12. " P2_PHY_MODE ,Select operation mode for PHY2" "10BASE-T HD/A-N disabled,10BASE-T FD/A-N disabled,10BASE-TX/FX HD/A-N disabled,10BASE-TX/FX FD/A-N disabled,100BASE-TX/HD advertised/A-N enabled,100BASE-TX/HD advertised/Repeater,Power down mode,A-N enabled/AutoMDIX enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " P2_FX_MODE ,Enable 100BASE-FX interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " P2_PHY_ENB ,Enable PHY2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P1_AUTOMDIXEN ,Enable AutoMDIX state machine for PHY1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2.--4. " P1_PHY_MODE ,Select operation mode for PHY1" "10BASE-T HD/A-N disabled,10BASE-T FD/A-N disabled,10BASE-TX/FX HD/A-N disabled,10BASE-TX/FX FD/A-N disabled,100BASE-TX/HD advertised/A-N enabled,100BASE-TX/HD advertised/Repeater,Power down mode,A-N enabled/AutoMDIX enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " P1_FX_MODE ,Enable 100BASE-FX interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " P1_PHY_ENB ,Enable PHY1" "Disabled,Enabled"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "PHY_STATUS,PHY1/2 Status Register"
|
|
bitfld.long 0x0 8. " P2_PWRUPRST ,PHY2 ready to operate" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 0. " P1_PWRUPRST ,PHY1 ready to operate" "Not ready,Ready"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "UART_CLK,UART Clock Section Register"
|
|
bitfld.long 0x0 0. " UART_TAKT ,Operation clock for UART" "50MHz,6MHz"
|
|
textline " "
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ERTEC400")
|
|
tree "SCR (System Control Registers)"
|
|
base ad:0x40002600
|
|
width 18.
|
|
rgroup.long 0x0++0xb
|
|
line.long 0x0 "ID_REG,Device Identification Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ERTEC400-ID ,Identification pattern"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HW-RELEASE ,Number representing the HW release"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " METAL-FIX ,Number representing the metal fix step"
|
|
line.long 0x4 "BOOT_REG,Boot Mode Pin Register"
|
|
bitfld.long 0x4 0.--2. " BOOT ,Logical level of the BOOT[3:0] pins during the active reset phase" "ROM/NOR 8-bit,ROM/NOR 16-bit,ROM/NOR 32-bit,Reserved,Reserved,SPI,UART1,PCI slave/LBU"
|
|
line.long 0x8 "CONFIG_REG,Config Pin Register"
|
|
bitfld.long 0x8 3.--4. " CONFIG[4:3] ,CPU core clock frequency select" "50 MHz,100 MHz,150 MHz,?..."
|
|
bitfld.long 0x8 2. " CONFIG2 ,Interface selecte" "Local bus,PCI"
|
|
textline " "
|
|
bitfld.long 0x8 1. " CONFIG1 ,Clock input to REF_CLK pin select" "50 MHz,25 MHz"
|
|
bitfld.long 0x8 0. " CONFIG0 ,Clock input select" "CLKP_A and CLKP_B,REF_CLK"
|
|
group.long 0xc++0x3
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line.long 0x0 "RES_CTRL_REG,Reset Control Register"
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bitfld.long 0x0 9. " XRES_PCI_STATE ,Reflects the status of the RES_PCI_N input pin" "Reset,No reset"
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bitfld.long 0x0 8. " XRES_PCI_AHB_SOFT ,Allows to trigger a SW reset of the AHB-side of the AHB-PCI bridge" "Reset,No reset"
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textline " "
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hexmask.long.byte 0x0 3.--7. 1. " PULSE_DUR ,Pulse duration"
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bitfld.long 0x0 1. " XRES_SOFT ,Trigger a reset under software control" "Not triggered,Triggered"
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textline " "
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bitfld.long 0x0 0. " WD_RES_FREI ,Enables reset triggered by watchdog timer 1" "Disabled,Enabled"
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rgroup.long 0x10++0x3
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line.long 0x0 "RES_STAT_REG,Reset Status Register"
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bitfld.long 0x0 2. " HW_RESET ,Hardware reset status" "No reset,Reset"
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bitfld.long 0x0 1. " SW_RESET ,Software reset status" "No reset,Reset"
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textline " "
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bitfld.long 0x0 0. " WD_RESET ,Watchdog reset status" "No reset,Reset"
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group.long 0x14++0x3
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line.long 0x0 "PLL_STAT_REG,PLL Status Register"
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bitfld.long 0x0 18. " INT_MASK_QVZ_PCI_SLAVE ,Interrupt masking for INT_QVZ_PCI_SLAVE_STATE interrupt" "Enabled,Masked"
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bitfld.long 0x0 17. " INT_MASK_LOSS ,Interrupt masking for INT_LOSS_STATE interrupt" "Enabled,Masked"
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textline " "
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bitfld.long 0x0 16. " INT_MASK_LOCK ,Interrupt masking for INT_LOCK_STATE interrupt" "Enabled,Masked"
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bitfld.long 0x0 5. " INT_QVZ_EMIF_STATE ,External memory interface timeout interrupt status" "Not active,Active"
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textline " "
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bitfld.long 0x0 4. " INT_QVZ_PCI_SLAVE_STATE ,PCI slave timeout interrupt status" "Not active,Active"
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bitfld.long 0x0 3. " INT_LOSS_STATE ,INT_LOSS_STATE interrupt status" "Not active,Active"
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textline " "
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bitfld.long 0x0 2. " INT_LOCK_STATE ,INT_LOCK_STATE interrupt status" "Not active,Active"
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bitfld.long 0x0 1. " PLL_INPUT_CLK_LOSS ,PLL input clock monitoring status" "Not present,Present"
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textline " "
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bitfld.long 0x0 0. " PLL_LOCK ,PLL lock state" "Not locked,Locked"
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group.long 0x18++0x3
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line.long 0x0 "Clk_CTRL_REG,Clock Control Register"
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bitfld.long 0x0 0. " Clk_Ctrl ,Enables the clock on the AHB-side of the PCI bridge" "Disabled,Enabled"
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rgroup.long 0x1C++0x3
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line.long 0x0 "PM_STATE_REQ_REG,PCI Power State Request Register"
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bitfld.long 0x0 0.--1. " PM_STATE_REQ ,Indicates the power state that was requested by the PCI host" "D0,D1,D2,D3"
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group.long 0x20++0x07
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line.long 0x0 "PM_STATE_ACK_REG,PCI Power State Acknowledge Register"
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bitfld.long 0x0 0.--1. " PM_STATE_ACK ,Indicates the current power state of ERTEC 400" "D0,D1,D2,D3"
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line.long 0x4 "PME_REG,PME Register"
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bitfld.long 0x4 0. " PME ,PME signal activation" "Not activated,Activated"
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rgroup.long 0x28++0x13
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line.long 0x0 "QVZ_AHB_ADR,AHB Timeout Address Register"
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line.long 0x4 "QVZ_AHB_CTRL,AHB Timeout Control Signal Register"
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bitfld.long 0x4 4.--6. " HBURST ,Logical level of the HBURST[2:0] signals" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x4 1.--3. " HSIZE ,Logical level of the HSIZE[2:0] signals" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x4 0. " HWRITE ,Logical level of the HWRITE signal" "Read,Write"
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line.long 0x8 "QVZ_AHB_M,AHB Timeout Master Register"
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bitfld.long 0x8 2. " IRT ,IRT switch state during incorrect multilayer AHB access" "Not master,Master"
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textline " "
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bitfld.long 0x8 1. " LBU/PCI ,LBU/PCI Block state during incorrect multilayer AHB access" "Not master,Master"
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textline " "
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bitfld.long 0x8 0. " ARM946E-S ,ARM946E-S CPU state during incorrect multilayer AHB access" "Not master,Master"
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line.long 0xc "QVZ_APB_ADR,APB Timeout Address Register"
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line.long 0x10 "QVZ_EMIF_ADR,EMIF Timeout Address Register"
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group.long 0x3C--0x43
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line.long 0x00 "PCI_RES_REQ,PCI Reset Request Register"
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hexmask.long.word 0x00 16.--31. 1. " MAX_DELAY_PCI ,Timeout delay"
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bitfld.long 0x00 1. " PCI_QVZ_EN ,Timeout monitoring enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " PCI_SOFT_RESREQ ,PCI soft reset request" "Not requested,Requested"
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line.long 0x04 "PCI_RES_ACK,PCI Reset Acknowledge Register"
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bitfld.long 0x04 0. " PCI_SOFT_RESACK ,PCI soft reset execute" "Not acknowledged,Acknowledged"
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group.long 0x44++0x3
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line.long 0x0 "MEM_SWAP,Memory Swap Register"
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bitfld.long 0x0 0. " MEM_SWAP ,Alternative memories to the original internal ROM address location" "Int boot ROM,Internal SRAM"
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group.long 0x48++0x03
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line.long 0x0 "PCI_INT_CTRL,PCI Interrupt Control Register"
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bitfld.long 0x0 0.--1. " PCI_INT_CTRL ,PCI interrupt routing" "IRQ0_HP,IRQ0_HP,IRQ_IRT_API_ERR/IRQ0_HP,IRQ0_HP or IRQ_IRT_API_ERR"
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group.long 0x4c++0xb
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line.long 0x0 "M_LOCK_CTRL,AHB Master Lock Control Register"
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bitfld.long 0x0 2. " M_LOCK_CTRL2 ,AHB master bus locking for IRT" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 1. " M_LOCK_CTRL1 ,AHB master bus locking for LBU" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 0. " M_LOCK_CTRL0 ,AHB master bus locking for ARM946E-S" "Disabled,Enabled"
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line.long 0x4 "ARM9_CTRL,ARM9 Control Register"
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bitfld.long 0x4 13. " BIGENDIAN ,Processor is running in little/big endian mode" "Little,Big"
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textline " "
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bitfld.long 0x4 12. " DISABLE_GATE_THE_CLK ,ARM9 CPU clock runs freely or not" "Paused,Free run"
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textline " "
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bitfld.long 0x4 11. " DBGEN ,Embedded ARM9 debugger" "Disabled,Enabled"
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textline " "
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bitfld.long 0x4 10. " MICEBYPASS ,Bypass TCK synchronisation to ARM9 clock" "Synchronized,Not synchronized"
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textline " "
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bitfld.long 0x4 9. " INITRAM ,TCMs are enabled/disabled to use" "Disabled,Enabled"
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textline " "
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hexmask.long.word 0x4 0.--8. 1. " SYSOPT ,ETM options"
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line.long 0x8 "ARM9_WE,ARM9 Control Write Enable Register"
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bitfld.long 0x8 0. " ARM9_WE ,ARM9_CTRL register write enable" "Disabled,Enabled"
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width 0xb
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tree.end
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endif
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textline " "
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