23725 lines
1.7 MiB
23725 lines
1.7 MiB
; --------------------------------------------------------------------------------
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; @Title: DA8XXA On-Chip Peripherals
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; @Props: Released
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; @Author: CIN
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; @Changelog: 2011-09-28 CIN
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; @Manufacturer: TI - Texas Instruments
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; @Doc: sprs483a.pdf; spruh79.pdf; spruh91.pdf
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; @Core: ARM926EJ-S
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perda8xxa.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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width 0xb
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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AUTOINDENT.POP
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tree.end
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tree "SYSCFG (Boot Config)"
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base asd:0x01c14000
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width 10.
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rgroup.long 0x00++0x03
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line.long 0x00 "REVID,Revision Identification Register"
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rgroup.long 0x08++0x13
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line.long 0x0 "DIEIDR0,Device Identification Register 0"
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line.long 0x4 "DIEIDR1,Device Identification Register 1"
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line.long 0x8 "DIEIDR2,Device Identification Register 2"
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line.long 0xC "DIEIDR3,Device Identification Register 3"
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line.long 0x10 "DEVIDR0,Device Identification Register 0"
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rgroup.long 0x20++0x03
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line.long 0x00 "BOOTCFG,Boot Configuration Register"
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hexmask.long 0x00 1.--15. 1. " BOOTMODE ,Boot Mode"
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group.long 0x38++0x0f
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line.long 0x00 "KICK0R,Kick 0 Register"
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line.long 0x04 "KICK1R,Kick 1 Register"
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line.long 0x08 "HOST0CFG,Host 0 Configuration Register"
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bitfld.long 0x08 0. " BOOTRDY ,ARM boot ready bit allowing ARM to boot" "Not ready,Ready"
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|
sif (CPU()!="AM1707")
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line.long 0x0c "HOST1CFG,Host 1 Configuration Register"
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endif
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group.long 0xe0++0x1b
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line.long 0x00 "IRAWSTAT,Interrupt Raw Status/Set Register"
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bitfld.long 0x00 1. " ADDRERR ,Addressing violation error" "No interrupt,Interrupt"
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bitfld.long 0x00 0. " PROTERR ,Protection violation error" "No interrupt,Interrupt"
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line.long 0x04 "IENSTAT,Interrupt Enable Status/Clear Register"
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bitfld.long 0x04 1. " ADDRERR ,Addressing violation error" "No interrupt,Interrupt"
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bitfld.long 0x04 0. " PROTERR ,Protection violation error" "No interrupt,Interrupt"
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line.long 0x08 "IENSET,Interrupt Enable Register"
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setclrfld.long 0x08 1. 0x08 1. 0x0C 1. " ADDRERREN_set/clr ,Addressing violation error interrupt" "Disabled,Enabled"
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|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " PROTERRN_set/clr ,Protection violation error interrupt" "Disabled,Enabled"
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line.long 0x10 "EOI,End of Interrupt Register"
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|
hexmask.long.byte 0x10 0.--7. 1. " EOIVECT ,EOI vector value"
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line.long 0x14 "FLTADDRR,Fault Address Register"
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line.long 0x18 "FLTSTAT,Fault Status Register"
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hexmask.long.byte 0x18 24.--31. 1. " ID ,Transfer ID of the first fault transfer"
|
|
hexmask.long.byte 0x18 16.--23. 1. " MSTID ,Master ID of the first fault transfer"
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textline " "
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bitfld.long 0x18 9.--12. " PRIVID ,Privilege ID of the first fault transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 0.--5. " TYPE ,Fault type of first fault transfer" "Notransfer,User execute,User write,Reserved,User read,Reserved,Reserved,Reserved,Supervisor execute,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read,?..."
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width 10.
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group.long 0x120++0x4f "Pin Multiplexing Control Registers"
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line.long 0x00 "PINMUX0,Pin Multiplexing Control Register 0"
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bitfld.long 0x00 28.--31. " PINMUX0[31:28] ,/EMB_WE Control" "Tri-stated,/EMB_WE,?..."
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bitfld.long 0x00 24.--27. " PINMUX0[27:24] ,/EMB_RAS Control" "Tri-stated,/EMB_RAS,?..."
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textline " "
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bitfld.long 0x00 20.--23. " PINMUX0[23:20] ,/EMB_CAS Control" "Tri-stated,/EMB_CAS,?..."
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bitfld.long 0x00 16.--19. " PINMUX0[19:16] ,/EMB_CS[0] Control" "Tri-stated,/EMB_CS[0],?..."
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textline " "
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bitfld.long 0x00 12.--15. " PINMUX0[15:12] ,EMB_CLK Control" "Tri-stated,EMIFB LPSC (CLK1),PLL DIV4P5/SYSCLK5 (CLK2),?..."
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bitfld.long 0x00 8.--11. " PINMUX0[11:8] ,EMB_SDCKE Control" "Tri-stated,EMB_SDCKE,?..."
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|
textline " "
|
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bitfld.long 0x00 4.--7. " PINMUX0[7:4] ,EMU[0] | GP7[15] Control" "Tri-stated,GP7[15],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EMU[0],?..."
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bitfld.long 0x00 0.--3. " PINMUX0[3:0] ,RTCK | GP7[14] Control" "RTCK,GP7[14],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,RTCK,?..."
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line.long 0x04 "PINMUX1,Multiplexing Control Register 1"
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|
bitfld.long 0x04 28.--31. " PINMUX1[31:28] ,EMB_A[5] | GP7[7] Control" "Tri-stated,EMB_A[5],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[7],?..."
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bitfld.long 0x04 24.--27. " PINMUX1[27:24] ,EMB_A[4] | GP7[6] Control" "Tri-stated,EMB_A[4],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[6],?..."
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|
textline " "
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bitfld.long 0x04 20.--23. " PINMUX1[23:20] ,EMB_A[3] | GP7[5] Control" "Tri-stated,EMB_A[3],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[5],?..."
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bitfld.long 0x04 16.--19. " PINMUX1[19:16] ,EMB_A[2] | GP7[4] Control" "Tri-stated,EMB_A[2],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[4],?..."
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|
textline " "
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bitfld.long 0x04 12.--15. " PINMUX1[15:12] ,EMB_A[1] | GP7[3] Control" "Tri-stated,EMB_A[1],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[3],?..."
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bitfld.long 0x04 8.--11. " PINMUX1[11:8] ,EMB_A[0] | GP7[2] Control" "Tri-stated,EMB_A[0],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[2],?..."
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textline " "
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bitfld.long 0x04 4.--7. " PINMUX1[7:4] ,EMB_BA[0] | GP7[1] Control" "Tri-stated,EMB_BA[0],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[1],?..."
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bitfld.long 0x04 0.--3. " PINMUX1[3:0] ,EMB_BA[1] | GP7[0] Control" "Tri-stated,EMB_BA[1],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[0],?..."
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line.long 0x08 "PINMUX2,Multiplexing Control Register 2"
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|
bitfld.long 0x08 28.--31. " PINMUX2[31:28] ,EMB_D[31] Control" "Tri-stated,EMB_D[31],?..."
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bitfld.long 0x08 24.--27. " PINMUX2[27:24] ,EMB_A[12] | GP3[13] Control" "Tri-stated,EMB_A[12],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP3[13],?..."
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|
textline " "
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bitfld.long 0x08 20.--23. " PINMUX2[23:20] ,EMB_A[11] | GP7[13] Control" "Tri-stated,EMB_A[11],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[13],?..."
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bitfld.long 0x08 16.--19. " PINMUX2[19:16] ,EMB_A[10] | GP7[12] Control" "Tri-stated,EMB_A[10],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[12],?..."
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|
textline " "
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bitfld.long 0x08 12.--15. " PINMUX2[15:12] ,EMB_A[9] | GP7[11] Control" "Tri-stated,EMB_A[9],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[11],?..."
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bitfld.long 0x08 8.--11. " PINMUX2[11:8] ,EMB_A[8] | GP7[10] Control" "Tri-stated,EMB_A[8],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[10],?..."
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|
textline " "
|
|
bitfld.long 0x08 4.--7. " PINMUX2[7:4] ,EMB_A[7] | GP7[9] Control" "Tri-stated,EMB_A[7],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[9],?..."
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bitfld.long 0x08 0.--3. " PINMUX2[3:0] ,EMB_A[6] | GP7[8] Control" "Tri-stated,EMB_A[6],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP7[8],?..."
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line.long 0x0c "PINMUX3,Multiplexing Control Register 3"
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|
bitfld.long 0x0C 28.--31. " PINMUX3[31:28] ,EMB_D[23] Control" "Tri-stated,EMB_D[23],?..."
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|
bitfld.long 0x0C 24.--27. " PINMUX3[27:24] ,EMB_D[24] Control" "Tri-stated,EMB_D[24],?..."
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|
textline " "
|
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bitfld.long 0x0C 20.--23. " PINMUX3[23:20] ,EMB_D[25] Control" "Tri-stated,EMB_D[25],?..."
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bitfld.long 0x0C 16.--19. " PINMUX3[19:16] ,EMB_D[26] Control" "Tri-stated,EMB_D[26],?..."
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textline " "
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bitfld.long 0x0C 12.--15. " PINMUX3[15:12] ,EMB_D[27] Control" "Tri-stated,EMB_D[27],?..."
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bitfld.long 0x0C 8.--11. " PINMUX3[11:8] ,EMB_D[28] Control" "Tri-stated,EMB_D[28],?..."
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textline " "
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bitfld.long 0x0C 4.--7. " PINMUX3[7:4] ,EMB_D[29] Control" "Tri-stated,EMB_D[29],?..."
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bitfld.long 0x0C 0.--3. " PINMUX3[3:0] ,EMB_D[30] Control" "Tri-stated,EMB_D[30],?..."
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line.long 0x10 "PINMUX4,Multiplexing Control Register 4"
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bitfld.long 0x10 28.--31. " PINMUX4[31:28] ,/EMB_WE_DQM[3] Control" "Tri-stated,/EMB_WE_DQM[3],?..."
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bitfld.long 0x10 24.--27. " PINMUX4[27:24] ,EMB_D[16] Control" "Tri-stated,EMB_D[16],?..."
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textline " "
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bitfld.long 0x10 20.--23. " PINMUX4[23:20] ,EMB_D[17] Control" "Tri-stated,EMB_D[17],?..."
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bitfld.long 0x10 16.--19. " PINMUX4[19:16] ,EMB_D[18] Control" "Tri-stated,EMB_D[18],?..."
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textline " "
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bitfld.long 0x10 12.--15. " PINMUX4[15:12] ,EMB_D[19] Control" "Tri-stated,EMB_D[19],?..."
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bitfld.long 0x10 8.--11. " PINMUX4[11:8] ,EMB_D[20] Control" "Tri-stated,EMB_D[20],?..."
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textline " "
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bitfld.long 0x10 4.--7. " PINMUX4[7:4] ,EMB_D[21] Control" "Tri-stated,EMB_D[21],?..."
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bitfld.long 0x10 0.--3. " PINMUX4[3:0] ,EMB_D[22] Control" "Tri-stated,EMB_D[22],?..."
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line.long 0x14 "PINMUX5,Multiplexing Control Register 5"
|
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bitfld.long 0x14 28.--31. " PINMUX5[31:28] ,EMB_D[6] | GP6[6] Control" "Tri-stated,EMB_D[6],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[6],?..."
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bitfld.long 0x14 24.--27. " PINMUX5[27:24] ,EMB_D[5] | GP6[5] Control" "Tri-stated,EMB_D[5],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[5],?..."
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textline " "
|
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bitfld.long 0x14 20.--23. " PINMUX5[23:20] ,EMB_D[4] | GP6[4] Control" "Tri-stated,EMB_D[4],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[4],?..."
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bitfld.long 0x14 16.--19. " PINMUX5[19:16] ,EMB_D[3] | GP6[3] Control" "Tri-stated,EMB_D[3],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[3],?..."
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|
textline " "
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bitfld.long 0x14 12.--15. " PINMUX5[15:12] ,EMB_D[2] | GP6[2] Control" "Tri-stated,EMB_D[2],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[2],?..."
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bitfld.long 0x14 8.--11. " PINMUX5[11:8] ,EMB_D[1] | GP6[1] Control" "Tri-stated,EMB_D[1],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[1],?..."
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|
textline " "
|
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bitfld.long 0x14 4.--7. " PINMUX5[7:4] ,EMB_D[0] | GP6[0] Control" "Tri-stated,EMB_D[0],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[0],?..."
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bitfld.long 0x14 0.--3. " PINMUX5[3:0] ,/EMB_WE_DQM[2] Control" "Tri-stated,/EMB_WE_DQM[2],?..."
|
|
line.long 0x18 "PINMUX6,Multiplexing Control Register 6"
|
|
bitfld.long 0x18 28.--31. " PINMUX6[31:28] ,EMB_D[14] | GP6[14] Control" "Tri-stated,EMB_D[14],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[14],?..."
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bitfld.long 0x18 24.--27. " PINMUX6[27:24] ,EMB_D[13] | GP6[13] Control" "Tri-stated,EMB_D[13],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[13],?..."
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|
textline " "
|
|
bitfld.long 0x18 20.--23. " PINMUX6[23:20] ,EMB_D[12] | GP6[12] Control" "Tri-stated,EMB_D[12],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[12],?..."
|
|
bitfld.long 0x18 16.--19. " PINMUX6[19:16] ,EMB_D[11] | GP6[11] Control" "Tri-stated,EMB_D[11],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[11],?..."
|
|
textline " "
|
|
bitfld.long 0x18 12.--15. " PINMUX6[15:12] ,EMB_D[10] | GP6[10] Control" "Tri-stated,EMB_D[10],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[10],?..."
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bitfld.long 0x18 8.--11. " PINMUX6[11:8] ,EMB_D[9] | GP6[9] Control" "Tri-stated,EMB_D[9],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[9],?..."
|
|
textline " "
|
|
bitfld.long 0x18 4.--7. " PINMUX6[7:4] ,EMB_D[8] | GP6[8] Control" "Tri-stated,EMB_D[8],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[8],?..."
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bitfld.long 0x18 0.--3. " PINMUX6[3:0] ,EMB_D[7] | GP6[7] Control" "Tri-stated,EMB_D[7],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[7],?..."
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line.long 0x1c "PINMUX7,Multiplexing Control Register 7"
|
|
bitfld.long 0x1C 28.--31. " PINMUX7[31:28] ,/SPI0_SCS[0] | /UART0_RTS | EQEP0B | GP5[4] | BOOT[4] Control" "Tri-stated,/SPI0_SCS[0],/UART0_RTS,Reserved,EQEP0B,Reserved,Reserved,Reserved,GP5[4],?..."
|
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bitfld.long 0x1C 24.--27. " PINMUX7[27:24] ,/SPI0_ENA | /UART0_CTS | EQEP0A | GP5[3] | BOOT[3] Control" "Tri-stated,/SPI0_ENA,/UART0_CTS,Reserved,EQEP0A,Reserved,Reserved,Reserved,GP5[3],?..."
|
|
textline " "
|
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bitfld.long 0x1C 20.--23. " PINMUX7[23:20] ,SPI0_CLK | EQEP1I | GP5[2] | BOOT[2] Control" "Tri-stated,SPI0_CLK,EQEP1I,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[2],?..."
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bitfld.long 0x1C 16.--19. " PINMUX7[19:16] ,SPIO_SOMI[0] | EQEP0S | GP5[1] Control" "Tri-stated,SPIO_SOMI[0],EQEP0S,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[1],?..."
|
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textline " "
|
|
bitfld.long 0x1C 12.--15. " PINMUX7[15:12] ,SPI0_SOMI[0] | EQEP0I | GP5[0] | BOOT[0] Control" "Tri-stated,SPI0_SOMI[0],EQEP0I,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[0],?..."
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bitfld.long 0x1C 8.--11. " PINMUX7[11:8] ,/EMB_WE_DQM[0] | GP5[15] Control" "Tri-stated,/EMB_WE_DQM[0],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[15],?..."
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " PINMUX7[7:4] ,/EMB_WE_DQM[1] | GP5[14] Control" "Tri-stated,/EMB_WE_DQM[1],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[14],?..."
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bitfld.long 0x1C 0.--3. " PINMUX7[3:0] ,EMB_D[15] | GP6[15] Control" "Tri-stated,EMB_D[15],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP6[15],?..."
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line.long 0x20 "PINMUX8,Multiplexing Control Register 8"
|
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bitfld.long 0x20 28.--31. " PINMUX8[31:28] ,/SPI1_ENA | UART2_RXD | GP5[12] Control" "Tri-stated,/SPI1_ENA,UART2_RXD,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[12],?..."
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bitfld.long 0x20 24.--27. " PINMUX8[27:24] ,AXR1[11] | GP5[11] Control" "Tri-stated,AXR1[11],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[11],?..."
|
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textline " "
|
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bitfld.long 0x20 20.--23. " PINMUX8[23:20] ,AXR1[10] | GP5[10] Control" "Tri-stated,AXR1[10],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[10],?..."
|
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bitfld.long 0x20 16.--19. " PINMUX8[19:16] ,UART0_TXD | I2C0_SCL | TM64P0_OUT12 | GP5[9] Control" "Tri-stated,UART0_TXD,I2C0_SCL,Reserved,TM64P0_OUT12,Reserved,Reserved,Reserved,GP5[9],?..."
|
|
textline " "
|
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bitfld.long 0x20 12.--15. " PINMUX8[15:12] ,UART0_RXD | I2C0_SDA | TM64P0_IN12 | GP5[8] | BOOT[8] Control" "Tri-stated,UART0_RXD,I2C0_SDA,Reserved,TM64P0_IN12,Reserved,Reserved,Reserved,GP5[8],?..."
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bitfld.long 0x20 8.--11. " PINMUX8[11:8] ,SPI1_CLK | EQEP1S | GP5[7] | BOOT[7] Control" "Tri-stated,SPI1_CLK,EQEP1S,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[7],?..."
|
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textline " "
|
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bitfld.long 0x20 4.--7. " PINMUX8[7:4] ,SPI1_SIMO[0] | I2C1_SDA | GP5[6] | BOOT[6] Control" "Tri-stated,SPI1_SIMO[0],I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[6],?..."
|
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bitfld.long 0x20 0.--3. " PINMUX8[3:0] ,SPI1_SOMI[0] | I2C1_SCL | GP5[5] | BOOT[5] Control" "Tri-stated,SPI1_SOMI[0],I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[5],?..."
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line.long 0x24 "PINMUX9,Multiplexing Control Register 9"
|
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bitfld.long 0x24 28.--31. " PINMUX9[31:28] ,AFSR0 | GP3[12] Control" "Tri-stated,AFSR0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP3[12],?..."
|
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bitfld.long 0x24 24.--27. " PINMUX9[27:24] ,ACLKR0 | ECAP1 | APWM1 | GP2[15] Control" "Tri-stated,ACLKR0,ECAP1 | APWM1,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[15],?..."
|
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textline " "
|
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bitfld.long 0x24 20.--23. " PINMUX9[23:20] ,AHCLKR0 | RMII_MHZ_50_CLK | GP2[14] | BOOT[11] Control" "Tri-stated,AHCLKR0,RMII_MHZ_50_CLK,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[14],?..."
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bitfld.long 0x24 16.--19. " PINMUX9[19:16] ,AFSX0 | GP2[13] Control" "Tri-stated,AFSX0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[13],?..."
|
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textline " "
|
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bitfld.long 0x24 12.--15. " PINMUX9[15:12] ,ACLKX0 | ECAP0 | APWM0 | GP2[12] Control" "Tri-stated,ACLKX0,ECAP0 | APWM0,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[12],?..."
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bitfld.long 0x24 8.--11. " PINMUX9[11:8] ,AHCLKX0 | AHCLKX2 | USB_REFCLKIN | GP2[11] Control" "Tri-stated,AHCLKX0,AHCLKX2,Reserved,USB_REFCLKIN,Reserved,Reserved,Reserved,GP2[11],?..."
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|
textline " "
|
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bitfld.long 0x24 4.--7. " PINMUX9[7:4] ,USB0_DRVVBUS | GP4[15] Control" "Tri-stated,USB0_DRVVBUS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[15],?..."
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bitfld.long 0x24 0.--3. " PINMUX9[3:0] ,SPI1_SCS[0] | UART2_TXD | GP5[13] Control" "Tri-stated,/SPI1_SCS[0],UART2_TXD,Reserved,Reserved,Reserved,Reserved,Reserved,GP5[13],?..."
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line.long 0x28 "PINMUX10,Multiplexing Control Register 10"
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bitfld.long 0x28 28.--31. " PINMUX10[31:28] ,AXR0[6] | RMII_RXER[0] | ACLKR2 | GP3[6] Control" "Tri-stated,AXR0[6],RMII_RXER,Reserved,ACLKR2,Reserved,Reserved,Reserved,GP3[6],?..."
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bitfld.long 0x28 24.--27. " PINMUX10[27:24] ,AXR0[5] | RMII_RXD[1] | AFSX2 | GP3[5] Control" "Tri-stated,AXR0[5],RMII_RXD[1],Reserved,AFSX2,Reserved,Reserved,Reserved,GP3[5],?..."
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textline " "
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bitfld.long 0x28 20.--23. " PINMUX10[23:20] ,AXR0[4] | RMII_RXD[0] | AXR2[1] | GP3[4] Control" "Tri-stated,AXR0[4],RMII_RXD[0],Reserved,AXR2[1],Reserved,Reserved,Reserved,GP3[4],?..."
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bitfld.long 0x28 16.--19. " PINMUX10[19:16] ,AXR0[3] | RMII_CRS_DV | AXR2[2] | GP3[3] Control" "Tri-stated,AXR0[3],RMII_CRS_DV,Reserved,AXR2[2],Reserved,Reserved,Reserved,GP3[3],?..."
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textline " "
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bitfld.long 0x28 12.--15. " PINMUX10[15:12] ,AXR0[2] | RMII_TXEN | AXR2[3] | GP3[2] Control" "Tri-stated,AXR0[2],RMII_TXEN,Reserved,AXR2[3],Reserved,Reserved,Reserved,GP3[2],?..."
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bitfld.long 0x28 8.--11. " PINMUX10[11:8] ,AXR0[1] | RMII_TXD[1] | ACLKX2 | GP3[1] Control" "Tri-stated,AXR0[1],RMII_TXD[1],Reserved,ACLKX2,Reserved,Reserved,Reserved,GP3[1],?..."
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textline " "
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bitfld.long 0x28 4.--7. " PINMUX10[7:4] ,AXR0[0] | RMII_TXD[0] | AFSR2 | GP3[0] Control" "Tri-stated,AXR0[0],RMII_TXD[0],Reserved,AFSR2,Reserved,Reserved,Reserved,GP3[0],?..."
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bitfld.long 0x28 0.--3. " PINMUX10[3:0] ,AMUTE0 | /RESETOUT" "/RESETOUT,AMUTE0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,/RESETOUT,?..."
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line.long 0x2c "PINMUX11,Multiplexing Control Register 11"
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bitfld.long 0x2C 28.--31. " PINMUX11[31:28] ,AFSX1 | EPWMSYNCI | EPWMSYNC0 | GP4[10] Control" "Tri-stated,AFSX1,EPWMSYNCI,Reserved,EPWMSYNC0,Reserved,Reserved,Reserved,GP4[10],?..."
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bitfld.long 0x2C 24.--27. " PINMUX11[27:24] ,ACLKX1 | EPWM0A | GP3[15] Control" "Tri-stated,ACLKX1,EPWM0A,Reserved,Reserved,Reserved,Reserved,Reserved,GP3[15],?..."
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textline " "
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bitfld.long 0x2C 20.--23. " PINMUX11[23:20] ,AHCLKX1 | EPWM0B | GP3[14] Control" "Tri-stated,AHCLKX1,EPWM0B,Reserved,Reserved,Reserved,Reserved,Reserved,GP3[14],?..."
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bitfld.long 0x2C 16.--19. " PINMUX11[19:16] ,AXR0[11] | AXR2[0] | GP3[11] Control" "Tri-stated,AXR0[11],Reserved,Reserved,AXR2[0],Reserved,Reserved,Reserved,GP3[11],?..."
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textline " "
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bitfld.long 0x2C 12.--15. " PINMUX11[15:12] ,UART1_TXD | AXR0[10] | GP3[10] Control" "Tri-stated,UART1_TXD,AXR0[10],Reserved,Reserved,Reserved,Reserved,Reserved,GP3[10],?..."
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bitfld.long 0x2C 8.--11. " PINMUX11[11:8] ,UART1_RXD | AXR0[9] | GP3[9] Control" "Tri-stated,UART1_RXD,AXR0[9],Reserved,Reserved,Reserved,Reserved,Reserved,GP3[9],?..."
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textline " "
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bitfld.long 0x2C 4.--7. " PINMUX11[7:4] ,AXR0[8] | MDIO_D | GP3[8] Control" "Tri-stated,AXR0[8],MDIO_D,Reserved,Reserved,Reserved,Reserved,Reserved,GP3[8],?..."
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bitfld.long 0x2C 0.--3. " PINMUX11[3:0] ,AXR0[7] | MDIO_CLK | GP3[7] Control" "Tri-stated,AXR0[7],MDIO_CLK,Reserved,Reserved,Reserved,Reserved,Reserved,GP3[7],?..."
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line.long 0x30 "PINMUX12,Multiplexing Control Register 12"
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bitfld.long 0x30 28.--31. " PINMUX12[31:28] ,AXR1[3] | EQEP1A | GP4[3] Control" "Tri-stated,AXR1[3],EQEP1A,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[3],?..."
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bitfld.long 0x30 24.--27. " PINMUX12[27:24] ,AXR1[2] | GP4[2] Control" "Tri-stated,AXR1[2],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[2],?..."
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textline " "
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bitfld.long 0x30 20.--23. " PINMUX12[23:20] ,AXR1[1] | GP4[1] Control" "Tri-stated,AXR1[1],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[1],?..."
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bitfld.long 0x30 16.--19. " PINMUX12[19:16] ,AXR1[0] | GP4[0] Control" "Tri-stated,AXR1[0],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[0],?..."
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textline " "
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bitfld.long 0x30 12.--15. " PINMUX12[15:12] ,AMUTE1 | EHRPWMTZ | GP4[14] Control" "Tri-stated,AMUTE1,EHRPWMTZ,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[14],?..."
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bitfld.long 0x30 8.--11. " PINMUX12[11:8] ,AFSR1 | GP4[13] Control" "Tri-stated,AFSR1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[13],?..."
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textline " "
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bitfld.long 0x30 4.--7. " PINMUX12[7:4] ,ACLKR1 | ECAP2 | APWM2 | GP4[12] Control" "Tri-stated,ACLKR1,ECAP2 / APWM2,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[12],?..."
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bitfld.long 0x30 0.--3. " PINMUX12[3:0] ,AHCLKR1 | GP4[11] Control" "Tri-stated,AHCLKR1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[11],?..."
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line.long 0x34 "PINMUX13,Multiplexing Control Register 13"
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bitfld.long 0x34 28.--31. " PINMUX13[31:28] ,EMA_D[1] | MMCSD_DAT[1] | UHPI_HD[1] | GP0[1] Control" "Tri-stated,EMA_D[1],MMCSD_DAT[1],Reserved,UHPI_HD[1],Reserved,Reserved,Reserved,GP0[1],?..."
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bitfld.long 0x34 24.--27. " PINMUX13[27:24] ,EMA_D[0] | MMCSD_DAT[0] | UHPI_HD[0] | GP0[0] | BOOT[12] Control" "Tri-stated,EMA_D[0],MMCSD_DAT[0],Reserved,UHPI_HD[0],Reserved,Reserved,Reserved,GP0[0],?..."
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textline " "
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bitfld.long 0x34 20.--23. " PINMUX13[23:20] ,AXR1[9] | GP4[9] Control" "Tri-stated,AXR1[9],Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[9],?..."
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bitfld.long 0x34 16.--19. " PINMUX13[19:16] ,AXR1[8] | EPWM1A | GP4[8] Control" "Tri-stated,AXR1[8],Reserved,Reserved,EPWM1A,Reserved,Reserved,Reserved,GP4[8],?..."
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textline " "
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bitfld.long 0x34 12.--15. " PINMUX13[15:12] ,AXR1[7] | EPWM1B | GP4[7] Control" "Tri-stated,AXR1[7],EPWM1B,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[7],?..."
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bitfld.long 0x34 8.--11. " PINMUX13[11:8] ,AXR1[6] | EPWM2A | GP4[6] Control" "Tri-stated,AXR1[6],EPWM2A,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[6],?..."
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textline " "
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bitfld.long 0x34 4.--7. " PINMUX13[7:4] ,AXR1[5] | EPWM2B | GP4[5] Control" "Tri-stated,AXR1[5],EPWM2B,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[5],?..."
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bitfld.long 0x34 0.--3. " PINMUX13[3:0] ,AXR1[4] | EQEP1B | GP4[4] Control" "Tri-stated,AXR1[4],EQEP1B,Reserved,Reserved,Reserved,Reserved,Reserved,GP4[4],?..."
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line.long 0x38 "PINMUX14,Multiplexing Control Register 14"
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bitfld.long 0x38 28.--31. " PINMUX14[31:28] ,EMA_D[9] | UHPI_HD[9] | LCD_D[9] | GP0[9] Control" "Tri-stated,EMA_D[9],UHPI_HD[9],Reserved,LCD_D[9],Reserved,Reserved,Reserved,GP0[9],?..."
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bitfld.long 0x38 24.--27. " PINMUX14[27:24] ,EMA_D[8] | UHPI_HD[8] | LCD_D[8] | GP0[8] Control" "Tri-stated,EMA_D[8],UHPI_HD[8],Reserved,LCD_D[8],Reserved,Reserved,Reserved,GP0[8],?..."
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textline " "
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bitfld.long 0x38 20.--23. " PINMUX14[23:20] ,EMA_D[7] | MMCSD_DAT[7] | UHPI_HD[7] | GP0[7] | BOOT[13] Control" "Tri-stated,EMA_D[7],MMCSD_DAT[7],Reserved,UHPI_HD[7],Reserved,Reserved,Reserved,GP0[7],?..."
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bitfld.long 0x38 16.--19. " PINMUX14[19:16] ,EMA_D[6] | MMCSD_DAT[6] | UHPI_HD[6] | GP0[6] Control" "Tri-stated,EMA_D[6],MMCSD_DAT[6],Reserved,UHPI_HD[6],Reserved,Reserved,Reserved,GP0[6],?..."
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textline " "
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bitfld.long 0x38 12.--15. " PINMUX14[15:12] ,EMA_D[5] | MMCSD_DAT[5] | UHPI_HD[5] | GP0[5] Control" "Tri-stated,EMA_D[5],MMCSD_DAT[5],Reserved,UHPI_HD[5],Reserved,Reserved,Reserved,GP0[5],?..."
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bitfld.long 0x38 8.--11. " PINMUX14[11:8] ,EMA_D[4] | MMCSD_DAT[4] | UHPI_HD[4] | GP0[4] Control" "Tri-stated,EMA_D[4],MMCSD_DAT[4],Reserved,UHPI_HD[4],Reserved,Reserved,Reserved,GP0[4],?..."
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textline " "
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bitfld.long 0x38 4.--7. " PINMUX14[7:4] ,EMA_D[3] | MMCSD_DAT[3] | UHPI_HD[3] | GP0[3] Control" "Tri-stated,EMA_D[3],MMCSD_DAT[3],Reserved,UHPI_HD[3],Reserved,Reserved,Reserved,GP0[3],?..."
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bitfld.long 0x38 0.--3. " PINMUX14[3:0] ,EMA_D[2] | MMCSD_DAT[2] | UHPI_HD[2] | GP0[2] Control" "Tri-stated,EMA_D[2],MMCSD_DAT[2],Reserved,UHPI_HD[2],Reserved,Reserved,Reserved,GP0[2],?..."
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line.long 0x3c "PINMUX15,Multiplexing Control Register 15"
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bitfld.long 0x3C 28.--31. " PINMUX15[31:28] ,EMA_A[1] | MMCSD_CLK | UHPI_HCNTL0 | GP1[1] Control" "Tri-stated,EMA_A[1],MMCSD_CLK,Reserved,UHPI_HCNTL0,Reserved,Reserved,Reserved,GP1[1],?..."
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bitfld.long 0x3C 24.--27. " PINMUX15[27:24] ,EMA_A[0] | LCD_D[7] | GP1[0] Control" "Tri-stated,EMA_A[0],LCD_D[7],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[0],?..."
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textline " "
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bitfld.long 0x3C 20.--23. " PINMUX15[23:20] ,EMA_D[15] | UHPI_HD[15] | LCD_D[15] | GP0[15] Control" "Tri-stated,EMA_D[15],UHPI_HD[15],Reserved,LCD_D[15],Reserved,Reserved,Reserved,GP0[15],?..."
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bitfld.long 0x3C 16.--19. " PINMUX15[19:16] ,EMA_D[14] | UHPI_HD[14] | LCD_D[14] | GP0[14] Control" "Tri-stated,EMA_D[14],UHPI_HD[14],Reserved,LCD_D[14],Reserved,Reserved,Reserved,GP0[14],?..."
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textline " "
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bitfld.long 0x3C 12.--15. " PINMUX15[15:12] ,EMA_D[13] | UHPI_HD[13] | LCD_D[13] | GP0[13] Control" "Tri-stated,EMA_D[13],UHPI_HD[13],Reserved,LCD_D[13],Reserved,Reserved,Reserved,GP0[13],?..."
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bitfld.long 0x3C 8.--11. " PINMUX15[11:8] ,EMA_D[12] | UHPI_HD[12] | LCD_D[12] | GP0[12] Control" "Tri-stated,EMA_D[12],UHPI_HD[12],Reserved,LCD_D[12],Reserved,Reserved,Reserved,GP0[12],?..."
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textline " "
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bitfld.long 0x3C 4.--7. " PINMUX15[7:4] ,EMA_D[11] | UHPI_HD[11] | LCD_D[11] | GP0[11] Control" "Tri-stated,EMA_D[11],UHPI_HD[11],Reserved,LCD_D[11],Reserved,Reserved,Reserved,GP0[11],?..."
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bitfld.long 0x3C 0.--3. " PINMUX15[3:0] ,EMA_D[10] | UHPI_HD[10] | LCD_D[10] | GP0[10] Control" "Tri-stated,EMA_D[10],UHPI_HD[10],Reserved,LCD_D[10],Reserved,Reserved,Reserved,GP0[10],?..."
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line.long 0x40 "PINMUX16,Multiplexing Control Register 16"
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bitfld.long 0x40 28.--31. " PINMUX16[31:28] ,EMA_A[9] | LCD_HSYNC | GP1[9] Control" "Tri-stated,EMA_A[9],LCD_HSYNC,Reserved,Reserved,Reserved,Reserved,Reserved,GP1[9],?..."
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bitfld.long 0x40 24.--27. " PINMUX16[27:24] ,EMA_A[8] | LCD_PCLK | GP1[8] Control" "Tri-stated,EMA_A[8],LCD_PCLK,Reserved,Reserved,Reserved,Reserved,Reserved,GP1[8],?..."
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textline " "
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bitfld.long 0x40 20.--23. " PINMUX16[23:20] ,EMA_A[7] | LCD_D[0] | GP1[7] Control" "Tri-stated,EMA_A[7],LCD_D[0],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[7],?..."
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bitfld.long 0x40 16.--19. " PINMUX16[19:16] ,EMA_A[6] | LCD_D[1] | GP1[6] Control" "Tri-stated,EMA_A[6],LCD_D[1],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[6],?..."
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textline " "
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bitfld.long 0x40 12.--15. " PINMUX16[15:12] ,EMA_A[5] | LCD_D[2] | GP1[5] Control" "Tri-stated,EMA_A[5],LCD_D[2],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[5],?..."
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bitfld.long 0x40 8.--11. " PINMUX16[11:8] ,EMA_A[4] | LCD_D[3] | GP1[4] Control" "Tri-stated,EMA_A[4],LCD_D[3],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[4],?..."
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textline " "
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bitfld.long 0x40 4.--7. " PINMUX16[7:4] ,EMA_A[3] | LCD_D[6] | GP1[3] Control" "Tri-stated,EMA_A[3],LCD_D[6],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[3],?..."
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bitfld.long 0x40 0.--3. " PINMUX16[3:0] ,EMA_A[2] | MMCSD_CMD | UHPI_HCNTL1 | GP1[2] Control" "Tri-stated,EMA_A[2],MMCSD_CMD,Reserved,UHPI_HCNTL1,Reserved,Reserved,Reserved,GP1[2],?..."
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line.long 0x44 "PINMUX17,Multiplexing Control Register 17"
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bitfld.long 0x44 28.--31. " PINMUX17[31:28] ,/EMA_CAS | /EMA_CS[4] | GP2[1] Control" "Tri-stated,/EMA_CAS,/EMA_CS[4],Reserved,Reserved,Reserved,Reserved,Reserved,GP2[1],?..."
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bitfld.long 0x44 24.--27. " PINMUX17[27:24] ,EMA_SDCKE | GP2[0] Control" "Tri-stated,EMA_SDCKE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[0],?..."
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textline " "
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bitfld.long 0x44 20.--23. " PINMUX17[23:20] ,EMA_CLK | OBSCLK | AHCLKR2 | GP1[15] Control" "Tri-stated,EMA_CLK,OBSCLK,Reserved,AHCLKR2,Reserved,Reserved,Reserved,GP1[15],?..."
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bitfld.long 0x44 16.--19. " PINMUX17[19:16] ,EMA_BA[0] | LCD_D[4] | GP1[14] Control" "Tri-stated,EMA_BA[0],LCD_D[4],Reserved,Reserved,Reserved,Reserved,Reserved,GP1[14],?..."
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textline " "
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bitfld.long 0x44 12.--15. " PINMUX17[15:12] ,EMA_BA[1] | LCD_D[5] | UHPI_HHWIL | GP1[13] Control" "Tri-stated,EMA_BA[1],LCD_D[5],Reserved,UHPI_HHWIL,Reserved,Reserved,Reserved,GP1[13],?..."
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bitfld.long 0x44 8.--11. " PINMUX17[11:8] ,EMA_A[12] | LCD_MCLK | GP1[12] Control" "Tri-stated,EMA_A[12],LCD_MCLK,Reserved,Reserved,Reserved,Reserved,Reserved,GP1[12],?..."
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textline " "
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bitfld.long 0x44 4.--7. " PINMUX17[7:4] ,EMA_A[11] | /LCD_AC_ENB_CS | GP1[11] Control" "Tri-stated,EMA_A[11],/LCD_AC_ENB_CS,Reserved,Reserved,Reserved,Reserved,Reserved,GP1[11],?..."
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bitfld.long 0x44 0.--3. " PINMUX17[3:0] ,EMA_A[10] | LCD_VSYNC | GP1[10] Control" "Tri-stated,EMA_A[10],LCD_VSYNC,Reserved,Reserved,Reserved,Reserved,Reserved,GP1[10],?..."
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line.long 0x48 "PINMUX18,Multiplexing Control Register 18"
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bitfld.long 0x48 28.--31. " PINMUX18[31:28] ,/EMA_WE_DQM[0] | /UHPI_HINT | AXR0[15] | GP2[9] Control" "Tri-stated,/EMA_WE_DQM[0],/UHPI_HINT,Reserved,AXR0[15],Reserved,Reserved,Reserved,GP2[9],?..."
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bitfld.long 0x48 24.--27. " PINMUX18[27:24] ,/EMA_WE_DQM[1] | /UHPI_HDS2 | AXR0[14] | GP2[8] Control" "Tri-stated,/EMA_WE_DQM[1],/UHPI_HDS2,Reserved,AXR0[14],Reserved,Reserved,Reserved,GP2[8],?..."
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textline " "
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bitfld.long 0x48 20.--23. " PINMUX18[23:20] ,/EMA_OE | /UHPI_HDS1 | AXR0[13] | GP2[7] Control" "Tri-stated,/EMA_OE,/UHPI_HDS1,Reserved,AXR0[13],Reserved,Reserved,Reserved,GP2[7],?..."
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bitfld.long 0x48 16.--19. " PINMUX18[19:16] ,/EMA_CS[3] | AMUTE2 | GP2[6]" "Tri-stated,/EMA_CS[3],Reserved,Reserved,AMUTE2,Reserved,Reserved,Reserved,GP2[6],?..."
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textline " "
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bitfld.long 0x48 12.--15. " PINMUX18[15:12] ,/EMA_CS[2] | /UHPI_HCS | GP2[5] | BOOT[15] Control" "Tri-stated,/EMA_CS[2],/UHPI_HCS,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[5],?..."
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bitfld.long 0x48 8.--11. " PINMUX18[11:8] ,/EMA_CS[0] | /UHPI_HAS | GP2[4] Control" "Tri-stated,/EMA_CS[0],/UHPI_HAS,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[4],?..."
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textline " "
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bitfld.long 0x48 4.--7. " PINMUX18[7:4] ,/EMA_WE | UHPI_HR/W | AXR0[12] | GP2[3] | BOOT[14] Control" "Tri-stated,/EMA_WE,UHPI_HR/W,Reserved,AXR0[12],Reserved,Reserved,Reserved,GP2[3],?..."
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bitfld.long 0x48 0.--3. " PINMUX18[3:0] ,/EMA_RAS | /EMA_CS[5] | GP2[2] Control" "Tri-stated,/EMA_RAS,/EMA_CS[5],Reserved,Reserved,Reserved,Reserved,Reserved,GP2[2],?..."
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line.long 0x4c "PINMUX19,Multiplexing Control Register 19"
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bitfld.long 0x4c 0.--3. " PINMUX19[3:0] ,EMA_WAIT[0] | /UHPI_HRDY | GP2[10] Control" "Tri-stated,EMA_WAIT[0],/UHPI_HRDY,Reserved,Reserved,Reserved,Reserved,Reserved,GP2[10],?..."
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width 9.
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group.long 0x110++0x0b "Bus Master Priority Configuration"
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line.long 0x00 "MSTPRI0,Master Priority 0 Register"
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sif (CPU()!="AM1707")
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bitfld.long 0x00 12.--14. " DSP_CFG ,Bus Priority for Bus Master DSP" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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bitfld.long 0x00 8.--10. " DSP_MDMA ,Bus Priority for Bus Master DSP" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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textline " "
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endif
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bitfld.long 0x00 4.--6. " ARM_D ,Bus Priority for Bus Master ARM" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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bitfld.long 0x00 0.--2. " ARM_I ,Bus Priority for Bus Master ARM" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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line.long 0x04 "MSTPRI1,Master Priority 1 Register"
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bitfld.long 0x04 12.--14. " TC1 ,Bus Priority for Bus Master EDMA3 TC1" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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bitfld.long 0x04 8.--10. " TC0 ,Bus Priority for Bus Master EDMA3 TC0" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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textline " "
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bitfld.long 0x04 4.--6. " PRU1 ,Bus Priority for Bus Master PRU1" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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bitfld.long 0x04 0.--2. " PRU0 ,Bus Priority for Bus Master PRU0" "0(Highest),1,2,3,4,5,6,7(Lowest)"
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line.long 0x08 "MSTPRI2,Master Priority 2 Register"
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bitfld.long 0x08 28.--30. " LCDC ,Bus Priority for Bus Master LCDC" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
bitfld.long 0x08 24.--26. " USB1 ,Bus Priority for Bus Master USB1" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
bitfld.long 0x08 20.--22. " UHPI ,Bus Priority for Bus Master UHPI" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " USB0 ,Bus Priority for Bus Master USB0" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
bitfld.long 0x08 8.--10. " USB0 ,Bus Priority for Bus Master USB0" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
bitfld.long 0x08 0.--2. " EMAC ,Bus Priority for Bus Master EMAC" "0(Highest),1,2,3,4,5,6,7(Lowest)"
|
|
group.long 0x17c++0x13 "Chip Configuration Registers"
|
|
line.long 0x00 "CFGCHIP0,Chip Configuration 0 Register"
|
|
bitfld.long 0x00 4. " PLL_MASTER_LOCK ,Lock the PLL MMRs" "Not locked,Locked"
|
|
bitfld.long 0x00 2.--3. " TC1DBS ,EDMA3 TC1 Default Burst Size" "16 byte,32 byte,64 byte,?..."
|
|
bitfld.long 0x00 0.--1. " TC0DBS ,EDMA3 TC1 Default Burst Size" "16 byte,32 byte,64 byte,?..."
|
|
line.long 0x04 "CFGCHIP1,Chip Configuration 1 Register"
|
|
bitfld.long 0x04 27.--31. " CAP2SRC ,eCAP2 Module Event Input Select" "eCAP2 Pin Input,McASP0 TX DMA Event,McASP0 RX DMA Event,McASP1 TX DMA Event,McASP1 RX DMA Event,McASP2 TX DMA Event,McASP2 RX DMA Event,EMAC C0 RX Threshold Pulse Interrupt,EMAC C0 RX Pulse Interrupt,EMAC C0 TX Pulse Interrupt,EMAC C0 Misc Interrupt,EMAC C1 RX Threshold Pulse Interrupt,EMAC C1 RX Pulse Interrupt,EMAC C1 TX Pulse Interrupt,EMAC C1 Misc Interrupt,EMAC C2 RX Threshold Pulse Interrupt,EMAC C2 RX Pulse Interrupt,EMAC C2 TX Pulse Interrupt,EMAC C2 Misc Interrupt,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--26. " CAP1SRC ,eCAP1 Module Event Input Select" "eCAP1 Pin Input,McASP0 TX DMA Event,McASP0 RX DMA Event,McASP1 TX DMA Event,McASP1 RX DMA Event,McASP2 TX DMA Event,McASP2 RX DMA Event,EMAC C0 RX Threshold Pulse Interrupt,EMAC C0 RX Pulse Interrupt,EMAC C0 TX Pulse Interrupt,EMAC C0 Misc Interrupt,EMAC C1 RX Threshold Pulse Interrupt,EMAC C1 RX Pulse Interrupt,EMAC C1 TX Pulse Interrupt,EMAC C1 Misc Interrupt,EMAC C2 RX Threshold Pulse Interrupt,EMAC C2 RX Pulse Interrupt,EMAC C2 TX Pulse Interrupt,EMAC C2 Misc Interrupt,?..."
|
|
textline " "
|
|
bitfld.long 0x04 17.--21. " CAP0SRC ,eCAP0 Module Event Input Select" "eCAP0 Pin Input,McASP0 TX DMA Event,McASP0 RX DMA Event,McASP1 TX DMA Event,McASP1 RX DMA Event,McASP2 TX DMA Event,McASP2 RX DMA Event,EMAC C0 RX Threshold Pulse Interrupt,EMAC C0 RX Pulse Interrupt,EMAC C0 TX Pulse Interrupt,EMAC C0 Misc Interrupt,EMAC C1 RX Threshold Pulse Interrupt,EMAC C1 RX Pulse Interrupt,EMAC C1 TX Pulse Interrupt,EMAC C1 Misc Interrupt,EMAC C2 RX Threshold Pulse Interrupt,EMAC C2 RX Pulse Interrupt,EMAC C2 TX Pulse Interrupt,EMAC C2 Misc Interrupt,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16. " HPIBYTEAD ,HPI Module Byte / Word Address Mode" "Word,Byte"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HPIENA ,HPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " TBCLKSYNC ,eHRPWM Module Time Base Clock Sync" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " AMUTESEL2 ,Source of the McASP2 AMUTEIN signal" "Drive McASP2 AMUTEIN Low,GPIO 0,GPIO 1,GPIO 2,GPIO 3,GPIO 4,GPIO 5,GPIO 6,GPIO 7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AMUTESEL1 ,Source of the McASP1 AMUTEIN signal" "Drive McASP1 AMUTEIN Low,GPIO 0,GPIO 1,GPIO 2,GPIO 3,GPIO 4,GPIO 5,GPIO 6,GPIO 7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AMUTESEL0 ,Source of the McASP0 AMUTEIN signal" "Drive McASP0 AMUTEIN Low,GPIO 0,GPIO 1,GPIO 2,GPIO 3,GPIO 4,GPIO 5,GPIO 6,GPIO 7,?..."
|
|
line.long 0x08 "CFGCHIP2,Chip Configuration 2 Register"
|
|
bitfld.long 0x08 17. " USB0PHYCLKGD ,USB 0 PHY Clock Good" "Not good,Good"
|
|
textline " "
|
|
bitfld.long 0x08 16. " USB0VBUSSENSE ,Status of VBUS detection" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x08 15. " RESET ,USB2.0 PHY reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 13.--14. " USB0OTGMODE ,USB0 OTG MODE" "Not overridden,Overridden to force USB Host Operation ,Overridden to force USB Device Operation,Overridden to force USB Host Operation with VBUS low"
|
|
textline " "
|
|
bitfld.long 0x08 12. " USB1PHYCLKMUX ,USB1 PHY Clock Source" "48 MHz output of the USB0 PHY,External pin"
|
|
textline " "
|
|
bitfld.long 0x08 11. " USB0PHYCLKMUX ,USB0 PHY Clock Source" "Comes from pin,Internally generated"
|
|
textline " "
|
|
bitfld.long 0x08 10. " USB0PHYPWDN ,Phy Powerdown" "Poweraed up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 9. " USB0OTGPWRDN ,OTG Analog Module Powerdown" "Poweraed up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x08 8. " USB0DATPOL ,USB0 Data Polarity" "Reversed,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 7. " USB1SUSPENDM ,USB1 Phy Suspend" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x08 6. " USB0PHY_PLLON ,Allowing or preventing it from stopping the 48 MHz clock during USB SUSPEND" "Allowed,Prevented"
|
|
textline " "
|
|
bitfld.long 0x08 5. " USB0SESNDEN ,USB2.0 Session End comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " USB0VBDTCTEN ,USB2.0 VBUS line comparators enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " USB0REF-FREQ ,USB0 Phy Clock Input Select" "Reserved,12 MHz,24 MHz,48 MHz,19.2 MHz,38.4 MHz,13 MHz,26 MHz,20 MHz,40 MHz,?..."
|
|
line.long 0x0c "CFGCHIP3,Chip Configuration 3 Register"
|
|
bitfld.long 0x0C 2. " DIV4P5ENA ,Fixed 4.5 divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " EMA_CLKSRC ,EMIF A Memory Clock Source Select" "PLLCTRL SYSCLK3 output,Fixed / 4.5 PLL output"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " EMB_CLKSRC ,EMIF B Memory Clock Source Select" "PLLCTRL SYSCLK5 output,Fixed / 4.5 PLL output"
|
|
line.long 0x10 "CFGCHIP4,Chip Configuration 4 Register"
|
|
bitfld.long 0x10 2. " AMUTECLR2 ,Clears the 'latched' GPIO interrupt for AMUTEIN of McASP2" "No effect,Cleared"
|
|
bitfld.long 0x10 1. " AMUTECLR1 ,Clears the 'latched' GPIO interrupt for AMUTEIN of McASP1" "No effect,Cleared"
|
|
bitfld.long 0x10 0. " AMUTECLR0 ,Clears the 'latched' GPIO interrupt for AMUTEIN of McASP0" "No effect,Cleared"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "SUSPSRC,Suspend Source Register"
|
|
sif (cpu()=="AM1707")
|
|
bitfld.long 0x00 28. " TIMER64P1 ,TIMER64P1 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 27. " TIMER64P0 ,TIMER64P0 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 25. " ePWM2SRC ,ePWM2 Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ePWM1SRC ,ePWM1 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 23. " ePWM0SRC ,ePWM0SRC ePWM0 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 22. " SPI1SRC ,SPI1 Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI0SRC ,SPI0 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 20. " UART2SRC ,UART2 SRC Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 19. " UART1SRC ,UART1 Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 18. " UART0SRC ,UART0 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 17. " I2C1SRC ,I2C1 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 16. " I2C0SRC ,I2C0 Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HPISRC ,HPI Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 9. " USB0SRC ,USB0 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 6. " PRUSRC ,PRU Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMACSRC ,EMAC Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 4. " eQEP1SRC ,eQEP1 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 3. " eQEP0SRC ,eQEP0 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 2. " eCAP2SRC ,eCAP2 Suspend Source" "ARM,No emulation suspend"
|
|
textline " "
|
|
bitfld.long 0x00 1. " eCAP1SRC ,eCAP1 Suspend Source" "ARM,No emulation suspend"
|
|
bitfld.long 0x00 0. " eCAP0SRC ,eCAP0 Suspend Source" "ARM,No emulation suspend"
|
|
else
|
|
bitfld.long 0x00 28. " TIMER64P1 ,TIMER64P1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 27. " TIMER64P0 ,TIMER64P0 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 25. " ePWM2SRC ,ePWM2 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 24. " ePWM1SRC ,ePWM1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 23. " ePWM0SRC ,ePWM0SRC ePWM0 Suspend Source" "ARM,DSP"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPI1SRC ,SPI1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 21. " SPI0SRC ,SPI0 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 20. " UART2SRC ,UART2 SRC Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 19. " UART1SRC ,UART1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 18. " UART0SRC ,UART0 Suspend Source" "ARM,DSP"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I2C1SRC ,I2C1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 16. " I2C0SRC ,I2C0 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 12. " HPISRC ,HPI Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 9. " USB0SRC ,USB0 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 5. " EMACSRC ,EMAC Suspend Source" "ARM,DSP"
|
|
textline " "
|
|
bitfld.long 0x00 4. " eQEP1SRC ,eQEP1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 3. " eQEP0SRC ,eQEP0 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 2. " eCAP2SRC ,eCAP2 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 1. " eCAP1SRC ,eCAP1 Suspend Source" "ARM,DSP"
|
|
bitfld.long 0x00 0. " eCAP0SRC ,eCAP0 Suspend Source" "ARM,DSP"
|
|
endif
|
|
width 13.
|
|
wgroup.long 0x174++0x07
|
|
line.long 0x00 "CHIPSIG,Chip Signal Register"
|
|
sif (cpu()!="AM1707")
|
|
bitfld.long 0x00 4. " CHIPSIG[4] ,Asserts DSP NMI Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " CHIPSIG[3] ,Asserts SYSCFG_CHIPINT3 interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 3. " CHIPSIG[3] ,Asserts SYSCFG_CHIPINT3 interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHIPSIG[2] ,Asserts SYSCFG_CHIPINT2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " CHIPSIG[1] ,Asserts SYSCFG_CHIPINT1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHIPSIG[0] ,Asserts SYSCFG_CHIPINT0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "CHIPSIG_CLR,Chip Signal Clear Register"
|
|
sif (cpu()!="AM1707")
|
|
bitfld.long 0x04 4. " CHIPSIG[4] ,Clears DSP NMI Interrupt" "No effect,Clear"
|
|
bitfld.long 0x04 3. " CHIPSIG[3] ,Clears SYSCFG_CHIPINT3 interrupt" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 3. " CHIPSIG[3] ,Clears SYSCFG_CHIPINT3 interrupt" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 2. " CHIPSIG[2] ,Clears SYSCFG_CHIPINT2 interrupt" "No effect,Clear"
|
|
bitfld.long 0x04 1. " CHIPSIG[1] ,Clears SYSCFG_CHIPINT1 interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CHIPSIG[0] ,Clears SYSCFG_CHIPINT0 interrupt" "No effect,Clear"
|
|
width 0xb
|
|
tree.end
|
|
tree "PLLC (PLL Controller)"
|
|
base asd:0x01c11000
|
|
width 9.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,PLL0 Revision Identification Register"
|
|
rgroup.long 0xe4++0x03
|
|
line.long 0x00 "RSTYPE,PLL0 Reset Type Status Register"
|
|
bitfld.long 0x00 2. " PLLSWRST ,PLL software reset" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " XWRST ,External warm reset" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " POR ,Power on reset" "Not occurred,Occurred"
|
|
sif (cpu()=="AM1806"||cpu()=="AM1802"||cpu()=="AM1808"||cpu()=="AM1810")
|
|
group.long 0xe8++0x3
|
|
line.long 0x00 "RSCTRL,PLL0 Reset Control Register"
|
|
bitfld.long 0x00 16. " SWRST ,PLL software reset" "Reset,No reset"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,RSCTRL unlock key"
|
|
endif
|
|
sif (cpu()!="AM1705")
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "PLLCTL,PLL0 Control Register"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1806"||cpu()=="AM1802"||cpu()=="AM1810")
|
|
bitfld.long 0x00 9. " EXTCLKSRC ,External clock source selection" "OSCIN,PLL1_SYSCLK3"
|
|
bitfld.long 0x00 8. " CLKMODE ,Reference Clock Selection" "Internal,Square wave"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " CLKMODE ,Reference Clock Selection" "Internal,Square wave"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PLLENSRC ,This bit must be cleared before PLLEN will have any effect" "0,1"
|
|
bitfld.long 0x00 3. " PLLRST ,Asserts RESET to PLL0" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLPWRDN ,PLL0 power-down" "Operation,Power-down"
|
|
bitfld.long 0x00 0. " PLLEN ,PLL0 mode enable" "Bypassed,PLL0"
|
|
line.long 0x04 "OCSEL,PLL0 OBSCLK Select Register"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1806"||cpu()=="AM1802"||cpu()=="AM1810")
|
|
bitfld.long 0x04 0.--4. " OCSRC ,PLL0 OBSCLK source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,OSCIN,Reserved,Reserved,PLLC0 SYSCLK1,PLLC0 SYSCLK2,PLLC0 SYSCLK3,PLLC0 SYSCLK4,PLLC0 SYSCLK5,PLLC0 SYSCLK6,PLLC0 SYSCLK7,PLLC1 OBSCLK,Disabled"
|
|
else
|
|
bitfld.long 0x04 0.--4. " OCSRC ,PLL0 OBSCLK source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,OSCIN,Reserved,Reserved,PLLC0 SYSCLK1,PLLC0 SYSCLK2,PLLC0 SYSCLK3,PLLC0 SYSCLK4,PLLC0 SYSCLK5,PLLC0 SYSCLK6,PLLC0 SYSCLK7,Reserved,Disabled"
|
|
endif
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PLLCTL,PLL0 Control Register"
|
|
bitfld.long 0x00 8. " CLKMODE ,Reference Clock Selection" "Internal,Square wave"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PLLENSRC ,This bit must be cleared before PLLEN will have any effect" "0,1"
|
|
bitfld.long 0x00 3. " PLLRST ,Asserts RESET to PLL0" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLPWRDN ,PLL0 power-down" "Operation,Power-down"
|
|
bitfld.long 0x00 0. " PLLEN ,PLL0 mode enable" "Bypassed,PLL0"
|
|
endif
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "PLLM,PLL0 Multiplier Control Register"
|
|
bitfld.long 0x00 0.--4. " PLLM ,PLL0 Multiplier Select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "PREDIV,PLL0 Pre-Divider Control Register"
|
|
bitfld.long 0x00 15. " PREDEN ,PLL0 Pre_Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x118++0xb
|
|
line.long 0x0 "PLLDIV1,PLL0 Controller Divider 1 Register"
|
|
bitfld.long 0x0 15. " D1EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x4 "PLLDIV2,PLL0 Controller Divider 2 Register"
|
|
bitfld.long 0x4 15. " D2EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x8 "PLLDIV3,PLL0 Controller Divider 3 Register"
|
|
bitfld.long 0x8 15. " D3EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x160++0x0f
|
|
line.long 0x0 "PLLDIV4,PLL0 Controller Divider 4 Register"
|
|
bitfld.long 0x0 15. " D4EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x4 "PLLDIV5,PLL0 Controller Divider 5 Register"
|
|
bitfld.long 0x4 15. " D5EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x8 "PLLDIV6,PLL0 Controller Divider 6 Register"
|
|
bitfld.long 0x8 15. " D6EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0xC "PLLDIV7,PLL0 Controller Divider 7 Register"
|
|
bitfld.long 0xC 15. " D7EN ,Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
sif (cpu()!="AM1705")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "OSCDIV,PLL0 Oscillator Divider 1 Register"
|
|
bitfld.long 0x00 15. " OD1EN ,Oscillator divider 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "POSTDIV,PLL0 Post-Divider Control Register"
|
|
bitfld.long 0x00 15. " POSTDEN ,Post-Divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " RATIO ,Divider ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PLLCMD,PLL0 Controller Command Register"
|
|
bitfld.long 0x00 0. " GOSET ,GO bit for SYSCLKx phase alignment" "No effect,Enabled"
|
|
rgroup.long 0x13c++0x03
|
|
line.long 0x00 "PLLSTAT,PLL0 Controller Status Register"
|
|
bitfld.long 0x00 2. " STABLE ,OSC counter done oscillator assumed to be stable" "Not stable,Stable"
|
|
bitfld.long 0x00 0. " GOSTAT ,Status of GO operation" "Not in progress,In progress"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ALNCTL,PLL0 Controller Clock Align Control Register"
|
|
bitfld.long 0x00 6. " ALN7 ,PLL0 SYSCLK7 needs to be aligned to others selected in this register" "No,Yes"
|
|
bitfld.long 0x00 5. " ALN6 ,PLL0 SYSCLK6 needs to be aligned to others selected in this register" "No,Yes"
|
|
bitfld.long 0x00 4. " ALN5 ,PLL0 SYSCLK5 needs to be aligned to others selected in this register" "No,Yes"
|
|
bitfld.long 0x00 3. " ALN4 ,PLL0 SYSCLK4 needs to be aligned to others selected in this register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ALN3 ,PLL0 SYSCLK3 needs to be aligned to others selected in this register" "No,Yes"
|
|
bitfld.long 0x00 1. " ALN2 ,PLL0 SYSCLK2 needs to be aligned to others selected in this register" "No,Yes"
|
|
bitfld.long 0x00 0. " ALN1 ,PLL0 SYSCLK1 needs to be aligned to others selected in this register" "No,Yes"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "DCHANGE,PLL0 PLLDIV Ratio Change Status Register"
|
|
bitfld.long 0x00 6. " SYS7 ,PLL0 SYSCLK7 divide ratio modified" "Not modified,Modified"
|
|
bitfld.long 0x00 5. " SYS6 ,PLL0 SYSCLK6 divide ratio modified" "Not modified,Modified"
|
|
bitfld.long 0x00 4. " SYS5 ,PLL0 SYSCLK5 divide ratio modified" "Not modified,Modified"
|
|
textline " "
|
|
sif (cpu()=="AM1806"||cpu()=="AM1802"||cpu()=="AM1808"||cpu()=="AM1810")
|
|
bitfld.long 0x00 3. " SYS4 ,PLL0 SYSCLK4 divide ratio modified" "Not modified,Modified"
|
|
else
|
|
bitfld.long 0x00 3. " SYS4 ,PLL0 SYSCLK4 divide ratio modified" "Not modified,Modified"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYS3 ,PLL0 SYSCLK3 divide ratio modified" "Not modified,Modified"
|
|
bitfld.long 0x00 1. " SYS2 ,PLL0 SYSCLK2 divide ratio modified" "Not modified,Modified"
|
|
bitfld.long 0x00 0. " SYS1 ,PLL0 SYSCLK1 divide ratio modified" "Not modified,Modified"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CKEN,PLL0 Clock Enable Control Register"
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x00 1. " OBSEN ,OBSCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " AUXEN ,AUXCLK enable" "Disabled,Enabled"
|
|
rgroup.long 0x14c++0x03
|
|
line.long 0x00 "CKSTAT,PLL0 Clock Status Register"
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x00 1. " OBSON ,OBSCLK on status" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " AUXEN ,AUXCLK on status" "Off,On"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SYSTAT,PLL0 SYSCLK Status Register"
|
|
bitfld.long 0x00 6. " SYS7ON ,PLL0 SYSCLK7 on status" "Off,On"
|
|
bitfld.long 0x00 5. " SYS6ON ,PLL0 SYSCLK6 on status" "Off,On"
|
|
bitfld.long 0x00 4. " SYS5ON ,PLL0 SYSCLK5 on status" "Off,On"
|
|
bitfld.long 0x00 3. " SYS4ON ,PLL0 SYSCLK4 on status" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYS3ON ,PLL0 SYSCLK3 on status" "Off,On"
|
|
bitfld.long 0x00 1. " SYS2ON ,PLL0 SYSCLK2 on status" "Off,On"
|
|
bitfld.long 0x00 0. " SYS1ON ,PLL0 SYSCLK1 on status" "Off,On"
|
|
rgroup.long 0x1f0++0x07
|
|
line.long 0x00 "EMUCNT0,PLL0 Emulation Performance Counter 0 Register"
|
|
line.long 0x04 "EMUCNT1,PLL0 Emulation Performance Counter 1 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "AINTC (ARM Interrupt Controller)"
|
|
base asd:0xfffee000
|
|
width 8.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 4. " PRHOLDMODE ,Enables priority holding mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " NESTMODE ,Nesting mode" "No nesting,Automatic individual,Automatic global,Manual"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GER,Global Enable Register"
|
|
bitfld.long 0x00 0. " ENABLE ,The current global enable value when read" "Disabled,Enabled"
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "GNLR,Global Nesting Level Register"
|
|
bitfld.long 0x00 31. " OVERRIDE ,Automatic nesting override" "Not overridden,Overridden"
|
|
hexmask.long.word 0x00 0.--8. 1. " NESTLVL ,Current global nesting level"
|
|
width 8.
|
|
wgroup.long 0x20++0x0f
|
|
line.long 0x00 "SISR,System Interrupt Status Indexed Set Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INDEX ,Status of the interrupt given in the INDEX value"
|
|
line.long 0x04 "SICR,System Interrupt Status Indexed Clear Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INDEX ,Clear the status of the interrupt given in the INDEX value"
|
|
line.long 0x08 "EISR,System Interrupt Enable Indexed Set Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " INDEX ,Set the enable of the interrupt given in the INDEX value"
|
|
line.long 0x0c "EICR,System Interrupt Enable Indexed Clear Register"
|
|
hexmask.long.byte 0x0c 0.--6. 1. " INDEX ,Clear the enable of the interrupt given in the INDEX value"
|
|
wgroup.long 0x34++0x07
|
|
line.long 0x00 "HIEISR,Host Interrupt Enable Indexed Set Register"
|
|
bitfld.long 0x00 0. " INDEX ,Set the enable of the host interrupt given in the INDEX value" "FIQ,IRQ"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
line.long 0x04 "HIDISR,Host Interrupt Enable Indexed Clear Register"
|
|
else
|
|
line.long 0x04 "HIEICR,Host Interrupt Enable Indexed Clear Register"
|
|
endif
|
|
bitfld.long 0x04 0. " INDEX ,Clear the enable of the host interrupt given in the INDEX value" "FIQ,IRQ"
|
|
group.long 0x50++0x0b
|
|
line.long 0x00 "VBR,Vector Base Register"
|
|
line.long 0x04 "VSR,Vector Size Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SIZE ,Size of ISR address spaces"
|
|
line.long 0x08 "VNR,Vector Null Register"
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "GPIR,Global Prioritized Index Register"
|
|
bitfld.long 0x00 31. " NONE ,No Interrupt is pending" "No,Yes"
|
|
hexmask.long.word 0x00 0.--9. 1. " PRI_INDX ,The currently highest priority interrupt index pending across all the host interrupts"
|
|
line.long 0x04 "GPVR,Global Prioritized Vector Register"
|
|
wgroup.long 0x200++0x0b
|
|
line.long 0x00 "SRSR1,System Interrupt Status Raw/Set Register 1"
|
|
bitfld.long 0x00 31. " RAW_STATUS[31] ,System interrupt SYSCFG_CHIPINT3 raw status" "No effect,Set"
|
|
bitfld.long 0x00 30. " RAW_STATUS[30] ,System interrupt SYSCFG_CHIPINT2 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RAW_STATUS[29] ,System interrupt SYSCFG_CHIPINT1 raw status" "No effect,Set"
|
|
bitfld.long 0x00 28. " RAW_STATUS[28] ,System interrupt SYSCFG_CHIPINT0 raw status" "No effect,Set"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138")
|
|
bitfld.long 0x00 27. " RAW_STATUS[27] ,System interrupt PROTERRMPU_BOOTCFG_ERR raw status" "No effect,Set"
|
|
elif (cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x00 27. " RAW_STATUS[27] ,System interrupt PROTERR raw status" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 27. " RAW_STATUS[27] ,System interrupt MPU_BOOTCFG_ERR raw status" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 25. " RAW_STATUS[25] ,System interrupt UART0_INT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RAW_STATUS[24] ,System interrupt T64P1_TINT34 raw status" "No effect,Set"
|
|
bitfld.long 0x00 23. " RAW_STATUS[23] ,System interrupt T64P1_TINT12 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RAW_STATUS[22] ,System interrupt T64P0_TINT34 raw status" "No effect,Set"
|
|
bitfld.long 0x00 21. " RAW_STATUS[21] ,System interrupt T64P0_TINT12 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RAW_STATUS[20] ,System interrupt SPI0_INT raw status" "No effect,Set"
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x00 19. " RAW_STATUS[19] ,System interrupt RTC_IRQS[1:0]" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " RAW_STATUS[18] ,System interrupt PSC0_ALLINT raw status" "No effect,Set"
|
|
bitfld.long 0x00 17. " RAW_STATUS[17] ,System interrupt MMCSD_INT1 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RAW_STATUS[16] ,System interrupt MMCSD_INT0 raw status" "No effect,Set"
|
|
bitfld.long 0x00 15. " RAW_STATUS[15] ,System interrupt IIC0_INT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RAW_STATUS[14] ,System interrupt EMIFA_INT raw status" "No effect,Set"
|
|
bitfld.long 0x00 13. " RAW_STATUS[13] ,System interrupt EDMA3_TC0_TCERRINT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RAW_STATUS[12] ,System interrupt EDMA3_CC0_CCERRINT raw status" "No effect,Set"
|
|
bitfld.long 0x00 11. " RAW_STATUS[11] ,System interrupt EDMA3_CC0_CCINT raw status" "No effect,Set"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
bitfld.long 0x00 10. " RAW_STATUS[10] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
bitfld.long 0x00 9. " RAW_STATUS[9] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RAW_STATUS[8] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
bitfld.long 0x00 7. " RAW_STATUS[7] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RAW_STATUS[6] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
bitfld.long 0x00 5. " RAW_STATUS[5] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAW_STATUS[4] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
bitfld.long 0x00 3. " RAW_STATUS[3] ,System interrupt PRUSS raw status" "No effect,Set"
|
|
textline " "
|
|
elif (cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x00 10. " RAW_STATUS[10] ,System interrupt PRU_EVTOUT7 raw status" "No effect,Set"
|
|
bitfld.long 0x00 9. " RAW_STATUS[9] ,System interrupt PRU_EVTOUT6 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RAW_STATUS[8] ,System interrupt PRU_EVTOUT5 raw status" "No effect,Set"
|
|
bitfld.long 0x00 7. " RAW_STATUS[7] ,System interrupt PRU_EVTOUT4 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RAW_STATUS[6] ,System interrupt PRU_EVTOUT3 raw status" "No effect,Set"
|
|
bitfld.long 0x00 5. " RAW_STATUS[5] ,System interrupt PRU_EVTOUT2 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAW_STATUS[4] ,System interrupt PRU_EVTOUT1 raw status" "No effect,Set"
|
|
bitfld.long 0x00 3. " RAW_STATUS[3] ,System interrupt PRU_EVTOUT0 raw status" "No effect,Set"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " RAW_STATUS[10] ,System interrupt DMAX_EVTOUT7 raw status" "No effect,Set"
|
|
bitfld.long 0x00 9. " RAW_STATUS[9] ,System interrupt DMAX_EVTOUT6 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RAW_STATUS[8] ,System interrupt DMAX_EVTOUT5 raw status" "No effect,Set"
|
|
bitfld.long 0x00 7. " RAW_STATUS[7] ,System interrupt DMAX_EVTOUT4 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RAW_STATUS[6] ,System interrupt DMAX_EVTOUT3 raw status" "No effect,Set"
|
|
bitfld.long 0x00 5. " RAW_STATUS[5] ,System interrupt DMAX_EVTOUT2 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RAW_STATUS[4] ,System interrupt DMAX_EVTOUT1 raw status" "No effect,Set"
|
|
bitfld.long 0x00 3. " RAW_STATUS[3] ,System interrupt DMAX_EVTOUT0 raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " RAW_STATUS[2] ,System interrupt NINT raw status" "No effect,Set"
|
|
bitfld.long 0x00 1. " RAW_STATUS[1] ,System interrupt COMMRX raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAW_STATUS[0] ,System interrupt COMMTX raw status" "No effect,Set"
|
|
line.long 0x04 "SRSR2,System Interrupt Status Raw/Set Register 2"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x04 31. " RAW_STATUS[63] ,System interrupt EHRPWM0 raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 29. " RAW_STATUS[61] ,System interrupt UART2_INT raw status" "No effect,Set"
|
|
textline " "
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1806"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 28. " RAW_STATUS[60] ,System interrupt USB1_R/WAKEUP raw status" "No effect,Set"
|
|
bitfld.long 0x04 27. " RAW_STATUS[59] ,System interrupt USB1_HCINT raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 26. " RAW_STATUS[58] ,System interrupt USB0_INT raw status" "No effect,Set"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 25. " RAW_STATUS[57] ,System interrupt UHPI_ARMINT raw status" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24. " RAW_STATUS[56] ,System interrupt SPI1_INT raw status" "No effect,Set"
|
|
bitfld.long 0x04 23. " RAW_STATUS[55] ,System interrupt PSC1_ALLINT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " RAW_STATUS[54] ,System interrupt MCASP_INT raw status" "No effect,Set"
|
|
bitfld.long 0x04 21. " RAW_STATUS[53] ,System interrupt UART_INT1 raw status" "No effect,Set"
|
|
textline " "
|
|
sif (cpu()!="AM1802")
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x04 20. " RAW_STATUS[52] ,System interrupt LCDC_INT raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " RAW_STATUS[51] ,System interrupt IIC1_INT raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 18. " RAW_STATUS[50] ,System interrupt GPIO_B8INT raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 17. " RAW_STATUS[49] ,System interrupt GPIO_B7INT raw status" "No effect,Set"
|
|
bitfld.long 0x04 16. " RAW_STATUS[48] ,System interrupt GPIO_B6INT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RAW_STATUS[47] ,System interrupt GPIO_B5INT raw status" "No effect,Set"
|
|
bitfld.long 0x04 14. " RAW_STATUS[46] ,System interrupt GPIO_B4INT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RAW_STATUS[45] ,System interrupt GPIO_B3INT raw status" "No effect,Set"
|
|
bitfld.long 0x04 12. " RAW_STATUS[44] ,System interrupt GPIO_B2INT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RAW_STATUS[43] ,System interrupt GPIO_B1INT raw status" "No effect,Set"
|
|
bitfld.long 0x04 10. " RAW_STATUS[42] ,System interrupt GPIO_B0INT raw status" "No effect,Set"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 9. " RAW_STATUS[41] ,System interrupt DDR2_MEMERR raw status" "No effect,Set"
|
|
else
|
|
bitfld.long 0x04 9. " RAW_STATUS[41] ,System interrupt EMIF_MEMERR raw status" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x04 8. " RAW_STATUS[40] ,System interrupt EMAC_C1MISC raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RAW_STATUS[39] ,System interrupt EMAC_C1TX raw status" "No effect,Set"
|
|
bitfld.long 0x04 6. " RAW_STATUS[38] ,System interrupt EMAC_C1RX raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RAW_STATUS[37] ,System interrupt EMAC_C1RXTHRESH raw status" "No effect,Set"
|
|
bitfld.long 0x04 4. " RAW_STATUS[36] ,System interrupt EMAC_C0MISC raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RAW_STATUS[35] ,System interrupt EMAC_C0TX raw status" "No effect,Set"
|
|
bitfld.long 0x04 2. " RAW_STATUS[34] ,System interrupt EMAC_C0RX raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RAW_STATUS[33] ,System interrupt EMAC_C0RXTHRESH raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " RAW_STATUS[32] ,System interrupt EDMA3_TC1_TCERRINT raw status" "No effect,Set"
|
|
line.long 0x08 "SRSR3,System Interrupt Status Raw/Set Register 3"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x08 30. " RAW_STATUS[95] ,System interrupt EDMA_1TC0_ERRINT raw status" "No effect,Set"
|
|
bitfld.long 0x08 30. " RAW_STATUS[94] ,System interrupt EDMA_1CC0_ERRINT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 29. " RAW_STATUS[93] ,System interrupt EDMA_1CC0_INT raw status" "No effect,Set"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 28. " RAW_STATUS[92] ,System interrupt VPIF raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RAW_STATUS[91] ,System interrupt uPP_ALLINT raw status" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 26. " RAW_STATUS[90] ,System interrupt ARMCLKSTOPREQ raw status" "No effect,Set"
|
|
bitfld.long 0x08 25. " RAW_STATUS[89] ,System interrupt T64P1_CMPINT7 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 24. " RAW_STATUS[88] ,System interrupt T64P1_CMPINT6 raw status" "No effect,Set"
|
|
bitfld.long 0x08 23. " RAW_STATUS[87] ,System interrupt T64P1_CMPINT5 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 22. " RAW_STATUS[86] ,System interrupt T64P1_CMPINT4 raw status" "No effect,Set"
|
|
bitfld.long 0x08 21. " RAW_STATUS[85] ,System interrupt T64P1_CMPINT3 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RAW_STATUS[84] ,System interrupt T64P1_CMPINT2 raw status" "No effect,Set"
|
|
bitfld.long 0x08 19. " RAW_STATUS[83] ,System interrupt T64P1_CMPINT1 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 18. " RAW_STATUS[82] ,System interrupt T64P1_CMPINT0 raw status" "No effect,Set"
|
|
bitfld.long 0x08 17. " RAW_STATUS[81] ,System interrupt T64P0_CMPINT7 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 16. " RAW_STATUS[80] ,System interrupt T64P0_CMPINT6 raw status" "No effect,Set"
|
|
bitfld.long 0x08 15. " RAW_STATUS[79] ,System interrupt T64P0_CMPINT5 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 14. " RAW_STATUS[78] ,System interrupt T64P0_CMPINT4 raw status" "No effect,Set"
|
|
bitfld.long 0x08 13. " RAW_STATUS[77] ,System interrupt T64P0_CMPINT3 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 12. " RAW_STATUS[76] ,System interrupt T64P0_CMPINT2 raw status" "No effect,Set"
|
|
bitfld.long 0x08 11. " RAW_STATUS[75] ,System interrupt T64P0_CMPINT1 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 10. " RAW_STATUS[74] ,System interrupt T64P0_CMPINT0 raw status" "No effect,Set"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 9. " RAW_STATUS[73] ,System interrupt MMCSD1_INT1 raw status" "No effect,Set"
|
|
bitfld.long 0x08 8. " RAW_STATUS[72] ,System interrupt MMCSD1_INT0 raw status" "No effect,Set"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 9. " RAW_STATUS[73] ,System interrupt EQEP1 raw status" "No effect,Set"
|
|
bitfld.long 0x08 8. " RAW_STATUS[72] ,System interrupt EQEP0 raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 7. " RAW_STATUS[71] ,System interrupt ECAP2 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 6. " RAW_STATUS[70] ,System interrupt ECAP1 raw status" "No effect,Set"
|
|
bitfld.long 0x08 5. " RAW_STATUS[69] ,System interrupt ECAP0 raw status" "No effect,Set"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 4. " RAW_STATUS[68] ,System interrupt T64P2_All raw status" "No effect,Set"
|
|
bitfld.long 0x08 3. " RAW_STATUS[67] ,System interrupt SATA_INT raw status" "No effect,Set"
|
|
elif (cpu()=="AM1802")
|
|
bitfld.long 0x08 4. " RAW_STATUS[68] ,System interrupt EHRPWM2TZ raw status" "No effect,Set"
|
|
else
|
|
bitfld.long 0x08 4. " RAW_STATUS[68] ,System interrupt EHRPWM2TZ raw status" "No effect,Set"
|
|
bitfld.long 0x08 3. " RAW_STATUS[67] ,System interrupt EHRPWM2 raw status" "No effect,Set"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
textline " "
|
|
bitfld.long 0x08 2. " RAW_STATUS[66] ,System interrupt EHRPWM1TZ raw status" "No effect,Set"
|
|
bitfld.long 0x08 1. " RAW_STATUS[65] ,System interrupt EHRPWM1 raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 0. " RAW_STATUS[64] ,System interrupt EHRPWM0TZ raw status" "No effect,Set"
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
wgroup.long 0x20C++0x03
|
|
line.long 0x00 "SRSR4,System Interrupt Status Raw/Set Register 4"
|
|
bitfld.long 0x00 4. " RAW_STATUS[100] ,System interrupt MCBSP1_XINT raw status" "No effect,Set"
|
|
bitfld.long 0x00 3. " RAW_STATUS[99] ,System interrupt MCBSP1_RINT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RAW_STATUS[98] ,System interrupt MCBSP0_XINT raw status" "No effect,Set"
|
|
bitfld.long 0x00 1. " RAW_STATUS[97] ,System interrupt MCBSP0_RINT raw status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RAW_STATUS[96] ,System interrupt T64P3_ALL raw status" "No effect,Set"
|
|
elif (cpu()=="AM1802")
|
|
wgroup.long 0x20C++0x03
|
|
line.long 0x00 "SRSR4,System Interrupt Status Raw/Set Register 4"
|
|
bitfld.long 0x00 0. " RAW_STATUS[96] ,System interrupt T64P3_ALL raw status" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x280++0x0b
|
|
line.long 0x00 "SECR1,System Interrupt Status Enabled/Clear Register 1"
|
|
bitfld.long 0x00 31. " ENBL_STATUS[31] ,System interrupt SYSCFG_CHIPINT3 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 30. " ENBL_STATUS[30] ,System interrupt SYSCFG_CHIPINT2 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ENBL_STATUS[29] ,System interrupt SYSCFG_CHIPINT1 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 28. " ENBL_STATUS[28] ,System interrupt SYSCFG_CHIPINT0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x00 27. " ENBL_STATUS[27] ,System interrupt PROTERR enabled status and clearing" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 27. " ENBL_STATUS[27] ,System interrupt MPU_BootCFG_ERR enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
bitfld.long 0x00 25. " ENBL_STATUS[25] ,System interrupt UART0_INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ENBL_STATUS[24] ,System interrupt T64P1_TINT34 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 23. " ENBL_STATUS[23] ,System interrupt T64P1_TINT12 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ENBL_STATUS[22] ,System interrupt T64P0_TINT34 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 21. " ENBL_STATUS[21] ,System interrupt T64P0_TINT12 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ENBL_STATUS[20] ,System interrupt SPI0_INT enabled status and clearing" "No effect,Clear"
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x00 19. " ENBL_STATUS[19] ,System interrupt RTC_IRQS[1:0] enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENBL_STATUS[18] ,System interrupt PSC0_ALLINT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 17. " ENBL_STATUS[17] ,System interrupt MMCSD_INT1 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENBL_STATUS[16] ,System interrupt MMCSD_INT0 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 15. " ENBL_STATUS[15] ,System interrupt IIC0_INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ENBL_STATUS[14] ,System interrupt EMIFA_INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 13. " ENBL_STATUS[13] ,System interrupt EDMA3_TC0_TCERRINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENBL_STATUS[12] ,System interrupt EDMA3_CC0_CCERRINT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 11. " ENBL_STATUS[11] ,System interrupt EDMA3_CC0_CCINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
bitfld.long 0x00 10. " ENBL_STATUS[10] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ENBL_STATUS[9] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENBL_STATUS[8] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ENBL_STATUS[7] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENBL_STATUS[6] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 5. " ENBL_STATUS[5] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENBL_STATUS[4] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ENBL_STATUS[3] ,System interrupt PRUSS enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
elif (cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x00 10. " ENBL_STATUS[10] ,System interrupt PRU_EVTOUT7 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ENBL_STATUS[9] ,System interrupt PRU_EVTOUT6 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENBL_STATUS[8] ,System interrupt PRU_EVTOUT5 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ENBL_STATUS[7] ,System interrupt PRU_EVTOUT4 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENBL_STATUS[6] ,System interrupt PRU_EVTOUT3 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 5. " ENBL_STATUS[5] ,System interrupt PRU_EVTOUT2 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENBL_STATUS[4] ,System interrupt PRU_EVTOUT1 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ENBL_STATUS[3] ,System interrupt PRU_EVTOUT0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " ENBL_STATUS[10] ,System interrupt DMAX_EVTOUT7 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ENBL_STATUS[9] ,System interrupt DMAX_EVTOUT6 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENBL_STATUS[8] ,System interrupt DMAX_EVTOUT5 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ENBL_STATUS[7] ,System interrupt DMAX_EVTOUT4 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENBL_STATUS[6] ,System interrupt DMAX_EVTOUT3 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 5. " ENBL_STATUS[5] ,System interrupt DMAX_EVTOUT2 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENBL_STATUS[4] ,System interrupt DMAX_EVTOUT1 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ENBL_STATUS[3] ,System interrupt DMAX_EVTOUT0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " ENBL_STATUS[2] ,System interrupt NINT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ENBL_STATUS[1] ,System interrupt COMMRX enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENBL_STATUS[0] ,System interrupt COMMTX enabled status and clearing" "No effect,Clear"
|
|
line.long 0x04 "SECR2,System Interrupt Status Enabled/Clear Register 2"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x04 31. " ENBL_STATUS[63] ,System interrupt EHRPWM0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 29. " ENBL_STATUS[61] ,System interrupt UART2_INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1806"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 28. " ENBL_STATUS[60] ,System interrupt USB1_R/WAKEUP enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 27. " ENBL_STATUS[59] ,System interrupt USB1_HCINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 26. " ENBL_STATUS[58] ,System interrupt USB0_INT enabled status and clearing" "No effect,Clear"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 25. " ENBL_STATUS[57] ,System interrupt UHPI_ARMINT enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24. " ENBL_STATUS[56] ,System interrupt SPI1_INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 23. " ENBL_STATUS[55] ,System interrupt PSC1_ALLINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ENBL_STATUS[54] ,System interrupt MCASP_INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 21. " ENBL_STATUS[53] ,System interrupt UART_INT1 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
sif (cpu()!="AM1802")
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x04 20. " ENBL_STATUS[52] ,System interrupt LCDC_INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " ENBL_STATUS[51] ,System interrupt IIC1_INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 18. " ENBL_STATUS[50] ,System interrupt GPIO_B8INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 17. " ENBL_STATUS[49] ,System interrupt GPIO_B7INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 16. " ENBL_STATUS[48] ,System interrupt GPIO_B6INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " ENBL_STATUS[47] ,System interrupt GPIO_B5INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 14. " ENBL_STATUS[46] ,System interrupt GPIO_B4INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ENBL_STATUS[45] ,System interrupt GPIO_B3INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 12. " ENBL_STATUS[44] ,System interrupt GPIO_B2INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ENBL_STATUS[43] ,System interrupt GPIO_B1INT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 10. " ENBL_STATUS[42] ,System interrupt GPIO_B0INT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 9. " ENBL_STATUS[41] ,System interrupt DDR2_MEMERR enabled status and clearing" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x04 9. " ENBL_STATUS[41] ,System interrupt EMIF_MEMERR enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x04 8. " ENBL_STATUS[40] ,System interrupt EMAC_C1MISC enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ENBL_STATUS[39] ,System interrupt EMAC_C1TX enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 6. " ENBL_STATUS[38] ,System interrupt EMAC_C1RX enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ENBL_STATUS[37] ,System interrupt EMAC_C1RXTHRESH enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 4. " ENBL_STATUS[36] ,System interrupt EMAC_C0MISC enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENBL_STATUS[35] ,System interrupt EMAC_C0TX enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x04 2. " ENBL_STATUS[34] ,System interrupt EMAC_C0RX enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ENBL_STATUS[33] ,System interrupt EMAC_C0RXTHRESH enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " ENBL_STATUS[32] ,System interrupt EDMA3_TC1_TCERRINT enabled status and clearing" "No effect,Clear"
|
|
line.long 0x08 "SECR3,System Interrupt Status Enabled/Clear Register 3"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x08 30. " ENBL_STATUS[95] ,System interrupt EDMA_1TC0_ERRINT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 30. " ENBL_STATUS[94] ,System interrupt EDMA_1CC0_ERRINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ENBL_STATUS[93] ,System interrupt EDMA_1CC0_INT enabled status and clearing" "No effect,Clear"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 28. " ENBL_STATUS[92] ,System interrupt VPIF enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ENBL_STATUS[91] ,System interrupt uPP_ALLINT enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 26. " ENBL_STATUS[90] ,System interrupt ARMCLKSTOPREQ enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 25. " ENBL_STATUS[89] ,System interrupt T64P1_CMPINT7 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 24. " ENBL_STATUS[88] ,System interrupt T64P1_CMPINT6 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 23. " ENBL_STATUS[87] ,System interrupt T64P1_CMPINT5 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " ENBL_STATUS[86] ,System interrupt T64P1_CMPINT4 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 21. " ENBL_STATUS[85] ,System interrupt T64P1_CMPINT3 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " ENBL_STATUS[84] ,System interrupt T64P1_CMPINT2 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 19. " ENBL_STATUS[83] ,System interrupt T64P1_CMPINT1 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 18. " ENBL_STATUS[82] ,System interrupt T64P1_CMPINT0 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 17. " ENBL_STATUS[81] ,System interrupt T64P0_CMPINT7 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " ENBL_STATUS[80] ,System interrupt T64P0_CMPINT6 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 15. " ENBL_STATUS[79] ,System interrupt T64P0_CMPINT5 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 14. " ENBL_STATUS[78] ,System interrupt T64P0_CMPINT4 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 13. " ENBL_STATUS[77] ,System interrupt T64P0_CMPINT3 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 12. " ENBL_STATUS[76] ,System interrupt T64P0_CMPINT2 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 11. " ENBL_STATUS[75] ,System interrupt T64P0_CMPINT1 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " ENBL_STATUS[74] ,System interrupt T64P0_CMPINT0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 9. " ENBL_STATUS[73] ,System interrupt MMCSD1_INT1 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 8. " ENBL_STATUS[72] ,System interrupt MMCSD1_INT0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 9. " ENBL_STATUS[73] ,System interrupt EQEP1 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 8. " ENBL_STATUS[72] ,System interrupt EQEP0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 7. " ENBL_STATUS[71] ,System interrupt ECAP2 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 6. " ENBL_STATUS[70] ,System interrupt ECAP1 enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 5. " ENBL_STATUS[69] ,System interrupt ECAP0 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 4. " ENBL_STATUS[68] ,System interrupt T64P2_ALL enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 3. " ENBL_STATUS[67] ,System interrupt SATA_INT enabled status and clearing" "No effect,Clear"
|
|
elif (cpu()=="AM1802")
|
|
bitfld.long 0x08 4. " RAW_STATUS[68] ,System interrupt EHRPWM2TZ raw status" "No effect,Set"
|
|
else
|
|
bitfld.long 0x08 4. " ENBL_STATUS[68] ,System interrupt EHRPWM2TZ enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 3. " ENBL_STATUS[67] ,System interrupt EHRPWM2 enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
textline " "
|
|
bitfld.long 0x08 2. " ENBL_STATUS[66] ,System interrupt EHRPWM1TZ enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x08 1. " ENBL_STATUS[65] ,System interrupt EHRPWM1 enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ENBL_STATUS[64] ,System interrupt EHRPWM0TZ enabled status and clearing" "No effect,Clear"
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
wgroup.long 0x28C++0x03
|
|
line.long 0x00 "SECR4,System Interrupt Status ENABLE/CLEAR Register 4"
|
|
bitfld.long 0x00 4. " ENBL_STATUS[100] ,System interrupt MCBSP1_XINT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ENBL_STATUS[99] ,System interrupt MCBSP1_RINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENBL_STATUS[98] ,System interrupt MCBSP0_XINT enabled status and clearing" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ENBL_STATUS[97] ,System interrupt MCBSP0_RINT enabled status and clearing" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENBL_STATUS[96] ,System interrupt T64P3_ALL enabled status and clearing" "No effect,Clear"
|
|
elif (cpu()=="AM1802")
|
|
wgroup.long 0x20C++0x03
|
|
line.long 0x00 "SRSR4,System Interrupt Status Raw/Set Register 4"
|
|
bitfld.long 0x00 0. " RAW_STATUS[96] ,System interrupt T64P3_ALL raw status" "No effect,Set"
|
|
endif
|
|
wgroup.long 0x300++0x0b
|
|
line.long 0x00 "ESR1,System Interrupt Enable Set Register 1"
|
|
bitfld.long 0x00 31. " ENABLE[31] ,System interrupt SYSCFG_CHIPINT3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENABLE[30] ,System interrupt SYSCFG_CHIPINT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENABLE[29] ,System interrupt SYSCFG_CHIPINT1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ENABLE[28] ,System interrupt SYSCFG_CHIPINT0 enable" "Disabled,Enabled"
|
|
sif (CPU()=="OMAP-L138"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x00 27. " ENABLE[27] ,System interrupt PROTERR enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 27. " ENABLE[27] ,System interrupt MPU_BOOTCFG_ERR enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 25. " ENABLE[25] ,System interrupt UART0_INT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ENABLE[24] ,System interrupt T64P1_TINT34 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENABLE[23] ,System interrupt T64P1_TINT12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENABLE[22] ,System interrupt T64P0_TINT34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ENABLE[21] ,System interrupt T64P0_TINT12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENABLE[20] ,System interrupt SPI0_INT enable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x00 19. " ENABLE[19] ,System interrupt RTC_IRQS[1:0] enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " ENABLE[18] ,System interrupt PSC0_ALLINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENABLE[17] ,System interrupt MMCSD_INT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENABLE[16] ,System interrupt MMCSD_INT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE[15] ,System interrupt IIC0_INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENABLE[14] ,System interrupt EMIFA_INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENABLE[13] ,System interrupt EDMA3_TC0_TCERRINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENABLE[12] ,System interrupt EDMA3_CC0_CCERRINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENABLE[11] ,System interrupt EDMA3_CC0_CCINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
bitfld.long 0x00 10. " ENABLE[10] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[9] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[8] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENABLE[7] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENABLE[6] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENABLE[5] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENABLE[4] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[3] ,System interrupt PRUSS enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x00 10. " ENABLE[10] ,System interrupt PRU_EVTOUT7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[9] ,System interrupt PRU_EVTOUT6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[8] ,System interrupt PRU_EVTOUT5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENABLE[7] ,System interrupt PRU_EVTOUT4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENABLE[6] ,System interrupt PRU_EVTOUT3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENABLE[5] ,System interrupt PRU_EVTOUT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENABLE[4] ,System interrupt PRU_EVTOUT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[3] ,System interrupt PRU_EVTOUT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " ENABLE[10] ,System interrupt DMAX_EVTOUT7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[9] ,System interrupt DMAX_EVTOUT6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ENABLE[8] ,System interrupt DMAX_EVTOUT5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENABLE[7] ,System interrupt DMAX_EVTOUT4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENABLE[6] ,System interrupt DMAX_EVTOUT3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENABLE[5] ,System interrupt DMAX_EVTOUT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENABLE[4] ,System interrupt DMAX_EVTOUT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[3] ,System interrupt DMAX_EVTOUT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " ENABLE[2] ,System interrupt NINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLE[1] ,System interrupt COMMRX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[0] ,System interrupt COMMTX enable" "Disabled,Enabled"
|
|
line.long 0x04 "ESR2,System Interrupt Enable Set Register 2"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x04 31. " ENABLE[63] ,System interrupt EHRPWM0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 29. " ENABLE[61] ,System interrupt UART2_INT enable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1806"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 28. " ENABLE[60] ,System interrupt USB1_R/WAKEUP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " ENABLE[59] ,System interrupt USB1_HCINT enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 26. " ENABLE[58] ,System interrupt USB0_INT enable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 25. " ENABLE[57] ,System interrupt UHPI_ARMINT enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24. " ENABLE[56] ,System interrupt SPI1_INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " ENABLE[55] ,System interrupt PSC1_ALLINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ENABLE[54] ,System interrupt MCASP_INT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ENABLE[53] ,System interrupt UART_INT1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AM1802")
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x04 20. " ENABLE[52] ,System interrupt LCDC_INT enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 19. " ENABLE[51] ,System interrupt IIC1_INT enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 18. " ENABLE[50] ,System interrupt GPIO_B8INT raw status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 17. " ENABLE[49] ,System interrupt GPIO_B7INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " ENABLE[48] ,System interrupt GPIO_B6INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " ENABLE[47] ,System interrupt GPIO_B5INT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " ENABLE[46] ,System interrupt GPIO_B4INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " ENABLE[45] ,System interrupt GPIO_B3INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " ENABLE[44] ,System interrupt GPIO_B2INT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ENABLE[43] ,System interrupt GPIO_B1INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ENABLE[42] ,System interrupt GPIO_B0INT enable" "Disabled,Enabled"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 9. " ENABLE[41] ,System interrupt DDR2_MEMERR enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 9. " ENABLE[41] ,System interrupt EMIF_MEMERR enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
textline " "
|
|
bitfld.long 0x04 8. " ENABLE[40] ,System interrupt EMAC_C1MISC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " ENABLE[39] ,System interrupt EMAC_C1TX enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ENABLE[38] ,System interrupt EMAC_C1RX enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ENABLE[37] ,System interrupt EMAC_C1RXTHRESH enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ENABLE[36] ,System interrupt EMAC_C0MISC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ENABLE[35] ,System interrupt EMAC_C0TX enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ENABLE[34] ,System interrupt EMAC_C0RX enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ENABLE[33] ,System interrupt EMAC_C0RXTHRESH enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " ENABLE[32] ,System interrupt EDMA3_TC1_TCERRINT enable" "Disabled,Enabled"
|
|
line.long 0x08 "ESR3,System Interrupt Enable Set Register 3"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x08 30. " ENABLE[95] ,System interrupt EDMA_1TC0_ERRINT renable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " ENABLE[94] ,System interrupt EDMA_1CC0_ERRINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ENABLE[93] ,System interrupt EDMA_1CC0_INT enable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 28. " ENABLE[92] ,System interrupt VPIF enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ENABLE[91] ,System interrupt uPP_ALLINT enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 26. " ENABLE[90] ,System interrupt ARMCLKSTOPREQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " ENABLE[89] ,System interrupt T64P1_CMPINT7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " ENABLE[88] ,System interrupt T64P1_CMPINT6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ENABLE[87] ,System interrupt T64P1_CMPINT5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " ENABLE[86] ,System interrupt T64P1_CMPINT4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " ENABLE[85] ,System interrupt T64P1_CMPINT3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " ENABLE[84] ,System interrupt T64P1_CMPINT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " ENABLE[83] ,System interrupt T64P1_CMPINT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " ENABLE[82] ,System interrupt T64P1_CMPINT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " ENABLE[81] ,System interrupt T64P0_CMPINT7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " ENABLE[80] ,System interrupt T64P0_CMPINT6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " ENABLE[79] ,System interrupt T64P0_CMPINT5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " ENABLE[78] ,System interrupt T64P0_CMPINT4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " ENABLE[77] ,System interrupt T64P0_CMPINT3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " ENABLE[76] ,System interrupt T64P0_CMPINT2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ENABLE[75] ,System interrupt T64P0_CMPINT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " ENABLE[74] ,System interrupt T64P0_CMPINT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 9. " ENABLE[73] ,System interrupt MMCSD1_INT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " ENABLE[72] ,System interrupt MMCSD1_INT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 9. " ENABLE[73] ,System interrupt EQEP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " ENABLE[72] ,System interrupt EQEP0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 7. " ENABLE[71] ,System interrupt ECAP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " ENABLE[70] ,System interrupt ECAP1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ENABLE[69] ,System interrupt ECAP0 enable" "Disabled,Enabled"
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 4. " ENABLE[68] ,System interrupt T64P2_ALL enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " ENABLE[67] ,System interrupt SATA_INT enable" "Disabled,Enabled"
|
|
elif (cpu()=="AM1802")
|
|
bitfld.long 0x08 4. " ENABLE[68] ,System interrupt EHRPWM2TZ enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 4. " ENABLE[68] ,System interrupt EHRPWM2TZ enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " ENABLE[67] ,System interrupt EHRPWM2 enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
textline " "
|
|
bitfld.long 0x08 2. " ENABLE[66] ,System interrupt EHRPWM1TZ enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " ENABLE[65] ,System interrupt EHRPWM1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLE[64] ,System interrupt EHRPWM0TZ enable" "Disabled,Enabled"
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
wgroup.long 0x30C++0x03
|
|
line.long 0x00 "ESR4,System Interrupt Status ENABLE/CLEAR Register 4"
|
|
bitfld.long 0x00 4. " ENABLE[100] ,System interrupt MCBSP1_XINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENABLE[99] ,System interrupt MCBSP1_RINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENABLE[98] ,System interrupt MCBSP0_XINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENABLE[97] ,System interrupt MCBSP0_RINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE[96] ,System interrupt T64P3_ALL enable" "Disabled,Enabled"
|
|
elif (cpu()=="AM1802")
|
|
wgroup.long 0x30C++0x03
|
|
line.long 0x00 "ESR4,System Interrupt Status ENABLE/CLEAR Register 4"
|
|
bitfld.long 0x00 0. " ENABLE[96] ,System interrupt T64P3_ALL enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x380++0x0b
|
|
line.long 0x00 "ECR1,System Interrupt Enable Clear Register 1"
|
|
bitfld.long 0x00 31. " DISABLE[31] ,System interrupt SYSCFG_CHIPINT3 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DISABLE[30] ,System interrupt SYSCFG_CHIPINT2 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DISABLE[29] ,System interrupt SYSCFG_CHIPINT1 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DISABLE[28] ,System interrupt SYSCFG_CHIPINT0 disable" "Disabled,Enabled"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x00 27. " DISABLE[27] ,System interrupt PROTERR disable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 27. " DISABLE[27] ,System interrupt MPU_BOOTCFG_ERR disable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 25. " DISABLE[25] ,System interrupt UART0_INT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DISABLE[24] ,System interrupt T64P1_TINT34 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " DISABLE[23] ,System interrupt T64P1_TINT12 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " DISABLE[22] ,System interrupt T64P0_TINT34 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DISABLE[21] ,System interrupt T64P0_TINT12 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DISABLE[20] ,System interrupt SPI0_INT disable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x00 19. " DISABLE[19] ,System interrupt RTC_IRQS[1:0] disable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " DISABLE[18] ,System interrupt PSC0_ALLINT disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DISABLE[17] ,System interrupt MMCSD_INT1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DISABLE[16] ,System interrupt MMCSD_INT0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DISABLE[15] ,System interrupt IIC0_INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DISABLE[14] ,System interrupt EMIFA_INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DISABLE[13] ,System interrupt EDMA3_TC0_TCERRINT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DISABLE[12] ,System interrupt EDMA3_CC0_CCERRINT disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DISABLE[11] ,System interrupt EDMA3_CC0_CCINT disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
bitfld.long 0x00 10. " DISABLE[10] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DISABLE[9] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DISABLE[8] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DISABLE[7] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DISABLE[6] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DISABLE[5] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DISABLE[4] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DISABLE[3] ,System interrupt PRUSS disable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x00 10. " DISABLE[10] ,System interrupt PRU_EVTOUT7 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DISABLE[9] ,System interrupt PRU_EVTOUT6 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DISABLE[8] ,System interrupt PRU_EVTOUT5 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DISABLE[7] ,System interrupt PRU_EVTOUT4 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DISABLE[6] ,System interrupt PRU_EVTOUT3 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DISABLE[5] ,System interrupt PRU_EVTOUT2 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DISABLE[4] ,System interrupt PRU_EVTOUT1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DISABLE[3] ,System interrupt PRU_EVTOUT0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " DISABLE[10] ,System interrupt DMAX_EVTOUT7 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DISABLE[9] ,System interrupt DMAX_EVTOUT6 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DISABLE[8] ,System interrupt DMAX_EVTOUT5 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DISABLE[7] ,System interrupt DMAX_EVTOUT4 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DISABLE[6] ,System interrupt DMAX_EVTOUT3 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DISABLE[5] ,System interrupt DMAX_EVTOUT2 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DISABLE[4] ,System interrupt DMAX_EVTOUT1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DISABLE[3] ,System interrupt DMAX_EVTOUT0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " DISABLE[2] ,System interrupt NINT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISABLE[1] ,System interrupt COMMRX disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DISABLE[0] ,System interrupt COMMTX disable" "Disabled,Enabled"
|
|
line.long 0x04 "ECR2,System Interrupt Enable Clear Register 2"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x04 31. " DISABLE[63] ,System interrupt EHRPWM0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 29. " DISABLE[61] ,System interrupt UART2_INT disable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1806"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 28. " DISABLE[60] ,System interrupt USB1_R/WAKEUP disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DISABLE[59] ,System interrupt USB1_HCINT disable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 26. " DISABLE[58] ,System interrupt USB0_INT disable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1802")
|
|
bitfld.long 0x04 25. " DISABLE[57] ,System interrupt UHPI_ARMINT disable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24. " DISABLE[56] ,System interrupt SPI1_INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " DISABLE[55] ,System interrupt PSC1_ALLINT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " DISABLE[54] ,System interrupt MCASP_INT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DISABLE[53] ,System interrupt UART_INT1 disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="AM1802")
|
|
sif (cpu()!="AM1705")
|
|
bitfld.long 0x04 20. " DISABLE[52] ,System interrupt LCDC_INT disable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 19. " DISABLE[51] ,System interrupt IIC1_INT disable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 18. " DISABLE[50] ,System interrupt GPIO_B8INT disable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 17. " DISABLE[49] ,System interrupt GPIO_B7INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DISABLE[48] ,System interrupt GPIO_B6INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " DISABLE[47] ,System interrupt GPIO_B5INT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DISABLE[46] ,System interrupt GPIO_B4INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " DISABLE[45] ,System interrupt GPIO_B3INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " DISABLE[44] ,System interrupt GPIO_B2INT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DISABLE[43] ,System interrupt GPIO_B1INT disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DISABLE[42] ,System interrupt GPIO_B0INT disable" "Disabled,Enabled"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x04 9. " DISABLE[41] ,System interrupt DDR2_MEMERR disable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 9. " DISABLE[41] ,System interrupt EMIF_MEMERR disable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISABLE[40] ,System interrupt EMAC_C1MISC disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DISABLE[39] ,System interrupt EMAC_C1TX disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DISABLE[38] ,System interrupt EMAC_C1RX disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DISABLE[37] ,System interrupt EMAC_C1RXTHRESH disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DISABLE[36] ,System interrupt EMAC_C0MISC disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DISABLE[35] ,System interrupt EMAC_C0TX disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DISABLE[34] ,System interrupt EMAC_C0RX disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DISABLE[33] ,System interrupt EMAC_C0RXTHRESH disable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0. " DISABLE[32] ,System interrupt EDMA3_TC1_TCERRINT disable" "Disabled,Enabled"
|
|
line.long 0x08 "ECR3,System Interrupt Enable Clear Register 3"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806")
|
|
bitfld.long 0x08 30. " DISABLE[95] ,System interrupt EDMA_1TC0_ERRINT disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DISABLE[94] ,System interrupt EDMA_1CC0_ERRINT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " DISABLE[93] ,System interrupt EDMA_1CC0_INT disable" "Disabled,Enabled"
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 28. " DISABLE[92] ,System interrupt VPIF disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " DISABLE[91] ,System interrupt uPP_ALLINT disable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 26. " DISABLE[90] ,System interrupt ARMCLKSTOPREQ disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DISABLE[89] ,System interrupt T64P1_CMPINT7 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " DISABLE[88] ,System interrupt T64P1_CMPINT6 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " DISABLE[87] ,System interrupt T64P1_CMPINT5 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " DISABLE[86] ,System interrupt T64P1_CMPINT4 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " DISABLE[85] ,System interrupt T64P1_CMPINT3 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " DISABLE[84] ,System interrupt T64P1_CMPINT2 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " DISABLE[83] ,System interrupt T64P1_CMPINT1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " DISABLE[82] ,System interrupt T64P1_CMPINT0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " DISABLE[81] ,System interrupt T64P0_CMPINT7 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " DISABLE[80] ,System interrupt T64P0_CMPINT6 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " DISABLE[79] ,System interrupt T64P0_CMPINT5 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " DISABLE[78] ,System interrupt T64P0_CMPINT4 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " DISABLE[77] ,System interrupt T64P0_CMPINT3 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " DISABLE[76] ,System interrupt T64P0_CMPINT2 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DISABLE[75] ,System interrupt T64P0_CMPINT1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DISABLE[74] ,System interrupt T64P0_CMPINT0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 9. " DISABLE[73] ,System interrupt MMCSD1_INT1 raw status" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " DISABLE[72] ,System interrupt MMCSD1_INT0 raw status" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 9. " DISABLE[73] ,System interrupt EQEP1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " DISABLE[72] ,System interrupt EQEP0 disable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
bitfld.long 0x08 7. " DISABLE[71] ,System interrupt ECAP2 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DISABLE[70] ,System interrupt ECAP1 disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DISABLE[69] ,System interrupt ECAP0 disable" "Disabled,Enabled"
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
bitfld.long 0x08 4. " DISABLE[68] ,System interrupt T64P2_ALL disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " DISABLE[67] ,System interrupt SATA_INT disable" "Disabled,Enabled"
|
|
elif (cpu()=="AM1802")
|
|
bitfld.long 0x08 4. " DISABLE[68] ,System interrupt EHRPWM2TZ disable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 4. " DISABLE[68] ,System interrupt EHRPWM2TZ disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " DISABLE[67] ,System interrupt EHRPWM2 disable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
textline " "
|
|
bitfld.long 0x08 2. " DISABLE[66] ,System interrupt EHRPWM1TZ disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DISABLE[65] ,System interrupt EHRPWM1 disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DISABLE[64] ,System interrupt EHRPWM0TZ disable" "Disabled,Enabled"
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1806")
|
|
wgroup.long 0x38C++0x03
|
|
line.long 0x00 "ECR4,System Interrupt Enable Clear Register 4"
|
|
bitfld.long 0x00 4. " DISABLE[100] ,System interrupt MCBSP1_XINT disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DISABLE[99] ,System interrupt MCBSP1_RINT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DISABLE[98] ,System interrupt MCBSP0_XINT disable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DISABLE[97] ,System interrupt MCBSP0_RINT disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DISABLE[96] ,System interrupt T64P3_ALL disable" "Disabled,Enabled"
|
|
elif (cpu()=="AM1802")
|
|
wgroup.long 0x38C++0x03
|
|
line.long 0x00 "ECR4,System Interrupt Enable Clear Register 4"
|
|
bitfld.long 0x00 0. " DISABLE[96] ,System interrupt T64P3_ALL disable" "Disabled,Enabled"
|
|
endif
|
|
width 8.
|
|
tree "Channel Map Registers"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CMR0,Channel Map Register 0"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_3 ,Sets the channel for the system interrupt 3"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_2 ,Sets the channel for the system interrupt 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_1 ,Sets the channel for the system interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_0 ,Sets the channel for the system interrupt 0"
|
|
sif (cpu()!="AM1802")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "CMR1,Channel Map Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_7 ,Sets the channel for the system interrupt 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_6 ,Sets the channel for the system interrupt 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_5 ,Sets the channel for the system interrupt 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_4 ,Sets the channel for the system interrupt 4"
|
|
endif
|
|
group.long 0x408++0x1B
|
|
line.long 0x00 "CMR2,Channel Map Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_11 ,Sets the channel for the system interrupt 11"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_10 ,Sets the channel for the system interrupt 10"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_9 ,Sets the channel for the system interrupt 9"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_8 ,Sets the channel for the system interrupt 8"
|
|
endif
|
|
line.long 0x04 "CMR3,Channel Map Register 3"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CHNL_15 ,Sets the channel for the system interrupt 15"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CHNL_14 ,Sets the channel for the system interrupt 14"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CHNL_13 ,Sets the channel for the system interrupt 13"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHNL_12 ,Sets the channel for the system interrupt 12"
|
|
line.long 0x08 "CMR4,Channel Map Register 4"
|
|
sif (cpu()!="AM1705")
|
|
hexmask.long.byte 0x08 24.--31. 1. " CHNL_19 ,Sets the channel for the system interrupt 19"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x08 16.--23. 1. " CHNL_18 ,Sets the channel for the system interrupt 18"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CHNL_17 ,Sets the channel for the system interrupt 17"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CHNL_16 ,Sets the channel for the system interrupt 16"
|
|
line.long 0x0c "CMR5,Channel Map Register 5"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " CHNL_23 ,Sets the channel for the system interrupt 23"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " CHNL_22 ,Sets the channel for the system interrupt 22"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " CHNL_21 ,Sets the channel for the system interrupt 21"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " CHNL_20 ,Sets the channel for the system interrupt 20"
|
|
line.long 0x10 "CMR6,Channel Map Register 6"
|
|
hexmask.long.byte 0x10 24.--31. 1. " CHNL_27 ,Sets the channel for the system interrupt 27"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CHNL_25 ,Sets the channel for the system interrupt 25"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CHNL_24 ,Sets the channel for the system interrupt 24"
|
|
line.long 0x14 "CMR7,Channel Map Register 7"
|
|
hexmask.long.byte 0x14 24.--31. 1. " CHNL_31 ,Sets the channel for the system interrupt 31"
|
|
hexmask.long.byte 0x14 16.--23. 1. " CHNL_30 ,Sets the channel for the system interrupt 30"
|
|
hexmask.long.byte 0x14 8.--15. 1. " CHNL_29 ,Sets the channel for the system interrupt 29"
|
|
hexmask.long.byte 0x14 0.--7. 1. " CHNL_28 ,Sets the channel for the system interrupt 28"
|
|
line.long 0x18 "CMR8,Channel Map Register 8"
|
|
sif (cpu()!="AM1806")
|
|
hexmask.long.byte 0x18 24.--31. 1. " CHNL_35 ,Sets the channel for the system interrupt 35"
|
|
hexmask.long.byte 0x18 16.--23. 1. " CHNL_34 ,Sets the channel for the system interrupt 34"
|
|
hexmask.long.byte 0x18 8.--15. 1. " CHNL_33 ,Sets the channel for the system interrupt 33"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x18 0.--7. 1. " CHNL_32 ,Sets the channel for the system interrupt 32"
|
|
sif (cpu()!="AM1806")
|
|
group.long 0x424++0x3
|
|
line.long 0x00 "CMR9,Channel Map Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_39 ,Sets the channel for the system interrupt 39"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_38 ,Sets the channel for the system interrupt 38"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_37 ,Sets the channel for the system interrupt 37"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_36 ,Sets the channel for the system interrupt 36"
|
|
endif
|
|
group.long 0x428++0x23
|
|
line.long 0x00 "CMR10,Channel Map Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_43 ,Sets the channel for the system interrupt 43"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_42 ,Sets the channel for the system interrupt 42"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_41 ,Sets the channel for the system interrupt 41"
|
|
sif (cpu()!="AM1806")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_40 ,Sets the channel for the system interrupt 40"
|
|
endif
|
|
line.long 0x04 "CMR11,Channel Map Register 11"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CHNL_47 ,Sets the channel for the system interrupt 47"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CHNL_46 ,Sets the channel for the system interrupt 46"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CHNL_45 ,Sets the channel for the system interrupt 45"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHNL_44 ,Sets the channel for the system interrupt 44"
|
|
line.long 0x08 "CMR12,Channel Map Register 12"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x08 24.--31. 1. " CHNL_51 ,Sets the channel for the system interrupt 51"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1806"||CPU()=="AM1808"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.byte 0x08 16.--23. 1. " CHNL_50 ,Sets the channel for the system interrupt 50"
|
|
endif
|
|
hexmask.long.byte 0x08 8.--15. 1. " CHNL_49 ,Sets the channel for the system interrupt 49"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CHNL_48 ,Sets the channel for the system interrupt 48"
|
|
line.long 0x0c "CMR13,Channel Map Register 13"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " CHNL_55 ,Sets the channel for the system interrupt 55"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " CHNL_54 ,Sets the channel for the system interrupt 54"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " CHNL_53 ,Sets the channel for the system interrupt 53"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1802")
|
|
hexmask.long.byte 0x0c 0.--7. 1. " CHNL_52 ,Sets the channel for the system interrupt 52"
|
|
endif
|
|
line.long 0x10 "CMR14,Channel Map Register 14"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1806"&&cpu()!="AM1802")
|
|
hexmask.long.byte 0x10 24.--31. 1. " CHNL_59 ,Sets the channel for the system interrupt 59"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CHNL_58 ,Sets the channel for the system interrupt 58"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CHNL_57 ,Sets the channel for the system interrupt 57"
|
|
elif (CPU()=="AM1806")
|
|
hexmask.long.byte 0x10 16.--23. 1. " CHNL_58 ,Sets the channel for the system interrupt 58"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CHNL_57 ,Sets the channel for the system interrupt 57"
|
|
else
|
|
hexmask.long.byte 0x10 16.--23. 1. " CHNL_58 ,Sets the channel for the system interrupt 58"
|
|
endif
|
|
hexmask.long.byte 0x10 0.--7. 1. " CHNL_56 ,Sets the channel for the system interrupt 56"
|
|
line.long 0x14 "CMR15,Channel Map Register 15"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x14 24.--31. 1. " CHNL_63 ,Sets the channel for the system interrupt 63"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x14 8.--15. 1. " CHNL_61 ,Sets the channel for the system interrupt 61"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1806"&&cpu()!="AM1802")
|
|
hexmask.long.byte 0x14 0.--7. 1. " CHNL_60 ,Sets the channel for the system interrupt 60"
|
|
endif
|
|
sif (cpu()!="AM1802")
|
|
group.long 0x440++0x3
|
|
line.long 0x00 "CMR16,Channel Map Register 16"
|
|
sif (cpu()!="AM1806")
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_67 ,Sets the channel for the system interrupt 67"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_66 ,Sets the channel for the system interrupt 66"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_65 ,Sets the channel for the system interrupt 65"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_64 ,Sets the channel for the system interrupt 64"
|
|
endif
|
|
group.long 0x444++0x23
|
|
line.long 0x00 "CMR17,Channel Map Register 17"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_71 ,Sets the channel for the system interrupt 71"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_70 ,Sets the channel for the system interrupt 70"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_69 ,Sets the channel for the system interrupt 69"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_68 ,Sets the channel for the system interrupt 68"
|
|
line.long 0x04 "CMR18,Channel Map Register 18"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CHNL_75 ,Sets the channel for the system interrupt 75"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CHNL_74 ,Sets the channel for the system interrupt 74"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x04 8.--15. 1. " CHNL_73 ,Sets the channel for the system interrupt 73"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHNL_72 ,Sets the channel for the system interrupt 72"
|
|
endif
|
|
line.long 0x08 "CMR19,Channel Map Register 19"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CHNL_79 ,Sets the channel for the system interrupt 79"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CHNL_78 ,Sets the channel for the system interrupt 78"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CHNL_77 ,Sets the channel for the system interrupt 77"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CHNL_76 ,Sets the channel for the system interrupt 76"
|
|
line.long 0x0C "CMR20,Channel Map Register 20"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " CHNL_83 ,Sets the channel for the system interrupt 83"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " CHNL_82 ,Sets the channel for the system interrupt 82"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CHNL_81 ,Sets the channel for the system interrupt 81"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CHNL_80 ,Sets the channel for the system interrupt 80"
|
|
line.long 0x10 "CMR21,Channel Map Register 21"
|
|
hexmask.long.byte 0x10 24.--31. 1. " CHNL_87 ,Sets the channel for the system interrupt 87"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CHNL_86 ,Sets the channel for the system interrupt 86"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CHNL_85 ,Sets the channel for the system interrupt 85"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CHNL_84 ,Sets the channel for the system interrupt 84"
|
|
line.long 0x14 "CMR22,Channel Map Register 22"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1806"||CPU()=="AM1808"||CPU()=="AM1810")
|
|
hexmask.long.byte 0x14 24.--31. 1. " CHNL_91 ,Sets the channel for the system interrupt 91"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x14 16.--23. 1. " CHNL_90 ,Sets the channel for the system interrupt 90"
|
|
hexmask.long.byte 0x14 8.--15. 1. " CHNL_89 ,Sets the channel for the system interrupt 89"
|
|
hexmask.long.byte 0x14 0.--7. 1. " CHNL_88 ,Sets the channel for the system interrupt 88"
|
|
sif (CPU()=="OMAP-L138"||CPU()=="AM1806"||CPU()=="AM1808"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
group.long 0x45C++0x07
|
|
line.long 0x00 "CMR23,Channel Map Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CHNL_95 ,Sets the channel for the system interrupt 95"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CHNL_94 ,Sets the channel for the system interrupt 94"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHNL_93 ,Sets the channel for the system interrupt 93"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_92 ,Sets the channel for the system interrupt 92"
|
|
endif
|
|
line.long 0x04 "CMR24,Channel Map Register 24"
|
|
sif (cpu()!="AM1802")
|
|
hexmask.long.byte 0x04 24.--31. 1. " CHNL_99 ,Sets the channel for the system interrupt 99"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CHNL_98 ,Sets the channel for the system interrupt 98"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CHNL_97 ,Sets the channel for the system interrupt 97"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHNL_96 ,Sets the channel for the system interrupt 96"
|
|
sif (cpu()!="AM1802")
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "CMR25,Channel Map Register 25"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CHNL_100 ,Sets the channel for the system interrupt 100"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
rgroup.long 0x900++0x07
|
|
line.long 0x00 "HIPIR1,Host Interrupt Prioritized Index Register 1"
|
|
bitfld.long 0x00 31. " NONE ,No Interrupt is pending" "No,Yes"
|
|
hexmask.long.word 0x00 0.--9. 1. " PRI_INDX ,Interrupt number of the highest priority pending interrupt for FIQ host interrupt"
|
|
line.long 0x04 "HIPIR2,Host Interrupt Prioritized Index Register 2"
|
|
bitfld.long 0x04 31. " NONE ,No Interrupt is pending" "No,Yes"
|
|
hexmask.long.word 0x04 0.--9. 1. " PRI_INDX ,Interrupt number of the highest priority pending interrupt for IRQ host interrupt"
|
|
group.long 0x1100++0x07
|
|
line.long 0x00 "HINLR1,Host Interrupt Nesting Level Register 1"
|
|
bitfld.long 0x00 31. " OVERRIDE ,Override the auto updating of the NEST_LVL" "Not overridden,Overridden"
|
|
hexmask.long.word 0x00 0.--8. 1. " NEST_LVL ,Nesting level for the FIQ host interrupt"
|
|
line.long 0x04 "HINLR2,Host Interrupt Nesting Level Register 2"
|
|
bitfld.long 0x04 31. " OVERRIDE ,Override the auto updating of the NEST_LVL" "Not overridden,Overridden"
|
|
hexmask.long.word 0x04 0.--8. 1. " NEST_LVL ,Nesting level for the IRQ host interrupt"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "HIER,Host Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " IRQ ,Enable of IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FIQ ,Enable of FIQ" "Disabled,Enabled"
|
|
rgroup.long 0x1600++0x07
|
|
line.long 0x00 "HIPVR1,Host Interrupt Prioritized Vector Register 1"
|
|
line.long 0x04 "HIPVR2,Host Interrupt Prioritized Vector Register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "GPIO (General-Purpose Input/Output)"
|
|
base asd:0x01e26000
|
|
width 8.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "BINTEN,GPIO Interrupt Per-Bank Enable Register"
|
|
sif (cpu()=="AM1705"||cpu()=="AM1707")
|
|
bitfld.long 0x00 8. " EN8 ,Bank 8 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " EN7 ,Bank 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN6 ,Bank 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN5 ,Bank 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN4 ,Bank 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN3 ,Bank 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN2 ,Bank 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN1 ,Bank 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN0 ,Bank 0 interrupt enable" "Disabled,Enabled"
|
|
width 16.
|
|
group.long 0x10++0x3 "GPIO Banks 0 and 1"
|
|
line.long 0x00 "DIR01,GPIO Banks 0 and 1 Direction Register"
|
|
bitfld.long 0x00 31. " B1P15DIR ,Bank 1 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 30. " B1P14DIR ,Bank 1 Pin 14 direction" "Output,Input"
|
|
bitfld.long 0x00 29. " B1P13DIR ,Bank 1 Pin 13 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B1P12DIR ,Bank 1 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 27. " B1P11DIR ,Bank 1 Pin 11 direction" "Output,Input"
|
|
bitfld.long 0x00 26. " B1P10DIR ,Bank 1 Pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B1P9DIR ,Bank 1 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 24. " B1P8DIR ,Bank 1 Pin 8 direction" "Output,Input"
|
|
bitfld.long 0x00 23. " B1P7DIR ,Bank 1 Pin 7 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B1P6DIR ,Bank 1 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 21. " B1P5DIR ,Bank 1 Pin 5 direction" "Output,Input"
|
|
bitfld.long 0x00 20. " B1P4DIR ,Bank 1 Pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B1P3DIR ,Bank 1 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 18. " B1P2DIR ,Bank 1 Pin 2 direction" "Output,Input"
|
|
bitfld.long 0x00 17. " B1P1DIR ,Bank 1 Pin 1 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B1P0DIR ,Bank 1 Pin 0 direction" "Output,Input"
|
|
bitfld.long 0x00 15. " B0P15DIR ,Bank 0 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 14. " B0P14DIR ,Bank 0 Pin 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B0P13DIR ,Bank 0 Pin 13 direction" "Output,Input"
|
|
bitfld.long 0x00 12. " B0P12DIR ,Bank 0 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 11. " B0P11DIR ,Bank 0 Pin 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B0P10DIR ,Bank 0 Pin 10 direction" "Output,Input"
|
|
bitfld.long 0x00 9. " B0P9DIR ,Bank 0 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 8. " B0P8DIR ,Bank 0 Pin 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B0P7DIR ,Bank 0 Pin 7 direction" "Output,Input"
|
|
bitfld.long 0x00 6. " B0P6DIR ,Bank 0 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 5. " B0P5DIR ,Bank 0 Pin 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B0P4DIR ,Bank 0 Pin 4 direction" "Output,Input"
|
|
bitfld.long 0x00 3. " B0P3DIR ,Bank 0 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 2. " B0P2DIR ,Bank 0 Pin 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B0P1DIR ,Bank 0 Pin 1 direction" "Output,Input"
|
|
bitfld.long 0x00 0. " B0P0DIR ,Bank 0 Pin 0 direction" "Output,Input"
|
|
group.long (0x10+0x04)++0x3
|
|
line.long 0x00 "OUT_DATA01,GPIO Banks 0 and 1 Output Data Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " B1P15OUT_set/clr ,Output drive state of Bank 1 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " B1P14OUT_set/clr ,Output drive state of Bank 1 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " B1P13OUT_set/clr ,Output drive state of Bank 1 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " B1P12OUT_set/clr ,Output drive state of Bank 1 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " B1P11OUT_set/clr ,Output drive state of Bank 1 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " B1P10OUT_set/clr ,Output drive state of Bank 1 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " B1P9OUT_set/clr ,Output drive state of Bank 1 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " B1P8OUT_set/clr ,Output drive state of Bank 1 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " B1P7OUT_set/clr ,Output drive state of Bank 1 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " B1P26UT_set/clr ,Output drive state of Bank 1 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " B1P5OUT_set/clr ,Output drive state of Bank 1 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " B1P4OUT_set/clr ,Output drive state of Bank 1 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " B1P3OUT_set/clr ,Output drive state of Bank 1 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " B1P2OUT_set/clr ,Output drive state of Bank 1 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " B1P1OUT_set/clr ,Output drive state of Bank 1 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " B1P0OUT_set/clr ,Output drive state of Bank 1 GPIO pin 0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " B0P15OUT_set/clr ,Output drive state of Bank 0 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " B0P14OUT_set/clr ,Output drive state of Bank 0 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " B0P13OUT_set/clr ,Output drive state of Bank 0 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " B0P12OUT_set/clr ,Output drive state of Bank 0 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " B0P11OUT_set/clr ,Output drive state of Bank 0 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " B0P10OUT_set/clr ,Output drive state of Bank 0 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " B0P9OUT_set/clr ,Output drive state of Bank 0 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " B0P8OUT_set/clr ,Output drive state of Bank 0 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " B0P7OUT_set/clr ,Output drive state of Bank 0 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " B0P6OUT_set/clr ,Output drive state of Bank 0 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " B0P5OUT_set/clr ,Output drive state of Bank 0 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " B0P4OUT_set/clr ,Output drive state of Bank 0 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " B0P3OUT_set/clr ,Output drive state of Bank 0 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " B0P2OUT_set/clr ,Output drive state of Bank 0 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " B0P1OUT_set/clr ,Output drive state of Bank 0 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " B0P0OUT_set/clr ,Output drive state of Bank 0 GPIO pin 0" "Low,High"
|
|
group.long (0x10+0x10)++0x3
|
|
line.long 0x00 "IN_DATA01,GPIO Banks 0 and 1 Input Data Register"
|
|
bitfld.long 0x00 31. " B1P15IN ,Status of Bank 1 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 30. " B1P14IN ,Status of Bank 1 GPIO pin 14" "Low,High"
|
|
bitfld.long 0x00 29. " B1P13IN ,Status of Bank 1 GPIO pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B1P12IN ,Status of Bank 1 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 27. " B1P11IN ,Status of Bank 1 GPIO pin 11" "Low,High"
|
|
bitfld.long 0x00 26. " B1P10IN ,Status of Bank 1 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B1P9IN ,Status of Bank 1 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 24. " B1P8IN ,Status of Bank 1 GPIO pin 8" "Low,High"
|
|
bitfld.long 0x00 23. " B1P7IN ,Status of Bank 1 GPIO pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B1P6IN ,Status of Bank 1 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 21. " B1P5IN ,Status of Bank 1 GPIO pin 5" "Low,High"
|
|
bitfld.long 0x00 20. " B1P4IN ,Status of Bank 1 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B1P3IN ,Status of Bank 1 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 18. " B1P2IN ,Status of Bank 1 GPIO pin 2" "Low,High"
|
|
bitfld.long 0x00 17. " B1P1IN ,Status of Bank 1 GPIO pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B1P0IN ,Status of Bank 1 GPIO pin 0" "Low,High"
|
|
bitfld.long 0x00 15. " B0P15IN ,Status of Bank 0 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " B0P14IN ,Status of Bank 0 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B0P13IN ,Status of Bank 0 GPIO pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " B0P12IN ,Status of Bank 0 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " B0P11IN ,Status of Bank 0 GPIO pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B0P10IN ,Status of Bank 0 GPIO pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " B0P9IN ,Status of Bank 0 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " B0P8IN ,Status of Bank 0 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B0P7IN ,Status of Bank 0 GPIO pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " B0P6IN ,Status of Bank 0 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " B0P5IN ,Status of Bank 0 GPIO pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B0P4IN ,Status of Bank 0 GPIO pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " B0P3IN ,Status of Bank 0 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " B0P2IN ,Status of Bank 0 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B0P1IN ,Status of Bank 0 GPIO pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " B0P0IN ,Status of Bank 0 GPIO pin 0" "Low,High"
|
|
width 16.
|
|
group.long (0x10+0x14)++0x3
|
|
line.long 0x00 "SET_RIS_TRIG01,GPIO Banks 0 and 1 Set Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B1P15SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B1P14SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B1P13SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B1P12SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B1P11SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B1P10SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B1P9SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B1P8SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B1P7SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B1P6SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B1P5SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B1P4SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B1P3SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B1P2SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B1P1SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B1P0SETRIS ,Enable rising edge interrupt detection on Bank 1 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B0P15SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B0P14SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B0P13SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B0P12SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B0P11SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B0P10SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B0P9SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B0P8SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B0P7SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B0P6SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B0P5SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B0P4SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B0P3SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B0P2SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B0P1SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B0P0SETRIS ,Enable rising edge interrupt detection on Bank 0 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x10+0x18)++0x3
|
|
line.long 0x00 "CLR_RIS_TRIG01,GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B1P15CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B1P14CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B1P13CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B1P12CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B1P11CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B1P10CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B1P9CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B1P8CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B1P7CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B1P6CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B1P5CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B1P4CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B1P3CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B1P2CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B1P1CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B1P0CLRRIS ,Disable rising edge interrupt detection on Bank 1 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B0P15CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B0P14CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B0P13CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B0P12CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B0P11CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B0P10CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B0P9CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B0P8CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B0P7CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B0P6CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B0P5CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B0P4CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B0P3CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B0P2CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B0P1CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B0P0CLRRIS ,Disable rising edge interrupt detection on Bank 0 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x10+0x1c)++0x3
|
|
line.long 0x00 "SET_FAL_TRIG01,GPIO Banks 0 and 1 Set Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B1P15SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B1P14SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B1P13SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B1P12SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B1P11SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B1P10SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B1P9SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B1P8SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B1P7SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B1P6SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B1P5SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B1P4SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B1P3SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B1P2SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B1P1SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B1P0SETFAL ,Enable falling edge interrupt detection on Bank 1 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B0P15SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B0P14SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B0P13SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B0P12SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B0P11SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B0P10SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B0P9SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B0P8SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B0P7SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B0P6SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B0P5SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B0P4SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B0P3SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B0P2SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B0P1SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B0P0SETFAL ,Enable falling edge interrupt detection on Bank 0 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x10+0x20)++0x3
|
|
line.long 0x00 "CLR_FAL_TRIG01,GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B1P15CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B1P14CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B1P13CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B1P12CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B1P11CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B1P10CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B1P9CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B1P8CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B1P7CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B1P6CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B1P5CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B1P4CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B1P3CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B1P2CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B1P1CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B1P0CLRFAL ,Disable falling edge interrupt detection on Bank 1 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B0P15CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B0P14CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B0P13CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B0P12CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B0P11CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B0P10CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B0P9CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B0P8CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B0P7CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B0P6CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B0P5CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B0P4CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B0P3CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B0P2CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B0P1CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B0P0CLRFAL ,Disable falling edge interrupt detection on Bank 0 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x10+0x24)++0x3
|
|
line.long 0x00 "INTSTAT01,GPIO Banks 0 and 1 Interrupt Status Register"
|
|
eventfld.long 0x00 31. " B1P15STAT ,Interrupt status of Bank 1 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " B1P14STAT ,Interrupt status of Bank 1 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 29. " B1P13STAT ,Interrupt status of Bank 1 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " B1P12STAT ,Interrupt status of Bank 1 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " B1P11STAT ,Interrupt status of Bank 1 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " B1P10STAT ,Interrupt status of Bank 1 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " B1P9STAT ,Interrupt status of Bank 1 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " B1P8STAT ,Interrupt status of Bank 1 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " B1P7STAT ,Interrupt status of Bank 1 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " B1P6STAT ,Interrupt status of Bank 1 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " B1P5STAT ,Interrupt status of Bank 1 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " B1P4STAT ,Interrupt status of Bank 1 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " B1P3STAT ,Interrupt status of Bank 1 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " B1P2STAT ,Interrupt status of Bank 1 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " B1P1STAT ,Interrupt status of Bank 1 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " B1P0STAT ,Interrupt status of Bank 1 GPIO pin 0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " B0P15STAT ,Interrupt status of Bank 0 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " B0P14STAT ,Interrupt status of Bank 0 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " B0P13STAT ,Interrupt status of Bank 0 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " B0P12STAT ,Interrupt status of Bank 0 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " B0P11STAT ,Interrupt status of Bank 0 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " B0P10STAT ,Interrupt status of Bank 0 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " B0P9STAT ,Interrupt status of Bank 0 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " B0P8STAT ,Interrupt status of Bank 0 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " B0P7STAT ,Interrupt status of Bank 0 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " B0P6STAT ,Interrupt status of Bank 0 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " B0P5STAT ,Interrupt status of Bank 0 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " B0P4STAT ,Interrupt status of Bank 0 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " B0P3STAT ,Interrupt status of Bank 0 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " B0P2STAT ,Interrupt status of Bank 0 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " B0P1STAT ,Interrupt status of Bank 0 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " B0P0STAT ,Interrupt status of Bank 0 GPIO pin 0" "Not pending,Pending"
|
|
group.long 0x38++0x3 "GPIO Banks 2 and 3"
|
|
line.long 0x00 "DIR23,GPIO Banks 2 and 3 Direction Register"
|
|
bitfld.long 0x00 31. " B3P15DIR ,Bank 3 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 30. " B3P14DIR ,Bank 3 Pin 14 direction" "Output,Input"
|
|
bitfld.long 0x00 29. " B3P13DIR ,Bank 3 Pin 13 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B3P12DIR ,Bank 3 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 27. " B3P11DIR ,Bank 3 Pin 11 direction" "Output,Input"
|
|
bitfld.long 0x00 26. " B3P10DIR ,Bank 3 Pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B3P9DIR ,Bank 3 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 24. " B3P8DIR ,Bank 3 Pin 8 direction" "Output,Input"
|
|
bitfld.long 0x00 23. " B3P7DIR ,Bank 3 Pin 7 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B3P6DIR ,Bank 3 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 21. " B3P5DIR ,Bank 3 Pin 5 direction" "Output,Input"
|
|
bitfld.long 0x00 20. " B3P4DIR ,Bank 3 Pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B3P3DIR ,Bank 3 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 18. " B3P2DIR ,Bank 3 Pin 2 direction" "Output,Input"
|
|
bitfld.long 0x00 17. " B3P1DIR ,Bank 3 Pin 1 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B3P0DIR ,Bank 3 Pin 0 direction" "Output,Input"
|
|
bitfld.long 0x00 15. " B2P15DIR ,Bank 2 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 14. " B2P14DIR ,Bank 2 Pin 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B2P13DIR ,Bank 2 Pin 13 direction" "Output,Input"
|
|
bitfld.long 0x00 12. " B2P12DIR ,Bank 2 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 11. " B2P11DIR ,Bank 2 Pin 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B2P10DIR ,Bank 2 Pin 10 direction" "Output,Input"
|
|
bitfld.long 0x00 9. " B2P9DIR ,Bank 2 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 8. " B2P8DIR ,Bank 2 Pin 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B2P7DIR ,Bank 2 Pin 7 direction" "Output,Input"
|
|
bitfld.long 0x00 6. " B2P6DIR ,Bank 2 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 5. " B2P5DIR ,Bank 2 Pin 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B2P4DIR ,Bank 2 Pin 4 direction" "Output,Input"
|
|
bitfld.long 0x00 3. " B2P3DIR ,Bank 2 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 2. " B2P2DIR ,Bank 2 Pin 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B2P1DIR ,Bank 2 Pin 1 direction" "Output,Input"
|
|
bitfld.long 0x00 0. " B2P0DIR ,Bank 2 Pin 0 direction" "Output,Input"
|
|
group.long (0x38+0x04)++0x3
|
|
line.long 0x00 "OUT_DATA23,GPIO Banks 2 and 3 Output Data Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " B3P15OUT_set/clr ,Output drive state of Bank 3 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " B3P14OUT_set/clr ,Output drive state of Bank 3 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " B3P13OUT_set/clr ,Output drive state of Bank 3 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " B3P12OUT_set/clr ,Output drive state of Bank 3 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " B3P11OUT_set/clr ,Output drive state of Bank 3 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " B3P10OUT_set/clr ,Output drive state of Bank 3 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " B3P9OUT_set/clr ,Output drive state of Bank 3 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " B3P8OUT_set/clr ,Output drive state of Bank 3 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " B3P7OUT_set/clr ,Output drive state of Bank 3 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " B3P26UT_set/clr ,Output drive state of Bank 3 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " B3P5OUT_set/clr ,Output drive state of Bank 3 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " B3P4OUT_set/clr ,Output drive state of Bank 3 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " B3P3OUT_set/clr ,Output drive state of Bank 3 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " B3P2OUT_set/clr ,Output drive state of Bank 3 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " B3P1OUT_set/clr ,Output drive state of Bank 3 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " B3P0OUT_set/clr ,Output drive state of Bank 3 GPIO pin 0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " B2P15OUT_set/clr ,Output drive state of Bank 2 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " B2P14OUT_set/clr ,Output drive state of Bank 2 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " B2P13OUT_set/clr ,Output drive state of Bank 2 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " B2P12OUT_set/clr ,Output drive state of Bank 2 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " B2P11OUT_set/clr ,Output drive state of Bank 2 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " B2P10OUT_set/clr ,Output drive state of Bank 2 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " B2P9OUT_set/clr ,Output drive state of Bank 2 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " B2P8OUT_set/clr ,Output drive state of Bank 2 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " B2P7OUT_set/clr ,Output drive state of Bank 2 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " B2P6OUT_set/clr ,Output drive state of Bank 2 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " B2P5OUT_set/clr ,Output drive state of Bank 2 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " B2P4OUT_set/clr ,Output drive state of Bank 2 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " B2P3OUT_set/clr ,Output drive state of Bank 2 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " B2P2OUT_set/clr ,Output drive state of Bank 2 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " B2P1OUT_set/clr ,Output drive state of Bank 2 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " B2P0OUT_set/clr ,Output drive state of Bank 2 GPIO pin 0" "Low,High"
|
|
group.long (0x38+0x10)++0x3
|
|
line.long 0x00 "IN_DATA23,GPIO Banks 2 and 3 Input Data Register"
|
|
bitfld.long 0x00 31. " B3P15IN ,Status of Bank 3 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 30. " B3P14IN ,Status of Bank 3 GPIO pin 14" "Low,High"
|
|
bitfld.long 0x00 29. " B3P13IN ,Status of Bank 3 GPIO pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B3P12IN ,Status of Bank 3 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 27. " B3P11IN ,Status of Bank 3 GPIO pin 11" "Low,High"
|
|
bitfld.long 0x00 26. " B3P10IN ,Status of Bank 3 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B3P9IN ,Status of Bank 3 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 24. " B3P8IN ,Status of Bank 3 GPIO pin 8" "Low,High"
|
|
bitfld.long 0x00 23. " B3P7IN ,Status of Bank 3 GPIO pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B3P6IN ,Status of Bank 3 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 21. " B3P5IN ,Status of Bank 3 GPIO pin 5" "Low,High"
|
|
bitfld.long 0x00 20. " B3P4IN ,Status of Bank 3 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B3P3IN ,Status of Bank 3 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 18. " B3P2IN ,Status of Bank 3 GPIO pin 2" "Low,High"
|
|
bitfld.long 0x00 17. " B3P1IN ,Status of Bank 3 GPIO pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B3P0IN ,Status of Bank 3 GPIO pin 0" "Low,High"
|
|
bitfld.long 0x00 15. " B2P15IN ,Status of Bank 2 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " B2P14IN ,Status of Bank 2 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B2P13IN ,Status of Bank 2 GPIO pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " B2P12IN ,Status of Bank 2 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " B2P11IN ,Status of Bank 2 GPIO pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B2P10IN ,Status of Bank 2 GPIO pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " B2P9IN ,Status of Bank 2 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " B2P8IN ,Status of Bank 2 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B2P7IN ,Status of Bank 2 GPIO pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " B2P6IN ,Status of Bank 2 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " B2P5IN ,Status of Bank 2 GPIO pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B2P4IN ,Status of Bank 2 GPIO pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " B2P3IN ,Status of Bank 2 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " B2P2IN ,Status of Bank 2 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B2P1IN ,Status of Bank 2 GPIO pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " B2P0IN ,Status of Bank 2 GPIO pin 0" "Low,High"
|
|
width 16.
|
|
group.long (0x38+0x14)++0x3
|
|
line.long 0x00 "SET_RIS_TRIG23,GPIO Banks 2 and 3 Set Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B3P15SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B3P14SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B3P13SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B3P12SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B3P11SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B3P10SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B3P9SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B3P8SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B3P7SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B3P6SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B3P5SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B3P4SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B3P3SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B3P2SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B3P1SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B3P0SETRIS ,Enable rising edge interrupt detection on Bank 3 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B2P15SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B2P14SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B2P13SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B2P12SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B2P11SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B2P10SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B2P9SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B2P8SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B2P7SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B2P6SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B2P5SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B2P4SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B2P3SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B2P2SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B2P1SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B2P0SETRIS ,Enable rising edge interrupt detection on Bank 2 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x38+0x18)++0x3
|
|
line.long 0x00 "CLR_RIS_TRIG23,GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B3P15CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B3P14CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B3P13CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B3P12CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B3P11CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B3P10CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B3P9CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B3P8CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B3P7CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B3P6CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B3P5CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B3P4CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B3P3CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B3P2CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B3P1CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B3P0CLRRIS ,Disable rising edge interrupt detection on Bank 3 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B2P15CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B2P14CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B2P13CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B2P12CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B2P11CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B2P10CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B2P9CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B2P8CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B2P7CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B2P6CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B2P5CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B2P4CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B2P3CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B2P2CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B2P1CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B2P0CLRRIS ,Disable rising edge interrupt detection on Bank 2 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x38+0x1c)++0x3
|
|
line.long 0x00 "SET_FAL_TRIG23,GPIO Banks 2 and 3 Set Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B3P15SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B3P14SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B3P13SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B3P12SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B3P11SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B3P10SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B3P9SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B3P8SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B3P7SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B3P6SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B3P5SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B3P4SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B3P3SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B3P2SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B3P1SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B3P0SETFAL ,Enable falling edge interrupt detection on Bank 3 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B2P15SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B2P14SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B2P13SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B2P12SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B2P11SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B2P10SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B2P9SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B2P8SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B2P7SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B2P6SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B2P5SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B2P4SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B2P3SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B2P2SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B2P1SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B2P0SETFAL ,Enable falling edge interrupt detection on Bank 2 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x38+0x20)++0x3
|
|
line.long 0x00 "CLR_FAL_TRIG23,GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B3P15CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B3P14CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B3P13CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B3P12CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B3P11CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B3P10CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B3P9CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B3P8CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B3P7CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B3P6CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B3P5CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B3P4CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B3P3CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B3P2CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B3P1CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B3P0CLRFAL ,Disable falling edge interrupt detection on Bank 3 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B2P15CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B2P14CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B2P13CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B2P12CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B2P11CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B2P10CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B2P9CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B2P8CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B2P7CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B2P6CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B2P5CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B2P4CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B2P3CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B2P2CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B2P1CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B2P0CLRFAL ,Disable falling edge interrupt detection on Bank 2 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x38+0x24)++0x3
|
|
line.long 0x00 "INTSTAT23,GPIO Banks 2 and 3 Interrupt Status Register"
|
|
eventfld.long 0x00 31. " B3P15STAT ,Interrupt status of Bank 3 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " B3P14STAT ,Interrupt status of Bank 3 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 29. " B3P13STAT ,Interrupt status of Bank 3 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " B3P12STAT ,Interrupt status of Bank 3 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " B3P11STAT ,Interrupt status of Bank 3 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " B3P10STAT ,Interrupt status of Bank 3 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " B3P9STAT ,Interrupt status of Bank 3 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " B3P8STAT ,Interrupt status of Bank 3 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " B3P7STAT ,Interrupt status of Bank 3 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " B3P6STAT ,Interrupt status of Bank 3 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " B3P5STAT ,Interrupt status of Bank 3 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " B3P4STAT ,Interrupt status of Bank 3 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " B3P3STAT ,Interrupt status of Bank 3 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " B3P2STAT ,Interrupt status of Bank 3 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " B3P1STAT ,Interrupt status of Bank 3 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " B3P0STAT ,Interrupt status of Bank 3 GPIO pin 0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " B2P15STAT ,Interrupt status of Bank 2 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " B2P14STAT ,Interrupt status of Bank 2 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " B2P13STAT ,Interrupt status of Bank 2 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " B2P12STAT ,Interrupt status of Bank 2 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " B2P11STAT ,Interrupt status of Bank 2 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " B2P10STAT ,Interrupt status of Bank 2 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " B2P9STAT ,Interrupt status of Bank 2 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " B2P8STAT ,Interrupt status of Bank 2 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " B2P7STAT ,Interrupt status of Bank 2 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " B2P6STAT ,Interrupt status of Bank 2 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " B2P5STAT ,Interrupt status of Bank 2 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " B2P4STAT ,Interrupt status of Bank 2 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " B2P3STAT ,Interrupt status of Bank 2 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " B2P2STAT ,Interrupt status of Bank 2 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " B2P1STAT ,Interrupt status of Bank 2 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " B2P0STAT ,Interrupt status of Bank 2 GPIO pin 0" "Not pending,Pending"
|
|
group.long 0x60++0x3 "GPIO Banks 4 and 5"
|
|
line.long 0x00 "DIR45,GPIO Banks 4 and 5 Direction Register"
|
|
bitfld.long 0x00 31. " B5P15DIR ,Bank 5 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 30. " B5P14DIR ,Bank 5 Pin 14 direction" "Output,Input"
|
|
bitfld.long 0x00 29. " B5P13DIR ,Bank 5 Pin 13 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B5P12DIR ,Bank 5 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 27. " B5P11DIR ,Bank 5 Pin 11 direction" "Output,Input"
|
|
bitfld.long 0x00 26. " B5P10DIR ,Bank 5 Pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B5P9DIR ,Bank 5 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 24. " B5P8DIR ,Bank 5 Pin 8 direction" "Output,Input"
|
|
bitfld.long 0x00 23. " B5P7DIR ,Bank 5 Pin 7 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B5P6DIR ,Bank 5 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 21. " B5P5DIR ,Bank 5 Pin 5 direction" "Output,Input"
|
|
bitfld.long 0x00 20. " B5P4DIR ,Bank 5 Pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B5P3DIR ,Bank 5 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 18. " B5P2DIR ,Bank 5 Pin 2 direction" "Output,Input"
|
|
bitfld.long 0x00 17. " B5P1DIR ,Bank 5 Pin 1 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B5P0DIR ,Bank 5 Pin 0 direction" "Output,Input"
|
|
bitfld.long 0x00 15. " B4P15DIR ,Bank 4 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 14. " B4P14DIR ,Bank 4 Pin 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B4P13DIR ,Bank 4 Pin 13 direction" "Output,Input"
|
|
bitfld.long 0x00 12. " B4P12DIR ,Bank 4 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 11. " B4P11DIR ,Bank 4 Pin 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B4P10DIR ,Bank 4 Pin 10 direction" "Output,Input"
|
|
bitfld.long 0x00 9. " B4P9DIR ,Bank 4 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 8. " B4P8DIR ,Bank 4 Pin 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B4P7DIR ,Bank 4 Pin 7 direction" "Output,Input"
|
|
bitfld.long 0x00 6. " B4P6DIR ,Bank 4 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 5. " B4P5DIR ,Bank 4 Pin 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B4P4DIR ,Bank 4 Pin 4 direction" "Output,Input"
|
|
bitfld.long 0x00 3. " B4P3DIR ,Bank 4 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 2. " B4P2DIR ,Bank 4 Pin 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B4P1DIR ,Bank 4 Pin 1 direction" "Output,Input"
|
|
bitfld.long 0x00 0. " B4P0DIR ,Bank 4 Pin 0 direction" "Output,Input"
|
|
group.long (0x60+0x04)++0x3
|
|
line.long 0x00 "OUT_DATA45,GPIO Banks 4 and 5 Output Data Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " B5P15OUT_set/clr ,Output drive state of Bank 5 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " B5P14OUT_set/clr ,Output drive state of Bank 5 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " B5P13OUT_set/clr ,Output drive state of Bank 5 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " B5P12OUT_set/clr ,Output drive state of Bank 5 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " B5P11OUT_set/clr ,Output drive state of Bank 5 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " B5P10OUT_set/clr ,Output drive state of Bank 5 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " B5P9OUT_set/clr ,Output drive state of Bank 5 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " B5P8OUT_set/clr ,Output drive state of Bank 5 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " B5P7OUT_set/clr ,Output drive state of Bank 5 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " B5P26UT_set/clr ,Output drive state of Bank 5 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " B5P5OUT_set/clr ,Output drive state of Bank 5 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " B5P4OUT_set/clr ,Output drive state of Bank 5 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " B5P3OUT_set/clr ,Output drive state of Bank 5 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " B5P2OUT_set/clr ,Output drive state of Bank 5 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " B5P1OUT_set/clr ,Output drive state of Bank 5 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " B5P0OUT_set/clr ,Output drive state of Bank 5 GPIO pin 0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " B4P15OUT_set/clr ,Output drive state of Bank 4 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " B4P14OUT_set/clr ,Output drive state of Bank 4 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " B4P13OUT_set/clr ,Output drive state of Bank 4 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " B4P12OUT_set/clr ,Output drive state of Bank 4 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " B4P11OUT_set/clr ,Output drive state of Bank 4 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " B4P10OUT_set/clr ,Output drive state of Bank 4 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " B4P9OUT_set/clr ,Output drive state of Bank 4 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " B4P8OUT_set/clr ,Output drive state of Bank 4 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " B4P7OUT_set/clr ,Output drive state of Bank 4 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " B4P6OUT_set/clr ,Output drive state of Bank 4 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " B4P5OUT_set/clr ,Output drive state of Bank 4 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " B4P4OUT_set/clr ,Output drive state of Bank 4 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " B4P3OUT_set/clr ,Output drive state of Bank 4 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " B4P2OUT_set/clr ,Output drive state of Bank 4 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " B4P1OUT_set/clr ,Output drive state of Bank 4 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " B4P0OUT_set/clr ,Output drive state of Bank 4 GPIO pin 0" "Low,High"
|
|
group.long (0x60+0x10)++0x3
|
|
line.long 0x00 "IN_DATA45,GPIO Banks 4 and 5 Input Data Register"
|
|
bitfld.long 0x00 31. " B5P15IN ,Status of Bank 5 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 30. " B5P14IN ,Status of Bank 5 GPIO pin 14" "Low,High"
|
|
bitfld.long 0x00 29. " B5P13IN ,Status of Bank 5 GPIO pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B5P12IN ,Status of Bank 5 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 27. " B5P11IN ,Status of Bank 5 GPIO pin 11" "Low,High"
|
|
bitfld.long 0x00 26. " B5P10IN ,Status of Bank 5 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B5P9IN ,Status of Bank 5 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 24. " B5P8IN ,Status of Bank 5 GPIO pin 8" "Low,High"
|
|
bitfld.long 0x00 23. " B5P7IN ,Status of Bank 5 GPIO pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B5P6IN ,Status of Bank 5 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 21. " B5P5IN ,Status of Bank 5 GPIO pin 5" "Low,High"
|
|
bitfld.long 0x00 20. " B5P4IN ,Status of Bank 5 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B5P3IN ,Status of Bank 5 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 18. " B5P2IN ,Status of Bank 5 GPIO pin 2" "Low,High"
|
|
bitfld.long 0x00 17. " B5P1IN ,Status of Bank 5 GPIO pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B5P0IN ,Status of Bank 5 GPIO pin 0" "Low,High"
|
|
bitfld.long 0x00 15. " B4P15IN ,Status of Bank 4 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " B4P14IN ,Status of Bank 4 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B4P13IN ,Status of Bank 4 GPIO pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " B4P12IN ,Status of Bank 4 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " B4P11IN ,Status of Bank 4 GPIO pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B4P10IN ,Status of Bank 4 GPIO pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " B4P9IN ,Status of Bank 4 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " B4P8IN ,Status of Bank 4 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B4P7IN ,Status of Bank 4 GPIO pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " B4P6IN ,Status of Bank 4 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " B4P5IN ,Status of Bank 4 GPIO pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B4P4IN ,Status of Bank 4 GPIO pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " B4P3IN ,Status of Bank 4 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " B4P2IN ,Status of Bank 4 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B4P1IN ,Status of Bank 4 GPIO pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " B4P0IN ,Status of Bank 4 GPIO pin 0" "Low,High"
|
|
width 16.
|
|
group.long (0x60+0x14)++0x3
|
|
line.long 0x00 "SET_RIS_TRIG45,GPIO Banks 4 and 5 Set Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B5P15SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B5P14SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B5P13SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B5P12SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B5P11SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B5P10SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B5P9SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B5P8SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B5P7SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B5P6SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B5P5SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B5P4SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B5P3SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B5P2SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B5P1SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B5P0SETRIS ,Enable rising edge interrupt detection on Bank 5 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B4P15SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B4P14SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B4P13SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B4P12SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B4P11SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B4P10SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B4P9SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B4P8SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B4P7SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B4P6SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B4P5SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B4P4SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B4P3SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B4P2SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B4P1SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B4P0SETRIS ,Enable rising edge interrupt detection on Bank 4 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x60+0x18)++0x3
|
|
line.long 0x00 "CLR_RIS_TRIG45,GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B5P15CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B5P14CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B5P13CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B5P12CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B5P11CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B5P10CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B5P9CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B5P8CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B5P7CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B5P6CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B5P5CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B5P4CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B5P3CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B5P2CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B5P1CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B5P0CLRRIS ,Disable rising edge interrupt detection on Bank 5 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B4P15CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B4P14CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B4P13CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B4P12CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B4P11CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B4P10CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B4P9CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B4P8CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B4P7CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B4P6CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B4P5CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B4P4CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B4P3CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B4P2CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B4P1CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B4P0CLRRIS ,Disable rising edge interrupt detection on Bank 4 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x60+0x1c)++0x3
|
|
line.long 0x00 "SET_FAL_TRIG45,GPIO Banks 4 and 5 Set Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B5P15SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B5P14SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B5P13SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B5P12SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B5P11SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B5P10SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B5P9SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B5P8SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B5P7SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B5P6SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B5P5SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B5P4SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B5P3SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B5P2SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B5P1SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B5P0SETFAL ,Enable falling edge interrupt detection on Bank 5 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B4P15SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B4P14SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B4P13SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B4P12SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B4P11SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B4P10SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B4P9SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B4P8SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B4P7SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B4P6SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B4P5SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B4P4SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B4P3SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B4P2SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B4P1SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B4P0SETFAL ,Enable falling edge interrupt detection on Bank 4 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x60+0x20)++0x3
|
|
line.long 0x00 "CLR_FAL_TRIG45,GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B5P15CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B5P14CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B5P13CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B5P12CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B5P11CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B5P10CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B5P9CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B5P8CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B5P7CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B5P6CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B5P5CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B5P4CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B5P3CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B5P2CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B5P1CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B5P0CLRFAL ,Disable falling edge interrupt detection on Bank 5 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B4P15CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B4P14CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B4P13CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B4P12CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B4P11CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B4P10CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B4P9CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B4P8CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B4P7CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B4P6CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B4P5CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B4P4CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B4P3CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B4P2CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B4P1CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B4P0CLRFAL ,Disable falling edge interrupt detection on Bank 4 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x60+0x24)++0x3
|
|
line.long 0x00 "INTSTAT45,GPIO Banks 4 and 5 Interrupt Status Register"
|
|
eventfld.long 0x00 31. " B5P15STAT ,Interrupt status of Bank 5 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " B5P14STAT ,Interrupt status of Bank 5 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 29. " B5P13STAT ,Interrupt status of Bank 5 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " B5P12STAT ,Interrupt status of Bank 5 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " B5P11STAT ,Interrupt status of Bank 5 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " B5P10STAT ,Interrupt status of Bank 5 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " B5P9STAT ,Interrupt status of Bank 5 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " B5P8STAT ,Interrupt status of Bank 5 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " B5P7STAT ,Interrupt status of Bank 5 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " B5P6STAT ,Interrupt status of Bank 5 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " B5P5STAT ,Interrupt status of Bank 5 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " B5P4STAT ,Interrupt status of Bank 5 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " B5P3STAT ,Interrupt status of Bank 5 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " B5P2STAT ,Interrupt status of Bank 5 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " B5P1STAT ,Interrupt status of Bank 5 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " B5P0STAT ,Interrupt status of Bank 5 GPIO pin 0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " B4P15STAT ,Interrupt status of Bank 4 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " B4P14STAT ,Interrupt status of Bank 4 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " B4P13STAT ,Interrupt status of Bank 4 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " B4P12STAT ,Interrupt status of Bank 4 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " B4P11STAT ,Interrupt status of Bank 4 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " B4P10STAT ,Interrupt status of Bank 4 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " B4P9STAT ,Interrupt status of Bank 4 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " B4P8STAT ,Interrupt status of Bank 4 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " B4P7STAT ,Interrupt status of Bank 4 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " B4P6STAT ,Interrupt status of Bank 4 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " B4P5STAT ,Interrupt status of Bank 4 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " B4P4STAT ,Interrupt status of Bank 4 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " B4P3STAT ,Interrupt status of Bank 4 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " B4P2STAT ,Interrupt status of Bank 4 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " B4P1STAT ,Interrupt status of Bank 4 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " B4P0STAT ,Interrupt status of Bank 4 GPIO pin 0" "Not pending,Pending"
|
|
group.long 0x88++0x3 "GPIO Banks 6 and 7"
|
|
line.long 0x00 "DIR67,GPIO Banks 6 and 7 Direction Register"
|
|
bitfld.long 0x00 31. " B7P15DIR ,Bank 7 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 30. " B7P14DIR ,Bank 7 Pin 14 direction" "Output,Input"
|
|
bitfld.long 0x00 29. " B7P13DIR ,Bank 7 Pin 13 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B7P12DIR ,Bank 7 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 27. " B7P11DIR ,Bank 7 Pin 11 direction" "Output,Input"
|
|
bitfld.long 0x00 26. " B7P10DIR ,Bank 7 Pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B7P9DIR ,Bank 7 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 24. " B7P8DIR ,Bank 7 Pin 8 direction" "Output,Input"
|
|
bitfld.long 0x00 23. " B7P7DIR ,Bank 7 Pin 7 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B7P6DIR ,Bank 7 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 21. " B7P5DIR ,Bank 7 Pin 5 direction" "Output,Input"
|
|
bitfld.long 0x00 20. " B7P4DIR ,Bank 7 Pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B7P3DIR ,Bank 7 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 18. " B7P2DIR ,Bank 7 Pin 2 direction" "Output,Input"
|
|
bitfld.long 0x00 17. " B7P1DIR ,Bank 7 Pin 1 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B7P0DIR ,Bank 7 Pin 0 direction" "Output,Input"
|
|
bitfld.long 0x00 15. " B6P15DIR ,Bank 6 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 14. " B6P14DIR ,Bank 6 Pin 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B6P13DIR ,Bank 6 Pin 13 direction" "Output,Input"
|
|
bitfld.long 0x00 12. " B6P12DIR ,Bank 6 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 11. " B6P11DIR ,Bank 6 Pin 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B6P10DIR ,Bank 6 Pin 10 direction" "Output,Input"
|
|
bitfld.long 0x00 9. " B6P9DIR ,Bank 6 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 8. " B6P8DIR ,Bank 6 Pin 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B6P7DIR ,Bank 6 Pin 7 direction" "Output,Input"
|
|
bitfld.long 0x00 6. " B6P6DIR ,Bank 6 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 5. " B6P5DIR ,Bank 6 Pin 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B6P4DIR ,Bank 6 Pin 4 direction" "Output,Input"
|
|
bitfld.long 0x00 3. " B6P3DIR ,Bank 6 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 2. " B6P2DIR ,Bank 6 Pin 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B6P1DIR ,Bank 6 Pin 1 direction" "Output,Input"
|
|
bitfld.long 0x00 0. " B6P0DIR ,Bank 6 Pin 0 direction" "Output,Input"
|
|
group.long (0x88+0x04)++0x3
|
|
line.long 0x00 "OUT_DATA67,GPIO Banks 6 and 7 Output Data Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " B7P15OUT_set/clr ,Output drive state of Bank 7 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " B7P14OUT_set/clr ,Output drive state of Bank 7 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " B7P13OUT_set/clr ,Output drive state of Bank 7 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " B7P12OUT_set/clr ,Output drive state of Bank 7 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " B7P11OUT_set/clr ,Output drive state of Bank 7 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " B7P10OUT_set/clr ,Output drive state of Bank 7 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " B7P9OUT_set/clr ,Output drive state of Bank 7 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " B7P8OUT_set/clr ,Output drive state of Bank 7 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " B7P7OUT_set/clr ,Output drive state of Bank 7 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " B7P26UT_set/clr ,Output drive state of Bank 7 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " B7P5OUT_set/clr ,Output drive state of Bank 7 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " B7P4OUT_set/clr ,Output drive state of Bank 7 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " B7P3OUT_set/clr ,Output drive state of Bank 7 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " B7P2OUT_set/clr ,Output drive state of Bank 7 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " B7P1OUT_set/clr ,Output drive state of Bank 7 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " B7P0OUT_set/clr ,Output drive state of Bank 7 GPIO pin 0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " B6P15OUT_set/clr ,Output drive state of Bank 6 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " B6P14OUT_set/clr ,Output drive state of Bank 6 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " B6P13OUT_set/clr ,Output drive state of Bank 6 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " B6P12OUT_set/clr ,Output drive state of Bank 6 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " B6P11OUT_set/clr ,Output drive state of Bank 6 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " B6P10OUT_set/clr ,Output drive state of Bank 6 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " B6P9OUT_set/clr ,Output drive state of Bank 6 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " B6P8OUT_set/clr ,Output drive state of Bank 6 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " B6P7OUT_set/clr ,Output drive state of Bank 6 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " B6P6OUT_set/clr ,Output drive state of Bank 6 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " B6P5OUT_set/clr ,Output drive state of Bank 6 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " B6P4OUT_set/clr ,Output drive state of Bank 6 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " B6P3OUT_set/clr ,Output drive state of Bank 6 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " B6P2OUT_set/clr ,Output drive state of Bank 6 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " B6P1OUT_set/clr ,Output drive state of Bank 6 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " B6P0OUT_set/clr ,Output drive state of Bank 6 GPIO pin 0" "Low,High"
|
|
group.long (0x88+0x10)++0x3
|
|
line.long 0x00 "IN_DATA67,GPIO Banks 6 and 7 Input Data Register"
|
|
bitfld.long 0x00 31. " B7P15IN ,Status of Bank 7 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 30. " B7P14IN ,Status of Bank 7 GPIO pin 14" "Low,High"
|
|
bitfld.long 0x00 29. " B7P13IN ,Status of Bank 7 GPIO pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " B7P12IN ,Status of Bank 7 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 27. " B7P11IN ,Status of Bank 7 GPIO pin 11" "Low,High"
|
|
bitfld.long 0x00 26. " B7P10IN ,Status of Bank 7 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B7P9IN ,Status of Bank 7 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 24. " B7P8IN ,Status of Bank 7 GPIO pin 8" "Low,High"
|
|
bitfld.long 0x00 23. " B7P7IN ,Status of Bank 7 GPIO pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B7P6IN ,Status of Bank 7 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 21. " B7P5IN ,Status of Bank 7 GPIO pin 5" "Low,High"
|
|
bitfld.long 0x00 20. " B7P4IN ,Status of Bank 7 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B7P3IN ,Status of Bank 7 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 18. " B7P2IN ,Status of Bank 7 GPIO pin 2" "Low,High"
|
|
bitfld.long 0x00 17. " B7P1IN ,Status of Bank 7 GPIO pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B7P0IN ,Status of Bank 7 GPIO pin 0" "Low,High"
|
|
bitfld.long 0x00 15. " B6P15IN ,Status of Bank 6 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " B6P14IN ,Status of Bank 6 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B6P13IN ,Status of Bank 6 GPIO pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " B6P12IN ,Status of Bank 6 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " B6P11IN ,Status of Bank 6 GPIO pin 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B6P10IN ,Status of Bank 6 GPIO pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " B6P9IN ,Status of Bank 6 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " B6P8IN ,Status of Bank 6 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B6P7IN ,Status of Bank 6 GPIO pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " B6P6IN ,Status of Bank 6 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " B6P5IN ,Status of Bank 6 GPIO pin 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B6P4IN ,Status of Bank 6 GPIO pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " B6P3IN ,Status of Bank 6 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " B6P2IN ,Status of Bank 6 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B6P1IN ,Status of Bank 6 GPIO pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " B6P0IN ,Status of Bank 6 GPIO pin 0" "Low,High"
|
|
width 16.
|
|
group.long (0x88+0x14)++0x3
|
|
line.long 0x00 "SET_RIS_TRIG67,GPIO Banks 6 and 7 Set Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B7P15SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B7P14SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B7P13SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B7P12SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B7P11SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B7P10SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B7P9SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B7P8SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B7P7SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B7P6SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B7P5SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B7P4SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B7P3SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B7P2SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B7P1SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B7P0SETRIS ,Enable rising edge interrupt detection on Bank 7 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B6P15SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B6P14SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B6P13SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B6P12SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B6P11SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B6P10SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B6P9SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B6P8SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B6P7SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B6P6SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B6P5SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B6P4SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B6P3SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B6P2SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B6P1SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B6P0SETRIS ,Enable rising edge interrupt detection on Bank 6 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x88+0x18)++0x3
|
|
line.long 0x00 "CLR_RIS_TRIG67,GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B7P15CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B7P14CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B7P13CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B7P12CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B7P11CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B7P10CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B7P9CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B7P8CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B7P7CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B7P6CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B7P5CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B7P4CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B7P3CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B7P2CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B7P1CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B7P0CLRRIS ,Disable rising edge interrupt detection on Bank 7 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B6P15CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B6P14CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B6P13CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B6P12CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B6P11CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B6P10CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B6P9CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B6P8CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B6P7CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B6P6CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B6P5CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B6P4CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B6P3CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B6P2CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B6P1CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B6P0CLRRIS ,Disable rising edge interrupt detection on Bank 6 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x88+0x1c)++0x3
|
|
line.long 0x00 "SET_FAL_TRIG67,GPIO Banks 6 and 7 Set Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B7P15SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " B7P14SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B7P13SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " B7P12SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B7P11SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " B7P10SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B7P9SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " B7P8SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B7P7SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " B7P6SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B7P5SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " B7P4SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B7P3SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " B7P2SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B7P1SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " B7P0SETFAL ,Enable falling edge interrupt detection on Bank 7 GPIO pin 0" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B6P15SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B6P14SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B6P13SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B6P12SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B6P11SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B6P10SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B6P9SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B6P8SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B6P7SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B6P6SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B6P5SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B6P4SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B6P3SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B6P2SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B6P1SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B6P0SETFAL ,Enable falling edge interrupt detection on Bank 6 GPIO pin 0" "No effect,Enabled"
|
|
group.long (0x88+0x20)++0x3
|
|
line.long 0x00 "CLR_FAL_TRIG67,GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 31. " B7P15CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " B7P14CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " B7P13CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " B7P12CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " B7P11CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " B7P10CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " B7P9CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " B7P8CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " B7P7CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " B7P6CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " B7P5CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " B7P4CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " B7P3CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " B7P2CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " B7P1CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " B7P0CLRFAL ,Disable falling edge interrupt detection on Bank 7 GPIO pin 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " B6P15CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B6P14CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B6P13CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B6P12CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B6P11CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B6P10CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B6P9CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B6P8CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B6P7CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B6P6CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B6P5CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B6P4CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B6P3CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B6P2CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B6P1CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B6P0CLRFAL ,Disable falling edge interrupt detection on Bank 6 GPIO pin 0" "No effect,Disabled"
|
|
group.long (0x88+0x24)++0x3
|
|
line.long 0x00 "INTSTAT67,GPIO Banks 6 and 7 Interrupt Status Register"
|
|
eventfld.long 0x00 31. " B7P15STAT ,Interrupt status of Bank 7 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " B7P14STAT ,Interrupt status of Bank 7 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 29. " B7P13STAT ,Interrupt status of Bank 7 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " B7P12STAT ,Interrupt status of Bank 7 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 27. " B7P11STAT ,Interrupt status of Bank 7 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " B7P10STAT ,Interrupt status of Bank 7 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " B7P9STAT ,Interrupt status of Bank 7 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " B7P8STAT ,Interrupt status of Bank 7 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 23. " B7P7STAT ,Interrupt status of Bank 7 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " B7P6STAT ,Interrupt status of Bank 7 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " B7P5STAT ,Interrupt status of Bank 7 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " B7P4STAT ,Interrupt status of Bank 7 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " B7P3STAT ,Interrupt status of Bank 7 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " B7P2STAT ,Interrupt status of Bank 7 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " B7P1STAT ,Interrupt status of Bank 7 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " B7P0STAT ,Interrupt status of Bank 7 GPIO pin 0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 15. " B6P15STAT ,Interrupt status of Bank 6 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " B6P14STAT ,Interrupt status of Bank 6 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " B6P13STAT ,Interrupt status of Bank 6 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " B6P12STAT ,Interrupt status of Bank 6 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " B6P11STAT ,Interrupt status of Bank 6 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " B6P10STAT ,Interrupt status of Bank 6 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " B6P9STAT ,Interrupt status of Bank 6 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " B6P8STAT ,Interrupt status of Bank 6 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " B6P7STAT ,Interrupt status of Bank 6 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " B6P6STAT ,Interrupt status of Bank 6 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " B6P5STAT ,Interrupt status of Bank 6 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " B6P4STAT ,Interrupt status of Bank 6 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " B6P3STAT ,Interrupt status of Bank 6 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " B6P2STAT ,Interrupt status of Bank 6 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " B6P1STAT ,Interrupt status of Bank 6 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " B6P0STAT ,Interrupt status of Bank 6 GPIO pin 0" "Not pending,Pending"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1802"||cpu()=="AM1806"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1705"||cpu()=="AM1707")
|
|
group.long 0xb0++0x3 "GPIO Bank 8"
|
|
line.long 0x00 "DIR8,GPIO Bank 8 Direction Register"
|
|
bitfld.long 0x00 15. " B8P15DIR ,Bank 8 Pin 15 direction" "Output,Input"
|
|
bitfld.long 0x00 14. " B8P14DIR ,Bank 8 Pin 14 direction" "Output,Input"
|
|
bitfld.long 0x00 13. " B8P13DIR ,Bank 8 Pin 13 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 12. " B8P12DIR ,Bank 8 Pin 12 direction" "Output,Input"
|
|
bitfld.long 0x00 11. " B8P11DIR ,Bank 8 Pin 11 direction" "Output,Input"
|
|
bitfld.long 0x00 10. " B8P10DIR ,Bank 8 Pin 10 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B8P9DIR ,Bank 8 Pin 9 direction" "Output,Input"
|
|
bitfld.long 0x00 8. " B8P8DIR ,Bank 8 Pin 8 direction" "Output,Input"
|
|
bitfld.long 0x00 7. " B8P7DIR ,Bank 8 Pin 7 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B8P6DIR ,Bank 8 Pin 6 direction" "Output,Input"
|
|
bitfld.long 0x00 5. " B8P5DIR ,Bank 8 Pin 5 direction" "Output,Input"
|
|
bitfld.long 0x00 4. " B8P4DIR ,Bank 8 Pin 4 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B8P3DIR ,Bank 8 Pin 3 direction" "Output,Input"
|
|
bitfld.long 0x00 2. " B8P2DIR ,Bank 8 Pin 2 direction" "Output,Input"
|
|
bitfld.long 0x00 1. " B8P1DIR ,Bank 8 Pin 1 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B8P0DIR ,Bank 8 Pin 0 direction" "Output,Input"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "OUT_DATA8,GPIO Bank 8 Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " B8P15OUT_set/clr ,Output drive state of Bank 8 GPIO pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " B8P14OUT_set/clr ,Output drive state of Bank 8 GPIO pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " B8P13OUT_set/clr ,Output drive state of Bank 8 GPIO pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " B8P12OUT_set/clr ,Output drive state of Bank 8 GPIO pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " B8P11OUT_set/clr ,Output drive state of Bank 8 GPIO pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " B8P10OUT_set/clr ,Output drive state of Bank 8 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " B8P9OUT_set/clr ,Output drive state of Bank 8 GPIO pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " B8P8OUT_set/clr ,Output drive state of Bank 8 GPIO pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " B8P7OUT_set/clr ,Output drive state of Bank 8 GPIO pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " B8P6OUT_set/clr ,Output drive state of Bank 8 GPIO pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " B8P5OUT_set/clr ,Output drive state of Bank 8 GPIO pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " B8P4OUT_set/clr ,Output drive state of Bank 8 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " B8P3OUT_set/clr ,Output drive state of Bank 8 GPIO pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " B8P2OUT_set/clr ,Output drive state of Bank 8 GPIO pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " B8P1OUT_set/clr ,Output drive state of Bank 8 GPIO pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " B8P0OUT_set/clr ,Output drive state of Bank 8 GPIO pin 0" "Low,High"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "IN_DATA8,GPIO Bank 8 Input Data Register"
|
|
bitfld.long 0x00 15. " B8P15IN ,Status of Bank 8 GPIO pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " B8P14IN ,Status of Bank 8 GPIO pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " B8P13IN ,Status of Bank 8 GPIO pin 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " B8P12IN ,Status of Bank 8 GPIO pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " B8P11IN ,Status of Bank 8 GPIO pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " B8P10IN ,Status of Bank 8 GPIO pin 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B8P9IN ,Status of Bank 8 GPIO pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " B8P8IN ,Status of Bank 8 GPIO pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " B8P7IN ,Status of Bank 8 GPIO pin 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B8P6IN ,Status of Bank 8 GPIO pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " B8P5IN ,Status of Bank 8 GPIO pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " B8P4IN ,Status of Bank 8 GPIO pin 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B8P3IN ,Status of Bank 8 GPIO pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " B8P2IN ,Status of Bank 8 GPIO pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " B8P1IN ,Status of Bank 8 GPIO pin 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B8P0IN ,Status of Bank 8 GPIO pin 0" "Low,High"
|
|
width 16.
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "SET_RIS_TRIG8,GPIO Bank 8 Set Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 15. " B8P15SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B8P14SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B8P13SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B8P12SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B8P11SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B8P10SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B8P9SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B8P8SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B8P7SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B8P6SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B8P5SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B8P4SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B8P3SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B8P2SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B8P1SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B8P0SETRIS ,Enable rising edge interrupt detection on Bank 8 GPIO pin 0" "No effect,Enabled"
|
|
group.long 0xc8++0x3
|
|
line.long 0x00 "CLR_RIS_TRIG8,GPIO Bank 8 Clear Rising Edge Interrupt Register"
|
|
bitfld.long 0x00 15. " B8P15CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B8P14CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B8P13CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B8P12CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B8P11CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B8P10CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B8P9CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B8P8CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B8P7CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B8P6CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B8P5CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B8P4CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B8P3CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B8P2CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B8P1CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B8P0CLRRIS ,Disable rising edge interrupt detection on Bank 8 GPIO pin 0" "No effect,Disabled"
|
|
group.long 0xcc++0x3
|
|
line.long 0x00 "SET_FAL_TRIG8,GPIO Bank 8 Set Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 15. " B8P15SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " B8P14SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 14" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B8P13SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " B8P12SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 12" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B8P11SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " B8P10SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 10" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B8P9SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 9" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " B8P8SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 8" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B8P7SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 7" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " B8P6SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 6" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B8P5SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 5" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " B8P4SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 4" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B8P3SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 3" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " B8P2SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B8P1SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 1" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " B8P0SETFAL ,Enable falling edge interrupt detection on Bank 8 GPIO pin 0" "No effect,Enabled"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "CLR_FAL_TRIG8,GPIO Bank 8 Clear Falling Edge Interrupt Register"
|
|
bitfld.long 0x00 15. " B8P15CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 15" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " B8P14CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 14" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B8P13CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 13" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " B8P12CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 12" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " B8P11CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 11" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " B8P10CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 10" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " B8P9CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 9" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " B8P8CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 8" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " B8P7CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 7" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " B8P6CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 6" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B8P5CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 5" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " B8P4CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 4" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B8P3CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 3" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " B8P2CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 2" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " B8P1CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 1" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " B8P0CLRFAL ,Disable falling edge interrupt detection on Bank 8 GPIO pin 0" "No effect,Disabled"
|
|
group.long 0xd4++0x3
|
|
line.long 0x00 "INTSTAT8,GPIO Bank 8 Interrupt Status Register"
|
|
eventfld.long 0x00 15. " B8P15STAT ,Interrupt status of Bank 8 GPIO pin 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " B8P14STAT ,Interrupt status of Bank 8 GPIO pin 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " B8P13STAT ,Interrupt status of Bank 8 GPIO pin 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " B8P12STAT ,Interrupt status of Bank 8 GPIO pin 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 11. " B8P11STAT ,Interrupt status of Bank 8 GPIO pin 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " B8P10STAT ,Interrupt status of Bank 8 GPIO pin 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " B8P9STAT ,Interrupt status of Bank 8 GPIO pin 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " B8P8STAT ,Interrupt status of Bank 8 GPIO pin 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " B8P7STAT ,Interrupt status of Bank 8 GPIO pin 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " B8P6STAT ,Interrupt status of Bank 8 GPIO pin 6" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " B8P5STAT ,Interrupt status of Bank 8 GPIO pin 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " B8P4STAT ,Interrupt status of Bank 8 GPIO pin 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " B8P3STAT ,Interrupt status of Bank 8 GPIO pin 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " B8P2STAT ,Interrupt status of Bank 8 GPIO pin 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " B8P1STAT ,Interrupt status of Bank 8 GPIO pin 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " B8P0STAT ,Interrupt status of Bank 8 GPIO pin 0" "Not pending,Pending"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "EDMA3"
|
|
tree "Parameter RAM"
|
|
base asd:0x01c04000
|
|
width 14.
|
|
tree "Parameter set 0"
|
|
group.long 0x0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 1"
|
|
group.long 0x20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 2"
|
|
group.long 0x40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 3"
|
|
group.long 0x60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 4"
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 5"
|
|
group.long 0xA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 6"
|
|
group.long 0xC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 7"
|
|
group.long 0xE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 8"
|
|
group.long 0x100++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 9"
|
|
group.long 0x120++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 10"
|
|
group.long 0x140++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 11"
|
|
group.long 0x160++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 12"
|
|
group.long 0x180++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 13"
|
|
group.long 0x1A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 14"
|
|
group.long 0x1C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 15"
|
|
group.long 0x1E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 16"
|
|
group.long 0x200++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 17"
|
|
group.long 0x220++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 18"
|
|
group.long 0x240++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 19"
|
|
group.long 0x260++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 20"
|
|
group.long 0x280++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 21"
|
|
group.long 0x2A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 22"
|
|
group.long 0x2C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 23"
|
|
group.long 0x2E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 24"
|
|
group.long 0x300++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 25"
|
|
group.long 0x320++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 26"
|
|
group.long 0x340++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 27"
|
|
group.long 0x360++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 28"
|
|
group.long 0x380++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 29"
|
|
group.long 0x3A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 30"
|
|
group.long 0x3C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 31"
|
|
group.long 0x3E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 32"
|
|
group.long 0x400++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 33"
|
|
group.long 0x420++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 34"
|
|
group.long 0x440++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 35"
|
|
group.long 0x460++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 36"
|
|
group.long 0x480++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 37"
|
|
group.long 0x4A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 38"
|
|
group.long 0x4C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 39"
|
|
group.long 0x4E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 40"
|
|
group.long 0x500++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 41"
|
|
group.long 0x520++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 42"
|
|
group.long 0x540++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 43"
|
|
group.long 0x560++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 44"
|
|
group.long 0x580++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 45"
|
|
group.long 0x5A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 46"
|
|
group.long 0x5C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 47"
|
|
group.long 0x5E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 48"
|
|
group.long 0x600++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 49"
|
|
group.long 0x620++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 50"
|
|
group.long 0x640++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 51"
|
|
group.long 0x660++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 52"
|
|
group.long 0x680++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 53"
|
|
group.long 0x6A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 54"
|
|
group.long 0x6C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 55"
|
|
group.long 0x6E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 56"
|
|
group.long 0x700++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 57"
|
|
group.long 0x720++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 58"
|
|
group.long 0x740++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 59"
|
|
group.long 0x760++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 60"
|
|
group.long 0x780++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 61"
|
|
group.long 0x7A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 62"
|
|
group.long 0x7C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 63"
|
|
group.long 0x7E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 64"
|
|
group.long 0x800++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 65"
|
|
group.long 0x820++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 66"
|
|
group.long 0x840++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 67"
|
|
group.long 0x860++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 68"
|
|
group.long 0x880++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 69"
|
|
group.long 0x8A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 70"
|
|
group.long 0x8C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 71"
|
|
group.long 0x8E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 72"
|
|
group.long 0x900++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 73"
|
|
group.long 0x920++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 74"
|
|
group.long 0x940++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 75"
|
|
group.long 0x960++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 76"
|
|
group.long 0x980++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 77"
|
|
group.long 0x9A0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 78"
|
|
group.long 0x9C0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 79"
|
|
group.long 0x9E0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 80"
|
|
group.long 0xA00++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 81"
|
|
group.long 0xA20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 82"
|
|
group.long 0xA40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 83"
|
|
group.long 0xA60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 84"
|
|
group.long 0xA80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 85"
|
|
group.long 0xAA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 86"
|
|
group.long 0xAC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 87"
|
|
group.long 0xAE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 88"
|
|
group.long 0xB00++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 89"
|
|
group.long 0xB20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 90"
|
|
group.long 0xB40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 91"
|
|
group.long 0xB60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 92"
|
|
group.long 0xB80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 93"
|
|
group.long 0xBA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 94"
|
|
group.long 0xBC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 95"
|
|
group.long 0xBE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 96"
|
|
group.long 0xC00++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 97"
|
|
group.long 0xC20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 98"
|
|
group.long 0xC40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 99"
|
|
group.long 0xC60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 100"
|
|
group.long 0xC80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 101"
|
|
group.long 0xCA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 102"
|
|
group.long 0xCC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 103"
|
|
group.long 0xCE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 104"
|
|
group.long 0xD00++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 105"
|
|
group.long 0xD20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 106"
|
|
group.long 0xD40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 107"
|
|
group.long 0xD60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 108"
|
|
group.long 0xD80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 109"
|
|
group.long 0xDA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 110"
|
|
group.long 0xDC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 111"
|
|
group.long 0xDE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 112"
|
|
group.long 0xE00++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 113"
|
|
group.long 0xE20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 114"
|
|
group.long 0xE40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 115"
|
|
group.long 0xE60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 116"
|
|
group.long 0xE80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 117"
|
|
group.long 0xEA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 118"
|
|
group.long 0xEC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 119"
|
|
group.long 0xEE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 120"
|
|
group.long 0xF00++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 121"
|
|
group.long 0xF20++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 122"
|
|
group.long 0xF40++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 123"
|
|
group.long 0xF60++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 124"
|
|
group.long 0xF80++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 125"
|
|
group.long 0xFA0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 126"
|
|
group.long 0xFC0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
tree "Parameter set 127"
|
|
group.long 0xFE0++0x1f
|
|
line.long 0x00 "OPT,Channel Options Parameter"
|
|
hexmask.long.byte 0x00 24.--27. 1. " PRIVID ,Privilege identification"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
|
|
bitfld.long 0x00 3. " STATIC ,Static PaRAM set" "Not static,Static"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
|
|
line.long 0x04 "SRC,Source Address"
|
|
line.long 0x08 "A_B_CNT,A Count/B Count Parameter"
|
|
sif (cpu()=="DM357"||cpu()=="DM365"||cpu()=="DM368"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="OMAP-L137"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,B count"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,A count for 1st Dimension"
|
|
else
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,Number of arrays of length"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,Number of bytes within the 1st dimension of a transfer"
|
|
endif
|
|
line.long 0x0c "DST,Destination Address"
|
|
line.long 0x10 "SRC_DST_BIDX,Source B Index/Destination B Index Parameter"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSTBIDX ,Destination B index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SRCBIDX ,Source B index"
|
|
line.long 0x14 "LINK_BCNTRLD,Link Address/B Count Reload Parameter"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,B count reload"
|
|
hexmask.long.word 0x14 0.--15. 1. " LINK ,Link address"
|
|
line.long 0x18 "SRC_DST_CIDX,Source C Index/Destination C Index Parameter"
|
|
hexmask.long.word 0x18 16.--31. 1. " DSTCIDX ,Destination C index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SRCCIDX ,Source C index"
|
|
line.long 0x1c "CCNT,C Count Parameter"
|
|
hexmask.long.word 0x1c 0.--15. 1. " CCNT ,Number of frames in a block"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "EDMA3 CC"
|
|
base asd:0x01c00000
|
|
width 10.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
line.long 0x04 "CCCFG,EDMA3CC Configuration Register"
|
|
bitfld.long 0x04 25. " MP_EXIST ,Memory protection existence" "Not supported,?..."
|
|
bitfld.long 0x04 24. " CHMAP_EXIST ,Channel mapping existence" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " NUM_REGN ,Number of shadow regions" "Reserved,Reserved,4 regions,?..."
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues / number of TCs" "Reserved,Reserved,2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM sets" "Reserved,Reserved,Reserved,128 sets,?..."
|
|
bitfld.long 0x04 8.--10. " NUM_INTCH ,Number of interrupt channels" "Reserved,Reserved,Reserved,Reserved,32 channels,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " NUM_QDMACH ,Number of QDMA channels" "Reserved,Reserved,Reserved,Reserved,8 channels,?..."
|
|
bitfld.long 0x04 0.--2. " NUM_DMACH ,Number of DMA channels" "Reserved,Reserved,Reserved,Reserved,Reserved,32 channels,?..."
|
|
tree "Global Registers"
|
|
group.long 0x200++0x1f "QDMA Channels Mapping Registers"
|
|
line.long 0x0 "QCHMAP0,QDMA Channel 0 Mapping Register"
|
|
hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 0"
|
|
hexmask.long.byte 0x0 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0x4 "QCHMAP1,QDMA Channel 1 Mapping Register"
|
|
hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 1"
|
|
hexmask.long.byte 0x4 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0x8 "QCHMAP2,QDMA Channel 2 Mapping Register"
|
|
hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 2"
|
|
hexmask.long.byte 0x8 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0xC "QCHMAP3,QDMA Channel 3 Mapping Register"
|
|
hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 3"
|
|
hexmask.long.byte 0xC 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0x10 "QCHMAP4,QDMA Channel 4 Mapping Register"
|
|
hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 4"
|
|
hexmask.long.byte 0x10 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0x14 "QCHMAP5,QDMA Channel 5 Mapping Register"
|
|
hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 5"
|
|
hexmask.long.byte 0x14 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0x18 "QCHMAP6,QDMA Channel 6 Mapping Register"
|
|
hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 6"
|
|
hexmask.long.byte 0x18 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
line.long 0x1C "QCHMAP7,QDMA Channel 7 Mapping Register"
|
|
hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,PaRAM set number for qDMA channel 7"
|
|
hexmask.long.byte 0x1C 2.--4. 1. " TRWORD ,Specific trigger word of the PaRAM set defined by PAENTRY"
|
|
group.long 0x240++0x0f
|
|
line.long 0x00 "DMAQNUM0,DMA Channel Queue Number Register 0"
|
|
bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,?..."
|
|
line.long 0x04 "DMAQNUM1,DMA Channel Queue Number Register 1"
|
|
bitfld.long 0x04 28.--30. " E15 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x04 24.--26. " E14 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x04 20.--22. " E13 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x04 16.--18. " E12 ,DMA queue number" "Q0,Q1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " E11 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x04 8.--10. " E10 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x04 4.--6. " E9 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x04 0.--2. " E8 ,DMA queue number" "Q0,Q1,?..."
|
|
line.long 0x08 "DMAQNUM2,DMA Channel Queue Number Register 2"
|
|
bitfld.long 0x08 28.--30. " E23 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x08 24.--26. " E22 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x08 20.--22. " E21 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x08 16.--18. " E20 ,DMA queue number" "Q0,Q1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " E19 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x08 8.--10. " E18 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x08 4.--6. " E17 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x08 0.--2. " E16 ,DMA queue number" "Q0,Q1,?..."
|
|
line.long 0x0c "DMAQNUM3,DMA Channel Queue Number Register 3"
|
|
bitfld.long 0x0c 28.--30. " E31 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x0c 24.--26. " E30 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x0c 20.--22. " E29 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x0c 16.--18. " E28 ,DMA queue number" "Q0,Q1,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 12.--14. " E27 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x0c 8.--10. " E26 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x0c 4.--6. " E25 ,DMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x0c 0.--2. " E24 ,DMA queue number" "Q0,Q1,?..."
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "QDMAQNUM,QDMA Channel Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,QDMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 24.--26. " E6 ,QDMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 20.--22. " E5 ,QDMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 16.--18. " E4 ,QDMA queue number" "Q0,Q1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " E3 ,QDMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 8.--10. " E2 ,QDMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 4.--6. " E1 ,QDMA queue number" "Q0,Q1,?..."
|
|
bitfld.long 0x00 0.--2. " E0 ,QDMA queue number" "Q0,Q1,?..."
|
|
group.long 0x284++0x3
|
|
line.long 0x00 "QUEPRI,Queue Priority Register"
|
|
width 10.
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
rgroup.long 0x300++0x3 "Error Registers"
|
|
else
|
|
rgroup.long 0x300++0x7
|
|
endif
|
|
line.long 0x00 "EMR,Event Missed Register"
|
|
bitfld.long 0x00 31. " E31 ,Channel 31 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 30. " E30 ,Channel 30 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 29. " E29 ,Channel 29 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 28. " E28 ,Channel 28 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Channel 27 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 26. " E26 ,Channel 26 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 25. " E25 ,Channel 25 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 24. " E24 ,Channel 24 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Channel 23 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 22. " E22 ,Channel 22 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 21. " E21 ,Channel 21 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 20. " E20 ,Channel 20 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Channel 19 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 18. " E18 ,Channel 18 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 17. " E17 ,Channel 17 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 16. " E16 ,Channel 16 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Channel 15 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 14. " E14 ,Channel 14 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 13. " E13 ,Channel 13 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 12. " E12 ,Channel 12 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Channel 11 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 10. " E10 ,Channel 10 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 9. " E9 ,Channel 9 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 8. " E8 ,Channel 8 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Channel 7 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 6. " E6 ,Channel 6 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 5. " E5 ,Channel 5 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 4. " E4 ,Channel 4 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Channel 3 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 2. " E2 ,Channel 2 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 1. " E1 ,Channel 1 event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 0. " E0 ,Channel 0 event missed" "Not missed,Missed"
|
|
sif (cpu()!="OMAP-L137"&&cpu()!="OMAP-L138"&&cpu()!="AM1808"&&cpu()!="AM1707"&&cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&CPU()!="AM1806"&&CPU()!="AM1810"&&CPU()!="AM1802")
|
|
line.long 0x04 "EMRH,Event Missed Register High"
|
|
bitfld.long 0x04 31. " E63 ,Channel 63 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 30. " E62 ,Channel 62 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 29. " E61 ,Channel 61 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 28. " E60 ,Channel 60 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 27. " E59 ,Channel 59 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 26. " E58 ,Channel 58 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 25. " E57 ,Channel 57 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 24. " E56 ,Channel 56 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 23. " E55 ,Channel 55 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 22. " E54 ,Channel 54 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 21. " E53 ,Channel 53 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 20. " E52 ,Channel 52 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Channel 51 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 18. " E50 ,Channel 50 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 17. " E49 ,Channel 49 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 16. " E48 ,Channel 48 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 15. " E47 ,Channel 47 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 14. " E46 ,Channel 46 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 13. " E45 ,Channel 45 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 12. " E44 ,Channel 44 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 11. " E43 ,Channel 43 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 10. " E42 ,Channel 42 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 9. " E41 ,Channel 41 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 8. " E40 ,Channel 40 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Channel 39 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 6. " E38 ,Channel 38 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 5. " E37 ,Channel 37 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 4. " E36 ,Channel 36 event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " E35 ,Channel 35 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 2. " E34 ,Channel 34 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 1. " E33 ,Channel 33 event missed" "Not missed,Missed"
|
|
bitfld.long 0x04 0. " E32 ,Channel 32 event missed" "Not missed,Missed"
|
|
endif
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
wgroup.long 0x308++0x3
|
|
else
|
|
wgroup.long 0x308++0x7
|
|
endif
|
|
line.long 0x00 "EMCR,Event Missed Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed 31 clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event missed 30 clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event missed 29 clear" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event missed 28 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Event missed 27 clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event missed 26 clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event missed 25 clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Event missed 24 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Event missed 23 clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event missed 22 clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event missed 21 clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event missed 20 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Event missed 19 clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event missed 18 clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Event missed 17 clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event missed 16 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Event missed 15 clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event missed 14 clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event missed 13 clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event missed 12 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Event missed 11 clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Event missed 10 clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event missed 9 clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event missed 8 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Event missed 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Event missed 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event missed 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed 0 clear" "No effect,Clear"
|
|
sif (cpu()!="OMAP-L137"&&cpu()!="OMAP-L138"&&cpu()!="AM1808"&&cpu()!="AM1707"&&cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&CPU()!="AM1806"&&CPU()!="AM1810"&&CPU()!="AM1802")
|
|
line.long 0x04 "EMCRH,Event Missed Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event missed 63 clear" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event missed 62 clear" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event missed 61 clear" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event missed 60 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 27. " E59 ,Event missed 59 clear" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event missed 58 clear" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event missed 57 clear" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Event missed 56 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 23. " E55 ,Event missed 55 clear" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event missed 54 clear" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event missed 53 clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event missed 52 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " E51 ,Event missed 51 clear" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event missed 50 clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Event missed 49 clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event missed 48 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 15. " E47 ,Event missed 47 clear" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event missed 46 clear" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event missed 45 clear" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event missed 44 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 11. " E43 ,Event missed 43 clear" "No effect,Clear"
|
|
bitfld.long 0x04 10. " E42 ,Event missed 42 clear" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event missed 41 clear" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event missed 40 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " E39 ,Event missed 39 clear" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event missed 38 clear" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event missed 37 clear" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event missed 36 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " E35 ,Event missed 35 clear" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event missed 34 clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event missed 33 clear" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event missed 32 clear" "No effect,Clear"
|
|
endif
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x00 "QEMR,QDMA Event Missed Register"
|
|
bitfld.long 0x00 7. " E7 ,Channel 7 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 6. " E6 ,Channel 6 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 5. " E5 ,Channel 5 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 4. " E4 ,Channel 4 QDMA event missed" "Not missed,Missed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Channel 3 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 2. " E2 ,Channel 2 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 1. " E1 ,Channel 1 QDMA event missed" "Not missed,Missed"
|
|
bitfld.long 0x00 0. " E0 ,Channel 0 QDMA event missed" "Not missed,Missed"
|
|
wgroup.long 0x314++0x3
|
|
line.long 0x00 "QEMCR,QDMA Event Missed Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event missed 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event missed 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event missed 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event missed 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event missed 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event missed 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event missed 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event missed 0 clear" "No effect,Clear"
|
|
textline ""
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x00 "CCERR,EDMA3CC Error Register"
|
|
bitfld.long 0x00 16. " TCCERR ,Transfer completion code error" "Not reached,Reached"
|
|
textline " "
|
|
sif (cpu()!="OMAP-L137"&&cpu()!="OMAP-L138"&&cpu()!="AM1808"&&cpu()!="AM1707"&&cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&CPU()!="AM1806"&&CPU()!="AM1810"&&CPU()!="AM1802")
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for queue 2" "Not exceeded,Exceeded"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for queue 1" "Not exceeded,Exceeded"
|
|
textline " "
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for queue 0" "Not exceeded,Exceeded"
|
|
wgroup.long 0x31c++0x3
|
|
line.long 0x00 "CCERRCLR,EDMA3CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCCERR ,Transfer completion code error clear" "No effect,Clear"
|
|
textline " "
|
|
sif (cpu()!="OMAP-L137"&&cpu()!="OMAP-L138"&&cpu()!="AM1808"&&cpu()!="AM1707"&&cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&CPU()!="AM1806"&&CPU()!="AM1810"&&CPU()!="AM1802")
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error clear for queue 2" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error clear for queue 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error clear for queue 0" "No effect,Clear"
|
|
wgroup.long 0x320++0x3
|
|
line.long 0x00 "EEVAL,Error Evaluation Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error interrupt evaluate" "No effect,Interrupt"
|
|
width 8.
|
|
tree.open "Region Access Enable Registers"
|
|
group.long 0x340++0x3
|
|
line.long 0x00 "DRAE0,DMA Region Access Enable Register for Region 0"
|
|
bitfld.long 0x00 31. " E31 ,DMA Region Access enable for bit/channel 31 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA Region Access enable for bit/channel 30 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA Region Access enable for bit/channel 29 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " E28 ,DMA Region Access enable for bit/channel 28 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,DMA Region Access enable for bit/channel 27 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA Region Access enable for bit/channel 26 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " E25 ,DMA Region Access enable for bit/channel 25 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA Region Access enable for bit/channel 24 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,DMA Region Access enable for bit/channel 23 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 22. " E22 ,DMA Region Access enable for bit/channel 22 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA Region Access enable for bit/channel 21 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA Region Access enable for bit/channel 20 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA Region Access enable for bit/channel 19 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA Region Access enable for bit/channel 18 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA Region Access enable for bit/channel 17 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 16. " E16 ,DMA Region Access enable for bit/channel 16 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,DMA Region Access enable for bit/channel 15 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA Region Access enable for bit/channel 14 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " E13 ,DMA Region Access enable for bit/channel 13 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA Region Access enable for bit/channel 12 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,DMA Region Access enable for bit/channel 11 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 10. " E10 ,DMA Region Access enable for bit/channel 10 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA Region Access enable for bit/channel 9 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA Region Access enable for bit/channel 8 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA Region Access enable for bit/channel 7 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA Region Access enable for bit/channel 6 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA Region Access enable for bit/channel 5 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " E4 ,DMA Region Access enable for bit/channel 4 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,DMA Region Access enable for bit/channel 3 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA Region Access enable for bit/channel 2 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " E1 ,DMA Region Access enable for bit/channel 1 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA Region Access enable for bit/channel 0 Region 0" "Not allowed,Allowed"
|
|
group.long 0x348++0x3
|
|
line.long 0x00 "DRAE1,DMA Region Access Enable Register for Region 1"
|
|
bitfld.long 0x00 31. " E31 ,DMA Region Access enable for bit/channel 31 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA Region Access enable for bit/channel 30 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA Region Access enable for bit/channel 29 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " E28 ,DMA Region Access enable for bit/channel 28 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,DMA Region Access enable for bit/channel 27 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA Region Access enable for bit/channel 26 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " E25 ,DMA Region Access enable for bit/channel 25 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA Region Access enable for bit/channel 24 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,DMA Region Access enable for bit/channel 23 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 22. " E22 ,DMA Region Access enable for bit/channel 22 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA Region Access enable for bit/channel 21 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA Region Access enable for bit/channel 20 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA Region Access enable for bit/channel 19 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA Region Access enable for bit/channel 18 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA Region Access enable for bit/channel 17 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 16. " E16 ,DMA Region Access enable for bit/channel 16 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,DMA Region Access enable for bit/channel 15 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA Region Access enable for bit/channel 14 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " E13 ,DMA Region Access enable for bit/channel 13 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA Region Access enable for bit/channel 12 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,DMA Region Access enable for bit/channel 11 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 10. " E10 ,DMA Region Access enable for bit/channel 10 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA Region Access enable for bit/channel 9 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA Region Access enable for bit/channel 8 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA Region Access enable for bit/channel 7 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA Region Access enable for bit/channel 6 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA Region Access enable for bit/channel 5 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " E4 ,DMA Region Access enable for bit/channel 4 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,DMA Region Access enable for bit/channel 3 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA Region Access enable for bit/channel 2 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " E1 ,DMA Region Access enable for bit/channel 1 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA Region Access enable for bit/channel 0 Region 1" "Not allowed,Allowed"
|
|
group.long 0x350++0x3
|
|
line.long 0x00 "DRAE2,DMA Region Access Enable Register for Region 2"
|
|
bitfld.long 0x00 31. " E31 ,DMA Region Access enable for bit/channel 31 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA Region Access enable for bit/channel 30 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA Region Access enable for bit/channel 29 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " E28 ,DMA Region Access enable for bit/channel 28 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,DMA Region Access enable for bit/channel 27 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA Region Access enable for bit/channel 26 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " E25 ,DMA Region Access enable for bit/channel 25 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA Region Access enable for bit/channel 24 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,DMA Region Access enable for bit/channel 23 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 22. " E22 ,DMA Region Access enable for bit/channel 22 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA Region Access enable for bit/channel 21 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA Region Access enable for bit/channel 20 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA Region Access enable for bit/channel 19 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA Region Access enable for bit/channel 18 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA Region Access enable for bit/channel 17 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 16. " E16 ,DMA Region Access enable for bit/channel 16 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,DMA Region Access enable for bit/channel 15 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA Region Access enable for bit/channel 14 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " E13 ,DMA Region Access enable for bit/channel 13 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA Region Access enable for bit/channel 12 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,DMA Region Access enable for bit/channel 11 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 10. " E10 ,DMA Region Access enable for bit/channel 10 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA Region Access enable for bit/channel 9 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA Region Access enable for bit/channel 8 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA Region Access enable for bit/channel 7 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA Region Access enable for bit/channel 6 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA Region Access enable for bit/channel 5 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " E4 ,DMA Region Access enable for bit/channel 4 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,DMA Region Access enable for bit/channel 3 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA Region Access enable for bit/channel 2 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " E1 ,DMA Region Access enable for bit/channel 1 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA Region Access enable for bit/channel 0 Region 2" "Not allowed,Allowed"
|
|
group.long 0x358++0x3
|
|
line.long 0x00 "DRAE3,DMA Region Access Enable Register for Region 3"
|
|
bitfld.long 0x00 31. " E31 ,DMA Region Access enable for bit/channel 31 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 30. " E30 ,DMA Region Access enable for bit/channel 30 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 29. " E29 ,DMA Region Access enable for bit/channel 29 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 28. " E28 ,DMA Region Access enable for bit/channel 28 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,DMA Region Access enable for bit/channel 27 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 26. " E26 ,DMA Region Access enable for bit/channel 26 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 25. " E25 ,DMA Region Access enable for bit/channel 25 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " E24 ,DMA Region Access enable for bit/channel 24 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,DMA Region Access enable for bit/channel 23 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 22. " E22 ,DMA Region Access enable for bit/channel 22 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 21. " E21 ,DMA Region Access enable for bit/channel 21 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " E20 ,DMA Region Access enable for bit/channel 20 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,DMA Region Access enable for bit/channel 19 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " E18 ,DMA Region Access enable for bit/channel 18 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 17. " E17 ,DMA Region Access enable for bit/channel 17 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 16. " E16 ,DMA Region Access enable for bit/channel 16 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,DMA Region Access enable for bit/channel 15 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " E14 ,DMA Region Access enable for bit/channel 14 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " E13 ,DMA Region Access enable for bit/channel 13 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " E12 ,DMA Region Access enable for bit/channel 12 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,DMA Region Access enable for bit/channel 11 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 10. " E10 ,DMA Region Access enable for bit/channel 10 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " E9 ,DMA Region Access enable for bit/channel 9 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " E8 ,DMA Region Access enable for bit/channel 8 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,DMA Region Access enable for bit/channel 7 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " E6 ,DMA Region Access enable for bit/channel 6 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " E5 ,DMA Region Access enable for bit/channel 5 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " E4 ,DMA Region Access enable for bit/channel 4 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,DMA Region Access enable for bit/channel 3 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " E2 ,DMA Region Access enable for bit/channel 2 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " E1 ,DMA Region Access enable for bit/channel 1 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " E0 ,DMA Region Access enable for bit/channel 0 Region 3" "Not allowed,Allowed"
|
|
group.long 0x380++0xF
|
|
line.long 0x0 "QRAE0,QDMA Region Access Enable Register 0"
|
|
bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for bit/channel 7 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for bit/channel 6 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for bit/channel 5 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for bit/channel 4 Region 0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for bit/channel 3 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for bit/channel 2 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for bit/channel 1 Region 0" "Not allowed,Allowed"
|
|
bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for bit/channel 0 Region 0" "Not allowed,Allowed"
|
|
line.long 0x4 "QRAE1,QDMA Region Access Enable Register 1"
|
|
bitfld.long 0x4 7. " E7 ,QDMA Region Access enable for bit/channel 7 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x4 6. " E6 ,QDMA Region Access enable for bit/channel 6 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x4 5. " E5 ,QDMA Region Access enable for bit/channel 5 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x4 4. " E4 ,QDMA Region Access enable for bit/channel 4 Region 1" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x4 3. " E3 ,QDMA Region Access enable for bit/channel 3 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x4 2. " E2 ,QDMA Region Access enable for bit/channel 2 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x4 1. " E1 ,QDMA Region Access enable for bit/channel 1 Region 1" "Not allowed,Allowed"
|
|
bitfld.long 0x4 0. " E0 ,QDMA Region Access enable for bit/channel 0 Region 1" "Not allowed,Allowed"
|
|
line.long 0x8 "QRAE2,QDMA Region Access Enable Register 2"
|
|
bitfld.long 0x8 7. " E7 ,QDMA Region Access enable for bit/channel 7 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x8 6. " E6 ,QDMA Region Access enable for bit/channel 6 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x8 5. " E5 ,QDMA Region Access enable for bit/channel 5 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x8 4. " E4 ,QDMA Region Access enable for bit/channel 4 Region 2" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x8 3. " E3 ,QDMA Region Access enable for bit/channel 3 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x8 2. " E2 ,QDMA Region Access enable for bit/channel 2 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x8 1. " E1 ,QDMA Region Access enable for bit/channel 1 Region 2" "Not allowed,Allowed"
|
|
bitfld.long 0x8 0. " E0 ,QDMA Region Access enable for bit/channel 0 Region 2" "Not allowed,Allowed"
|
|
line.long 0xC "QRAE3,QDMA Region Access Enable Register 3"
|
|
bitfld.long 0xC 7. " E7 ,QDMA Region Access enable for bit/channel 7 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0xC 6. " E6 ,QDMA Region Access enable for bit/channel 6 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0xC 5. " E5 ,QDMA Region Access enable for bit/channel 5 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0xC 4. " E4 ,QDMA Region Access enable for bit/channel 4 Region 3" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0xC 3. " E3 ,QDMA Region Access enable for bit/channel 3 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0xC 2. " E2 ,QDMA Region Access enable for bit/channel 2 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0xC 1. " E1 ,QDMA Region Access enable for bit/channel 1 Region 3" "Not allowed,Allowed"
|
|
bitfld.long 0xC 0. " E0 ,QDMA Region Access enable for bit/channel 0 Region 3" "Not allowed,Allowed"
|
|
tree.end
|
|
tree "Status/Debug Visibility Registers"
|
|
rgroup.long 0x400++0x3f "Event Queue 0 Registers"
|
|
line.long 0x0 "Q0E0 ,Event Queue Entry 0 Register"
|
|
bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x0 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x4 "Q0E1 ,Event Queue Entry 1 Register"
|
|
bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x4 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x8 "Q0E2 ,Event Queue Entry 2 Register"
|
|
bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x8 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0xC "Q0E3 ,Event Queue Entry 3 Register"
|
|
bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0xC 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x10 "Q0E4 ,Event Queue Entry 4 Register"
|
|
bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x10 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x14 "Q0E5 ,Event Queue Entry 5 Register"
|
|
bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x14 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x18 "Q0E6 ,Event Queue Entry 6 Register"
|
|
bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x18 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x1C "Q0E7 ,Event Queue Entry 7 Register"
|
|
bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x1C 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x20 "Q0E8 ,Event Queue Entry 8 Register"
|
|
bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x20 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x24 "Q0E9 ,Event Queue Entry 9 Register"
|
|
bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x24 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x28 "Q0E10,Event Queue Entry 10 Register"
|
|
bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x28 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x2C "Q0E11,Event Queue Entry 11 Register"
|
|
bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x2C 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x30 "Q0E12,Event Queue Entry 12 Register"
|
|
bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x30 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x34 "Q0E13,Event Queue Entry 13 Register"
|
|
bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x34 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x38 "Q0E14,Event Queue Entry 14 Register"
|
|
bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x38 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x3C "Q0E15,Event Queue Entry 15 Register"
|
|
bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x3C 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
rgroup.long 0x440++0x3f "Event Queue 1 Registers"
|
|
line.long 0x0 "Q1E0 ,Event Queue Entry 0 Register"
|
|
bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x0 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x4 "Q1E1 ,Event Queue Entry 1 Register"
|
|
bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x4 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x8 "Q1E2 ,Event Queue Entry 2 Register"
|
|
bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x8 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0xC "Q1E3 ,Event Queue Entry 3 Register"
|
|
bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0xC 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x10 "Q1E4 ,Event Queue Entry 4 Register"
|
|
bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x10 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x14 "Q1E5 ,Event Queue Entry 5 Register"
|
|
bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x14 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x18 "Q1E6 ,Event Queue Entry 6 Register"
|
|
bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x18 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x1C "Q1E7 ,Event Queue Entry 7 Register"
|
|
bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x1C 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x20 "Q1E8 ,Event Queue Entry 8 Register"
|
|
bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x20 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x24 "Q1E9 ,Event Queue Entry 9 Register"
|
|
bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x24 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x28 "Q1E10,Event Queue Entry 10 Register"
|
|
bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x28 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x2C "Q1E11,Event Queue Entry 11 Register"
|
|
bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x2C 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x30 "Q1E12,Event Queue Entry 12 Register"
|
|
bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x30 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x34 "Q1E13,Event Queue Entry 13 Register"
|
|
bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x34 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x38 "Q1E14,Event Queue Entry 14 Register"
|
|
bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x38 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
line.long 0x3C "Q1E15,Event Queue Entry 15 Register"
|
|
bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x3C 0.--4. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA/QDMA 4,DMA/QDMA 5,DMA/QDMA 6,DMA/QDMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31"
|
|
else
|
|
bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0 ,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63"
|
|
endif
|
|
rgroup.long 0x600++0x7 "Queue Status Registers"
|
|
line.long 0x0 "QSTAT0,Queue 0 Status Register"
|
|
bitfld.long 0x0 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1707"||cpu()=="AM1705"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x0 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x0 8.--12. " NUMVAL ,Number of valid entrier in queue 0" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
elif (CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="AM1808")
|
|
bitfld.long 0x0 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10(full),?..."
|
|
bitfld.long 0x0 8.--12. " NUMVAL ,Number of valid entrier in queue 0" "0(empty),1,2,3,4,5,6,7,8,9,10(full),?..."
|
|
else
|
|
bitfld.long 0x0 16.--20. " WM ,Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0 8.--12. " NUMVAL ,Number of valid entrier in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x0 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "QSTAT1,Queue 1 Status Register"
|
|
bitfld.long 0x4 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1707"||cpu()=="AM1705"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x4 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
bitfld.long 0x4 8.--12. " NUMVAL ,Number of valid entrier in queue 1" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..."
|
|
elif (CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="AM1808")
|
|
bitfld.long 0x4 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10(full),?..."
|
|
bitfld.long 0x4 8.--12. " NUMVAL ,Number of valid entrier in queue 1" "0(empty),1,2,3,4,5,6,7,8,9,10(full),?..."
|
|
else
|
|
bitfld.long 0x4 16.--20. " WM ,Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x4 8.--12. " NUMVAL ,Number of valid entrier in queue 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x4 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline ""
|
|
textline ""
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "QWMTHRA,Queue Watermark Threshold A Register"
|
|
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for queue 1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..."
|
|
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for queue 0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..."
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x00 "CCSTAT,EDMA3CC Status Register"
|
|
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active" "Not active,Active"
|
|
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active" "Not active,Active"
|
|
textline " "
|
|
sif (cpu()=="OMAP-L137"||cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="AM1707"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "No requests,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Not active,Active"
|
|
else
|
|
hexmask.long.byte 0x00 8.--13. 1. " COMPACTV ,Completion request active"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Not active,Active"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " WSTATACTV ,Write status interface active" "Idle,Busy"
|
|
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active"
|
|
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active"
|
|
tree.end
|
|
tree.end
|
|
tree "Global Channel Registers"
|
|
width 7.
|
|
group.long (0x1000+0x00)++0x3 "Event Registers"
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
rgroup.long (0x1000+0x18)++0x3
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
group.long (0x1000+0x20)++0x3
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
rgroup.long (0x1000+0x38)++0x3
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
wgroup.long (0x1000+0x40)++0x3
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event clear 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event clear 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event clear 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Secondary event clear 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Secondary event clear 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event clear 26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Secondary event clear 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event clear 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Secondary event clear 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Secondary event clear 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event clear 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event clear 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event clear 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event clear 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event clear 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Secondary event clear 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Secondary event clear 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event clear 14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Secondary event clear 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event clear 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Secondary event clear 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Secondary event clear 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event clear 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event clear 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event clear 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event clear 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event clear 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Secondary event clear 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Secondary event clear 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event clear 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Secondary event clear 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event clear 0" "No effect,Clear"
|
|
group.long (0x1000+0x50)++0x3 "Interrupt Registers"
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x1000+0x68)++0x3
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
wgroup.long (0x1000+0x70)++0x3
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
wgroup.long (0x1000+0x78)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
rgroup.long (0x1000+0x80)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x1000+0x84)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x1000+0x90)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x1000+0x94)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
width 0xb
|
|
tree.end
|
|
tree "Shadow Region 0 Channel Registers"
|
|
width 7.
|
|
group.long (0x2000+0x00)++0x3 "Event Registers"
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
rgroup.long (0x2000+0x18)++0x3
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
group.long (0x2000+0x20)++0x3
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
rgroup.long (0x2000+0x38)++0x3
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
wgroup.long (0x2000+0x40)++0x3
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event clear 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event clear 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event clear 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Secondary event clear 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Secondary event clear 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event clear 26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Secondary event clear 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event clear 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Secondary event clear 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Secondary event clear 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event clear 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event clear 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event clear 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event clear 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event clear 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Secondary event clear 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Secondary event clear 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event clear 14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Secondary event clear 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event clear 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Secondary event clear 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Secondary event clear 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event clear 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event clear 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event clear 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event clear 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event clear 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Secondary event clear 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Secondary event clear 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event clear 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Secondary event clear 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event clear 0" "No effect,Clear"
|
|
group.long (0x2000+0x50)++0x3 "Interrupt Registers"
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2000+0x68)++0x3
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
wgroup.long (0x2000+0x70)++0x3
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
wgroup.long (0x2000+0x78)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
rgroup.long (0x2000+0x80)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2000+0x84)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2000+0x90)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2000+0x94)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
width 0xb
|
|
tree.end
|
|
tree "Shadow Region 1 Channel Registers"
|
|
width 7.
|
|
group.long (0x2200+0x00)++0x3 "Event Registers"
|
|
line.long 0x00 "ER,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted"
|
|
rgroup.long (0x2200+0x18)++0x3
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized"
|
|
bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized"
|
|
bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized"
|
|
bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized"
|
|
bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized"
|
|
bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized"
|
|
bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized"
|
|
bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized"
|
|
bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized"
|
|
bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized"
|
|
bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized"
|
|
bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized"
|
|
bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized"
|
|
bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized"
|
|
bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized"
|
|
bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized"
|
|
bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized"
|
|
bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized"
|
|
bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized"
|
|
group.long (0x2200+0x20)++0x3
|
|
line.long 0x00 "EER,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled"
|
|
rgroup.long (0x2200+0x38)++0x3
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored"
|
|
bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored"
|
|
wgroup.long (0x2200+0x40)++0x3
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Secondary event clear 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Secondary event clear 30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Secondary event clear 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Secondary event clear 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " E27 ,Secondary event clear 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Secondary event clear 26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Secondary event clear 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Secondary event clear 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " E23 ,Secondary event clear 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Secondary event clear 22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Secondary event clear 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Secondary event clear 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " E19 ,Secondary event clear 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Secondary event clear 18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Secondary event clear 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Secondary event clear 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " E15 ,Secondary event clear 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Secondary event clear 14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Secondary event clear 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Secondary event clear 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " E11 ,Secondary event clear 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Secondary event clear 10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Secondary event clear 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Secondary event clear 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " E7 ,Secondary event clear 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Secondary event clear 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Secondary event clear 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Secondary event clear 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,Secondary event clear 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Secondary event clear 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Secondary event clear 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Secondary event clear 0" "No effect,Clear"
|
|
group.long (0x2200+0x50)++0x3 "Interrupt Registers"
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2200+0x68)++0x3
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected"
|
|
wgroup.long (0x2200+0x70)++0x3
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear"
|
|
wgroup.long (0x2200+0x78)++0x3
|
|
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
|
|
bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse"
|
|
rgroup.long (0x2200+0x80)++0x3
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
|
|
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
|
|
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
|
|
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
|
|
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
|
|
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
|
|
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
|
|
group.long (0x2200+0x84)++0x3
|
|
line.long 0x00 "QEER,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
|
|
rgroup.long (0x2200+0x90)++0x3
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored"
|
|
wgroup.long (0x2200+0x94)++0x3
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear"
|
|
width 0xb
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "EDMA3 TC0"
|
|
base asd:0x01c08000
|
|
width 8.
|
|
rgroup.long 0x00++0x7
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
else
|
|
line.long 0x00 "PID,Peripheral Identification Register"
|
|
endif
|
|
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth" "1 entry,2 entry,4 entry,?..."
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "32-bit,64-bit,?..."
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "32-byte,64-byte,128-byte,256-byte,?..."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
|
|
bitfld.long 0x00 11.--12. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
width 13.
|
|
rgroup.long 0x120++0x03 "Error Registers"
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ERREN,Error Enable Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable for transfer request error" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt enable for bus error" "Disabled,Enabled"
|
|
wgroup.long 0x128++0x03
|
|
line.long 0x00 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable clear for the MMR address error" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable clear for the transfer request error" "No effect,Clear"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt clear for the bus error" "No effect,Clear"
|
|
rgroup.long 0x12c++0x3
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read addressing error,Read privilege error,Read timeout error,Read data error,Reserved,Reserved,Read exclusive operation error,Reserved,Write addressing error,Write privilege error,Write timeout error,Write data error,Reserved,Reserved,Write exclusive operation error"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulse"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "As fast as possible,4 cycles,8 cycles,16 cycles,32 cycles,?..."
|
|
group.long 0x240++0x3 "Source Active Registers"
|
|
line.long 0x00 "SAOPT,Source Active Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long 0x244++0x1f
|
|
line.long 0x00 "SASRC,Source Active Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "SADST,Source Active Destination Address Register"
|
|
line.long 0x0c "SABIDX,Source Active Source B-Dimension Index Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "SAMPPRXY,Source Active Memory Protection Proxy Register"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
line.long 0x14 "SACNTRLD,Source Active Count Reload Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x18 "SASRCBREF,Source Active Source Address B-Reference Register"
|
|
line.long 0x1c "SADSTBREF,Source Active Destination Address B-Reference Register"
|
|
rgroup.long 0x280++0xb "Destination FIFO Registers"
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x04 "DFSRCBREF,Destination FIFO Set Source Address B-Reference Register"
|
|
line.long 0x08 "DFDSTBREF,Destination FIFO Set Destination Address B-Reference"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DFOPT0,Destination FIFO Options Register 0"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x300+0x4)++0x13
|
|
line.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0"
|
|
line.long 0x04 "DFCNT0,Destination FIFO Count Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST0,Destination FIFO Destination Address Register 0"
|
|
line.long 0x0c "DFBIDX0,Destination FIFO B-Dimension Index Register 0"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "DFOPT1,Destination FIFO Options Register 1"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x340+0x4)++0x13
|
|
line.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1"
|
|
line.long 0x04 "DFCNT1,Destination FIFO Count Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST1,Destination FIFO Destination Address Register 1"
|
|
line.long 0x0c "DFBIDX1,Destination FIFO B-Dimension Index Register 1"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DFOPT2,Destination FIFO Options Register 2"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x380+0x4)++0x13
|
|
line.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2"
|
|
line.long 0x04 "DFCNT2,Destination FIFO Count Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST2,Destination FIFO Destination Address Register 2"
|
|
line.long 0x0c "DFBIDX2,Destination FIFO B-Dimension Index Register 2"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "DFOPT3,Destination FIFO Options Register 3"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x3C0+0x4)++0x13
|
|
line.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3"
|
|
line.long 0x04 "DFCNT3,Destination FIFO Count Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST3,Destination FIFO Destination Address Register 3"
|
|
line.long 0x0c "DFBIDX3,Destination FIFO B-Dimension Index Register 3"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
tree.end
|
|
tree "EDMA3 TC1"
|
|
base asd:0x01c08400
|
|
width 8.
|
|
rgroup.long 0x00++0x7
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
else
|
|
line.long 0x00 "PID,Peripheral Identification Register"
|
|
endif
|
|
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth" "1 entry,2 entry,4 entry,?..."
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "32-bit,64-bit,?..."
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "32-byte,64-byte,128-byte,256-byte,?..."
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
|
|
bitfld.long 0x00 11.--12. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
width 13.
|
|
rgroup.long 0x120++0x03 "Error Registers"
|
|
line.long 0x00 "ERRSTAT,Error Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ERREN,Error Enable Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable for transfer request error" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt enable for bus error" "Disabled,Enabled"
|
|
wgroup.long 0x128++0x03
|
|
line.long 0x00 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x00 3. " MMRAERR ,Interrupt enable clear for the MMR address error" "No effect,Clear"
|
|
bitfld.long 0x00 2. " TRERR ,Interrupt enable clear for the transfer request error" "No effect,Clear"
|
|
bitfld.long 0x00 0. " BUSERR ,Interrupt clear for the bus error" "No effect,Clear"
|
|
rgroup.long 0x12c++0x3
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read addressing error,Read privilege error,Read timeout error,Read data error,Reserved,Reserved,Read exclusive operation error,Reserved,Write addressing error,Write privilege error,Write timeout error,Write data error,Reserved,Reserved,Write exclusive operation error"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
|
|
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulse"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "As fast as possible,4 cycles,8 cycles,16 cycles,32 cycles,?..."
|
|
group.long 0x240++0x3 "Source Active Registers"
|
|
line.long 0x00 "SAOPT,Source Active Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long 0x244++0x1f
|
|
line.long 0x00 "SASRC,Source Active Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "SADST,Source Active Destination Address Register"
|
|
line.long 0x0c "SABIDX,Source Active Source B-Dimension Index Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "SAMPPRXY,Source Active Memory Protection Proxy Register"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
line.long 0x14 "SACNTRLD,Source Active Count Reload Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x18 "SASRCBREF,Source Active Source Address B-Reference Register"
|
|
line.long 0x1c "SADSTBREF,Source Active Destination Address B-Reference Register"
|
|
rgroup.long 0x280++0xb "Destination FIFO Registers"
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
|
|
line.long 0x04 "DFSRCBREF,Destination FIFO Set Source Address B-Reference Register"
|
|
line.long 0x08 "DFDSTBREF,Destination FIFO Set Destination Address B-Reference"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DFOPT0,Destination FIFO Options Register 0"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x300+0x4)++0x13
|
|
line.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0"
|
|
line.long 0x04 "DFCNT0,Destination FIFO Count Register 0"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST0,Destination FIFO Destination Address Register 0"
|
|
line.long 0x0c "DFBIDX0,Destination FIFO B-Dimension Index Register 0"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "DFOPT1,Destination FIFO Options Register 1"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x340+0x4)++0x13
|
|
line.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1"
|
|
line.long 0x04 "DFCNT1,Destination FIFO Count Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST1,Destination FIFO Destination Address Register 1"
|
|
line.long 0x0c "DFBIDX1,Destination FIFO B-Dimension Index Register 1"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DFOPT2,Destination FIFO Options Register 2"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x380+0x4)++0x13
|
|
line.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2"
|
|
line.long 0x04 "DFCNT2,Destination FIFO Count Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST2,Destination FIFO Destination Address Register 2"
|
|
line.long 0x0c "DFBIDX2,Destination FIFO B-Dimension Index Register 2"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "DFOPT3,Destination FIFO Options Register 3"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,?..."
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
|
|
rgroup.long (0x3C0+0x4)++0x13
|
|
line.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3"
|
|
line.long 0x04 "DFCNT3,Destination FIFO Count Register 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
|
|
line.long 0x08 "DFDST3,Destination FIFO Destination Address Register 3"
|
|
line.long 0x0c "DFBIDX3,Destination FIFO B-Dimension Index Register 3"
|
|
hexmask.long.word 0x0c 16.--31. 1. " DSTBIDX ,B-Index offset between destination arrays"
|
|
hexmask.long.word 0x0c 0.--15. 1. " SRCBIDX ,B-Index offset between source arrays"
|
|
line.long 0x10 "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3"
|
|
bitfld.long 0x10 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,CPU sets,?..."
|
|
else
|
|
bitfld.long 0x10 0.--3. " PRIVID ,Privilege ID" "Any other master,DSP sets,?..."
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "EMIF (External Memory Interface)"
|
|
tree "EMIFA"
|
|
base asd:0x68000000
|
|
width 11.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MIDR,Module ID Register"
|
|
group.long 0x04++0x0b
|
|
line.long 0x00 "AWCC,Asynchronous Wait Cycle Configuration Register"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||cpu()=="AM1707"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 29. " WP1 ,EMA_WAIT [1] Polarity bit" "Low,High"
|
|
bitfld.long 0x00 28. " WP0 ,EMA_WAIT[0] Polarity bit" "Low,High"
|
|
else
|
|
bitfld.long 0x00 28. " WP0 ,EMA_WAIT[0] Polarity bit" "Low,High"
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||cpu()=="AM1707"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 22.--23. " CS5_WAIT ,Chip Select 5 WAIT signal selection" "EMA_WAIT[0],EMA_WAIT[1],?..."
|
|
bitfld.long 0x00 20.--21. " CS4_WAIT ,Chip Select 4 WAIT signal selection" "EMA_WAIT[0],EMA_WAIT[1],?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CS3_WAIT ,Chip Select 3 WAIT signal selection" "EMA_WAIT[0],EMA_WAIT[1],?..."
|
|
bitfld.long 0x00 16.--17. " CS2_WAIT ,Chip Select 2 WAIT signal selection" "EMA_WAIT[0],EMA_WAIT[1],?..."
|
|
else
|
|
bitfld.long 0x00 22.--23. " CS5_WAIT ,Chip Select 5 WAIT signal selection" "EMA_WAIT[0],?..."
|
|
bitfld.long 0x00 20.--21. " CS4_WAIT ,Chip Select 4 WAIT signal selection" "EMA_WAIT[0],?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CS3_WAIT ,Chip Select 3 WAIT signal selection" "EMA_WAIT[0],?..."
|
|
bitfld.long 0x00 16.--17. " CS2_WAIT ,Chip Select 2 WAIT signal selection" "EMA_WAIT[0],?..."
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MAX_EXT_WAIT ,Maximum extended wait cycles"
|
|
line.long 0x04 "SDCR,SDRAM Configuration Register"
|
|
bitfld.long 0x04 31. " SR ,Self-Refresh mode bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " PD ,Power Down bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " PDWR ,Perform refreshes during power down" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NM ,Narrow mode bit" "32-bit,16-bit"
|
|
bitfld.long 0x04 9.--11. " CL ,CAS Latency" "Reserved,Reserved,2 cycles,3 cycles,?..."
|
|
bitfld.long 0x04 8. " BIT11_9LOCK ,Bits 11 to 9 lock" "Not writeable,Writeable"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " IBANK ,Internal SDRAM Bank size" "1,2,4,?..."
|
|
bitfld.long 0x04 0.--2. " PAGESIZE ,Page Size" "256,512,1024,2048,?..."
|
|
line.long 0x08 "SDRCR,SDRAM Refresh Control Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " RR ,Refresh Rate"
|
|
group.long 0x10--0x1F
|
|
line.long 0x0 "CE2CFG,Asynchronous 2 Configuration Register"
|
|
bitfld.long 0x0 31. " SS ,Select strobe mode" "Normal,Strobe"
|
|
bitfld.long 0x0 30. " EW ,Extended wait cycles enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. " TA ,Minimum turn-around time" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
|
|
line.long 0x4 "CE3CFG,Asynchronous 3 Configuration Register"
|
|
bitfld.long 0x4 31. " SS ,Select strobe mode" "Normal,Strobe"
|
|
bitfld.long 0x4 30. " EW ,Extended wait cycles enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x4 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x4 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2.--3. " TA ,Minimum turn-around time" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
|
|
line.long 0x8 "CE4CFG,Asynchronous 4 Configuration Register"
|
|
bitfld.long 0x8 31. " SS ,Select strobe mode" "Normal,Strobe"
|
|
bitfld.long 0x8 30. " EW ,Extended wait cycles enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x8 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x8 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2.--3. " TA ,Minimum turn-around time" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
|
|
line.long 0xC "CE5CFG,Asynchronous 5 Configuration Register"
|
|
bitfld.long 0xC 31. " SS ,Select strobe mode" "Normal,Strobe"
|
|
bitfld.long 0xC 30. " EW ,Extended wait cycles enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0xC 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0xC 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 2.--3. " TA ,Minimum turn-around time" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SDTIMR,SDRAM Timing Register"
|
|
bitfld.long 0x00 27.--31. " T_RFC ,EMA_CLK cycles from a refresh command to a refresh command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
bitfld.long 0x00 24.--26. " T_RP ,EMA_CLK cycles from a precharge command to a refresh or activate command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 20.--22. " T_RCD ,EMA_CLK cycles from an activate command to a read or write command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " T_WR ,EMA_CLK cycles from the last write transfer to a precharge command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 12.--15. " T_RAS ,EMA_CLK cycles from an activate command to a precharge command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x00 8.--11. " T_RC ,EMA_CLK cycles from an activate command to an activate command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " T_RRD ,EMA_CLK cycles from an activate command to an activate command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
group.long 0x3c++0x03
|
|
line.long 0x00 "SDSRETR,SDRAM Self Refresh Exit Timing Register"
|
|
bitfld.long 0x00 0.--4. " T_XS ,Minimum number of ECLKOUT cycles from Self-Refresh exit to any command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "INTRAW,EMIF Interrupt Raw Register"
|
|
eventfld.long 0x00 2. " WR ,Wait Rise" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " LT ,Line Trap" "No effect,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " AT ,Asynchronous timeout occurre" "Not occurred,Occurred"
|
|
line.long 0x04 "INTMSK,EMIF Interrupt Mask Register"
|
|
setclrfld.long 0x04 2. 0x08 2. 0x0c 2. " WRM_set/clr ,Wait Rise Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0c 1. " LTM_set/clr ,Masked Line Trap" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0c 0. " ATM_set/clr ,Asynchronous Timeout Mask" "Disabled,Enabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "NANDFCR,NAND Flash Control Register"
|
|
bitfld.long 0x00 13. " 4BITECC_ADD_CALC_START ,NAND Flash 4-bit ECC address and error value calculation Start" "Not started,Started"
|
|
bitfld.long 0x00 12. " 4BITECC_START ,Nand Flash 4-bit ECC start for the selected chip select" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CS5ECC ,NAND Flash ECC start for chip select 5" "Not started,Started"
|
|
bitfld.long 0x00 10. " CS4ECC ,NAND Flash ECC start for chip select 4" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CS3ECC ,NAND Flash ECC start for chip select 3" "Not started,Started"
|
|
bitfld.long 0x00 8. " CS2ECC ,NAND Flash ECC start for chip select 2" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " 4BITECCSEL ,4 Bit ECC selection" "CS2,CS3,CS4,CS5"
|
|
bitfld.long 0x00 3. " CS5NAND ,NAND Flash mode for chip select 5" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CS4NAND ,NAND Flash mode for chip select 4" "Not used,Used"
|
|
bitfld.long 0x00 1. " CS3NAND ,NAND Flash mode for chip select 3" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CS2NAND ,NAND Flash mode for chip select 2" "Not used,Used"
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x00 "NANDFSR,NAND Flash Status Register"
|
|
bitfld.long 0x00 16.--17. " ECC_ERRNUM ,Number of Errors found after the 4-Bit ECC Error Address and Error Value Calculation" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ECC_STATE ,NECC correction state while performing 4-bit ECC Address and Error Value Calculation" "No errors,Errors cannot be corrected (5 or more),Error correction complete(errors on bit 8 or 9),Error correction complete(error exists),Reserved,Calculating number of errors,Preparing for error search,Preparing for error search,Searching for errors,Reserved,Reserved,Reserved,Calculating error value,Calculating error value,Calculating error value,Calculating error value"
|
|
textline " "
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||cpu()=="DA828"||cpu()=="DA830"||cpu()=="AM1705"||cpu()=="AM1707"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 1. " WAITST1 ,Raw status of the EMA_WAIT input pin" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " WAITST0 ,Raw status of the EMA_WAIT input pin" "0,1"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830")
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "PMCR,Page Mode Control Register"
|
|
hexmask.long.byte 0x00 26.--31. 1. " CS5_PG_DEL ,Page access delay for NOR Flash connected on CS5"
|
|
bitfld.long 0x00 25. " CS5_PG_SIZE ,Page Size for NOR Flash connected on CS5" "4 words,8 words"
|
|
bitfld.long 0x00 24. " CS5_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS5" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--23. 1. " CS4_PG_DEL ,Page access delay for NOR Flash connected on CS4"
|
|
bitfld.long 0x00 17. " CS4_PG_SIZE ,Page Size for NOR Flash connected on CS4" "4 words,8 words"
|
|
bitfld.long 0x00 16. " CS4_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS4" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 10.--15. 1. " CS3_PG_DEL ,Page access delay for NOR Flash connected on CS3"
|
|
bitfld.long 0x00 14. " CS3_PG_SIZE ,Page Size for NOR Flash connected on CS3" "4 words,8 words"
|
|
bitfld.long 0x00 13. " CS3_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS3" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--7. 1. " CS2_PG_DEL ,Page access delay for NOR Flash connected on CS2"
|
|
bitfld.long 0x00 1. " CS2_PG_SIZE ,Page Size for NOR Flash connected on CS2" "4 words,8 words"
|
|
bitfld.long 0x00 0. " CS2_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS2" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x70--0x7F
|
|
line.long 0x0 "NANDF1ECC,NAND Flash 1 ECC Register"
|
|
bitfld.long 0x0 27. " P2048O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 24. " P256O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 23. " P128O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 21. " P32O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 19. " P8O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 18. " P4O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 8. " P256E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 7. " P128E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 5. " P32E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 3. " P8E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 2. " P4E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
line.long 0x4 "NANDF2ECC,NAND Flash 2 ECC Register"
|
|
bitfld.long 0x4 27. " P2048O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 24. " P256O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 23. " P128O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 21. " P32O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 19. " P8O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 18. " P4O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 8. " P256E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 7. " P128E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 5. " P32E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 3. " P8E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 2. " P4E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
line.long 0x8 "NANDF3ECC,NAND Flash 3 ECC Register"
|
|
bitfld.long 0x8 27. " P2048O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 24. " P256O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 23. " P128O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 21. " P32O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 19. " P8O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 18. " P4O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 8. " P256E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 7. " P128E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 5. " P32E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 3. " P8E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 2. " P4E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
line.long 0xC "NANDF4ECC,NAND Flash 4 ECC Register"
|
|
bitfld.long 0xC 27. " P2048O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 24. " P256O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 23. " P128O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 21. " P32O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 19. " P8O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 18. " P4O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 8. " P256E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 7. " P128E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 5. " P32E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 3. " P8E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 2. " P4E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,ECC code calculated while reading/writing NAND Flash" "0,1"
|
|
width 16.
|
|
group.long 0xbc++0x13
|
|
line.long 0x00 "NAND4BITECCLOAD,NAND Flash 4-bit ECC LOAD Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " 4BITECCLOAD ,4-bit ECC load"
|
|
line.long 0x04 "NAND4BITECC1,NAND Flash 4-bit ECC Register 1"
|
|
hexmask.long.word 0x04 16.--25. 1. " 4BITECCVAL2 ,Calculated 4-bit ECC or Syndrom Value2"
|
|
hexmask.long.word 0x04 0.--9. 1. " 4BITECCVAL1 ,Calculated 4-bit ECC or Syndrom Value1"
|
|
line.long 0x08 "NAND4BITECC2,NAND Flash 4-bit ECC Register 2"
|
|
hexmask.long.word 0x08 16.--25. 1. " 4BITECCVAL4 ,Calculated 4-bit ECC or Syndrom Value4"
|
|
hexmask.long.word 0x08 0.--9. 1. " 4BITECCVAL3 ,Calculated 4-bit ECC or Syndrom Value3"
|
|
line.long 0x0c "NAND4BITECC3,NAND Flash 4-bit ECC Register 3"
|
|
hexmask.long.word 0x0C 16.--25. 1. " 4BITECCVAL6 ,Calculated 4-bit ECC or Syndrom Value6"
|
|
hexmask.long.word 0x0C 0.--9. 1. " 4BITECCVAL5 ,Calculated 4-bit ECC or Syndrom Value5"
|
|
line.long 0x10 "NAND4BITECC4,NAND Flash 4-bit ECC Register 4"
|
|
hexmask.long.word 0x10 16.--25. 1. " 4BITECCVAL8 ,Calculated 4-bit ECC or Syndrom Value8"
|
|
hexmask.long.word 0x10 0.--9. 1. " 4BITECCVAL7 ,Calculated 4-bit ECC or Syndrom Value7"
|
|
hgroup.long 0xd0++0x3
|
|
hide.long 0x00 "NANDERRADD1,NAND Flash 4-bit ECC Error Address Register 1"
|
|
in
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "NANDERRADD2,NAND Flash 4-bit ECC Error Address Register 2"
|
|
in
|
|
hgroup.long 0xd8++0x3
|
|
hide.long 0x00 "NANDERRVAL1,NAND Flash 4-bit ECC Error Value Register 1"
|
|
in
|
|
hgroup.long 0xdc++0x3
|
|
hide.long 0x00 "NANDERRVAL2,NAND Flash 4-bit ECC Error Value Register 2"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "EMIFB"
|
|
base asd:0xb0000000
|
|
width 9.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
group.long 0x08++0xf
|
|
line.long 0x00 "SDCFG,SDRAM Configuration Register"
|
|
bitfld.long 0x00 26. " IBANK_POS ,Internal bank position" "SDR,Mobile"
|
|
bitfld.long 0x00 25. " MSDRAM_EN ,Mobile SDRAM Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " BOOT_UNLOCK ,Boot unlock" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " SDREN ,SDRAM enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMUNLOCK ,Timing unlock" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " NM ,Narrow mode" "32-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL ,CAS latency" "Reserved,Reserved,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " IBANK ,Internal SDRAM bank setup" "1 bank,2 bank,4 bank,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " EBANK ,External chip select setup" "EMB_CS,?..."
|
|
bitfld.long 0x00 0.--2. " PAGESIZE ,Page size" "256-word,512-word,1024-word,2048-word,?..."
|
|
line.long 0x04 "SDRFC,SDRAM Refresh Control Register"
|
|
bitfld.long 0x04 31. " LP_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " MCLKSTOP_EN ,Mclk Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SR_PD ,Self-refresh or power-down select" "Self-refresh,Power-down"
|
|
hexmask.long.word 0x04 0.--15. 1. " REFRESH_RATE ,Refresh rate"
|
|
line.long 0x08 "SDTIM1,SDRAM Timing 1 Register"
|
|
hexmask.long.byte 0x08 25.--31. 1. " T_RFC ,EMB_CLK cycles from a refresh or load mode command to a refresh or activate command"
|
|
bitfld.long 0x08 22.--24. " T_RP ,EMB_CLK cycles from a precharge command to a refresh or activate command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x08 19.--21. " T_RCD ,EMB_CLK cycles from an activate command to a read or write command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " T_WR ,EMB_CLK cycles from the last write transfer to a precharge command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x08 11.--15. " T_RAS ,EMB_CLK cycles from an activate command to a precharge command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
bitfld.long 0x08 6.--10. " T_RC ,EMB_CLK cycles from an activate command to an activate command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " T_RRD ,EMB_CLK cycles from an activate command to an activate command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
line.long 0x0c "SDTIM2,SDRAM Timing 2 Register"
|
|
bitfld.long 0x0c 27.--30. " T_RAS_MAX ,Maximum number of refresh_rate intervals from Activate to Precharge command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
hexmask.long.byte 0x0c 16.--22. 1. " T_XSR ,EMB_CLK cycles from Self-Refresh exit to any command other than read"
|
|
bitfld.long 0x0c 0.--4. " T_CKE ,EMIFx_CLK cycles between EMB_SDCKE changes" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
group.long 0x1c++0x7
|
|
line.long 0x00 "SDCFG2,SDRAM Configuration 2 Register"
|
|
bitfld.long 0x00 16.--18. " PASR ,Partial Array Self Refresh" "4 banks,2 banks,1 bank,Reserved,Reserved,1/2 bank,1/4 bank,?..."
|
|
bitfld.long 0x00 0.--2. " ROWSIZE ,Number of row address bits of connected mobile SDRAM devices" "9,10,11,12,13,14,?..."
|
|
line.long 0x04 "BPRIO,Peripheral Bus Burst Priority Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PRIO_RAISE ,Priority raise old counter"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x00 "PC1,Performance Counter 1 Register"
|
|
line.long 0x04 "PC2,Performance Counter 2 Register"
|
|
group.long 0x48++0x7
|
|
line.long 0x00 "PCC,Performance Counter Configuration Register"
|
|
bitfld.long 0x00 31. " CNTR2_MSTID_EN ,Master ID filter enable for performance counter 2 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CNTR2_REGION_EN ,Chip select filter enable for performance counter 2 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for performance counter 2 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CNTR1_MSTID_EN ,Master ID filter enable for performance counter 1 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CNTR1_REGION_EN ,Chip select filter enable for performance counter 1 register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for performance counter 1 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PCMRS,Performance Counter Master Region Select Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MST_ID2 ,Master ID for performance counter 2 register"
|
|
bitfld.long 0x04 16.--19. " REGION_SEL2 ,Region select for performance counter 2 register" "SDRAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EMIFB,?..."
|
|
hexmask.long.byte 0x04 8.--15. 1. " MST_ID1 ,Master ID for performance counter 1 register"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " REGION_SEL1 ,Region select for performance counter 1 register" "SDRAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EMIFB,?..."
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x00 "PCT,Performance Counter Time Register"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "IRR,Interrupt Raw Register"
|
|
bitfld.long 0x00 2. " LT ,Line Trap" "Not occurred,Occurred"
|
|
group.long 0xc4++0x3
|
|
line.long 0x00 "IMR,Interrupt Masked Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " LTM_set/clr ,Masked Line Trap" "Not occurred,Occurred"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "MMC/SD (Multimedia Card/Secure Digital Card Controller)"
|
|
base asd:0x01C40000
|
|
width 12.
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MMCCTL,MMC Control Register"
|
|
bitfld.long 0x0 10. " PERMDX ,Endian select when writing" "Little,Big"
|
|
bitfld.long 0x0 9. " PERMDR ,Endian select when reading" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x0 8. 2. " WIDTH ,Data bus width 1" "1 bit,4 bits,8 bits,?..."
|
|
bitfld.long 0x0 6.--7. " DATEG ,DAT3 edge detection select" "Disabled,Rising-edge,Falling-edge,Rising/falling-edge"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CMDRST ,CMD logic reset" "No reset,Reset"
|
|
bitfld.long 0x0 0. " DATRST ,DAT logic reset" "No reset,Reset"
|
|
line.long 0x4 "MMCCLK,MMC Memory Clock Control Register"
|
|
bitfld.long 0x4 9. " DIV4 ,DIV4 option" "Clock/2,Clock/4"
|
|
bitfld.long 0x4 8. " CLKEN ,CLK pin enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " CLKRT ,Clock rate"
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x0 "MMCST0,MMC Status Register 0"
|
|
in
|
|
rgroup.long 0xc++0x3
|
|
line.long 0x0 "MMCST1,MMC Status Register 1"
|
|
bitfld.long 0x0 6. " FIFOFUL ,FIFO is full" "Not full,Full"
|
|
bitfld.long 0x0 5. " FIFOEMP ,FIFO is empty" "Not empty,Empty"
|
|
bitfld.long 0x0 4. " DAT3ST ,DAT3 signal level status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DRFUL ,Data receive register (MMCDRR) is full" "Not full,Full"
|
|
bitfld.long 0x0 2. " DXEMP ,Data transmit register (MMCDXR) is empty" "Not empty,Empty"
|
|
bitfld.long 0x0 1. " CLKSTP ,Clock stop status" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BUSY ,Busy signal" "Not busy,Busy"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "MMCIM,MMC Interrupt Mask Register"
|
|
bitfld.long 0x0 13. " ECCS ,Command completion signal interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " ETRNDNE ,Transfer done (TRNDNE) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " EDATED ,DAT3 edge detect (DATED) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " EDRRDY ,Data receive register ready (DRRDY) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " EDXRDY ,Data transmit register (MMCDXR) ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " ECRCRS ,Response CRC error (CRCRS) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " ECRCRD ,Read-data CRC error (CRCRD) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " ECRCWR ,Write-data CRC error (CRCWR) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " ETOUTRS ,Response time-out event (TOUTRS) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " ETOUTRD ,Read-data time-out event (TOUTRD) interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " ERSPDNE ,Command/response done (RSPDNE) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " EBSYDNE ,Busy done (BSYDNE) interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " EDATDNE ,Data done (DATDNE) interrupt enable" "Disabled,Enabled"
|
|
line.long 0x4 "MMCTOR,MMC Response Time-Out Register"
|
|
hexmask.long.word 0x4 8.--17. 1. " TOD_25_16 ,Data read time-out count upper 10 bits"
|
|
hexmask.long.byte 0x4 0.--7. 1. " TOR ,Time-out count for response"
|
|
line.long 0x8 "MMCTOD,MMC Data Read Time-Out Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " TOD_15_0 ,Data read time-out count"
|
|
line.long 0xc "MMCBLEN,MMC Block Length Register"
|
|
hexmask.long.word 0xc 0.--11. 1. " BLEN ,Block length"
|
|
line.long 0x10 "MMCNBLK,MMC Number of Blocks Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " NBLK ,Number of blocks"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "MMCNBLC,MMC Number of Blocks Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " NBLC ,Number of blocks counter"
|
|
group.long 0x28++0x0f
|
|
line.long 0x0 "MMCDRR,MMC Data Receive Register"
|
|
line.long 0x4 "MMCDXR,MMC Data Transmit Register"
|
|
line.long 0x8 "MMCCMD,MMC Command Register"
|
|
bitfld.long 0x8 16. " DMATRIG ,DMA transfer event generation enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 15. " DCLR ,Data receive/transmit clear" "Not cleared,Cleared"
|
|
bitfld.long 0x8 14. " INITCK ,Initialization clock cycles" "No cycles,80 cycles"
|
|
textline " "
|
|
bitfld.long 0x8 13. " WDATX ,Data transfer indicator" "No data,Data"
|
|
bitfld.long 0x8 12. " STRMTP ,Block/Stream transfer mode" "Block,Stream"
|
|
bitfld.long 0x8 11. " DTRW ,Read/Write operation" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x8 9.--10. " RSPFMT ,Response format" "No response,R1/R4/R5/R6 ->48 bits,R2 -> 136 bits,R3 -> 48 bits"
|
|
bitfld.long 0x8 8. " BSYEXP ,Busy expected" "Not expected,Expected"
|
|
textline " "
|
|
bitfld.long 0x8 7. " PPLEN ,Push pull enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--5. " CMD ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xc "MMCARGHL,MMC Argument Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " ARGH ,Argument high part"
|
|
hexmask.long.word 0x0c 0.--15. 1. " ARGL ,Argument low part"
|
|
if (((data.long(asd:0x01C40000+0x30))&0x600)==(0x200||0x600))
|
|
hgroup.long 0x38++0x07
|
|
hide.long 0x00 "MMCRSP01,MMC Response Register 0 and 1"
|
|
hide.long 0x04 "MMCRSP23,MMC Response Register 2 and 3"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "MMCRSP5,MMC Response Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " MMCRSP5 ,MMC Response 5"
|
|
line.long 0x04 "MMCRSP67,MMC Response Register 6 and 7"
|
|
hexmask.long.word 0x04 16.--31. 1. " MMCRSP7 ,MMC Response 7"
|
|
hexmask.long.word 0x04 0.--15. 1. " MMCRSP6 ,MMC Response 6"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "MMCCIDX,MMC Command Index Register"
|
|
bitfld.long 0x0 7. " STRT ,Start bit" "Not started,Started"
|
|
bitfld.long 0x0 6. " XMIT ,Transmission bit" "Not transmitted,Transmitted"
|
|
hexmask.long.byte 0x0 0.--5. 1. " CIDX ,Command index"
|
|
elif (((data.long(asd:0x01C40000+0x30))&0x600)==0x400)
|
|
group.long 0x38++0x0f
|
|
line.long 0x00 "MMCRSP01,MMC Response Register 0 and 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " MMCRSP1 ,MMC Response 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " MMCRSP0 ,MMC Response 0"
|
|
line.long 0x04 "MMCRSP23,MMC Response Register 2 and 3"
|
|
hexmask.long.word 0x04 16.--31. 1. " MMCRSP3 ,MMC Response 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " MMCRSP2 ,MMC Response 2"
|
|
line.long 0x08 "MMCRSP45,MMC Response Register 4 and 5"
|
|
hexmask.long.word 0x08 16.--31. 1. " MMCRSP5 ,MMC Response 5"
|
|
hexmask.long.word 0x08 0.--15. 1. " MMCRSP4 ,MMC Response 4"
|
|
line.long 0x0c "MMCRSP67,MMC Response Register 6 and 7"
|
|
hexmask.long.word 0x0c 16.--31. 1. " MMCRSP7 ,MMC Response 7"
|
|
hexmask.long.word 0x0c 0.--15. 1. " MMCRSP6 ,MMC Response 6"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "MMCCIDX,MMC Command Index Register"
|
|
bitfld.long 0x0 7. " STRT ,Start bit" "Not started,Started"
|
|
bitfld.long 0x0 6. " XMIT ,Transmission bit" "Not transmitted,Transmitted"
|
|
hexmask.long.byte 0x0 0.--5. 1. " CIDX ,Command index"
|
|
else
|
|
hgroup.long 0x38++0x0f
|
|
hide.long 0x00 "MMCRSP01,MMC Response Register 0 and 1"
|
|
hide.long 0x04 "MMCRSP23,MMC Response Register 2 and 3"
|
|
hide.long 0x08 "MMCRSP45,MMC Response Register 4 and 5"
|
|
hide.long 0x0c "MMCRSP67,MMC Response Register 6 and 7"
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x0 "MMCCIDX,MMC Command Index Register"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MMCDRSP,MMC Data Response Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DRSP ,CRC status token during a write operation"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "SDIOCTL,SDIO Control Register"
|
|
bitfld.long 0x0 1. " RDWTCR ,Read wait enable for CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RDWTRQ ,Read wait request" "Not requested,Requested"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "SDIOST0,SDIO Status Register 0"
|
|
bitfld.long 0x0 2. " RDWTST ,Read wait status" "No wait,Wait"
|
|
bitfld.long 0x0 1. " INTPRD ,Interrupt period" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " DAT1 ,External state of the SD_DATA1 pin" "Low,High"
|
|
group.long 0x6c++0xb
|
|
line.long 0x0 "SDIOIEN,SDIO Interrupt Enable Register"
|
|
bitfld.long 0x0 1. " RWSEN ,Read wait interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " IOINTEN ,SDIO card interrupt enable" "Disabled,Enabled"
|
|
line.long 0x4 "SDIOIST,SDIO Interrupt Status Register"
|
|
eventfld.long 0x04 1. " RWS ,Read wait interrupt status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " IOINT ,SDIO card interrupt status" "Not occurred,Occurred"
|
|
line.long 0x8 "MMCFIFOCTL,MMC FIFO Control Register"
|
|
bitfld.long 0x08 3.--4. " ACCWD ,Access width" "4 bytes,3 bytes,2 bytes,1 byte"
|
|
bitfld.long 0x08 2. " FIFOLEV ,FIFO level / EDMA request threshold level" "256 bits,512 bits"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FIFODIR ,FIFO direction" "Read,Write"
|
|
bitfld.long 0x08 0. " FIFORST ,FIFO reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMAC/MDIO (Ethernet Media Access Controller/Management Data Input/Output Module)"
|
|
tree "EMAC Control Module"
|
|
base asd:0x01e22000
|
|
width 17.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,EMAC Control Module Revision ID Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SOFTRESET,EMAC Control Module Software Reset Register"
|
|
bitfld.long 0x00 0. " RESET ,Software reset bit for the EMAC Control Module" "No reset,Reset"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "INTCONTROL,EMAC Control Module Interrupt Control Register"
|
|
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505")
|
|
bitfld.long 0x00 31. " INTTEST ,Interrupt Test" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " C2TXPACEEN ,Enable pacing for TX interrupt pulse generation on Interrupt Core 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " C2RXPACEEN ,Enable pacing for RX interrupt pulse generation on Interrupt Core 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " C1TXPACEEN ,Enable pacing for TX interrupt pulse generation on Interrupt Core 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " C1RXPACEEN ,Enable pacing for RX interrupt pulse generation on Interrupt Core 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " C0TXPACEEN ,Enable pacing for TX interrupt pulse generation on Interrupt Core 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " C0RXPACEEN ,Enable pacing for RX interrupt pulse generation on Interrupt Core 0" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " INTPRESCALE ,Number of internal EMAC module reference clock periods within a 4 us time window"
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "C0RXTHRESHEN,EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "C0RXEN,EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register 0"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Enable C0RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Enable C0RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RXCH5EN ,Enable C0RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RXCH4EN ,Enable C0RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RXCH3EN ,Enable C0RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Enable C0RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Enable C0RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Enable C0RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "C0TXEN,EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register"
|
|
bitfld.long 0x08 7. " TXCH7EN ,Enable C0TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TXCH6EN ,Enable C0TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TXCH5EN ,Enable C0TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXCH4EN ,Enable C0TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TXCH3EN ,Enable C0TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXCH2EN ,Enable C0TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1EN ,Enable C0TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCH0EN ,Enable C0TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "C0MISCEN,EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " STATPENDEN ,Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HOSTPENDEN ,Enable C0MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LINKINT0EN ,Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts are generated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USERINT0EN ,Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts are generated" "Disabled,Enabled"
|
|
group.long 0x20++0x0f
|
|
line.long 0x00 "C1RXTHRESHEN,EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C1RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "C1RXEN,EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register 1"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Enable C1RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Enable C1RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RXCH5EN ,Enable C1RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RXCH4EN ,Enable C1RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RXCH3EN ,Enable C1RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Enable C1RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Enable C1RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Enable C1RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "C1TXEN,EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register"
|
|
bitfld.long 0x08 7. " TXCH7EN ,Enable C1TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TXCH6EN ,Enable C1TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TXCH5EN ,Enable C1TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXCH4EN ,Enable C1TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TXCH3EN ,Enable C1TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXCH2EN ,Enable C1TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1EN ,Enable C1TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCH0EN ,Enable C1TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "C1MISCEN,EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " STATPENDEN ,Enable C1MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HOSTPENDEN ,Enable C1MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LINKINT0EN ,Enable C1MISCPULSE interrupt generation when MDIO LINKINT0 interrupts are generated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USERINT0EN ,Enable C1MISCPULSE interrupt generation when MDIO USERINT0 interrupts are generated" "Disabled,Enabled"
|
|
group.long 0x30++0x0f
|
|
line.long 0x00 "C2RXTHRESHEN,EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C2RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "C2RXEN,EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register 2"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Enable C2RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Enable C2RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RXCH5EN ,Enable C2RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RXCH4EN ,Enable C2RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RXCH3EN ,Enable C2RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Enable C2RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Enable C2RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Enable C2RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "C2TXEN,EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register"
|
|
bitfld.long 0x08 7. " TXCH7EN ,Enable C2TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " TXCH6EN ,Enable C2TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TXCH5EN ,Enable C2TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TXCH4EN ,Enable C2TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TXCH3EN ,Enable C2TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TXCH2EN ,Enable C2TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1EN ,Enable C2TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TXCH0EN ,Enable C2TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "C2MISCEN,EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " STATPENDEN ,Enable C2MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HOSTPENDEN ,Enable C2MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " LINKINT0EN ,Enable C2MISCPULSE interrupt generation when MDIO LINKINT0 interrupts are generated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USERINT0EN ,Enable C2MISCPULSE interrupt generation when MDIO USERINT0 interrupts are generated" "Disabled,Enabled"
|
|
rgroup.long 0x40++0x0f
|
|
line.long 0x00 "C0RXTHRESHSTAT,EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
line.long 0x04 "C0RXSTAT,EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
line.long 0x08 "C0TXSTAT,EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
line.long 0x0c "C0MISCSTAT,EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register"
|
|
bitfld.long 0x0C 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
rgroup.long 0x50++0x0f
|
|
line.long 0x00 "C1RXTHRESHSTAT,EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
line.long 0x04 "C0RXSTAT,EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
line.long 0x08 "C1TXSTAT,EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
line.long 0x0c "C1MISCSTAT,EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register"
|
|
bitfld.long 0x0C 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
rgroup.long 0x60++0x0f
|
|
line.long 0x00 "C2RXTHRESHSTAT,EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register"
|
|
bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register" "No interrupt,Interrupt"
|
|
line.long 0x04 "C0RXSTAT,EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register"
|
|
bitfld.long 0x04 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the CnRXEN register" "No interrupt,Interrupt"
|
|
line.long 0x08 "C2TXSTAT,EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register"
|
|
bitfld.long 0x08 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the CnTXEN register" "No interrupt,Interrupt"
|
|
line.long 0x0c "C2MISCSTAT,EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register"
|
|
bitfld.long 0x0C 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the CnMISCEN register" "No interrupt,Interrupt"
|
|
group.long 0x70--0x87
|
|
line.long 0x0 "C0RXIMAX,EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register"
|
|
bitfld.long 0x0 0.--5. " RXIMAX ,Desired number of C0RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long (0x0+0x04) "C0TXIMAX,EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register"
|
|
bitfld.long (0x0+0x04) 0.--5. " TXIMAX ,Desired number of C0TXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "C1RXIMAX,EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register"
|
|
bitfld.long 0x8 0.--5. " RXIMAX ,Desired number of C1RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long (0x8+0x04) "C1TXIMAX,EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register"
|
|
bitfld.long (0x8+0x04) 0.--5. " TXIMAX ,Desired number of C1TXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "C2RXIMAX,EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register"
|
|
bitfld.long 0x10 0.--5. " RXIMAX ,Desired number of C2RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long (0x10+0x04) "C2TXIMAX,EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register"
|
|
bitfld.long (0x10+0x04) 0.--5. " TXIMAX ,Desired number of C2TXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree "MDIO"
|
|
base asd:0x01e24000
|
|
width 9.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,MDIO Revision ID Register"
|
|
sif (cpuis("AM389*")||cpuis("C6A816*")||cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168"||cpu()=="DM8165DSP"||cpu()=="DM8166DSP"||cpu()=="DM8167DSP"||cpu()=="DM8168DSP"||cpuis("AM335*"))
|
|
hexmask.long.word 0x00 16.--31. 1. " MODID ,Type of peripheral"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Major revision of peripheral"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision of peripheral"
|
|
endif
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "CONTROL,MDIO Control Register"
|
|
bitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE status" "Busy,Idle"
|
|
bitfld.long 0x00 30. " ENABLE ,MDIO state machine enable control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--28. 1. " HUC ,Highest User-access Channel"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PREAMBLE ,MDIO frame preamble disable" "No,Yes"
|
|
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Failure"
|
|
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505"||cpuis("AM335*"))
|
|
bitfld.long 0x00 17. " INT_TEST_ENABLE ,Interrupt test enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
|
|
endif
|
|
line.long 0x04 "ALIVE,MDIO PHY Alive Indication Register"
|
|
eventfld.long 0x04 31. " ALIVE[31] ,MDIO ALIVE bit 31" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 30. " ALIVE[30] ,MDIO ALIVE bit 30" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 29. " ALIVE[29] ,MDIO ALIVE bit 29" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 28. " ALIVE[28] ,MDIO ALIVE bit 28" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 27. " ALIVE[27] ,MDIO ALIVE bit 27" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 26. " ALIVE[26] ,MDIO ALIVE bit 26" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 25. " ALIVE[25] ,MDIO ALIVE bit 25" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 24. " ALIVE[24] ,MDIO ALIVE bit 24" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 23. " ALIVE[23] ,MDIO ALIVE bit 23" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 22. " ALIVE[22] ,MDIO ALIVE bit 22" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 21. " ALIVE[21] ,MDIO ALIVE bit 21" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 20. " ALIVE[20] ,MDIO ALIVE bit 20" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 19. " ALIVE[19] ,MDIO ALIVE bit 19" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 18. " ALIVE[18] ,MDIO ALIVE bit 18" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 17. " ALIVE[17] ,MDIO ALIVE bit 17" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 16. " ALIVE[16] ,MDIO ALIVE bit 16" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 15. " ALIVE[15] ,MDIO ALIVE bit 15" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 14. " ALIVE[14] ,MDIO ALIVE bit 14" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 13. " ALIVE[13] ,MDIO ALIVE bit 13" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 12. " ALIVE[12] ,MDIO ALIVE bit 12" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 11. " ALIVE[11] ,MDIO ALIVE bit 11" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 10. " ALIVE[10] ,MDIO ALIVE bit 10" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 9. " ALIVE[9] ,MDIO ALIVE bit 9" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 8. " ALIVE[8] ,MDIO ALIVE bit 8" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 7. " ALIVE[7] ,MDIO ALIVE bit 7" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 6. " ALIVE[6] ,MDIO ALIVE bit 6" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 5. " ALIVE[5] ,MDIO ALIVE bit 5" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 4. " ALIVE[4] ,MDIO ALIVE bit 4" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 3. " ALIVE[3] ,MDIO ALIVE bit 3" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 2. " ALIVE[2] ,MDIO ALIVE bit 2" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
eventfld.long 0x04 1. " ALIVE[1] ,MDIO ALIVE bit 1" "Not acknowledged,Acknowledged"
|
|
eventfld.long 0x04 0. " ALIVE[0] ,MDIO ALIVE bit 0" "Not acknowledged,Acknowledged"
|
|
rgroup.long 0x0c++0x3
|
|
line.long 0x00 "LINK,MDIO PHY Link Status Register"
|
|
bitfld.long 0x00 31. " LINK[31] ,MDIO link state bit 31" "No link,Link"
|
|
bitfld.long 0x00 30. " LINK[30] ,MDIO link state bit 30" "No link,Link"
|
|
bitfld.long 0x00 29. " LINK[29] ,MDIO link state bit 29" "No link,Link"
|
|
bitfld.long 0x00 28. " LINK[28] ,MDIO link state bit 28" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LINK[27] ,MDIO link state bit 27" "No link,Link"
|
|
bitfld.long 0x00 26. " LINK[26] ,MDIO link state bit 26" "No link,Link"
|
|
bitfld.long 0x00 25. " LINK[25] ,MDIO link state bit 25" "No link,Link"
|
|
bitfld.long 0x00 24. " LINK[24] ,MDIO link state bit 24" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LINK[23] ,MDIO link state bit 23" "No link,Link"
|
|
bitfld.long 0x00 22. " LINK[22] ,MDIO link state bit 22" "No link,Link"
|
|
bitfld.long 0x00 21. " LINK[21] ,MDIO link state bit 21" "No link,Link"
|
|
bitfld.long 0x00 20. " LINK[20] ,MDIO link state bit 20" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LINK[19] ,MDIO link state bit 19" "No link,Link"
|
|
bitfld.long 0x00 18. " LINK[18] ,MDIO link state bit 18" "No link,Link"
|
|
bitfld.long 0x00 17. " LINK[17] ,MDIO link state bit 17" "No link,Link"
|
|
bitfld.long 0x00 16. " LINK[16] ,MDIO link state bit 16" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LINK[15] ,MDIO link state bit 15" "No link,Link"
|
|
bitfld.long 0x00 14. " LINK[14] ,MDIO link state bit 14" "No link,Link"
|
|
bitfld.long 0x00 13. " LINK[13] ,MDIO link state bit 13" "No link,Link"
|
|
bitfld.long 0x00 12. " LINK[12] ,MDIO link state bit 12" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LINK[11] ,MDIO link state bit 11" "No link,Link"
|
|
bitfld.long 0x00 10. " LINK[10] ,MDIO link state bit 10" "No link,Link"
|
|
bitfld.long 0x00 9. " LINK[9] ,MDIO link state bit 9" "No link,Link"
|
|
bitfld.long 0x00 8. " LINK[8] ,MDIO link state bit 8" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LINK[7] ,MDIO link state bit 7" "No link,Link"
|
|
bitfld.long 0x00 6. " LINK[6] ,MDIO link state bit 6" "No link,Link"
|
|
bitfld.long 0x00 5. " LINK[5] ,MDIO link state bit 5" "No link,Link"
|
|
bitfld.long 0x00 4. " LINK[4] ,MDIO link state bit 4" "No link,Link"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LINK[3] ,MDIO link state bit 3" "No link,Link"
|
|
bitfld.long 0x00 2. " LINK[2] ,MDIO link state bit 2" "No link,Link"
|
|
bitfld.long 0x00 1. " LINK[1] ,MDIO link state bit 1" "No link,Link"
|
|
bitfld.long 0x00 0. " LINK[0] ,MDIO link state bit 0" "No link,Link"
|
|
width 18.
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "LINKINTRAW,MDIO Link Status Change Interrupt Register"
|
|
eventfld.long 0x00 1. " USERPHY1 ,MDIO link change event" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " USERPHY0 ,MDIO link change event" "Not changed,Changed"
|
|
line.long 0x04 "LINKINTMASKED,MDIO Link Status Change Interrupt (Masked) Register"
|
|
eventfld.long 0x04 1. " USERPHY1 ,MDIO link change interrupt" "Not changed,Changed"
|
|
eventfld.long 0x04 0. " USERPHY0 ,MDIO link change interrupt" "Not changed,Changed"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "USERINTRAW,MDIO User Command Complete Interrupt Register"
|
|
eventfld.long 0x00 1. " USERACCESS1 ,MDIO user command complete event" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " USERACCESS0 ,MDIO user command complete event" "Not completed,Completed"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "USERINTMASKED,MDIO User Command Complete Interrupt (Masked) Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
|
|
group.long 0x80++0x0f
|
|
line.long 0x00 "USERACCESS0,MDIO User Access Register 0"
|
|
bitfld.long 0x00 31. " GO ,GO bit" "No effect,MDIO accessed"
|
|
bitfld.long 0x00 30. " WRITE ,Write enable" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
|
|
hexmask.long.word 0x00 21.--25. 0x20 " REGADR ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data"
|
|
line.long 0x04 "USERPHYSEL0,MDIO User PHY Select Register 0"
|
|
bitfld.long 0x04 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
|
|
bitfld.long 0x04 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
|
|
line.long 0x08 "USERACCESS1,MDIO User Access Register 1"
|
|
bitfld.long 0x08 31. " GO ,GO bit" "No effect,MDIO accessed"
|
|
bitfld.long 0x08 30. " WRITE ,Write enable" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x08 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
|
|
hexmask.long.word 0x08 21.--25. 0x20 " REGADR ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--20. 1. " PHYADR ,PHY address"
|
|
hexmask.long.word 0x08 0.--15. 1. " DATA ,User data"
|
|
line.long 0x0c "USERPHYSEL1,MDIO User PHY Select Register 1"
|
|
bitfld.long 0x0c 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
|
|
bitfld.long 0x0c 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMAC Module"
|
|
base asd:0x01e23000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "TXREVID,Transmit Revision ID Register"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "TXCONTROL,Transmit Control Register"
|
|
bitfld.long 0x00 0. " TXEN ,Transmit enable" "Disabled,Enabled"
|
|
line.long 0x04 "TXTEARDOWN,Transmit Teardown Register"
|
|
bitfld.long 0x04 0.--2. " TXTDNCH ,Transmit teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RXREVID,Receive Revision ID Register"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "RXCONTROL,Receive Control Register"
|
|
bitfld.long 0x00 0. " RXEN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "RXTEARDOWN,Receive Teardown Register"
|
|
bitfld.long 0x04 0.--2. " RXTDNCH ,Receive teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "TXINTSTATRAW,Transmit Interrupt Status (Unmasked) Register"
|
|
bitfld.long 0x00 7. " TX7PEND ,TX7PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " TX6PEND ,TX6PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX5PEND ,TX5PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " TX4PEND ,TX4PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX3PEND ,TX3PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TX2PEND ,TX2PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1PEND ,TX1PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TX0PEND ,TX0PEND raw interrupt read" "No interrupt,Interrupt"
|
|
line.long 0x04 "TXINTSTATMASKED,Transmit Interrupt Status (Masked) Register"
|
|
bitfld.long 0x04 7. " TX7PEND ,TX7PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " TX6PEND ,TX6PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX5PEND ,TX5PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " TX4PEND ,TX4PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TX3PEND ,TX3PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " TX2PEND ,TX2PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX1PEND ,TX1PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TX0PEND ,TX0PEND masked interrupt read" "No interrupt,Interrupt"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "TXINTMASKSET,Transmit Interrupt Status Mask Set Register"
|
|
bitfld.long 0x00 7. " TX7MASK ,Transmit channel 7 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " TX6MASK ,Transmit channel 6 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 5. " TX5MASK ,Transmit channel 5 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TX4MASK ,Transmit channel 4 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 3. " TX3MASK ,Transmit channel 3 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " TX2MASK ,Transmit channel 2 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX1MASK ,Transmit channel 1 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " TX0MASK ,Transmit channel 0 interrupt mask set" "No effect,Enabled"
|
|
line.long 0x04 "TXINTMASKCLEAR,Transmit Interrupt Status Mask Clear Register"
|
|
eventfld.long 0x04 7. " TX7MASK ,Transmit channel 7 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 6. " TX6MASK ,Transmit channel 6 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 5. " TX5MASK ,Transmit channel 5 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 4. " TX4MASK ,Transmit channel 4 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 3. " TX3MASK ,Transmit channel 3 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 2. " TX2MASK ,Transmit channel 2 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 1. " TX1MASK ,Transmit channel 1 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " TX0MASK ,Transmit channel 0 interrupt mask clear" "No effect,Cleared"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "MACINVECTOR,MAC Input Vector Register"
|
|
bitfld.long 0x00 27. " STATPEND ,EMAC module statistics interrupt (STATPEND) pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " HOSTPEND ,EMAC module host error interrupt (HOSTPEND) pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINKINT0 ,MDIO module USERPHYSEL0 (LINKINT0) status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " USERINT0 ,MDIO module USERACCESS0 (USERINT0) status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TX7PEND ,Transmit channel interrupt 7 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " TX6PEND ,Transmit channel interrupt 6 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TX5PEND ,Transmit channel interrupt 5 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TX4PEND ,Transmit channel interrupt 4 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TX3PEND ,Transmit channel interrupt 3 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " TX2PEND ,Transmit channel interrupt 2 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TX1PEND ,Transmit channel interrupt 1 pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " TX0PEND ,Transmit channel interrupt 0 pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RX7THRESHPEND ,Receive channel 7 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " RX6THRESHPEND ,Receive channel 6 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5THRESHPEND ,Receive channel 5 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " RX4THRESHPEND ,Receive channel 4 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3THRESHPEND ,Receive channel 3 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " RX2THRESHPEND ,Receive channel 2 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1THRESHPEND ,Receive channel 1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " RX0THRESHPEND ,Receive channel 0 interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7PEND ,Receive channel 7 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " RX6PEND ,Receive channel 6 interrupt pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5PEND ,Receive channel 5 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " RX4PEND ,Receive channel 4 interrupt pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3PEND ,Receive channel 3 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " RX2PEND ,Receive channel 2 interrupt pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1PEND ,Receive channel 1 interrupt pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " RX0PEND ,Receive channel 0 interrupt pending status" "Not pending,Pending"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MACEOIVECTOR,MAC End Of Interrupt Vector Register"
|
|
bitfld.long 0x00 0.--4. " INTVECT ,Acknowledge EMAC Control Module Interrupts" "C0RXTHRESH,C0RX,C0TX,C0MISC,C1RXTHRESH,C1RX,C1TX,C1MISC,C2RXTHRESH,C2RX,C2TX,C2MISC,?..."
|
|
rgroup.long 0xa0++0x7
|
|
line.long 0x00 "RXINTSTATRAW,Receive Interrupt Status (Unmasked) Register"
|
|
bitfld.long 0x00 15. " RX7THRESHPEND ,RX7THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " RX6THRESHPEND ,RX6THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5THRESHPEND ,RX5THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " RX4THRESHPEND ,RX4THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3THRESHPEND ,RX3THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " RX2THRESHPEND ,RX2THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1THRESHPEND ,RX1THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RX0THRESHPEND ,RX0THRESHPEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7PEND ,RX7PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RX6PEND ,RX6PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5PEND ,RX5PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RX4PEND ,RX4PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3PEND ,RX3PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RX2PEND ,RX2PEND raw interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1PEND ,RX1PEND raw interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RX0PEND ,RX0PEND raw interrupt read" "No interrupt,Interrupt"
|
|
line.long 0x04 "RXINTSTATMASKED,Receive Interrupt Status (Masked) Register"
|
|
bitfld.long 0x04 15. " RX7THRESHPEND ,RX7THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " RX6THRESHPEND ,RX6THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RX5THRESHPEND ,RX5THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " RX4THRESHPEND ,RX4THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RX3THRESHPEND ,RX3THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " RX2THRESHPEND ,RX2THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RX1THRESHPEND ,RX1THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RX0THRESHPEND ,RX0THRESHPEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RX7PEND ,RX7PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " RX6PEND ,RX6PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RX5PEND ,RX5PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RX4PEND ,RX4PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX3PEND ,RX3PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " RX2PEND ,RX2PEND masked interrupt read" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RX1PEND ,RX1PEND masked interrupt read" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " RX0PEND ,RX0PEND masked interrupt read" "No interrupt,Interrupt"
|
|
group.long 0xa8++0x7
|
|
line.long 0x00 "RXINTMASKSET,Receive Interrupt Status Mask Set Register"
|
|
bitfld.long 0x00 15. " RX7THRESHMASK ,Receive channel 7 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " RX6THRESHMASK ,Receive channel 6 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RX5THRESHMASK ,Receive channel 5 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " RX4THRESHMASK ,Receive channel 4 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX3THRESHMASK ,Receive channel 3 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " RX2THRESHMASK ,Receive channel 2 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RX1THRESHMASK ,Receive channel 1 threshold mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " RX0THRESHMASK ,Receive channel 0 threshold mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RX7MASK ,Receive channel 7 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " RX6MASK ,Receive channel 6 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RX5MASK ,Receive channel 5 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " RX4MASK ,Receive channel 4 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RX3MASK ,Receive channel 3 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " RX2MASK ,Receive channel 2 interrupt mask set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX1MASK ,Receive channel 1 interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " RX0MASK ,Receive channel 0 interrupt mask set" "No effect,Enabled"
|
|
line.long 0x04 "RXINTMASKCLEAR,Receive Interrupt Mask Clear Register"
|
|
eventfld.long 0x04 15. " RX7THRESHMASK ,Receive channel 7 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 14. " RX6THRESHMASK ,Receive channel 6 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 13. " RX5THRESHMASK ,Receive channel 5 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 12. " RX4THRESHMASK ,Receive channel 4 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 11. " RX3THRESHMASK ,Receive channel 3 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 10. " RX2THRESHMASK ,Receive channel 2 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 9. " RX1THRESHMASK ,Receive channel 1 threshold mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 8. " RX0THRESHMASK ,Receive channel 0 threshold mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 7. " RX7MASK ,Receive channel 7 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 6. " RX6MASK ,Receive channel 6 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 5. " RX5MASK ,Receive channel 5 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 4. " RX4MASK ,Receive channel 4 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " RX3MASK ,Receive channel 3 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 2. " RX2MASK ,Receive channel 2 interrupt mask clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 1. " RX1MASK ,Receive channel 1 interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " RX0MASK ,Receive channel 0 interrupt mask set" "No effect,Cleared"
|
|
rgroup.long 0xb0++0x7
|
|
line.long 0x00 "MACINTSTATRAW,MAC Interrupt Status (Unmasked) Register"
|
|
bitfld.long 0x00 1. " HOSTPEND ,Host pending interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " STATPEND ,Statistics pending interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "MACINTSTATMASKED,MAC Interrupt Status (Masked) Register"
|
|
bitfld.long 0x04 1. " HOSTPEND ,Host pending interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " STATPEND ,Statistics pending interrupt" "No interrupt,Interrupt"
|
|
group.long 0xb8++0x7
|
|
line.long 0x00 "MACINTSTATMASKSET,MAC Interrupt Status Mask Set Register"
|
|
bitfld.long 0x00 1. " HOSTMASK ,Host error interrupt mask set" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " STATMASK ,Statistics interrupt mask set" "No effect,Enabled"
|
|
line.long 0x04 "MACINTSTATMASKCLEAR,MAC Interrupt Status Mask Clear Register"
|
|
eventfld.long 0x04 1. " HOSTMASK ,Host error interrupt mask clear" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " STATMASK ,Statistics interrupt mask clear" "No effect,Cleared"
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "RXMBPENABLE,Receive Multicast/Broadcast/Promiscuous Channel Enable Register"
|
|
bitfld.long 0x00 30. " RXPASSCRC ,Pass received CRC enable" "Discarded,Transferred"
|
|
bitfld.long 0x00 29. " RXQOSEN ,Receive quality of service enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single"
|
|
bitfld.long 0x00 24. " RXCMFEN ,Receive copy MAC control frames enable" "Filtered,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RXCSFEN ,Receive copy short frames enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 22. " RXCEFEN ,Receive copy error frames enable" "Filtered,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RXCAFEN ,Receive copy all frames enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 16.--18. " RXPROMCH ,Receive promiscuous channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXBROADEN ,Receive broadcast enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 8.--10. " RXBROADCH ,Receive broadcast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXMULTEN ,Receive multicast enable" "Filtered,Transferred"
|
|
bitfld.long 0x00 0.--2. " RXMULTCH ,Receive multicast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
line.long 0x04 "RXUNICASTSET,Receive Unicast Set Register"
|
|
bitfld.long 0x04 7. " RXCH7EN ,Receive channel 7 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 6. " RXCH6EN ,Receive channel 6 unicast enable set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXCH5EN ,Receive channel 5 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 4. " RXCH4EN ,Receive channel 4 unicast enable set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RXCH3EN ,Receive channel 3 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 2. " RXCH2EN ,Receive channel 2 unicast enable set" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RXCH1EN ,Receive channel 1 unicast enable set" "No effect,Enabled"
|
|
bitfld.long 0x04 0. " RXCH0EN ,Receive channel 0 unicast enable set" "No effect,Enabled"
|
|
line.long 0x08 "RXUNICASTCLEAR,Receive Unicast Clear Register"
|
|
eventfld.long 0x08 7. " RXCH7CLEAR ,Receive channel 7 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 6. " RXCH6CLEAR ,Receive channel 6 unicast enable clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 5. " RXCH5CLEAR ,Receive channel 5 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 4. " RXCH4CLEAR ,Receive channel 4 unicast enable clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RXCH3CLEAR ,Receive channel 3 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 2. " RXCH2CLEAR ,Receive channel 2 unicast enable clear" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x08 1. " RXCH1CLEAR ,Receive channel 1 unicast enable clear" "No effect,Cleared"
|
|
eventfld.long 0x08 0. " RXCH0CLEAR ,Receive channel 0 unicast enable clear" "No effect,Cleared"
|
|
line.long 0x0c "RXMAXLEN,Receive Maximum Length Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " RXMAXLEN ,Received maximum frame length"
|
|
line.long 0x10 "RXBUFFEROFFSET,Receive Buffer Offset Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " BUFFEROFFSET ,Receive buffer offset"
|
|
line.long 0x14 "RXFILTERLOWTHRESH,Receive Filter Low Priority Frame Threshold Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RXFILTERTHRESH ,Receive filter low threshold"
|
|
group.long 0x120++0x1f
|
|
line.long 0x0 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " RX0FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x4 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " RX1FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x8 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " RX2FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0xC "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. " RX3FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x10 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " RX4FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x14 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RX5FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x18 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " RX6FLOWTHRESH ,Receive flow threshold"
|
|
line.long 0x1C "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " RX7FLOWTHRESH ,Receive flow threshold"
|
|
wgroup.long 0x140++0x1f
|
|
line.long 0x0 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " RX0FREEBUF ,Receive free buffer count"
|
|
line.long 0x4 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " RX1FREEBUF ,Receive free buffer count"
|
|
line.long 0x8 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " RX2FREEBUF ,Receive free buffer count"
|
|
line.long 0xC "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " RX3FREEBUF ,Receive free buffer count"
|
|
line.long 0x10 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " RX4FREEBUF ,Receive free buffer count"
|
|
line.long 0x14 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RX5FREEBUF ,Receive free buffer count"
|
|
line.long 0x18 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " RX6FREEBUF ,Receive free buffer count"
|
|
line.long 0x1C "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " RX7FREEBUF ,Receive free buffer count"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "MACCONTROL,MAC Control Register"
|
|
bitfld.long 0x00 15. " RRMIISPEED ,RMII interface transmit and receive speed select" "10 Mbps,100 Mbps"
|
|
bitfld.long 0x00 14. " RXOFFLENBLOCK ,Receive offset / length word write block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RXOWNERSHIP ,Receive ownership write bit value" "Zero,One"
|
|
bitfld.long 0x00 11. " CMDIDLE ,Command Idle" "Not commanded,Commanded"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXSHORTGAPEN ,Transmit Short Gap Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXPTYPE ,Transmit queue priority type" "Round-robin,Fixed-priority"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GMIIEN ,MII enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXBUFFERFLOWEN ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LOOPBACK ,Loopback mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FULLDUPLEX ,Full-duplex mode enable" "Half-duplex,Full-duplex"
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "MACSTATUS,MAC Status Register"
|
|
bitfld.long 0x00 31. " IDLE ,EMAC idle" "Busy,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TXERRCODE ,Transmit host error code" "No error,SOP error,Ownership bit not set in SOP buffer,Zero next buffer descriptor pointer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TXERRCH ,Transmit host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " RXERRCODE ,Receive host error code" "No error,Reserved,Ownership bit not set in SOP buffer,Reserved,Zero buffer pointer,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RXERRCH ,Receive host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
bitfld.long 0x00 2. " RXQOSACT ,Receive quality of service (QOS) active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXFLOWACT ,Receive flow control active" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TXFLOWACT ,Transmit flow control active" "Disabled,Enabled"
|
|
group.long 0x168++0x07
|
|
line.long 0x00 "EMCONTROL,Emulation Control Register"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation soft" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FREE ,Emulation free" "Disabled,Enabled"
|
|
line.long 0x04 "FIFOCONTROL,FIFO Control Register"
|
|
bitfld.long 0x04 0.--1. " TXCELLTHRESH ,Transmit FIFO cell threshold" "Not valid,Not valid,2 cells,3 cells"
|
|
rgroup.long 0x170++0x3
|
|
line.long 0x00 "MACCONFIG,MAC Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TXCELLDEPTH ,Transmit cell depth"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RXCELLDEPTH ,Receive cell depth"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ADDRESSTYPE ,Address type"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACCFIG ,MAC configuration value"
|
|
group.long 0x174++0x3
|
|
line.long 0x00 "SOFTRESET,Soft Reset Register"
|
|
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
group.long 0x1d0++0xf
|
|
line.long 0x00 "MACSRCADDRLO,MAC Source Address Low Bytes Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits (byte 0)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15-8 (byte 1)"
|
|
line.long 0x04 "MACSRCADDRHI,MAC Source Address High Bytes Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23-16 (byte 2)"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31-24 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39-32 (byte 4)"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47-40 (byte 5)"
|
|
line.long 0x08 "MACHASH1,MAC Address Hash 1 Register"
|
|
line.long 0x0c "MACHASH2,MAC Address Hash 2 Register"
|
|
rgroup.long 0x1e0++0xf
|
|
line.long 0x00 "BOFFTEST,Backoff Test Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " RNDNUM ,Backoff random number generator"
|
|
hexmask.long.byte 0x00 12.--15. 1. " COLLCOUNT ,Collision count"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " TXBACKOFF ,Backoff count"
|
|
line.long 0x04 "TPACETEST,Transmit Pacing Test Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " PACEVAL ,Pacing register current value"
|
|
line.long 0x08 "RXPAUSE,Receive Pause Timer Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PAUSETIMER ,Receive pause timer value"
|
|
line.long 0x0c "TXPAUSE,Transmit Pause Timer Register"
|
|
hexmask.long.word 0x0c 0.--15. 1. " PAUSETIMER ,Transmit pause timer value"
|
|
group.long 0x500++0xb
|
|
line.long 0x00 "MACADDRLO,MAC Address Low Bytes Register"
|
|
bitfld.long 0x00 20. " VALID ,Address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 19. " MATCHFILT ,Match or filter" "Filter,Match"
|
|
bitfld.long 0x00 16.--18. " CHANNEL ,Channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MACADDR0 ,MAC address lower 8 bits (byte 0)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MACADDR1 ,MAC address bits 15-8 (byte 1)"
|
|
line.long 0x04 "MACADDRHI,MAC Address High Bytes Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MACADDR2 ,MAC source address bits 23-16 (byte 2)"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MACADDR3 ,MAC source address bits 31-24 (byte 3)"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " MACADDR4 ,MAC source address bits 39-32 (byte 4)"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MACADDR5 ,MAC source address bits 47-40 (byte 5)"
|
|
line.long 0x08 "MACINDEX,MAC Index Register"
|
|
hexmask.long.byte 0x08 0.--2. 1. " MACINDEX ,MAC address index"
|
|
group.long 0x600--0x67f
|
|
line.long 0x0 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register"
|
|
line.long 0x4 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register"
|
|
line.long 0x8 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register"
|
|
line.long 0xC "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register"
|
|
line.long 0x10 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register"
|
|
line.long 0x14 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register"
|
|
line.long 0x18 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register"
|
|
line.long 0x1C "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register"
|
|
line.long 0x20 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register"
|
|
line.long 0x24 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register"
|
|
line.long 0x28 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register"
|
|
line.long 0x2C "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register"
|
|
line.long 0x30 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register"
|
|
line.long 0x34 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register"
|
|
line.long 0x38 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register"
|
|
line.long 0x3C "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register"
|
|
line.long 0x40 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x44 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x48 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x4C "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x50 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x54 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x58 "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x5C "TX0CP,Transmit Channel Completion Pointer Register"
|
|
line.long 0x60 "RX0CP,Receive Channel 0 Completion Pointer Register"
|
|
line.long 0x64 "RX1CP,Receive Channel 1 Completion Pointer Register"
|
|
line.long 0x68 "RX2CP,Receive Channel 2 Completion Pointer Register"
|
|
line.long 0x6C "RX3CP,Receive Channel 3 Completion Pointer Register"
|
|
line.long 0x70 "RX4CP,Receive Channel 4 Completion Pointer Register"
|
|
line.long 0x74 "RX5CP,Receive Channel 5 Completion Pointer Register"
|
|
line.long 0x78 "RX6CP,Receive Channel 6 Completion Pointer Register"
|
|
line.long 0x7C "RX7CP,Receive Channel 7 Completion Pointer Register"
|
|
group.long 0x200++0x8f "Network Statistics Registers"
|
|
line.long 0x00 "RXGOODFRAMES,Good Receive Frames Register"
|
|
line.long 0x04 "RXBCASTFRAMES,Broadcast Receive Frames Register"
|
|
line.long 0x08 "RXMCASTFRAMES,Multicast Receive Frames Register"
|
|
line.long 0x0c "RXPAUSEFRAMES,Pause Receive Frames Register"
|
|
line.long 0x10 "RXCRCERRORS,Receive CRC Errors Register"
|
|
line.long 0x14 "RXALIGNCODEERRORS,Receive Alignment/Code Errors Register"
|
|
line.long 0x18 "RXOVERSIZED,Receive Oversized Frames Register"
|
|
line.long 0x1c "RXJABBER,Receive Jabber Frames Register"
|
|
line.long 0x20 "RXUNDERSIZED,Receive Undersized Frames Register"
|
|
line.long 0x24 "RXFRAGMENTS,Receive Frame Fragments Register"
|
|
line.long 0x28 "RXFILTERED,Filtered Receive Frames Register"
|
|
line.long 0x2c "RXQOSFILTERED,Receive QOS Filtered Frames Register"
|
|
line.long 0x30 "RXOCTETS,Receive Octet Frames Register"
|
|
line.long 0x34 "TXGOODFRAMES,Good Transmit Frames Register"
|
|
line.long 0x38 "TXBCASTFRAMES,Broadcast Transmit Frames Register"
|
|
line.long 0x3c "TXMCASTFRAMES,Multicast Transmit Frames Register"
|
|
line.long 0x40 "TXPAUSEFRAMES,Pause Transmit Frames Register"
|
|
line.long 0x44 "TXDEFERRED,Deferred Transmit Frames Register"
|
|
line.long 0x48 "TXCOLLISION,Transmit Collision Frames Register"
|
|
line.long 0x4c "TXSINGLECOLL,Transmit Single Collision Frames Register"
|
|
line.long 0x50 "TXMULTICOLL,Transmit Multiple Collision Frames Register"
|
|
line.long 0x54 "TXEXCESSIVECOLL,Transmit Excessive Collision Frames Register"
|
|
line.long 0x58 "TXLATECOLL,Transmit Late Collision Frames Register"
|
|
line.long 0x5c "TXUNDERRUN,Transmit Underrun Error Register"
|
|
line.long 0x60 "TXCARRIERSENSE,Transmit Carrier Sense Errors Register"
|
|
line.long 0x64 "TXOCTETS,Transmit Octet Frames Register"
|
|
line.long 0x68 "FRAME64,Transmit and Receive 64 Octet Frames Register"
|
|
line.long 0x6c "FRAME65T127,Transmit and Receive 65 to 127 Octet Frames Register"
|
|
line.long 0x70 "FRAME128T255,Transmit and Receive 128 to 255 Octet Frames Register"
|
|
line.long 0x74 "FRAME256T511,Transmit and Receive 256 to 511 Octet Frames Register"
|
|
line.long 0x78 "FRAME512T1023,Transmit and Receive 512 to 1023 Octet Frames Register"
|
|
line.long 0x7c "FRAME1024TUP,Transmit and Receive 1024 to RXMAXLEN Octet Frames Register"
|
|
line.long 0x80 "NETOCTETS,Network Octet Frames Register"
|
|
line.long 0x84 "RXSOFOVERRUNS,Receive FIFO or DMA Start of Frame Overruns Register"
|
|
line.long 0x88 "RXMOFOVERRUNS,Receive FIFO or DMA Middle of Frame Overruns Register"
|
|
line.long 0x8c "RXDMAOVERRUNS,Receive DMA Overruns Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "McASP (Multichannel Audio Serial Port)"
|
|
tree "McASP 0"
|
|
base asd:0x01D00000
|
|
width 7.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR0 ,AFSR0 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR0 ,AHCLKR0 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR0 ,ACLKR0 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX0 ,AFSX0 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 27. " AHCLKX0 ,AHCLKX0 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX0 ,ACLKX0 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE0 ,AMUTE0 pin function" "McASP,GPIO"
|
|
sif (cpu()!="DA828")
|
|
bitfld.long 0x00 25. " AMUTE0 ,AMUTE0 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 15. " AXR0_15 ,AXR0[15] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 14. " AXR0_14 ,AXR0[14] pin function" "McASP,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " AXR0_13 ,AXR0[13] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 12. " AXR0_12 ,AXR0[12] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR0_11 ,AXR0[11] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AXR0_10 ,AXR0[10] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AXR0_9 ,AXR0[9] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AXR0_8 ,AXR0[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR0_7 ,AXR0[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR0_6 ,AXR0[6] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 5. " AXR0_5 ,AXR0[5] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AXR0_4 ,AXR0[4] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AXR0_3 ,AXR0[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR0_2 ,AXR0[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR0_1 ,AXR0[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR0_0 ,AXR0[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR0 ,AFSR0 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR0 ,AHCLKR0 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR0 ,ACLKR0 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX0 ,AFSX0 pin direction" "Input,Output"
|
|
bitfld.long 0x00 27. " AHCLKX0 ,AHCLKX0 pin direction" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX0 ,ACLKX0 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE0 ,AMUTE0 pin direction" "Input,Output"
|
|
sif (cpu()!="DA828")
|
|
bitfld.long 0x00 25. " AMUTE0 ,AMUTE0 pin direction" "Input,Output"
|
|
bitfld.long 0x00 15. " AXR0_15 ,AXR0[15] pin direction" "Input,Output"
|
|
bitfld.long 0x00 14. " AXR0_14 ,AXR0[14] pin direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " AXR0_13 ,AXR0[13] pin direction" "Input,Output"
|
|
bitfld.long 0x00 12. " AXR0_12 ,AXR0[12] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR0_11 ,AXR0[11] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AXR0_10 ,AXR0[10] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AXR0_9 ,AXR0[9] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AXR0_8 ,AXR0[8] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR0_7 ,AXR0[7] pin direction" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR0_6 ,AXR0[6] pin direction" "Input,Output"
|
|
bitfld.long 0x00 5. " AXR0_5 ,AXR0[5] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AXR0_4 ,AXR0[4] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AXR0_3 ,AXR0[3] pin direction" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR0_2 ,AXR0[2] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR0_1 ,AXR0[1] pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR0_0 ,AXR0[0] pin direction" "Input,Output"
|
|
width 7.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR0_set/clr ,Drive on AFSR0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR0_set/clr ,Drive on AHCLKR0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR0_set/clr ,Drive on ACLKR0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX0_set/clr ,Drive on AFSX0" "Low,High"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX0_set/clr ,Drive on AHCLKX0" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX0_set/clr ,Drive on ACLKX0" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE0_set/clr ,Drive on AMUTE0" "Low,High"
|
|
sif (cpu()!="DA828")
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE0_set/clr ,Drive on AMUTE0" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " AXR0_15_set/clr ,Drive on AXR0[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR0_14_set/clr ,Drive on AXR0[14]" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR0_13_set/clr ,Drive on AXR0[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR0_12_set/clr ,Drive on AXR0[12]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " AXR0_11_set/clr ,Drive on AXR0[11]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR0_10_set/clr ,Drive on AXR0[10]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR0_9_set/clr ,Drive on AXR0[9]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR0_8_set/clr ,Drive on AXR0[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR0_7_set/clr ,Drive on AXR0[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR0_6_set/clr ,Drive on AXR0[6]" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " AXR0_5_set/clr ,Drive on AXR0[5]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR0_4_set/clr ,Drive on AXR0[4]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR0_3_set/clr ,Drive on AXR0[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR0_2_set/clr ,Drive on AXR0[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR0_1_set/clr ,Drive on AXR0[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_0_set/clr ,Drive on AXR0[0]" "Low,High"
|
|
width 7.
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR0 ,AFSR0 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR0 ,AHCLKR0 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR0 ,ACLKR0 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX0 ,AFSX0 logic level" "Low,High"
|
|
bitfld.long 0x00 27. " AHCLKX0 ,AHCLKX0 logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX0 ,ACLKX0 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE0 ,AMUTE0 logic level" "Low,High"
|
|
sif (cpu()!="DA828")
|
|
bitfld.long 0x00 25. " AMUTE0 ,AMUTE0 logic level" "Low,High"
|
|
bitfld.long 0x00 15. " AXR0_15 ,AXR0[15] logic level" "Low,High"
|
|
bitfld.long 0x00 14. " AXR0_14 ,AXR0[14] logic level" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " AXR0_13 ,AXR0[13] logic level" "Low,High"
|
|
bitfld.long 0x00 12. " AXR0_12 ,AXR0[12] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AXR0_11 ,AXR0[11] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AXR0_10 ,AXR0[10] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AXR0_9 ,AXR0[9] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AXR0_8 ,AXR0[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR0_7 ,AXR0[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR0_6 ,AXR0[6] logic level" "Low,High"
|
|
bitfld.long 0x00 5. " AXR0_5 ,AXR0[5] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AXR0_4 ,AXR0[4] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AXR0_3 ,AXR0[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR0_2 ,AXR0[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR0_1 ,AXR0[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR0_0 ,AXR0[0] logic level" "Low,High"
|
|
width 8.
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCKFAIL ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XSYNCERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " XUNDRN ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTL,Receiver Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DMA port,Peripheral configuration port"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,Disabled"
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "XMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " XMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " XMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " XMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " XMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " XMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " XMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " XMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " XMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " XMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " XMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " XMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " XMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " XMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " XMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " XMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " XMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " XMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " XMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " XMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " XMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " XMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " XMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " XMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " XMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " XMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " XMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "XFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DMA port,Peripheral configuration port"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "XTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " XTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " XTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " XTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " XTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " XTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " XTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " XTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " XTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " XTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " XTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " XTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " XTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " XTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " XTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " XTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " XTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " XTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " XTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " XTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " XTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " XTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " XTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " XTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " XTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " XTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " XTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "XSTAT,Transmitter Status Register"
|
|
bitfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "XCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,Disabled"
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "SRCTL0 ,Serializer Control Register 0 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "SRCTL1 ,Serializer Control Register 1 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "SRCTL2 ,Serializer Control Register 2 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "SRCTL3 ,Serializer Control Register 3 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "SRCTL4 ,Serializer Control Register 4 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "SRCTL5 ,Serializer Control Register 5 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "SRCTL6 ,Serializer Control Register 6 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "SRCTL7 ,Serializer Control Register 7 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "SRCTL8 ,Serializer Control Register 8 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "SRCTL9 ,Serializer Control Register 9 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "SRCTL10,Serializer Control Register 10"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1AC++0x3
|
|
line.long 0x00 "SRCTL11,Serializer Control Register 11"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "SRCTL12,Serializer Control Register 12"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1B4++0x3
|
|
line.long 0x00 "SRCTL13,Serializer Control Register 13"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1B8++0x3
|
|
line.long 0x00 "SRCTL14,Serializer Control Register 14"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1BC++0x3
|
|
line.long 0x00 "SRCTL15,Serializer Control Register 15"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x3f
|
|
line.long 0x0 "XBUF0 ,Transmit Buffer Register"
|
|
line.long 0x4 "XBUF1 ,Transmit Buffer Register"
|
|
line.long 0x8 "XBUF2 ,Transmit Buffer Register"
|
|
line.long 0xC "XBUF3 ,Transmit Buffer Register"
|
|
line.long 0x10 "XBUF4 ,Transmit Buffer Register"
|
|
line.long 0x14 "XBUF5 ,Transmit Buffer Register"
|
|
line.long 0x18 "XBUF6 ,Transmit Buffer Register"
|
|
line.long 0x1C "XBUF7 ,Transmit Buffer Register"
|
|
line.long 0x20 "XBUF8 ,Transmit Buffer Register"
|
|
line.long 0x24 "XBUF9 ,Transmit Buffer Register"
|
|
line.long 0x28 "XBUF10,Transmit Buffer Register"
|
|
line.long 0x2C "XBUF11,Transmit Buffer Register"
|
|
line.long 0x30 "XBUF12,Transmit Buffer Register"
|
|
line.long 0x34 "XBUF13,Transmit Buffer Register"
|
|
line.long 0x38 "XBUF14,Transmit Buffer Register"
|
|
line.long 0x3C "XBUF15,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x3f
|
|
line.long 0x0 "RBUF0 ,Receive Buffer Register"
|
|
line.long 0x4 "RBUF1 ,Receive Buffer Register"
|
|
line.long 0x8 "RBUF2 ,Receive Buffer Register"
|
|
line.long 0xC "RBUF3 ,Receive Buffer Register"
|
|
line.long 0x10 "RBUF4 ,Receive Buffer Register"
|
|
line.long 0x14 "RBUF5 ,Receive Buffer Register"
|
|
line.long 0x18 "RBUF6 ,Receive Buffer Register"
|
|
line.long 0x1C "RBUF7 ,Receive Buffer Register"
|
|
line.long 0x20 "RBUF8 ,Receive Buffer Register"
|
|
line.long 0x24 "RBUF9 ,Receive Buffer Register"
|
|
line.long 0x28 "RBUF10,Receive Buffer Register"
|
|
line.long 0x2C "RBUF11,Receive Buffer Register"
|
|
line.long 0x30 "RBUF12,Receive Buffer Register"
|
|
line.long 0x34 "RBUF13,Receive Buffer Register"
|
|
line.long 0x38 "RBUF14,Receive Buffer Register"
|
|
line.long 0x3C "RBUF15,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
rgroup.long 0x1000++0x3
|
|
line.long 0x00 "AFIFOREV,AFIFO Revision Identification Register"
|
|
group.long 0x1010++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1014++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1018++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x101c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 1"
|
|
base asd:0x01D04000
|
|
width 7.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR1 ,AFSR1 pin function" "McASP,GPIO"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR1 ,AHCLKR1 pin function" "McASP,GPIO"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR1 ,ACLKR1 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX1 ,AFSX1 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 27. " AHCLKX1 ,AHCLKX1 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX1 ,ACLKX1 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE1 ,AMUTE1 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 11. " AXR1_11 ,AXR1[11] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AXR1_10 ,AXR1[10] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AXR1_8 ,AXR1[8] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR1_7 ,AXR1[7] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 6. " AXR1_6 ,AXR1[6] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 5. " AXR1_5 ,AXR1[5] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AXR1_4 ,AXR1[4] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AXR1_3 ,AXR1[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR1_2 ,AXR1[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1_1 ,AXR1[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR1_0 ,AXR1[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR1 ,AFSR1 pin direction" "Input,Output"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR1 ,AHCLKR1 pin direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR1 ,ACLKR1 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX1 ,AFSX1 pin direction" "Input,Output"
|
|
bitfld.long 0x00 27. " AHCLKX1 ,AHCLKX1 pin direction" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX1 ,ACLKX1 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE1 ,AMUTE1 pin direction" "Input,Output"
|
|
bitfld.long 0x00 11. " AXR1_11 ,AXR1[11] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AXR1_10 ,AXR1[10] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AXR1_8 ,AXR1[8] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR1_7 ,AXR1[7] pin direction" "Input,Output"
|
|
bitfld.long 0x00 6. " AXR1_6 ,AXR1[6] pin direction" "Input,Output"
|
|
bitfld.long 0x00 5. " AXR1_5 ,AXR1[5] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AXR1_4 ,AXR1[4] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AXR1_3 ,AXR1[3] pin direction" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR1_2 ,AXR1[2] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1_1 ,AXR1[1] pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR1_0 ,AXR1[0] pin direction" "Input,Output"
|
|
width 7.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR1_set/clr ,Drive on AFSR1" "Low,High"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR1_set/clr ,Drive on AHCLKR1" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR1_set/clr ,Drive on ACLKR1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX1_set/clr ,Drive on AFSX1" "Low,High"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX1_set/clr ,Drive on AHCLKX1" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX1_set/clr ,Drive on ACLKX1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE1_set/clr ,Drive on AMUTE1" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " AXR1_11_set/clr ,Drive on AXR1[11]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR1_10_set/clr ,Drive on AXR1[10]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR1_8_set/clr ,Drive on AXR1[8]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR1_7_set/clr ,Drive on AXR1[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR1_6_set/clr ,Drive on AXR1[6]" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " AXR1_5_set/clr ,Drive on AXR1[5]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR1_4_set/clr ,Drive on AXR1[4]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR1_3_set/clr ,Drive on AXR1[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR1_2_set/clr ,Drive on AXR1[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_1_set/clr ,Drive on AXR1[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR1_0_set/clr ,Drive on AXR1[0]" "Low,High"
|
|
width 7.
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR1 ,AFSR1 logic level" "Low,High"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR1 ,AHCLKR1 logic level" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR1 ,ACLKR1 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX1 ,AFSX1 logic level" "Low,High"
|
|
bitfld.long 0x00 27. " AHCLKX1 ,AHCLKX1 logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX1 ,ACLKX1 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE1 ,AMUTE1 logic level" "Low,High"
|
|
bitfld.long 0x00 11. " AXR1_11 ,AXR1[11] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AXR1_10 ,AXR1[10] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AXR1_8 ,AXR1[8] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AXR1_7 ,AXR1[7] logic level" "Low,High"
|
|
bitfld.long 0x00 6. " AXR1_6 ,AXR1[6] logic level" "Low,High"
|
|
bitfld.long 0x00 5. " AXR1_5 ,AXR1[5] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AXR1_4 ,AXR1[4] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AXR1_3 ,AXR1[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR1_2 ,AXR1[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR1_1 ,AXR1[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR1_0 ,AXR1[0] logic level" "Low,High"
|
|
width 8.
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCKFAIL ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XSYNCERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " XUNDRN ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTL,Receiver Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DMA port,Peripheral configuration port"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,Disabled"
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "XMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " XMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " XMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " XMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " XMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " XMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " XMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " XMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " XMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " XMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " XMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " XMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " XMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " XMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " XMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " XMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " XMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " XMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " XMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " XMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " XMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " XMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " XMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " XMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " XMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " XMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " XMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "XFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DMA port,Peripheral configuration port"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "XTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " XTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " XTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " XTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " XTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " XTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " XTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " XTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " XTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " XTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " XTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " XTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " XTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " XTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " XTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " XTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " XTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " XTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " XTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " XTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " XTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " XTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " XTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " XTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " XTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " XTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " XTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "XSTAT,Transmitter Status Register"
|
|
bitfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "XCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,Disabled"
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "SRCTL0 ,Serializer Control Register 0 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "SRCTL1 ,Serializer Control Register 1 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "SRCTL2 ,Serializer Control Register 2 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "SRCTL3 ,Serializer Control Register 3 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "SRCTL4 ,Serializer Control Register 4 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "SRCTL5 ,Serializer Control Register 5 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "SRCTL6 ,Serializer Control Register 6 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "SRCTL7 ,Serializer Control Register 7 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "SRCTL8 ,Serializer Control Register 8 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "SRCTL9 ,Serializer Control Register 9 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "SRCTL10,Serializer Control Register 10"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x1AC++0x3
|
|
line.long 0x00 "SRCTL11,Serializer Control Register 11"
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x3f
|
|
line.long 0x0 "XBUF0 ,Transmit Buffer Register"
|
|
line.long 0x4 "XBUF1 ,Transmit Buffer Register"
|
|
line.long 0x8 "XBUF2 ,Transmit Buffer Register"
|
|
line.long 0xC "XBUF3 ,Transmit Buffer Register"
|
|
line.long 0x10 "XBUF4 ,Transmit Buffer Register"
|
|
line.long 0x14 "XBUF5 ,Transmit Buffer Register"
|
|
line.long 0x18 "XBUF6 ,Transmit Buffer Register"
|
|
line.long 0x1C "XBUF7 ,Transmit Buffer Register"
|
|
line.long 0x20 "XBUF8 ,Transmit Buffer Register"
|
|
line.long 0x24 "XBUF9 ,Transmit Buffer Register"
|
|
line.long 0x28 "XBUF10,Transmit Buffer Register"
|
|
line.long 0x2C "XBUF11,Transmit Buffer Register"
|
|
line.long 0x30 "XBUF12,Transmit Buffer Register"
|
|
line.long 0x34 "XBUF13,Transmit Buffer Register"
|
|
line.long 0x38 "XBUF14,Transmit Buffer Register"
|
|
line.long 0x3C "XBUF15,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x3f
|
|
line.long 0x0 "RBUF0 ,Receive Buffer Register"
|
|
line.long 0x4 "RBUF1 ,Receive Buffer Register"
|
|
line.long 0x8 "RBUF2 ,Receive Buffer Register"
|
|
line.long 0xC "RBUF3 ,Receive Buffer Register"
|
|
line.long 0x10 "RBUF4 ,Receive Buffer Register"
|
|
line.long 0x14 "RBUF5 ,Receive Buffer Register"
|
|
line.long 0x18 "RBUF6 ,Receive Buffer Register"
|
|
line.long 0x1C "RBUF7 ,Receive Buffer Register"
|
|
line.long 0x20 "RBUF8 ,Receive Buffer Register"
|
|
line.long 0x24 "RBUF9 ,Receive Buffer Register"
|
|
line.long 0x28 "RBUF10,Receive Buffer Register"
|
|
line.long 0x2C "RBUF11,Receive Buffer Register"
|
|
line.long 0x30 "RBUF12,Receive Buffer Register"
|
|
line.long 0x34 "RBUF13,Receive Buffer Register"
|
|
line.long 0x38 "RBUF14,Receive Buffer Register"
|
|
line.long 0x3C "RBUF15,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
rgroup.long 0x1000++0x3
|
|
line.long 0x00 "AFIFOREV,AFIFO Revision Identification Register"
|
|
group.long 0x1010++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1014++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1018++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x101c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "McASP 2"
|
|
base asd:0x01D08000
|
|
width 7.
|
|
tree "General Registers"
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REV,Revision Identification Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PFUNC,Pin Function Register"
|
|
bitfld.long 0x00 31. " AFSR2 ,AFSR2 pin function" "McASP,GPIO"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR2 ,AHCLKR2 pin function" "McASP,GPIO"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR2 ,ACLKR2 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX2 ,AFSX2 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 27. " AHCLKX2 ,AHCLKX2 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 26. " ACLKX2 ,ACLKX2 pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE2 ,AMUTE2 pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 3. " AXR2_3 ,AXR2[3] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 2. " AXR2_2 ,AXR2[2] pin function" "McASP,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR2_1 ,AXR2[1] pin function" "McASP,GPIO"
|
|
bitfld.long 0x00 0. " AXR2_0 ,AXR2[0] pin function" "McASP,GPIO"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "PDIR,Pin Direction Register"
|
|
bitfld.long 0x00 31. " AFSR2 ,AFSR2 pin direction" "Input,Output"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR2 ,AHCLKR2 pin direction" "Input,Output"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR2 ,ACLKR2 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX2 ,AFSX2 pin direction" "Input,Output"
|
|
bitfld.long 0x00 27. " AHCLKX2 ,AHCLKX2 pin direction" "Input,Output"
|
|
bitfld.long 0x00 26. " ACLKX2 ,ACLKX2 pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE2 ,AMUTE2 pin direction" "Input,Output"
|
|
bitfld.long 0x00 3. " AXR2_3 ,AXR2[3] pin direction" "Input,Output"
|
|
bitfld.long 0x00 2. " AXR2_2 ,AXR2[2] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR2_1 ,AXR2[1] pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " AXR2_0 ,AXR2[0] pin direction" "Input,Output"
|
|
width 7.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "PDOUT,Pin Data Output Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR2_set/clr ,Drive on AFSR2" "Low,High"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR2_set/clr ,Drive on AHCLKR2" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR2_set/clr ,Drive on ACLKR2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX2_set/clr ,Drive on AFSX2" "Low,High"
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX2_set/clr ,Drive on AHCLKX2" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX2_set/clr ,Drive on ACLKX2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE2_set/clr ,Drive on AMUTE2" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR2_3_set/clr ,Drive on AXR2[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_2_set/clr ,Drive on AXR2[2]" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR2_1_set/clr ,Drive on AXR2[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR2_0_set/clr ,Drive on AXR2[0]" "Low,High"
|
|
width 7.
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "PDIN,Pin Data Input Register"
|
|
bitfld.long 0x00 31. " AFSR2 ,AFSR2 logic level" "Low,High"
|
|
sif (cpu()!="DA828")
|
|
textline " "
|
|
bitfld.long 0x00 30. " AHCLKR2 ,AHCLKR2 logic level" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 29. " ACLKR2 ,ACLKR2 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AFSX2 ,AFSX2 logic level" "Low,High"
|
|
bitfld.long 0x00 27. " AHCLKX2 ,AHCLKX2 logic level" "Low,High"
|
|
bitfld.long 0x00 26. " ACLKX2 ,ACLKX2 logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AMUTE2 ,AMUTE2 logic level" "Low,High"
|
|
bitfld.long 0x00 3. " AXR2_3 ,AXR2[3] logic level" "Low,High"
|
|
bitfld.long 0x00 2. " AXR2_2 ,AXR2[2] logic level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AXR2_1 ,AXR2[1] logic level" "Low,High"
|
|
bitfld.long 0x00 0. " AXR2_0 ,AXR2[0] logic level" "Low,High"
|
|
width 8.
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "GBLCTL,Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "AMUTE,Audio Mute Control Register"
|
|
bitfld.long 0x00 12. " XDMAERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDMAERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCKFAIL ,AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCKFAIL ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XSYNCERR ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RSYNCERR ,AMUTE active enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " XUNDRN ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROVRN ,AMUTE active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
|
|
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
|
|
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
|
|
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
|
|
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "DITCTL,Digital Mode Control Register"
|
|
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
|
|
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
|
|
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
tree "Receive Registers"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RGBLCTL,Receiver Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RMASK,Receive Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " RMASK31 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " RMASK30 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " RMASK29 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RMASK28 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " RMASK27 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " RMASK26 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RMASK25 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " RMASK24 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " RMASK23 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RMASK22 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " RMASK21 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " RMASK20 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RMASK19 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RMASK18 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " RMASK17 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RMASK16 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " RMASK15 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " RMASK14 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RMASK13 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " RMASK12 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " RMASK11 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RMASK10 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " RMASK9 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " RMASK8 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RMASK7 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " RMASK6 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " RMASK5 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RMASK4 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " RMASK3 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " RMASK2 ,Receive data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RMASK1 ,Receive data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " RMASK0 ,Receive data mask enable" "Masked,Not masked"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RFMT,Receive Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DMA port,Peripheral configuration port"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0x6c++0x3
|
|
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
|
|
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
|
|
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RTDM,Receive TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " RTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " RTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " RTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " RTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " RTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " RTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " RTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " RTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " RTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " RTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " RTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " RTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " RTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " RTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " RTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " RTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " RTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " RTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " RTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0x7c++0x3
|
|
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
|
|
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RSTAT,Receiver Status Register"
|
|
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
|
|
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
|
|
group.long 0x88++0x7
|
|
line.long 0x00 "RCLKCHK,Receive Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
|
|
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,Disabled"
|
|
tree.end
|
|
tree "Transmit Registers"
|
|
group.long 0xa0++0x3
|
|
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
|
|
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Enabled,Disabled"
|
|
group.long 0xa4++0x3
|
|
line.long 0x00 "XMASK,Transmit Format Unit Bit Mask Register"
|
|
bitfld.long 0x00 31. " XMASK31 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " XMASK30 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " XMASK29 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " XMASK28 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " XMASK27 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " XMASK26 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " XMASK25 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " XMASK24 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " XMASK23 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " XMASK22 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " XMASK21 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " XMASK20 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " XMASK19 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " XMASK18 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " XMASK17 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XMASK16 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " XMASK15 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " XMASK14 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XMASK13 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " XMASK12 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " XMASK11 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XMASK10 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " XMASK9 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " XMASK8 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XMASK7 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " XMASK6 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " XMASK5 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XMASK4 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " XMASK3 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " XMASK2 ,Transmit data mask enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XMASK1 ,Transmit data mask enable" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " XMASK0 ,Transmit data mask enable" "Masked,Not masked"
|
|
group.long 0xa8++0x3
|
|
line.long 0x00 "XFMT,Transmit Bit Stream Format Register"
|
|
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
|
|
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
|
|
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DMA port,Peripheral configuration port"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
|
|
group.long 0xac++0x3
|
|
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
|
|
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
|
|
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
|
|
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
|
|
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
|
|
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
|
|
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
|
|
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
|
|
group.long 0xb8++0x3
|
|
line.long 0x00 "XTDM,Transmit TDM Time Slot Register"
|
|
bitfld.long 0x00 31. " XTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " XTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " XTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " XTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
|
|
bitfld.long 0x00 27. " XTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " XTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " XTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " XTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
|
|
bitfld.long 0x00 23. " XTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " XTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " XTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " XTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " XTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " XTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " XTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
|
|
bitfld.long 0x00 15. " XTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " XTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " XTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
|
|
bitfld.long 0x00 11. " XTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " XTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " XTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " XTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " XTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " XTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
|
|
bitfld.long 0x00 3. " XTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " XTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " XTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
|
|
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
|
|
group.long 0xc0++0x3
|
|
line.long 0x00 "XSTAT,Transmitter Status Register"
|
|
bitfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
|
|
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
|
|
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
|
|
textline " "
|
|
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
|
|
rgroup.long 0xc4++0x3
|
|
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
|
|
group.long 0xc8++0x7
|
|
line.long 0x00 "XCLKCHK,Transmit Clock Check Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
|
|
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
|
|
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
|
|
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,Disabled"
|
|
tree.end
|
|
width 9.
|
|
tree "Serializer Control Registers"
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "SRCTL0 ,Serializer Control Register 0 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "SRCTL1 ,Serializer Control Register 1 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "SRCTL2 ,Serializer Control Register 2 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "SRCTL3 ,Serializer Control Register 3 "
|
|
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
|
|
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
|
|
tree.end
|
|
tree "DIT Channel Registers"
|
|
group.long 0x100++0x17
|
|
line.long 0x0 "DITCSRA0,DIT Left Channel Status Register 0"
|
|
line.long 0x4 "DITCSRA1,DIT Left Channel Status Register 1"
|
|
line.long 0x8 "DITCSRA2,DIT Left Channel Status Register 2"
|
|
line.long 0xC "DITCSRA3,DIT Left Channel Status Register 3"
|
|
line.long 0x10 "DITCSRA4,DIT Left Channel Status Register 4"
|
|
line.long 0x14 "DITCSRA5,DIT Left Channel Status Register 5"
|
|
group.long 0x118++0x17
|
|
line.long 0x0 "DITCSRB0,DIT Right Channel Status Register 0"
|
|
line.long 0x4 "DITCSRB1,DIT Right Channel Status Register 1"
|
|
line.long 0x8 "DITCSRB2,DIT Right Channel Status Register 2"
|
|
line.long 0xC "DITCSRB3,DIT Right Channel Status Register 3"
|
|
line.long 0x10 "DITCSRB4,DIT Right Channel Status Register 4"
|
|
line.long 0x14 "DITCSRB5,DIT Right Channel Status Register 5"
|
|
group.long 0x130++0x17
|
|
line.long 0x0 "DITUDRA0,DIT Left Channel User Data Register 0"
|
|
line.long 0x4 "DITUDRA1,DIT Left Channel User Data Register 1"
|
|
line.long 0x8 "DITUDRA2,DIT Left Channel User Data Register 2"
|
|
line.long 0xC "DITUDRA3,DIT Left Channel User Data Register 3"
|
|
line.long 0x10 "DITUDRA4,DIT Left Channel User Data Register 4"
|
|
line.long 0x14 "DITUDRA5,DIT Left Channel User Data Register 5"
|
|
group.long 0x148++0x17
|
|
line.long 0x0 "DITUDRB0,DIT Right Channel User Data Register 0"
|
|
line.long 0x4 "DITUDRB1,DIT Right Channel User Data Register 1"
|
|
line.long 0x8 "DITUDRB2,DIT Right Channel User Data Register 2"
|
|
line.long 0xC "DITUDRB3,DIT Right Channel User Data Register 3"
|
|
line.long 0x10 "DITUDRB4,DIT Right Channel User Data Register 4"
|
|
line.long 0x14 "DITUDRB5,DIT Right Channel User Data Register 5"
|
|
tree.end
|
|
tree "Transmit Buffer Registers"
|
|
group.long 0x200++0x3f
|
|
line.long 0x0 "XBUF0 ,Transmit Buffer Register"
|
|
line.long 0x4 "XBUF1 ,Transmit Buffer Register"
|
|
line.long 0x8 "XBUF2 ,Transmit Buffer Register"
|
|
line.long 0xC "XBUF3 ,Transmit Buffer Register"
|
|
line.long 0x10 "XBUF4 ,Transmit Buffer Register"
|
|
line.long 0x14 "XBUF5 ,Transmit Buffer Register"
|
|
line.long 0x18 "XBUF6 ,Transmit Buffer Register"
|
|
line.long 0x1C "XBUF7 ,Transmit Buffer Register"
|
|
line.long 0x20 "XBUF8 ,Transmit Buffer Register"
|
|
line.long 0x24 "XBUF9 ,Transmit Buffer Register"
|
|
line.long 0x28 "XBUF10,Transmit Buffer Register"
|
|
line.long 0x2C "XBUF11,Transmit Buffer Register"
|
|
line.long 0x30 "XBUF12,Transmit Buffer Register"
|
|
line.long 0x34 "XBUF13,Transmit Buffer Register"
|
|
line.long 0x38 "XBUF14,Transmit Buffer Register"
|
|
line.long 0x3C "XBUF15,Transmit Buffer Register"
|
|
tree.end
|
|
tree "Receive Buffer Registers"
|
|
group.long 0x280++0x3f
|
|
line.long 0x0 "RBUF0 ,Receive Buffer Register"
|
|
line.long 0x4 "RBUF1 ,Receive Buffer Register"
|
|
line.long 0x8 "RBUF2 ,Receive Buffer Register"
|
|
line.long 0xC "RBUF3 ,Receive Buffer Register"
|
|
line.long 0x10 "RBUF4 ,Receive Buffer Register"
|
|
line.long 0x14 "RBUF5 ,Receive Buffer Register"
|
|
line.long 0x18 "RBUF6 ,Receive Buffer Register"
|
|
line.long 0x1C "RBUF7 ,Receive Buffer Register"
|
|
line.long 0x20 "RBUF8 ,Receive Buffer Register"
|
|
line.long 0x24 "RBUF9 ,Receive Buffer Register"
|
|
line.long 0x28 "RBUF10,Receive Buffer Register"
|
|
line.long 0x2C "RBUF11,Receive Buffer Register"
|
|
line.long 0x30 "RBUF12,Receive Buffer Register"
|
|
line.long 0x34 "RBUF13,Receive Buffer Register"
|
|
line.long 0x38 "RBUF14,Receive Buffer Register"
|
|
line.long 0x3C "RBUF15,Receive Buffer Register"
|
|
tree.end
|
|
tree "McASP AFIFO Registers"
|
|
rgroup.long 0x1000++0x3
|
|
line.long 0x00 "AFIFOREV,AFIFO Revision Identification Register"
|
|
group.long 0x1010++0x3
|
|
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
|
|
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
|
|
rgroup.long 0x1014++0x3
|
|
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
|
|
group.long 0x1018++0x3
|
|
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
|
|
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
|
|
rgroup.long 0x101c++0x3
|
|
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "SPI (Serial Port Interface)"
|
|
tree "SPI 0"
|
|
base asd:0x01c41000
|
|
width 10.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "SPIGCR0,SPI0 Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,Reset bit for the SPI0 module" "No reset,Reset"
|
|
line.long 0x04 "SPIGCR1,SPI0 Global Control Register 1"
|
|
bitfld.long 0x04 24. " ENABLE ,SPI0 enable" "Reset,Enabled"
|
|
bitfld.long 0x04 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " POWERDOWN ,SPI0 state machine enters a power-down state" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MASTER/CLKMOD ,Master/Slave Clock mode" "Slave/Input,Reserved,Reserved,Master/Output"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 "SPIINT,SPI0 Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLEHIGHZ ,/SPI0_ENA pin high-impedance enable" "Pulled high,High-impedance"
|
|
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTEN ,Receive interrupt enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OVRNINTEN ,Overrun interrupt enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on /SPI0_ENA signal time-out" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
line.long 0x04 "SPILVL,SPI0 Interrupt Level Register"
|
|
bitfld.long 0x04 9. " TXINTLVL ,Transmit interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 8. " RXINTLVL ,Receive interrupt level" "Reserved,INT1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OVRNINTLVL ,Receive overrun interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 4. " BITERRLVL ,Bit error interrupt level" "Reserved,INT1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DESYNCLVL ,Desynchronized slave interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 2. " PARERRLVL ,Parity error interrupt level" "Reserved,INT1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TIMEOUTLVL ,/SPI0_ENA signal time-out interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 0. " DLENERRLVL ,Data length error interrupt enable level" "Reserved,INT1"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "SPIFLG,SPI0 Flag Register"
|
|
in
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "SPIPC0,SPI0 Pin Control Register 0"
|
|
bitfld.long 0x00 11. " SOMIFUN ,Slave out - master in pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 10. " SIMOFUN ,Slave in - master out pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI0 clock pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPI0 enable pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCS0FUN[5] ,SPI0 chip select pin 5 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 4. " SCS0FUN[4] ,SPI0 chip select pin 4 function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCS0FUN[3] ,SPI0 chip select pin 3 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 2. " SCS0FUN[2] ,SPI0 chip select pin 2 function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCS0FUN[1] ,SPI0 chip select pin 1 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 0. " SCS0FUN[0] ,SPI0 chip select pin 0 function" "GPIO pin,SPI functional"
|
|
line.long 0x04 "SPIPC1,SPI0 Pin Control Register 1"
|
|
bitfld.long 0x04 11. " SOMIDIR ,SPI0_SOMI pin direction" "Input,Output"
|
|
bitfld.long 0x04 10. " SIMODIR ,SPI0_SIMO pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI0_CLK pin direction" "Input,Output"
|
|
bitfld.long 0x04 8. " ENADIR ,/SPI0_ENA pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCS0DIR[5] ,SPI0_SCS[5] pin direction" "Input,Output"
|
|
bitfld.long 0x04 4. " SCS0DIR[4] ,SPI0_SCS[4] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SCS0DIR[3] ,SPI0_SCS[3] pin direction" "Input,Output"
|
|
bitfld.long 0x04 2. " SCS0DIR[2] ,SPI0_SCS[2] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SCS0DIR[1] ,SPI0_SCS[1] pin direction" "Input,Output"
|
|
bitfld.long 0x04 0. " SCS0DIR[0] ,SPI0_SCS[0] pin direction" "Input,Output"
|
|
rgroup.long 0x1c++0xf
|
|
line.long 0x00 "SPIPC2,SPI0 Pin Control Register 2"
|
|
bitfld.long 0x00 11. " SOMIDIN ,SPI0_SOMI data in" "0,1"
|
|
bitfld.long 0x00 10. " SIMODIN ,SPI0_SIMO data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,SPI0 Clock data in" "0,1"
|
|
bitfld.long 0x00 8. " ENADIN ,SPI slave 0 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCS0DIN[5] ,SPI0_SCS[5] data in" "0,1"
|
|
bitfld.long 0x00 4. " SCS0DIN[4] ,SPI0_SCS[4] data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCS0DIN[3] ,SPI0_SCS[3] data in" "0,1"
|
|
bitfld.long 0x00 2. " SCS0DIN[2] ,SPI0_SCS[2] data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCS0DIN[1] ,SPI0_SCS[1] data in" "0,1"
|
|
bitfld.long 0x00 0. " SCS0DIN[0] ,SPI0_SCS[0] data in" "0,1"
|
|
line.long 0x04 "SPIPC3,SPI0 Pin Control Register 3"
|
|
bitfld.long 0x04 11. " SOMIDOUT ,SPI0_SOMI data out write" "0,1"
|
|
bitfld.long 0x04 10. " SIMODOUT ,SPI0_SIMO data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDOUT ,SPI Clock data out write" "0,1"
|
|
bitfld.long 0x04 8. " ENADOUT ,SPI slave 0 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCS0DOUT[5] ,SPI0_SCS[5] data out write" "0,1"
|
|
bitfld.long 0x04 4. " SCS0DOUT[4] ,SPI0_SCS[4] data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SCS0DOUT[3] ,SPI0_SCS[3] data out write" "0,1"
|
|
bitfld.long 0x04 2. " SCS0DOUT[2] ,SPI0_SCS[2] data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SCS0DOUT[1] ,SPI0_SCS[1] data out write" "0,1"
|
|
bitfld.long 0x04 0. " SCS0DOUT[0] ,SPI0_SCS[0] data out write" "0,1"
|
|
line.long 0x08 "SPIPC4,SPI0 Pin Control Register 3"
|
|
bitfld.long 0x08 11. " SOMISET ,SPI0_SOMI data out set" "No effect,Set"
|
|
bitfld.long 0x08 10. " SIMOSET ,SPI0_SIMO data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CLKSET ,SPI Clock data out set" "No effect,Set"
|
|
bitfld.long 0x08 8. " ENASET ,SPI slave 0 (SPI_EN1) pin value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SCS0SET[5] ,SPI0_SCS[5] data out set" "No effect,Set"
|
|
bitfld.long 0x08 4. " SCS0SET[4] ,SPI0_SCS[4] data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SCS0SET[3] ,SPI0_SCS[3] data out set" "No effect,Set"
|
|
bitfld.long 0x08 2. " SCS0SET[2] ,SPI0_SCS[2] data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SCS0SET[1] ,SPI0_SCS[1] data out set" "No effect,Set"
|
|
bitfld.long 0x08 0. " SCS0SET[0] ,SPI0_SCS[0] data out set" "No effect,Set"
|
|
line.long 0x0c "SPIPC5,SPI0 Pin Control Register 5"
|
|
bitfld.long 0x0c 11. " SOMICLR ,SPI0_SOMI data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " SIMOCLR ,SPI0_SIMO data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CLKCLR ,SPI Clock data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " ENACLR ,SPI slave 0 (SPI_EN1) pin value" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SCS0CLR[5] ,SPI0_SCS[5] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 4. " SCS0CLR[4] ,SPI0_SCS[4] data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SCS0CLR[3] ,SPI0_SCS[3] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 2. " SCS0CLR[2] ,SPI0_SCS[2] data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SCS0CLR[1] ,SPI0_SCS[1] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 0. " SCS0CLR[0] ,SPI0_SCS[0] data out clear" "No effect,Cleared"
|
|
else
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "SPIPC0,SPI0 Pin Control Register 0"
|
|
bitfld.long 0x00 11. " SOMIFUN ,Slave out - master in pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 10. " SIMOFUN ,Slave in - master out pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI0 clock pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPI0 enable pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCS0FUN[0] ,SPI0 chip select pin 0 function" "GPIO pin,SPI functional"
|
|
line.long 0x04 "SPIPC1,SPI0 Pin Control Register 1"
|
|
bitfld.long 0x04 11. " SOMIDIR ,SPI0_SOMI pin direction" "Input,Output"
|
|
bitfld.long 0x04 10. " SIMODIR ,SPI0_SIMO pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI0_CLK pin direction" "Input,Output"
|
|
bitfld.long 0x04 8. " ENADIR ,/SPI0_ENA pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SCS0DIR[0] ,SPI0_SCS[0] pin direction" "Input,Output"
|
|
rgroup.long 0x1c++0xf
|
|
line.long 0x00 "SPIPC2,SPI0 Pin Control Register 2"
|
|
bitfld.long 0x00 11. " SOMIDIN ,SPI0_SOMI data in" "0,1"
|
|
bitfld.long 0x00 10. " SIMODIN ,SPI0_SIMO data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,SPI0 Clock data in" "0,1"
|
|
bitfld.long 0x00 8. " ENADIN ,SPI slave 0 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCS0DIN[0] ,SPI0_SCS[0] data in" "0,1"
|
|
line.long 0x04 "SPIPC3,SPI0 Pin Control Register 3"
|
|
bitfld.long 0x04 11. " SOMIDOUT ,SPI0_SOMI data out write" "0,1"
|
|
bitfld.long 0x04 10. " SIMODOUT ,SPI0_SIMO data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDOUT ,SPI0 Clock data out write" "0,1"
|
|
bitfld.long 0x04 8. " ENADOUT ,SPI slave 0 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SCS0DOUT[0] ,SPI0_SCS[0] data out write" "0,1"
|
|
line.long 0x08 "SPIPC4,SPI0 Pin Control Register 3"
|
|
bitfld.long 0x08 11. " SOMISET ,SPI0_SOMI data out set" "No effect,Set"
|
|
bitfld.long 0x08 10. " SIMOSET ,SPI0_SIMO data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CLKSET ,SPI0 Clock data out set" "No effect,Set"
|
|
bitfld.long 0x08 8. " ENASET ,SPI slave 0 (SPI_EN1) pin value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SCS0SET[0] ,SPI0_SCS[0] data out set" "No effect,Set"
|
|
line.long 0x0c "SPIPC5,SPI0 Pin Control Register 5"
|
|
bitfld.long 0x0c 11. " SOMICLR ,SPI0_SOMI data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " SIMOCLR ,SPI0_SIMO data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CLKCLR ,SPI0 Clock data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " ENACLR ,SPI slave 0 (SPI_EN1) pin value" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " SCS0CLR[0] ,SPI0_SCS[0] data out clear" "No effect,Cleared"
|
|
endif
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "SPIDAT0,SPI0 Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI0 transmit data"
|
|
line.long 0x04 "SPIDAT1,SPI0 Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Deactivated,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
textline " "
|
|
bitfld.long 0x04 21. " CSNR[5] ,State of the /SPI0_SCS[5] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 20. " CSNR[4] ,State of the /SPI0_SCS[4] pin during a master data transfer" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CSNR[3] ,State of the /SPI0_SCS[3] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 18. " CSNR[2] ,State of the /SPI0_SCS[2] pin during a master data transfer" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " CSNR[1] ,State of the /SPI0_SCS[1] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 16. " CSNR[0] ,State of the /SPI0_SCS[0] pin during a master data transfer" "Low,High"
|
|
else
|
|
bitfld.long 0x04 16. " CSNR[0] ,State of the /SPI0_SCS[0] pin during a master data transfer" "Low,High"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "SPIBUF,SPI0 Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "SPIEMU,SPI0 Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI0 receive data"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "SPIDELAY,SPI0 Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active-to-transmit-start-delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished-to-SPI0_ENA-pin-inactive-time-out"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active-to-SPI0_ENA-signal-active-time-out"
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "SPIDEF,SPI0 Default Chip Select Register"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 5. " CSDEF[5] ,State of the the /SPI0_SCS[5] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF[4] ,State of the the /SPI0_SCS[4] pin when no transmissions are performed" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF[3] ,State of the the /SPI0_SCS[3] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF[2] ,State of the the /SPI0_SCS[2] pin when no transmissions are performed" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSDEF[1] ,State of the the /SPI0_SCS[1] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF[0] ,State of the the /SPI0_SCS[0] pin when no transmissions are performed" "Low,High"
|
|
else
|
|
bitfld.long 0x00 0. " CSDEF[0] ,State of the the /SPI0_SCS[0] pin when no transmissions are performed" "Low,High"
|
|
endif
|
|
width 10.
|
|
group.long 0x50++0xf
|
|
line.long 0x0 "SPIFMT0,SPI0 Data Format Register 0"
|
|
hexmask.long.byte 0x0 24.--29. 1. " WDELAY0 ,Delay in between transmissions"
|
|
bitfld.long 0x0 23. " PARPOL0 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x0 22. " PARENA0 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " WAITENA0 ,The master waits for /SPI0_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB first,LSB first"
|
|
bitfld.long 0x0 18. " DISCSTIMERS0 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 17. " POLARITY0 ,Clock polarity for data format 0" "Low-inactive,High-inactive"
|
|
bitfld.long 0x0 16. " PHASE0 ,Clock delay for data format 0" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE0[7:0] ,Prescaler for data format 0"
|
|
bitfld.long 0x0 0.--4. " CHARLEN0[4:0] ,Data word lenght for data format 0" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
line.long 0x4 "SPIFMT1,SPI0 Data Format Register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. " WDELAY1 ,Delay in between transmissions"
|
|
bitfld.long 0x4 23. " PARPOL1 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x4 22. " PARENA1 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA1 ,The master waits for /SPI0_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x4 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB first,LSB first"
|
|
bitfld.long 0x4 18. " DISCSTIMERS1 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x4 17. " POLARITY1 ,Clock polarity for data format 1" "Low-inactive,High-inactive"
|
|
bitfld.long 0x4 16. " PHASE1 ,Clock delay for data format 1" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE1[7:0] ,Prescaler for data format 1"
|
|
bitfld.long 0x4 0.--4. " CHARLEN1[4:0] ,Data word lenght for data format 1" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
line.long 0x8 "SPIFMT2,SPI0 Data Format Register 2"
|
|
hexmask.long.byte 0x8 24.--29. 1. " WDELAY2 ,Delay in between transmissions"
|
|
bitfld.long 0x8 23. " PARPOL2 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x8 22. " PARENA2 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA2 ,The master waits for /SPI0_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x8 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB first,LSB first"
|
|
bitfld.long 0x8 18. " DISCSTIMERS2 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x8 17. " POLARITY2 ,Clock polarity for data format 2" "Low-inactive,High-inactive"
|
|
bitfld.long 0x8 16. " PHASE2 ,Clock delay for data format 2" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE2[7:0] ,Prescaler for data format 2"
|
|
bitfld.long 0x8 0.--4. " CHARLEN2[4:0] ,Data word lenght for data format 2" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
line.long 0xC "SPIFMT3,SPI0 Data Format Register 3"
|
|
hexmask.long.byte 0xC 24.--29. 1. " WDELAY3 ,Delay in between transmissions"
|
|
bitfld.long 0xC 23. " PARPOL3 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0xC 22. " PARENA3 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA3 ,The master waits for /SPI0_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0xC 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB first,LSB first"
|
|
bitfld.long 0xC 18. " DISCSTIMERS3 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xC 17. " POLARITY3 ,Clock polarity for data format 3" "Low-inactive,High-inactive"
|
|
bitfld.long 0xC 16. " PHASE3 ,Clock delay for data format 3" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE3[7:0] ,Prescaler for data format 3"
|
|
bitfld.long 0xC 0.--4. " CHARLEN3[4:0] ,Data word lenght for data format 3" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x00 "INTVECT1,SPI0 Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt pending,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Error interrupt pending,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "SPI 1"
|
|
base asd:0x01e12000
|
|
width 10.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "SPIGCR0,SPI1 Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,Reset bit for the SPI1 module" "No reset,Reset"
|
|
line.long 0x04 "SPIGCR1,SPI1 Global Control Register 1"
|
|
bitfld.long 0x04 24. " ENABLE ,SPI1 enable" "Reset,Enabled"
|
|
bitfld.long 0x04 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " POWERDOWN ,SPI1 state machine enters a power-down state" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MASTER/CLKMOD ,Master/Slave Clock mode" "Slave/Input,Reserved,Reserved,Master/Output"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 "SPIINT,SPI1 Interrupt Register"
|
|
bitfld.long 0x00 24. " ENABLEHIGHZ ,/SPI1_ENA pin high-impedance enable" "Pulled high,High-impedance"
|
|
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " RXINTEN ,Receive interrupt enable" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OVRNINTEN ,Overrun interrupt enable" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on /SPI1_ENA signal time-out" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
line.long 0x04 "SPILVL,SPI1 Interrupt Level Register"
|
|
bitfld.long 0x04 9. " TXINTLVL ,Transmit interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 8. " RXINTLVL ,Receive interrupt level" "Reserved,INT1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OVRNINTLVL ,Receive overrun interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 4. " BITERRLVL ,Bit error interrupt level" "Reserved,INT1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DESYNCLVL ,Desynchronized slave interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 2. " PARERRLVL ,Parity error interrupt level" "Reserved,INT1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TIMEOUTLVL ,/SPI1_ENA signal time-out interrupt level" "Reserved,INT1"
|
|
bitfld.long 0x04 0. " DLENERRLVL ,Data length error interrupt enable level" "Reserved,INT1"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "SPIFLG,SPI1 Flag Register"
|
|
in
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "SPIPC0,SPI1 Pin Control Register 0"
|
|
bitfld.long 0x00 11. " SOMIFUN ,Slave out - master in pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 10. " SIMOFUN ,Slave in - master out pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI1 clock pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPI1 enable pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCS1FUN[7] ,SPI1 chip select pin 7 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 6. " SCS1FUN[6] ,SPI1 chip select pin 6 function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCS1FUN[5] ,SPI1 chip select pin 5 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 4. " SCS1FUN[4] ,SPI1 chip select pin 4 function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCS1FUN[3] ,SPI1 chip select pin 3 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 2. " SCS1FUN[2] ,SPI1 chip select pin 2 function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCS1FUN[1] ,SPI1 chip select pin 1 function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 0. " SCS1FUN[0] ,SPI1 chip select pin 0 function" "GPIO pin,SPI functional"
|
|
line.long 0x04 "SPIPC1,SPI1 Pin Control Register 1"
|
|
bitfld.long 0x04 11. " SOMIDIR ,SPI1_SOMI pin direction" "Input,Output"
|
|
bitfld.long 0x04 10. " SIMODIR ,SPI1_SIMO pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI1_CLK pin direction" "Input,Output"
|
|
bitfld.long 0x04 8. " ENADIR ,/SPI1_ENA pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SCS1DIR[7] ,SPI1_SCS[7] pin direction" "Input,Output"
|
|
bitfld.long 0x04 6. " SCS1DIR[6] ,SPI1_SCS[6] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCS1DIR[5] ,SPI1_SCS[5] pin direction" "Input,Output"
|
|
bitfld.long 0x04 4. " SCS1DIR[4] ,SPI1_SCS[4] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SCS1DIR[3] ,SPI1_SCS[3] pin direction" "Input,Output"
|
|
bitfld.long 0x04 2. " SCS1DIR[2] ,SPI1_SCS[2] pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SCS1DIR[1] ,SPI1_SCS[1] pin direction" "Input,Output"
|
|
bitfld.long 0x04 0. " SCS1DIR[0] ,SPI1_SCS[0] pin direction" "Input,Output"
|
|
rgroup.long 0x1c++0xf
|
|
line.long 0x00 "SPIPC2,SPI1 Pin Control Register 2"
|
|
bitfld.long 0x00 11. " SOMIDIN ,SPI1_SOMI data in" "0,1"
|
|
bitfld.long 0x00 10. " SIMODIN ,SPI1_SIMO data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,SPI1 Clock data in" "0,1"
|
|
bitfld.long 0x00 8. " ENADIN ,SPI slave 1 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCS1DIN[7] ,SPI1_SCS[7] data in" "0,1"
|
|
bitfld.long 0x00 6. " SCS1DIN[6] ,SPI1_SCS[6] data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCS1DIN[5] ,SPI1_SCS[5] data in" "0,1"
|
|
bitfld.long 0x00 4. " SCS1DIN[4] ,SPI1_SCS[4] data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCS1DIN[3] ,SPI1_SCS[3] data in" "0,1"
|
|
bitfld.long 0x00 2. " SCS1DIN[2] ,SPI1_SCS[2] data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCS1DIN[1] ,SPI1_SCS[1] data in" "0,1"
|
|
bitfld.long 0x00 0. " SCS1DIN[0] ,SPI1_SCS[0] data in" "0,1"
|
|
line.long 0x04 "SPIPC3,SPI1 Pin Control Register 3"
|
|
bitfld.long 0x04 11. " SOMIDOUT ,SPI1_SOMI data out write" "0,1"
|
|
bitfld.long 0x04 10. " SIMODOUT ,SPI1_SIMO data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDOUT ,SPI Clock data out write" "0,1"
|
|
bitfld.long 0x04 8. " ENADOUT ,SPI slave 1 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SCS1DOUT[7] ,SPI1_SCS[7] data out write" "0,1"
|
|
bitfld.long 0x04 6. " SCS1DOUT[6] ,SPI1_SCS[6] data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCS1DOUT[5] ,SPI1_SCS[5] data out write" "0,1"
|
|
bitfld.long 0x04 4. " SCS1DOUT[4] ,SPI1_SCS[4] data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SCS1DOUT[3] ,SPI1_SCS[3] data out write" "0,1"
|
|
bitfld.long 0x04 2. " SCS1DOUT[2] ,SPI1_SCS[2] data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SCS1DOUT[1] ,SPI1_SCS[1] data out write" "0,1"
|
|
bitfld.long 0x04 0. " SCS1DOUT[0] ,SPI1_SCS[0] data out write" "0,1"
|
|
line.long 0x08 "SPIPC4,SPI1 Pin Control Register 3"
|
|
bitfld.long 0x08 11. " SOMISET ,SPI1_SOMI data out set" "No effect,Set"
|
|
bitfld.long 0x08 10. " SIMOSET ,SPI1_SIMO data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CLKSET ,SPI Clock data out set" "No effect,Set"
|
|
bitfld.long 0x08 8. " ENASET ,SPI slave 1 (SPI_EN1) pin value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SCS1SET[7] ,SPI1_SCS[7] data out set" "No effect,Set"
|
|
bitfld.long 0x08 6. " SCS1SET[6] ,SPI1_SCS[6] data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SCS1SET[5] ,SPI1_SCS[5] data out set" "No effect,Set"
|
|
bitfld.long 0x08 4. " SCS1SET[4] ,SPI1_SCS[4] data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SCS1SET[3] ,SPI1_SCS[3] data out set" "No effect,Set"
|
|
bitfld.long 0x08 2. " SCS1SET[2] ,SPI1_SCS[2] data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SCS1SET[1] ,SPI1_SCS[1] data out set" "No effect,Set"
|
|
bitfld.long 0x08 0. " SCS1SET[0] ,SPI1_SCS[0] data out set" "No effect,Set"
|
|
line.long 0x0c "SPIPC5,SPI1 Pin Control Register 5"
|
|
bitfld.long 0x0c 11. " SOMICLR ,SPI1_SOMI data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " SIMOCLR ,SPI1_SIMO data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CLKCLR ,SPI Clock data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " ENACLR ,SPI slave 1 (SPI_EN1) pin value" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SCS1CLR[7] ,SPI1_SCS[7] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 6. " SCS1CLR[6] ,SPI1_SCS[6] data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SCS1CLR[5] ,SPI1_SCS[5] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 4. " SCS1CLR[4] ,SPI1_SCS[4] data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SCS1CLR[3] ,SPI1_SCS[3] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 2. " SCS1CLR[2] ,SPI1_SCS[2] data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SCS1CLR[1] ,SPI1_SCS[1] data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 0. " SCS1CLR[0] ,SPI1_SCS[0] data out clear" "No effect,Cleared"
|
|
else
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "SPIPC0,SPI1 Pin Control Register 0"
|
|
bitfld.long 0x00 11. " SOMIFUN ,Slave out - master in pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 10. " SIMOFUN ,Slave in - master out pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI1 clock pin function" "GPIO pin,SPI functional"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPI1 enable pin function" "GPIO pin,SPI functional"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCS1FUN[0] ,SPI1 chip select pin 0 function" "GPIO pin,SPI functional"
|
|
line.long 0x04 "SPIPC1,SPI1 Pin Control Register 1"
|
|
bitfld.long 0x04 11. " SOMIDIR ,SPI1_SOMI pin direction" "Input,Output"
|
|
bitfld.long 0x04 10. " SIMODIR ,SPI1_SIMO pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI1_CLK pin direction" "Input,Output"
|
|
bitfld.long 0x04 8. " ENADIR ,/SPI1_ENA pin direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SCS1DIR[0] ,SPI1_SCS[0] pin direction" "Input,Output"
|
|
rgroup.long 0x1c++0xf
|
|
line.long 0x00 "SPIPC2,SPI1 Pin Control Register 2"
|
|
bitfld.long 0x00 11. " SOMIDIN ,SPI1_SOMI data in" "0,1"
|
|
bitfld.long 0x00 10. " SIMODIN ,SPI1_SIMO data in" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKDIN ,SPI1 Clock data in" "0,1"
|
|
bitfld.long 0x00 8. " ENADIN ,SPI slave 1 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCS1DIN[0] ,SPI1_SCS[0] data in" "0,1"
|
|
line.long 0x04 "SPIPC3,SPI1 Pin Control Register 3"
|
|
bitfld.long 0x04 11. " SOMIDOUT ,SPI1_SOMI data out write" "0,1"
|
|
bitfld.long 0x04 10. " SIMODOUT ,SPI1_SIMO data out write" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CLKDOUT ,SPI1 Clock data out write" "0,1"
|
|
bitfld.long 0x04 8. " ENADOUT ,SPI slave 1 (SPI_EN1) pin value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SCS1DOUT[0] ,SPI1_SCS[0] data out write" "0,1"
|
|
line.long 0x08 "SPIPC4,SPI1 Pin Control Register 3"
|
|
bitfld.long 0x08 11. " SOMISET ,SPI1_SOMI data out set" "No effect,Set"
|
|
bitfld.long 0x08 10. " SIMOSET ,SPI1_SIMO data out set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CLKSET ,SPI1 Clock data out set" "No effect,Set"
|
|
bitfld.long 0x08 8. " ENASET ,SPI slave 1 (SPI_EN1) pin value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SCS1SET[0] ,SPI1_SCS[0] data out set" "No effect,Set"
|
|
line.long 0x0c "SPIPC5,SPI1 Pin Control Register 5"
|
|
bitfld.long 0x0c 11. " SOMICLR ,SPI1_SOMI data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " SIMOCLR ,SPI1_SIMO data out Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CLKCLR ,SPI1 Clock data out Clear" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " ENACLR ,SPI slave 1 (SPI_EN1) pin value" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " SCS1CLR[0] ,SPI1_SCS[0] data out clear" "No effect,Cleared"
|
|
endif
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "SPIDAT0,SPI1 Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI1 transmit data"
|
|
line.long 0x04 "SPIDAT1,SPI1 Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Deactivated,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
textline " "
|
|
bitfld.long 0x04 23. " CSNR[7] ,State of the /SPI1_SCS[7] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 22. " CSNR[6] ,State of the /SPI1_SCS[6] pin during a master data transfer" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " CSNR[5] ,State of the /SPI1_SCS[5] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 20. " CSNR[4] ,State of the /SPI1_SCS[4] pin during a master data transfer" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CSNR[3] ,State of the /SPI1_SCS[3] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 18. " CSNR[2] ,State of the /SPI1_SCS[2] pin during a master data transfer" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " CSNR[1] ,State of the /SPI1_SCS[1] pin during a master data transfer" "Low,High"
|
|
bitfld.long 0x04 16. " CSNR[0] ,State of the /SPI1_SCS[0] pin during a master data transfer" "Low,High"
|
|
else
|
|
bitfld.long 0x04 16. " CSNR[0] ,State of the /SPI1_SCS[0] pin during a master data transfer" "Low,High"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "SPIBUF,SPI1 Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "SPIEMU,SPI1 Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI1 receive data"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "SPIDELAY,SPI1 Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active-to-transmit-start-delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished-to-SPI1_ENA-pin-inactive-time-out"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active-to-SPI1_ENA-signal-active-time-out"
|
|
group.long 0x4c++0x3
|
|
line.long 0x00 "SPIDEF,SPI1 Default Chip Select Register"
|
|
sif (cpu()=="OMAP-L138"||cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 7. " CSDEF[7] ,State of the the /SPI1_SCS[7] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 6. " CSDEF[6] ,State of the the /SPI1_SCS[6] pin when no transmissions are performed" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSDEF[5] ,State of the the /SPI1_SCS[5] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 4. " CSDEF[4] ,State of the the /SPI1_SCS[4] pin when no transmissions are performed" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSDEF[3] ,State of the the /SPI1_SCS[3] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 2. " CSDEF[2] ,State of the the /SPI1_SCS[2] pin when no transmissions are performed" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSDEF[1] ,State of the the /SPI1_SCS[1] pin when no transmissions are performed" "Low,High"
|
|
bitfld.long 0x00 0. " CSDEF[0] ,State of the the /SPI1_SCS[0] pin when no transmissions are performed" "Low,High"
|
|
else
|
|
bitfld.long 0x00 0. " CSDEF[0] ,State of the the /SPI1_SCS[0] pin when no transmissions are performed" "Low,High"
|
|
endif
|
|
width 10.
|
|
group.long 0x50++0xf
|
|
line.long 0x0 "SPIFMT0,SPI1 Data Format Register 0"
|
|
hexmask.long.byte 0x0 24.--29. 1. " WDELAY0 ,Delay in between transmissions"
|
|
bitfld.long 0x0 23. " PARPOL0 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x0 22. " PARENA0 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " WAITENA0 ,The master waits for /SPI1_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB first,LSB first"
|
|
bitfld.long 0x0 18. " DISCSTIMERS0 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 17. " POLARITY0 ,Clock polarity for data format 0" "Low-inactive,High-inactive"
|
|
bitfld.long 0x0 16. " PHASE0 ,Clock delay for data format 0" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE0[7:0] ,Prescaler for data format 0"
|
|
bitfld.long 0x0 0.--4. " CHARLEN0[4:0] ,Data word lenght for data format 0" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
line.long 0x4 "SPIFMT1,SPI1 Data Format Register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. " WDELAY1 ,Delay in between transmissions"
|
|
bitfld.long 0x4 23. " PARPOL1 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x4 22. " PARENA1 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA1 ,The master waits for /SPI1_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x4 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB first,LSB first"
|
|
bitfld.long 0x4 18. " DISCSTIMERS1 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x4 17. " POLARITY1 ,Clock polarity for data format 1" "Low-inactive,High-inactive"
|
|
bitfld.long 0x4 16. " PHASE1 ,Clock delay for data format 1" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE1[7:0] ,Prescaler for data format 1"
|
|
bitfld.long 0x4 0.--4. " CHARLEN1[4:0] ,Data word lenght for data format 1" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
line.long 0x8 "SPIFMT2,SPI1 Data Format Register 2"
|
|
hexmask.long.byte 0x8 24.--29. 1. " WDELAY2 ,Delay in between transmissions"
|
|
bitfld.long 0x8 23. " PARPOL2 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x8 22. " PARENA2 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA2 ,The master waits for /SPI1_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x8 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB first,LSB first"
|
|
bitfld.long 0x8 18. " DISCSTIMERS2 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x8 17. " POLARITY2 ,Clock polarity for data format 2" "Low-inactive,High-inactive"
|
|
bitfld.long 0x8 16. " PHASE2 ,Clock delay for data format 2" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE2[7:0] ,Prescaler for data format 2"
|
|
bitfld.long 0x8 0.--4. " CHARLEN2[4:0] ,Data word lenght for data format 2" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
line.long 0xC "SPIFMT3,SPI1 Data Format Register 3"
|
|
hexmask.long.byte 0xC 24.--29. 1. " WDELAY3 ,Delay in between transmissions"
|
|
bitfld.long 0xC 23. " PARPOL3 ,Parity polarity" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0xC 22. " PARENA3 ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA3 ,The master waits for /SPI1_ENA signal from slave" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0xC 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB first,LSB first"
|
|
bitfld.long 0xC 18. " DISCSTIMERS3 ,Disable chip select timers for this format register" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xC 17. " POLARITY3 ,Clock polarity for data format 3" "Low-inactive,High-inactive"
|
|
bitfld.long 0xC 16. " PHASE3 ,Clock delay for data format 3" "No delay,Half cycle"
|
|
textline " "
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE3[7:0] ,Prescaler for data format 3"
|
|
bitfld.long 0xC 0.--4. " CHARLEN3[4:0] ,Data word lenght for data format 3" "Not detected,Not detected,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected,Not detected"
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x00 "INTVECT1,SPI1 Interrupt Vector Register 1"
|
|
bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt pending,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Error interrupt pending,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "eCAP (Enhanced Capture Module)"
|
|
tree "eCAP 0"
|
|
base asd:0x01f06000
|
|
width 8.
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter Register"
|
|
line.long 0x4 "CTRPHS,Counter Phase Control Register"
|
|
line.long 0x8 "CAP1,Capture 1 Register"
|
|
line.long 0xc "CAP2,Capture 2 Register"
|
|
line.long 0x10 "CAP3,Capture 3 Register"
|
|
line.long 0x14 "CAP4,Capture 4 Register"
|
|
group.word 0x28++0x5
|
|
line.word 0x0 "ECCTL1,ECAP Control Register"
|
|
bitfld.word 0x0 14.--15. " FREE/SOFT ,Emulation Control" "Stopped,Run Until = 0,Run Free,Run Free"
|
|
bitfld.word 0x0 9.--13. " PRESCALE ,Event Filter prescale select" "Divide by 1,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,Divide by 12,Divide by 14,Divide by 16,Divide by 18,Divide by 20,Divide by 22,Divide by 24,Divide by 26,Divide by 28,Divide by 30,Divide by 32,Divide by 34,Divide by 36,Divide by 38,Divide by 40,Divide by 42,Divide by 44,Divide by 46,Divide by 48,Divide by 50,Divide by 52,Divide by 54,Divide by 56,Divide by 58,Divide by 60,Divide by 62"
|
|
textline " "
|
|
bitfld.word 0x0 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4" "No reset,Reset"
|
|
bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3" "No reset,Reset"
|
|
bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2" "No reset,Reset"
|
|
bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1" "No reset,Reset"
|
|
bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge"
|
|
line.word 0x2 "ECCTL2,ECAP Control Register"
|
|
bitfld.word 0x2 10. " APWMPOL ,APWM output polarity select" "High,Low"
|
|
bitfld.word 0x2 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
textline " "
|
|
bitfld.word 0x2 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "Not forced,Forced"
|
|
bitfld.word 0x2 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-In,CTR=PRD,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x2 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled"
|
|
bitfld.word 0x2 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x2 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,Re-armed"
|
|
bitfld.word 0x2 1.--2. " STOP_WRAP ,Stop value for One-Shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
textline " "
|
|
bitfld.word 0x2 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot"
|
|
line.word 0x4 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x4 7. " CTR=CMP ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 6. " CTR=PRD ,Counter Equal Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 5. " CTROVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x2e++0x1
|
|
line.word 0x0 "ECFLG,ECAP Interrupt Flag Register"
|
|
setclrfld.word 0x0 7. 0x4 7. 0x2 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not equal,Equal"
|
|
setclrfld.word 0x0 6. 0x4 6. 0x2 6. " CTR=PRD_set/clr ,Counter Equal Period Status Flag" "Not equal,Equal"
|
|
textline " "
|
|
setclrfld.word 0x0 5. 0x4 5. 0x2 5. " CTROVF_set/clr ,Counter Overflow Status Flag" "No overflow,Overflow"
|
|
setclrfld.word 0x0 4. 0x4 4. 0x2 4. " CEVT4_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.word 0x0 3. 0x4 3. 0x2 3. " CETV3_set/clr ,Capture Event 3 Status Flag" "Not occurred,Occurred"
|
|
setclrfld.word 0x0 2. 0x4 2. 0x2 2. " CETV2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.word 0x0 1. 0x4 1. 0x2 1. " CETV1_set/clr ,Capture Event 1 Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "ECCLR,ECAP Interrupt Clear Register"
|
|
bitfld.word 0x0 0. " INT_clr ,Global Interrupt Clear Flag" "No effect,Cleared"
|
|
rgroup.long 0x5c++0x03
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "eCAP 1"
|
|
base asd:0x01f07000
|
|
width 8.
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter Register"
|
|
line.long 0x4 "CTRPHS,Counter Phase Control Register"
|
|
line.long 0x8 "CAP1,Capture 1 Register"
|
|
line.long 0xc "CAP2,Capture 2 Register"
|
|
line.long 0x10 "CAP3,Capture 3 Register"
|
|
line.long 0x14 "CAP4,Capture 4 Register"
|
|
group.word 0x28++0x5
|
|
line.word 0x0 "ECCTL1,ECAP Control Register"
|
|
bitfld.word 0x0 14.--15. " FREE/SOFT ,Emulation Control" "Stopped,Run Until = 0,Run Free,Run Free"
|
|
bitfld.word 0x0 9.--13. " PRESCALE ,Event Filter prescale select" "Divide by 1,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,Divide by 12,Divide by 14,Divide by 16,Divide by 18,Divide by 20,Divide by 22,Divide by 24,Divide by 26,Divide by 28,Divide by 30,Divide by 32,Divide by 34,Divide by 36,Divide by 38,Divide by 40,Divide by 42,Divide by 44,Divide by 46,Divide by 48,Divide by 50,Divide by 52,Divide by 54,Divide by 56,Divide by 58,Divide by 60,Divide by 62"
|
|
textline " "
|
|
bitfld.word 0x0 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4" "No reset,Reset"
|
|
bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3" "No reset,Reset"
|
|
bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2" "No reset,Reset"
|
|
bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1" "No reset,Reset"
|
|
bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge"
|
|
line.word 0x2 "ECCTL2,ECAP Control Register"
|
|
bitfld.word 0x2 10. " APWMPOL ,APWM output polarity select" "High,Low"
|
|
bitfld.word 0x2 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
textline " "
|
|
bitfld.word 0x2 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "Not forced,Forced"
|
|
bitfld.word 0x2 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-In,CTR=PRD,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x2 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled"
|
|
bitfld.word 0x2 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x2 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,Re-armed"
|
|
bitfld.word 0x2 1.--2. " STOP_WRAP ,Stop value for One-Shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
textline " "
|
|
bitfld.word 0x2 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot"
|
|
line.word 0x4 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x4 7. " CTR=CMP ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 6. " CTR=PRD ,Counter Equal Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 5. " CTROVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x2e++0x1
|
|
line.word 0x0 "ECFLG,ECAP Interrupt Flag Register"
|
|
setclrfld.word 0x0 7. 0x4 7. 0x2 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not equal,Equal"
|
|
setclrfld.word 0x0 6. 0x4 6. 0x2 6. " CTR=PRD_set/clr ,Counter Equal Period Status Flag" "Not equal,Equal"
|
|
textline " "
|
|
setclrfld.word 0x0 5. 0x4 5. 0x2 5. " CTROVF_set/clr ,Counter Overflow Status Flag" "No overflow,Overflow"
|
|
setclrfld.word 0x0 4. 0x4 4. 0x2 4. " CEVT4_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.word 0x0 3. 0x4 3. 0x2 3. " CETV3_set/clr ,Capture Event 3 Status Flag" "Not occurred,Occurred"
|
|
setclrfld.word 0x0 2. 0x4 2. 0x2 2. " CETV2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.word 0x0 1. 0x4 1. 0x2 1. " CETV1_set/clr ,Capture Event 1 Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "ECCLR,ECAP Interrupt Clear Register"
|
|
bitfld.word 0x0 0. " INT_clr ,Global Interrupt Clear Flag" "No effect,Cleared"
|
|
rgroup.long 0x5c++0x03
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "eCAP 2"
|
|
base asd:0x01f08000
|
|
width 8.
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "TSCTR,Time-Stamp Counter Register"
|
|
line.long 0x4 "CTRPHS,Counter Phase Control Register"
|
|
line.long 0x8 "CAP1,Capture 1 Register"
|
|
line.long 0xc "CAP2,Capture 2 Register"
|
|
line.long 0x10 "CAP3,Capture 3 Register"
|
|
line.long 0x14 "CAP4,Capture 4 Register"
|
|
group.word 0x28++0x5
|
|
line.word 0x0 "ECCTL1,ECAP Control Register"
|
|
bitfld.word 0x0 14.--15. " FREE/SOFT ,Emulation Control" "Stopped,Run Until = 0,Run Free,Run Free"
|
|
bitfld.word 0x0 9.--13. " PRESCALE ,Event Filter prescale select" "Divide by 1,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,Divide by 12,Divide by 14,Divide by 16,Divide by 18,Divide by 20,Divide by 22,Divide by 24,Divide by 26,Divide by 28,Divide by 30,Divide by 32,Divide by 34,Divide by 36,Divide by 38,Divide by 40,Divide by 42,Divide by 44,Divide by 46,Divide by 48,Divide by 50,Divide by 52,Divide by 54,Divide by 56,Divide by 58,Divide by 60,Divide by 62"
|
|
textline " "
|
|
bitfld.word 0x0 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4" "No reset,Reset"
|
|
bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3" "No reset,Reset"
|
|
bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2" "No reset,Reset"
|
|
bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1" "No reset,Reset"
|
|
bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge"
|
|
line.word 0x2 "ECCTL2,ECAP Control Register"
|
|
bitfld.word 0x2 10. " APWMPOL ,APWM output polarity select" "High,Low"
|
|
bitfld.word 0x2 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
textline " "
|
|
bitfld.word 0x2 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "Not forced,Forced"
|
|
bitfld.word 0x2 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-In,CTR=PRD,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x2 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled"
|
|
bitfld.word 0x2 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x2 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,Re-armed"
|
|
bitfld.word 0x2 1.--2. " STOP_WRAP ,Stop value for One-Shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
textline " "
|
|
bitfld.word 0x2 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot"
|
|
line.word 0x4 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x4 7. " CTR=CMP ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 6. " CTR=PRD ,Counter Equal Period Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 5. " CTROVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x4 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x4 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x2e++0x1
|
|
line.word 0x0 "ECFLG,ECAP Interrupt Flag Register"
|
|
setclrfld.word 0x0 7. 0x4 7. 0x2 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not equal,Equal"
|
|
setclrfld.word 0x0 6. 0x4 6. 0x2 6. " CTR=PRD_set/clr ,Counter Equal Period Status Flag" "Not equal,Equal"
|
|
textline " "
|
|
setclrfld.word 0x0 5. 0x4 5. 0x2 5. " CTROVF_set/clr ,Counter Overflow Status Flag" "No overflow,Overflow"
|
|
setclrfld.word 0x0 4. 0x4 4. 0x2 4. " CEVT4_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.word 0x0 3. 0x4 3. 0x2 3. " CETV3_set/clr ,Capture Event 3 Status Flag" "Not occurred,Occurred"
|
|
setclrfld.word 0x0 2. 0x4 2. 0x2 2. " CETV2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.word 0x0 1. 0x4 1. 0x2 1. " CETV1_set/clr ,Capture Event 1 Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "ECCLR,ECAP Interrupt Clear Register"
|
|
bitfld.word 0x0 0. " INT_clr ,Global Interrupt Clear Flag" "No effect,Cleared"
|
|
rgroup.long 0x5c++0x03
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "eQEP (Enhanced Quadrature Encoder Pulse Module)"
|
|
tree "eQEP 0"
|
|
base asd:0x01f09000
|
|
width 0xb
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "QPOSCNT,eQEP Position Counter Register"
|
|
line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register"
|
|
line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register"
|
|
line.long 0x0c "QPOSCMP,eQEP Position-Compare Register"
|
|
rgroup.long 0x10++0x0b
|
|
line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register"
|
|
line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register"
|
|
line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register"
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "QUTMR,eQEP Unit Timer Register"
|
|
line.long 0x04 "QUPRD,eQEP Unit Period Register"
|
|
group.word 0x24++0x0d
|
|
line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register"
|
|
line.word 0x02 "QWDPRD,eQEP Watchdog Period Register"
|
|
line.word 0x04 "QDECCTL,QEP Decoder Control Register"
|
|
bitfld.word 0x04 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count"
|
|
bitfld.word 0x04 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 12. " SPSEL ,Sync output pin selection" "Index,Strobe"
|
|
textline " "
|
|
bitfld.word 0x04 11. " XCR ,External clock rate" "2 resolution: rising/falling,1 resolution: rising"
|
|
textline " "
|
|
bitfld.word 0x04 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
|
|
bitfld.word 0x04 9. " IGATE ,Index pulse gating option" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " QAP ,QEPA input polarity" "No effect,Negated"
|
|
textline " "
|
|
bitfld.word 0x04 7. " QBP ,QEPB input polarity" "No effect,Negated"
|
|
bitfld.word 0x04 6. " QIP ,QEPI input polarity" "No effect,Negated"
|
|
bitfld.word 0x04 5. " QSP ,QEPS input polarity" "No effect,Negated"
|
|
line.word 0x06 "QEPCTL,eQEP Control Register"
|
|
bitfld.word 0x06 14.--15. " FREE/SOFT ,Emulation Control (QPOSCNT/QWDTMR/QUTMR/QCTMR)" "Stopped immediately,Until period,Unaffected,Unaffected"
|
|
textline " "
|
|
bitfld.word 0x06 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
|
|
textline " "
|
|
bitfld.word 0x06 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising,Clockwise:rising/Count. Clockwise:falling"
|
|
textline " "
|
|
bitfld.word 0x06 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising,Falling"
|
|
textline " "
|
|
bitfld.word 0x06 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 6. " SEL ,Strobe event latch of position counter" "Rising,Clockwise:Rising/Count. Clockwise:falling"
|
|
textline " "
|
|
bitfld.word 0x06 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising,Falling,Software index marker"
|
|
textline " "
|
|
bitfld.word 0x06 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out"
|
|
textline " "
|
|
bitfld.word 0x06 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled"
|
|
line.word 0x08 "QCAPCTL,eQEP Capture Control Register"
|
|
bitfld.word 0x08 15. " CEN ,Enable eQEP capture" "Disabled,Enabled"
|
|
bitfld.word 0x08 4.--6. " CCPS ,eQEP capture timer clock prescaler" "SYSCLKOUT/1,SYSCLKOUT/2,SYSCLKOUT/4,SYSCLKOUT/8,SYSCLKOUT/16,SYSCLKOUT/32,SYSCLKOUT/64,SYSCLKOUT/128"
|
|
bitfld.word 0x08 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
|
|
line.word 0x0a "QPOSCTL,eQEP Position-Compare Control Register"
|
|
bitfld.word 0x0a 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
|
|
bitfld.word 0x0a 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT=0,QPOSCNT=QPOSCMP"
|
|
bitfld.word 0x0a 13. " PCPOL ,Polarity of sync output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x0a 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
|
|
hexmask.word 0x0a 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
|
|
line.word 0x0c "QEINT,eQEP Interrupt Enable Register"
|
|
bitfld.word 0x0c 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0c 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0c 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "QFLG,eQEP Interrupt Flag Register"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x34++0x09
|
|
line.word 0x00 "QCLR,eQEP Interrupt Clear Register"
|
|
bitfld.word 0x00 11. " UTO ,Clear Unit time out interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 10. " IEL ,Clear Index event latch interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 9. " SEL ,Clear Strobe event latch interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 8. " PCM ,Clear Position-compare match interrupt flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PCR ,Clear Position-compare ready interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 6. " PCO ,Clear Position counter overflow interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " PCU ,Clear Position counter underflow interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 4. " WTO ,Clear Watchdog time out interrupt flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 3. " QDC ,Clear Quadrature direction change interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 2. " PHE ,Clear Quadrature phase error interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 1. " PCE ,Clear Position counter error interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Cleared"
|
|
line.word 0x02 "QFRC,eQEP Interrupt Force Register"
|
|
bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
|
|
line.word 0x04 "QEPSTS,eQEP Status Register"
|
|
eventfld.word 0x04 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
|
|
bitfld.word 0x04 6. " FDF ,Direction on the first index marker" "Counter-clockwise rot.,Clockwise rot."
|
|
textline " "
|
|
bitfld.word 0x04 5. " QDF ,Quadrature direction flag" "Counter-clockwise rot.,Clockwise rot."
|
|
bitfld.word 0x04 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rot.,Clockwise rot."
|
|
textline " "
|
|
eventfld.word 0x04 3. " COEF ,Capture overflow error flag" "No error,Error"
|
|
eventfld.word 0x04 2. " CDEF ,Capture direction error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x04 1. " FIMF ,First index marker flag" "No error,Error"
|
|
bitfld.word 0x04 0. " PCEF ,Position counter error flag" "No error,Error"
|
|
line.word 0x06 "QCTMR,eQEP Capture Timer Register"
|
|
line.word 0x08 "QCPRD,eQEP Capture Period Register"
|
|
rgroup.word 0x3e++0x01
|
|
line.word 0x00 "QCTMRLAT,eQEP Capture Timer Latch Register"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "QCPRDLAT,eQEP Capture Period Latch Register"
|
|
rgroup.long 0x5c++0x03
|
|
line.long 0x00 "REVID,eQEP Revision ID Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "eQEP 1"
|
|
base asd:0x01f0a000
|
|
width 0xb
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "QPOSCNT,eQEP Position Counter Register"
|
|
line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register"
|
|
line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register"
|
|
line.long 0x0c "QPOSCMP,eQEP Position-Compare Register"
|
|
rgroup.long 0x10++0x0b
|
|
line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register"
|
|
line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register"
|
|
line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register"
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "QUTMR,eQEP Unit Timer Register"
|
|
line.long 0x04 "QUPRD,eQEP Unit Period Register"
|
|
group.word 0x24++0x0d
|
|
line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register"
|
|
line.word 0x02 "QWDPRD,eQEP Watchdog Period Register"
|
|
line.word 0x04 "QDECCTL,QEP Decoder Control Register"
|
|
bitfld.word 0x04 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count"
|
|
bitfld.word 0x04 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 12. " SPSEL ,Sync output pin selection" "Index,Strobe"
|
|
textline " "
|
|
bitfld.word 0x04 11. " XCR ,External clock rate" "2 resolution: rising/falling,1 resolution: rising"
|
|
textline " "
|
|
bitfld.word 0x04 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
|
|
bitfld.word 0x04 9. " IGATE ,Index pulse gating option" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " QAP ,QEPA input polarity" "No effect,Negated"
|
|
textline " "
|
|
bitfld.word 0x04 7. " QBP ,QEPB input polarity" "No effect,Negated"
|
|
bitfld.word 0x04 6. " QIP ,QEPI input polarity" "No effect,Negated"
|
|
bitfld.word 0x04 5. " QSP ,QEPS input polarity" "No effect,Negated"
|
|
line.word 0x06 "QEPCTL,eQEP Control Register"
|
|
bitfld.word 0x06 14.--15. " FREE/SOFT ,Emulation Control (QPOSCNT/QWDTMR/QUTMR/QCTMR)" "Stopped immediately,Until period,Unaffected,Unaffected"
|
|
textline " "
|
|
bitfld.word 0x06 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
|
|
textline " "
|
|
bitfld.word 0x06 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising,Clockwise:rising/Count. Clockwise:falling"
|
|
textline " "
|
|
bitfld.word 0x06 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising,Falling"
|
|
textline " "
|
|
bitfld.word 0x06 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 6. " SEL ,Strobe event latch of position counter" "Rising,Clockwise:Rising/Count. Clockwise:falling"
|
|
textline " "
|
|
bitfld.word 0x06 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising,Falling,Software index marker"
|
|
textline " "
|
|
bitfld.word 0x06 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out"
|
|
textline " "
|
|
bitfld.word 0x06 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x06 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled"
|
|
line.word 0x08 "QCAPCTL,eQEP Capture Control Register"
|
|
bitfld.word 0x08 15. " CEN ,Enable eQEP capture" "Disabled,Enabled"
|
|
bitfld.word 0x08 4.--6. " CCPS ,eQEP capture timer clock prescaler" "SYSCLKOUT/1,SYSCLKOUT/2,SYSCLKOUT/4,SYSCLKOUT/8,SYSCLKOUT/16,SYSCLKOUT/32,SYSCLKOUT/64,SYSCLKOUT/128"
|
|
bitfld.word 0x08 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
|
|
line.word 0x0a "QPOSCTL,eQEP Position-Compare Control Register"
|
|
bitfld.word 0x0a 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
|
|
bitfld.word 0x0a 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT=0,QPOSCNT=QPOSCMP"
|
|
bitfld.word 0x0a 13. " PCPOL ,Polarity of sync output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x0a 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
|
|
hexmask.word 0x0a 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
|
|
line.word 0x0c "QEINT,eQEP Interrupt Enable Register"
|
|
bitfld.word 0x0c 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0c 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0c 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x0c 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "QFLG,eQEP Interrupt Flag Register"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x34++0x09
|
|
line.word 0x00 "QCLR,eQEP Interrupt Clear Register"
|
|
bitfld.word 0x00 11. " UTO ,Clear Unit time out interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 10. " IEL ,Clear Index event latch interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 9. " SEL ,Clear Strobe event latch interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 8. " PCM ,Clear Position-compare match interrupt flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PCR ,Clear Position-compare ready interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 6. " PCO ,Clear Position counter overflow interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " PCU ,Clear Position counter underflow interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 4. " WTO ,Clear Watchdog time out interrupt flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 3. " QDC ,Clear Quadrature direction change interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 2. " PHE ,Clear Quadrature phase error interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 1. " PCE ,Clear Position counter error interrupt flag" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Cleared"
|
|
line.word 0x02 "QFRC,eQEP Interrupt Force Register"
|
|
bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
|
|
line.word 0x04 "QEPSTS,eQEP Status Register"
|
|
eventfld.word 0x04 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
|
|
bitfld.word 0x04 6. " FDF ,Direction on the first index marker" "Counter-clockwise rot.,Clockwise rot."
|
|
textline " "
|
|
bitfld.word 0x04 5. " QDF ,Quadrature direction flag" "Counter-clockwise rot.,Clockwise rot."
|
|
bitfld.word 0x04 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rot.,Clockwise rot."
|
|
textline " "
|
|
eventfld.word 0x04 3. " COEF ,Capture overflow error flag" "No error,Error"
|
|
eventfld.word 0x04 2. " CDEF ,Capture direction error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x04 1. " FIMF ,First index marker flag" "No error,Error"
|
|
bitfld.word 0x04 0. " PCEF ,Position counter error flag" "No error,Error"
|
|
line.word 0x06 "QCTMR,eQEP Capture Timer Register"
|
|
line.word 0x08 "QCPRD,eQEP Capture Period Register"
|
|
rgroup.word 0x3e++0x01
|
|
line.word 0x00 "QCTMRLAT,eQEP Capture Timer Latch Register"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "QCPRDLAT,eQEP Capture Period Latch Register"
|
|
rgroup.long 0x5c++0x03
|
|
line.long 0x00 "REVID,eQEP Revision ID Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "eHRPWM (Enhanced High-Resolution Pulse-Width Modulator)"
|
|
tree "eHRPWM 0"
|
|
base asd:0x01f00000
|
|
width 7.
|
|
group.word 0x00++0x03 "Time-Base Submodule Registers"
|
|
line.word 0x00 "TBCTL,Time-Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode" "Stop after next time-base count. incr/decr.,Stop when count. completes whole cycle,Free run,Free run"
|
|
textline " "
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction" "Count down,Count up"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disable EPWMxSYNCO"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "TBCNT=0,Immediately"
|
|
textline " "
|
|
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
|
|
line.word 0x02 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status" "Not reached,Reached"
|
|
eventfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status" "Count down,Count up"
|
|
group.word 0x06++0x05
|
|
line.word 0x00 "TBPHS,Time-Base Phase Register"
|
|
line.word 0x02 "TBCNT,Time-Base Counter Register"
|
|
line.word 0x04 "TBPRD,Time-Base Period Register"
|
|
width 8.
|
|
group.word 0x0e++0x01 "Counter-Compare Submodule Registers"
|
|
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
|
|
bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full"
|
|
bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow,Immediate"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow,Immediate"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze"
|
|
group.word 0x12++0x03
|
|
line.word 0x00 "CMPA,Counter-Compare A Register"
|
|
line.word 0x02 "CMPB,Counter-Compare B Register"
|
|
width 9.
|
|
group.word 0x16++0x07 "Action-Qualifier Submodule Registers"
|
|
line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register"
|
|
bitfld.word 0x02 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register"
|
|
bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "0,Period,0/Period,Immediately"
|
|
bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
|
|
bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register"
|
|
bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Disabled,Low,High,Disabled"
|
|
bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Disabled,Low,High,Disabled"
|
|
width 7.
|
|
group.word 0x1e++0x05 "Dead-Band Generator Submodule Registers"
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control (Falling-edge/rising-edge)" "EPWMxA/EPWMxA,EPWMxA/EPWMxB,EPWMxB/EPWMxA,EPWMxB/EPWMxB"
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control (Falling-edge/rising-edge)" "Disabled/Disabled,Enabled/Disabled,Disabled/Enabled,Enabled/Enabled"
|
|
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register"
|
|
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
|
|
line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register"
|
|
hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count"
|
|
group.word 0x3c++0x01 "PWM-Chopper Submodule Register"
|
|
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1*SYSCLKOUT/8,2*SYSCLKOUT/8,3*SYSCLKOUT/8,4*SYSCLKOUT/8,5*SYSCLKOUT/8,6*SYSCLKOUT/8,7*SYSCLKOUT/8,8*SYSCLKOUT/8,9*SYSCLKOUT/8,10*SYSCLKOUT/8,11*SYSCLKOUT/8,12*SYSCLKOUT/8,13*SYSCLKOUT/8,14*SYSCLKOUT/8,15*SYSCLKOUT/8,16*SYSCLKOUT/8"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
|
|
width 8.
|
|
group.word 0x24++0x01 "Trip-Zone Submodule Registers"
|
|
line.word 0x00 "TZSEL,Trip-Zone Select Register"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-Shot (OSHT) trip-zone 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone 1 enable/disable" "Disabled,Enabled"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "TZCTL,Trip-Zone Control Register"
|
|
bitfld.word 0x00 2.--3. " TZB ,Action taken on output EPWMxB" "Tri-state,High,Low,No action"
|
|
bitfld.word 0x00 0.--1. " TZA ,Action taken on output EPWMxA" "Tri-state,High,Low,No action"
|
|
line.word 0x02 "TZEINT,Trip-Zone Enable Interrupt Register"
|
|
bitfld.word 0x02 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x2e++0x03
|
|
line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
|
bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Cleared"
|
|
bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Cleared"
|
|
line.word 0x02 "TZFRC,Trip-Zone Force Register"
|
|
bitfld.word 0x02 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced"
|
|
bitfld.word 0x02 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced"
|
|
width 9.
|
|
group.word 0x32++0x03 "Event-Trigger Submodule Registers"
|
|
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
|
|
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,TBCNT=0,TBCNT=TBPRD,Reserved,TBCNT=CMPA when incr.,TBCNT=CMPA when decr.,TBCNT=CMPB when incr.,TBCNT=CMPB when decr."
|
|
line.word 0x02 "ETPS,Event-Trigger Prescale Register"
|
|
bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3"
|
|
bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event"
|
|
rgroup.word 0x36++0x05
|
|
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
|
|
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "No interrupt,Interrupt"
|
|
line.word 0x02 "ETCLR,Event-Trigger Clear Register"
|
|
bitfld.word 0x02 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear" "No effect,Cleared"
|
|
line.word 0x04 "ETFRC,Event-Trigger Force Register"
|
|
bitfld.word 0x04 0. " INT ,INT Force" "No effect,Interrupt"
|
|
group.word 0x04++0x01 "High-Resolution PWM Submodule Registers"
|
|
line.word 0x00 "TBPHSHR,Time-Base Phase High-Resolution Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CMPAHR,Counter-Compare A High-Resolution Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control"
|
|
group.word 0x1020++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 3. " HRLOAD ,Shadow mode" "CTR=0,CTR=PRD"
|
|
bitfld.word 0x00 2. " CTLMODE ,Control Mode" "CMPAHR(8),TBPHSHR(8)"
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode" "Disabled,Rising,Falling,Both"
|
|
width 0x0b
|
|
tree.end
|
|
tree "eHRPWM 1"
|
|
base asd:0x01f02000
|
|
width 7.
|
|
group.word 0x00++0x03 "Time-Base Submodule Registers"
|
|
line.word 0x00 "TBCTL,Time-Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode" "Stop after next time-base count. incr/decr.,Stop when count. completes whole cycle,Free run,Free run"
|
|
textline " "
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction" "Count down,Count up"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disable EPWMxSYNCO"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "TBCNT=0,Immediately"
|
|
textline " "
|
|
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
|
|
line.word 0x02 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status" "Not reached,Reached"
|
|
eventfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status" "Count down,Count up"
|
|
group.word 0x06++0x05
|
|
line.word 0x00 "TBPHS,Time-Base Phase Register"
|
|
line.word 0x02 "TBCNT,Time-Base Counter Register"
|
|
line.word 0x04 "TBPRD,Time-Base Period Register"
|
|
width 8.
|
|
group.word 0x0e++0x01 "Counter-Compare Submodule Registers"
|
|
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
|
|
bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full"
|
|
bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow,Immediate"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow,Immediate"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze"
|
|
group.word 0x12++0x03
|
|
line.word 0x00 "CMPA,Counter-Compare A Register"
|
|
line.word 0x02 "CMPB,Counter-Compare B Register"
|
|
width 9.
|
|
group.word 0x16++0x07 "Action-Qualifier Submodule Registers"
|
|
line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register"
|
|
bitfld.word 0x02 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register"
|
|
bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "0,Period,0/Period,Immediately"
|
|
bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
|
|
bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register"
|
|
bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Disabled,Low,High,Disabled"
|
|
bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Disabled,Low,High,Disabled"
|
|
width 7.
|
|
group.word 0x1e++0x05 "Dead-Band Generator Submodule Registers"
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control (Falling-edge/rising-edge)" "EPWMxA/EPWMxA,EPWMxA/EPWMxB,EPWMxB/EPWMxA,EPWMxB/EPWMxB"
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control (Falling-edge/rising-edge)" "Disabled/Disabled,Enabled/Disabled,Disabled/Enabled,Enabled/Enabled"
|
|
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register"
|
|
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
|
|
line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register"
|
|
hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count"
|
|
group.word 0x3c++0x01 "PWM-Chopper Submodule Register"
|
|
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1*SYSCLKOUT/8,2*SYSCLKOUT/8,3*SYSCLKOUT/8,4*SYSCLKOUT/8,5*SYSCLKOUT/8,6*SYSCLKOUT/8,7*SYSCLKOUT/8,8*SYSCLKOUT/8,9*SYSCLKOUT/8,10*SYSCLKOUT/8,11*SYSCLKOUT/8,12*SYSCLKOUT/8,13*SYSCLKOUT/8,14*SYSCLKOUT/8,15*SYSCLKOUT/8,16*SYSCLKOUT/8"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
|
|
width 8.
|
|
group.word 0x24++0x01 "Trip-Zone Submodule Registers"
|
|
line.word 0x00 "TZSEL,Trip-Zone Select Register"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-Shot (OSHT) trip-zone 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone 1 enable/disable" "Disabled,Enabled"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "TZCTL,Trip-Zone Control Register"
|
|
bitfld.word 0x00 2.--3. " TZB ,Action taken on output EPWMxB" "Tri-state,High,Low,No action"
|
|
bitfld.word 0x00 0.--1. " TZA ,Action taken on output EPWMxA" "Tri-state,High,Low,No action"
|
|
line.word 0x02 "TZEINT,Trip-Zone Enable Interrupt Register"
|
|
bitfld.word 0x02 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x2e++0x03
|
|
line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
|
bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Cleared"
|
|
bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Cleared"
|
|
line.word 0x02 "TZFRC,Trip-Zone Force Register"
|
|
bitfld.word 0x02 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced"
|
|
bitfld.word 0x02 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced"
|
|
width 9.
|
|
group.word 0x32++0x03 "Event-Trigger Submodule Registers"
|
|
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
|
|
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,TBCNT=0,TBCNT=TBPRD,Reserved,TBCNT=CMPA when incr.,TBCNT=CMPA when decr.,TBCNT=CMPB when incr.,TBCNT=CMPB when decr."
|
|
line.word 0x02 "ETPS,Event-Trigger Prescale Register"
|
|
bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3"
|
|
bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event"
|
|
rgroup.word 0x36++0x05
|
|
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
|
|
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "No interrupt,Interrupt"
|
|
line.word 0x02 "ETCLR,Event-Trigger Clear Register"
|
|
bitfld.word 0x02 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear" "No effect,Cleared"
|
|
line.word 0x04 "ETFRC,Event-Trigger Force Register"
|
|
bitfld.word 0x04 0. " INT ,INT Force" "No effect,Interrupt"
|
|
group.word 0x04++0x01 "High-Resolution PWM Submodule Registers"
|
|
line.word 0x00 "TBPHSHR,Time-Base Phase High-Resolution Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CMPAHR,Counter-Compare A High-Resolution Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control"
|
|
group.word 0x1020++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 3. " HRLOAD ,Shadow mode" "CTR=0,CTR=PRD"
|
|
bitfld.word 0x00 2. " CTLMODE ,Control Mode" "CMPAHR(8),TBPHSHR(8)"
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode" "Disabled,Rising,Falling,Both"
|
|
width 0x0b
|
|
tree.end
|
|
tree "eHRPWM 2"
|
|
base asd:0x01f04000
|
|
width 7.
|
|
group.word 0x00++0x03 "Time-Base Submodule Registers"
|
|
line.word 0x00 "TBCTL,Time-Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode" "Stop after next time-base count. incr/decr.,Stop when count. completes whole cycle,Free run,Free run"
|
|
textline " "
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction" "Count down,Count up"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disable EPWMxSYNCO"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "TBCNT=0,Immediately"
|
|
textline " "
|
|
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
|
|
line.word 0x02 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status" "Not reached,Reached"
|
|
eventfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status" "Count down,Count up"
|
|
group.word 0x06++0x05
|
|
line.word 0x00 "TBPHS,Time-Base Phase Register"
|
|
line.word 0x02 "TBCNT,Time-Base Counter Register"
|
|
line.word 0x04 "TBPRD,Time-Base Period Register"
|
|
width 8.
|
|
group.word 0x0e++0x01 "Counter-Compare Submodule Registers"
|
|
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
|
|
bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full"
|
|
bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow,Immediate"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow,Immediate"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze"
|
|
group.word 0x12++0x03
|
|
line.word 0x00 "CMPA,Counter-Compare A Register"
|
|
line.word 0x02 "CMPB,Counter-Compare B Register"
|
|
width 9.
|
|
group.word 0x16++0x07 "Action-Qualifier Submodule Registers"
|
|
line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register"
|
|
bitfld.word 0x02 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled"
|
|
textline " "
|
|
bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register"
|
|
bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "0,Period,0/Period,Immediately"
|
|
bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
|
|
bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggled"
|
|
bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggled"
|
|
line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register"
|
|
bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Disabled,Low,High,Disabled"
|
|
bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Disabled,Low,High,Disabled"
|
|
width 7.
|
|
group.word 0x1e++0x05 "Dead-Band Generator Submodule Registers"
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control (Falling-edge/rising-edge)" "EPWMxA/EPWMxA,EPWMxA/EPWMxB,EPWMxB/EPWMxA,EPWMxB/EPWMxB"
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control (Falling-edge/rising-edge)" "Disabled/Disabled,Enabled/Disabled,Disabled/Enabled,Enabled/Enabled"
|
|
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register"
|
|
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
|
|
line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register"
|
|
hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count"
|
|
group.word 0x3c++0x01 "PWM-Chopper Submodule Register"
|
|
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1*SYSCLKOUT/8,2*SYSCLKOUT/8,3*SYSCLKOUT/8,4*SYSCLKOUT/8,5*SYSCLKOUT/8,6*SYSCLKOUT/8,7*SYSCLKOUT/8,8*SYSCLKOUT/8,9*SYSCLKOUT/8,10*SYSCLKOUT/8,11*SYSCLKOUT/8,12*SYSCLKOUT/8,13*SYSCLKOUT/8,14*SYSCLKOUT/8,15*SYSCLKOUT/8,16*SYSCLKOUT/8"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
|
|
width 8.
|
|
group.word 0x24++0x01 "Trip-Zone Submodule Registers"
|
|
line.word 0x00 "TZSEL,Trip-Zone Select Register"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-Shot (OSHT) trip-zone 1 enable/disable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone 1 enable/disable" "Disabled,Enabled"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "TZCTL,Trip-Zone Control Register"
|
|
bitfld.word 0x00 2.--3. " TZB ,Action taken on output EPWMxB" "Tri-state,High,Low,No action"
|
|
bitfld.word 0x00 0.--1. " TZA ,Action taken on output EPWMxA" "Tri-state,High,Low,No action"
|
|
line.word 0x02 "TZEINT,Trip-Zone Enable Interrupt Register"
|
|
bitfld.word 0x02 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.word 0x2c++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x2e++0x03
|
|
line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
|
bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Cleared"
|
|
bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Cleared"
|
|
line.word 0x02 "TZFRC,Trip-Zone Force Register"
|
|
bitfld.word 0x02 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced"
|
|
bitfld.word 0x02 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced"
|
|
width 9.
|
|
group.word 0x32++0x03 "Event-Trigger Submodule Registers"
|
|
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
|
|
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,TBCNT=0,TBCNT=TBPRD,Reserved,TBCNT=CMPA when incr.,TBCNT=CMPA when decr.,TBCNT=CMPB when incr.,TBCNT=CMPB when decr."
|
|
line.word 0x02 "ETPS,Event-Trigger Prescale Register"
|
|
bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3"
|
|
bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event"
|
|
rgroup.word 0x36++0x05
|
|
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
|
|
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "No interrupt,Interrupt"
|
|
line.word 0x02 "ETCLR,Event-Trigger Clear Register"
|
|
bitfld.word 0x02 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear" "No effect,Cleared"
|
|
line.word 0x04 "ETFRC,Event-Trigger Force Register"
|
|
bitfld.word 0x04 0. " INT ,INT Force" "No effect,Interrupt"
|
|
group.word 0x04++0x01 "High-Resolution PWM Submodule Registers"
|
|
line.word 0x00 "TBPHSHR,Time-Base Phase High-Resolution Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CMPAHR,Counter-Compare A High-Resolution Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control"
|
|
group.word 0x1020++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 3. " HRLOAD ,Shadow mode" "CTR=0,CTR=PRD"
|
|
bitfld.word 0x00 2. " CTLMODE ,Control Mode" "CMPAHR(8),TBPHSHR(8)"
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode" "Disabled,Rising,Falling,Both"
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree "LCDC (LCD Controller)"
|
|
base asd:0x01e13000
|
|
width 9.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "REVID,LCD Revision Identification Register"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "LCD_CTRL,LCD Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divisor"
|
|
bitfld.long 0x00 0. " MODESEL ,LCD mode select" "LIDD,Raster"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "LCD_STAT,LCD Status Register"
|
|
bitfld.long 0x00 9. " EOF1 ,End of frame 1" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " EOF0 ,End of frame 0" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " PL ,Loaded palette" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FUF ,FIFO underflow status" "No underflow,Underflow"
|
|
bitfld.long 0x00 3. " ABC ,AC bias count status" "Not decremented,Decremented"
|
|
bitfld.long 0x00 2. " SYNC ,Sync lost" "Normal,Lost"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DONE ,Raster or LIDD frame done" "Enabled,Disabled"
|
|
width 15.
|
|
group.long 0x0c++0x3 "LIDD (LCD Interface Display Driver)"
|
|
line.long 0x00 "LIDD_CTRL,LCD LIDD Control Register"
|
|
bitfld.long 0x00 10. " DONE_INT_EN ,LIDD frame done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DMA_CS0_CS1 ,CS0/CS1 select for LIDD DMA writes" "CS0,CS1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LIDD_DMA_EN ,LIDD DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS1_E1_POL ,Chip select 1/enable 1 (secondary) polarity control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CS0_E0_POL ,Chip select 0/enable 0 (primary) polarity control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 5. " WS_DIR_POL ,Write strobe/direction polarity control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RS_EN_POL ,Read strobe/enable polarity control" "Not inverted,Inverted"
|
|
bitfld.long 0x00 3. " ALEPOL ,Address latch enable (ALE) polarity control" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LIDD_MODE_SEL ,LIDD mode select" "Sync MPU68,Async MPU68,Sync MPU80,Async MPU80,Hitachi,?..."
|
|
group.long 0x10++0xb
|
|
line.long 0x00 "LIDD_CS0_CONF,LCD LIDD CS0 Configuration Register"
|
|
bitfld.long 0x00 27.--31. " W_SU ,Write strobe set-up cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--26. " W_STROBE ,Write strobe duration cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 17.--20. " W_HOLD ,Write strobe hold cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--16. " R_SU ,Read strobe set-up cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " R_STROBE ,Read strobe duration cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2.--5. " R_HOLD ,Read strobe hold cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TA ,MCLK cycles between the end of one CS0 device access and start of another CS0 device access" "0,1,2,3"
|
|
line.long 0x04 "LIDD_CS0_ADDR,LCD LIDD CS0 Address Read/Write Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ADR_INDX ,Peripheral device address/index value"
|
|
line.long 0x08 "LIDD_CS0_DATA,LCD LIDD CS0 Data Read/Write Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DATA ,Peripheral Device Data value"
|
|
group.long 0x1c++0xb
|
|
line.long 0x00 "LIDD_CS1_CONF,LCD LIDD CS1 Configuration Register"
|
|
bitfld.long 0x00 27.--31. " W_SU ,Write strobe set-up cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--26. " W_STROBE ,Write strobe duration cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 17.--20. " W_HOLD ,Write strobe hold cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--16. " R_SU ,Read strobe set-up cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--11. " R_STROBE ,Read strobe duration cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2.--5. " R_HOLD ,Read strobe hold cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TA ,MCLK cycles between the end of one CS0 device access and start of another CS0 device access" "0,1,2,3"
|
|
line.long 0x04 "LIDD_CS1_ADDR,LCD LIDD CS1 Address Read/Write Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ADR_INDX ,Peripheral device address/index value"
|
|
line.long 0x08 "LIDD_CS1_DATA,LCD LIDD CS1 Data Read/Write Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DATA ,Peripheral Device Data value"
|
|
width 17.
|
|
group.long 0x28++0x13 "Raster Registers"
|
|
line.long 0x00 "RASTER_CTRL,LCD Raster Control Register"
|
|
bitfld.long 0x00 24. " STN_565 ,12-bit-per-pixel (5-6-5) mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TFT_ALT_MAP ,TFT alternative signal mapping" "Right alligned,Converted to 5-6-5"
|
|
textline " "
|
|
bitfld.long 0x00 22. " NIB_MODE ,Nibble mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " PLM ,Palette Loading Mode" "Palette/data,Palette,Data,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--19. 1. " FIFO_DMA_DELAY ,FIFO DMA request delay"
|
|
bitfld.long 0x00 9. " MONO8B ,Mono 8-bit mode" "LCD_P[3:0],LCD_P[7:0]"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RD_ORDER ,Raster data order select" "LSB,MSB"
|
|
bitfld.long 0x00 7. " TFT_STN ,TFT/STN mode" "STN,TFT"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FUF_EN ,FIFO underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SL_EN ,Sync lost interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PL_EN ,Palette loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DONE_EN ,Frame done interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC_EN ,AC bias count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MONO_COLOR ,LCD monochrome or color" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RASTER_EN ,LCD raster controller enable" "Disabled,Enabled"
|
|
line.long 0x04 "RASTER_TIMING_0,LCD Raster Timing Register 0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " HBP ,Horizontal back porch"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HFP ,Horizontal front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x04 10.--15. 1. " HSW ,Horizontal sync pulse width"
|
|
hexmask.long.byte 0x04 4.--9. 1. " PPL ,Pixels per line"
|
|
line.long 0x08 "RASTER_TIMING_1,LCD Raster Timing Register 1"
|
|
hexmask.long.byte 0x08 24.--31. 1. " VBP ,Vertical back porch"
|
|
hexmask.long.byte 0x08 16.--23. 1. " VFP ,Vertical front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x08 10.--15. 1. " VSW ,Vertical sync pulse width"
|
|
hexmask.long.word 0x08 0.--9. 1. " LPP ,Lines per Panel"
|
|
line.long 0x0c "RASTER_TIMING_2,LCD Raster Timing Register 2"
|
|
bitfld.long 0x0c 25. " SYNC_CTRL ,Horizontal and vertical sync control" "Inactive,Active"
|
|
bitfld.long 0x0c 24. " SYNC_EDGE ,Horizontal and vertical dync edge" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " BIAS ,Invert AC bias" "Active high,Active low"
|
|
bitfld.long 0x0c 22. " IPC ,Invert pixel clock" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " IHS ,Invert line clock" "Active high,Active low"
|
|
bitfld.long 0x0c 20. " IVS ,Invert frame clock" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--19. " ACB_I ,AC Bias number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " ACB ,AC bias pin frequency"
|
|
line.long 0x10 "RASTER_SUBPANEL,LCD Raster Subpanel Display Register"
|
|
bitfld.long 0x10 31. " SPEN ,Subpanel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " HOLS ,High or low signal" "Low/below,High/above"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--25. 1. " LPPT ,Line per panel threshold"
|
|
hexmask.long.word 0x10 4.--15. 1. " DPD ,Default pixel data"
|
|
width 20.
|
|
group.long 0x40++0x3 "DMA"
|
|
line.long 0x00 "LCDDMA_CTRL,LCD DMA Control Register"
|
|
sif (cpu()!="AM1707")
|
|
bitfld.long 0x00 8.--10. " TH_FIFO_READY ,DMA FIFO threshold" "8,16,32,64,128,256,512,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " BURST_SIZE ,Burst size" "1,2,4,8,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOF_INTEN ,End-of-frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIGENDIAN ,Big endian enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRAME_MODE ,Frame mode" "One buffer,Two buffers"
|
|
group.long 0x44++0x7
|
|
line.long 0x00 "LCDDMA_FB0_BASE,LCD DMA Frame Buffer 0 Base Address Register"
|
|
sif (cpu()!="AM1707")
|
|
hexmask.long 0x00 2.--31. 0x4 " FB0_BASE ,Frame buffer 0 base address"
|
|
endif
|
|
line.long 0x04 "LCDDMA_FB0_CEILING,LCD DMA Frame Buffer 0 Ceiling Address Register"
|
|
sif (cpu()!="AM1707")
|
|
hexmask.long 0x04 2.--31. 0x4 " FB0_CEIL ,Frame buffer 0 ceiling address"
|
|
endif
|
|
if (((d.l(asd:0x01e13000+0x40))&0x1)==0x1)
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "LCDDMA_FB1_BASE,LCD DMA Frame Buffer 1 Base Address Register"
|
|
sif (cpu()!="AM1707")
|
|
hexmask.long 0x00 2.--31. 0x4 " FB1_BASE ,Frame buffer 1 base address"
|
|
endif
|
|
line.long 0x04 "LCDDMA_FB1_CEILING,LCD DMA Frame Buffer 1 Ceiling Address Register"
|
|
sif (cpu()!="AM1707")
|
|
hexmask.long 0x04 2.--31. 0x4 " FB1_CEIL ,Frame buffer 0 ceiling address"
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "64-Bit Timer"
|
|
tree "Timer64P 0"
|
|
base asd:0x01c20000
|
|
width 15.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
group.long 0x04++0xb
|
|
line.long 0x00 "EMUMGT,Emulation Management Register"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation suspend event stop mode" "Immediately,After finish"
|
|
bitfld.long 0x00 0. " FREE ,Emulation suspend event response" "SOFT bit select,Free-running"
|
|
line.long 0x04 "GPINTGPEN,GPIO Interrupt Control and Enable Register"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x04 25. " GPENO34 ,Enable TM64P_OUT34 to function in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 24. " GPENI34 ,Enable TM64P_IN34 to function in GPIO mode" "TIMER,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 17. " GPENO12 ,Enable TM64P_OUT12 to function in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 16. " GPENI12 ,Enable TM64P_IN12 to function in GPIO mode" "TIMER,GPIO"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x04 13. " GPINT34INVO ,Invert interrupt/event signal for TM64P_OUT34" "Rising,Falling"
|
|
bitfld.long 0x04 12. " GPINT34INVI ,Invert interrupt/event signal for TM64P_IN34" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GPINT34ENO ,Enable TM64P_OUT34 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 8. " GPINT34ENI ,Enable TM64P_IN34 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " GPINT12INVO ,Invert interrupt/event signal from TM64P_OUT12" "Rising,Falling"
|
|
bitfld.long 0x04 4. " GPINT12INVI ,Invert interrupt/event signal for TM64P_IN12" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GPINT12ENO ,Enable TM64P_OUT12 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 0. " GPINT12ENI ,Enable TM64P_IN12 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
line.long 0x08 "GPDATGPDIR,GPIO Data and Direction Register"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x08 25. " GPDIRO34 ,Select direction of TM64P_OUT34 in GPIO mode" "Input,Output"
|
|
bitfld.long 0x08 24. " GPDIRI34 ,Select direction of TM64P_IN34 in GPIO mode" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 17. " GPDIRO12 ,Select direction of TM64P_OUT12 in GPIO mode" "Input,Output"
|
|
bitfld.long 0x08 16. " GPDIRI12 ,Select direction of TM64P_IN12 in GPIO mode" "Input,Output"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x08 9. " GPDATO34 ,Data on TM64P_OUT34 in GPIO mode" "Low,High"
|
|
bitfld.long 0x08 8. " GPDATI34 ,Data on TM64P_IN34 in GPIO mode" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " GPDATO12 ,Data on TM64P_OUT12 in GPIO mode" "Low,High"
|
|
bitfld.long 0x08 0. " GPDATI12 ,Data on TM64P_IN12 in GPIO mode" "Low,High"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "TIM12,Timer Counter Register"
|
|
line.long 0x04 "TIM34,Timer Counter Register"
|
|
line.long 0x08 "PRD12,Timer Period Register"
|
|
line.long 0x0c "PRD34,Timer Period Register "
|
|
line.long 0x10 "TCR,Timer Control Register"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x10 28.--29. " CAPEVTMODE34 ,Capture event mode" "Rising edge,Falling edge,Both edge,?..."
|
|
bitfld.long 0x10 27. " CAPMODE34 ,Capture mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 26. " READRSTMODE34 ,Read reset mode enable" "Disabled,Enabled"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x10 25. " TIEN34 ,Timer input gate enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CLKSRC34 ,Clock source" "Internal,External"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 22.--23. " ENAMODE34 ,Enabling mode" "Disabled,Enabled once,Enabled continously,Enabled continously reload"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x10 20.--21. " PWID34 ,Pulse width" "1,2,3,4"
|
|
bitfld.long 0x10 19. " CP34 ,Clock/Pulse bit" "Pulse,Clock"
|
|
textline " "
|
|
bitfld.long 0x10 18. " INVINP34 ,Invert TM64P_IN34" "Not inverted,Inverted"
|
|
bitfld.long 0x10 17. " INVOUTP34 ,Invert TM64P_OUT34" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TSTAT34 ,Timer status" "Not asserted,Asserted"
|
|
bitfld.long 0x10 12.--13. " CAPVTMODE12 ,Capture event mode" "Rising edge,Falling edge,Both edge,?..."
|
|
else
|
|
bitfld.long 0x10 12.--13. " CAPVTMODE12 ,Capture event mode" "Rising edge,Falling edge,Both edge,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 11. " CAPMODE12 ,Capture mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " READRSTMODE12 ,Read reset mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " TIEN12 ,Timer input gate enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CLKSRC12 ,Clock source" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x10 6.--7. " ENAMODE12 ,Enabling mode" "Disabled,Enabled once,Enabled continously,Enabled continously reload"
|
|
textline " "
|
|
bitfld.long 0x10 4.--5. " PWID12 ,Pulse width" "1,2,3,4"
|
|
bitfld.long 0x10 3. " CP12 ,Clock/Pulse bit" "Pulse,Clock"
|
|
textline " "
|
|
bitfld.long 0x10 2. " INVINP12 ,Invert TM64P_IN34" "Not inverted,Inverted"
|
|
bitfld.long 0x10 1. " INVOUTP12 ,Invert TM64P_OUT34" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x10 0. " TSTAT12 ,Timer status" "Not asserted,Asserted"
|
|
line.long 0x14 "TGCR,Timer Global Control Register"
|
|
hexmask.long.byte 0x14 12.--15. 1. " TDDR34 ,Timer divide-down ratio"
|
|
hexmask.long.byte 0x14 8.--11. 1. " PSC34 ,Prescale period"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PLUSEN ,Enable new timer plus features" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " TIMMODE ,Timer mode" "64-bit GP,32-bit unchained,64-bit watchdog,32-bit chained"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TIM34RS ,Timer 3:4 reset" "Reset,No reset"
|
|
bitfld.long 0x14 0. " TIM12RS ,Timer 1:2 reset" "Reset,No reset"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "WDTCR,Watchdog Timer Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WDKEY ,16-bit watchdog timer service key"
|
|
bitfld.long 0x00 15. " WDFLAG ,Watchdog flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " WDEN ,Watchdog timer enable" "Disabled,Enabled"
|
|
width 15.
|
|
group.long 0x34++0x13
|
|
line.long 0x00 "REL12,Timer Reload Register 12 Register"
|
|
line.long 0x04 "REL34,Timer Reload Register 34 Register"
|
|
line.long 0x08 "CAP12,Timer Capture Register 12 Register"
|
|
line.long 0x0c "CAP34,Timer Capture Register 34 Register"
|
|
line.long 0x10 "INTCTLSTAT,Timer Interrupt Control and Status Register"
|
|
eventfld.long 0x10 19. " EVTINTSTAT34 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " EVTINTEN34 ,Enables the interrupt generation" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 17. " PRDINTSTAT34 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " PRDINTEN34 ,Enable interrupt generation" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 3. " EVTINTSTAT12 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " EVTINTEN12 ,Enables the interrupt generation" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 1. " PRDINTSTAT12 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " PRDINTEN12 ,Enable interrupt generation" "Disabled,Enabled"
|
|
group.long 0x60++0x1f
|
|
line.long 0x00 "CMP0,Compare Register 0"
|
|
line.long 0x04 "CMP1,Compare Register 1"
|
|
line.long 0x08 "CMP2,Compare Register 2"
|
|
line.long 0x0c "CMP3,Compare Register 3"
|
|
line.long 0x10 "CMP4,Compare Register 4"
|
|
line.long 0x14 "CMP5,Compare Register 5"
|
|
line.long 0x18 "CMP6,Compare Register 6"
|
|
line.long 0x1c "CMP7,Compare Register 7"
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer64P 1"
|
|
base asd:0x01c21000
|
|
width 15.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
group.long 0x04++0xb
|
|
line.long 0x00 "EMUMGT,Emulation Management Register"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation suspend event stop mode" "Immediately,After finish"
|
|
bitfld.long 0x00 0. " FREE ,Emulation suspend event response" "SOFT bit select,Free-running"
|
|
line.long 0x04 "GPINTGPEN,GPIO Interrupt Control and Enable Register"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x04 25. " GPENO34 ,Enable TM64P_OUT34 to function in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 24. " GPENI34 ,Enable TM64P_IN34 to function in GPIO mode" "TIMER,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 17. " GPENO12 ,Enable TM64P_OUT12 to function in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 16. " GPENI12 ,Enable TM64P_IN12 to function in GPIO mode" "TIMER,GPIO"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x04 13. " GPINT34INVO ,Invert interrupt/event signal for TM64P_OUT34" "Rising,Falling"
|
|
bitfld.long 0x04 12. " GPINT34INVI ,Invert interrupt/event signal for TM64P_IN34" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GPINT34ENO ,Enable TM64P_OUT34 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 8. " GPINT34ENI ,Enable TM64P_IN34 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " GPINT12INVO ,Invert interrupt/event signal from TM64P_OUT12" "Rising,Falling"
|
|
bitfld.long 0x04 4. " GPINT12INVI ,Invert interrupt/event signal for TM64P_IN12" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GPINT12ENO ,Enable TM64P_OUT12 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
bitfld.long 0x04 0. " GPINT12ENI ,Enable TM64P_IN12 to source interrupts/events in GPIO mode" "TIMER,GPIO"
|
|
line.long 0x08 "GPDATGPDIR,GPIO Data and Direction Register"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x08 25. " GPDIRO34 ,Select direction of TM64P_OUT34 in GPIO mode" "Input,Output"
|
|
bitfld.long 0x08 24. " GPDIRI34 ,Select direction of TM64P_IN34 in GPIO mode" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 17. " GPDIRO12 ,Select direction of TM64P_OUT12 in GPIO mode" "Input,Output"
|
|
bitfld.long 0x08 16. " GPDIRI12 ,Select direction of TM64P_IN12 in GPIO mode" "Input,Output"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x08 9. " GPDATO34 ,Data on TM64P_OUT34 in GPIO mode" "Low,High"
|
|
bitfld.long 0x08 8. " GPDATI34 ,Data on TM64P_IN34 in GPIO mode" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " GPDATO12 ,Data on TM64P_OUT12 in GPIO mode" "Low,High"
|
|
bitfld.long 0x08 0. " GPDATI12 ,Data on TM64P_IN12 in GPIO mode" "Low,High"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "TIM12,Timer Counter Register"
|
|
line.long 0x04 "TIM34,Timer Counter Register"
|
|
line.long 0x08 "PRD12,Timer Period Register"
|
|
line.long 0x0c "PRD34,Timer Period Register "
|
|
line.long 0x10 "TCR,Timer Control Register"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x10 28.--29. " CAPEVTMODE34 ,Capture event mode" "Rising edge,Falling edge,Both edge,?..."
|
|
bitfld.long 0x10 27. " CAPMODE34 ,Capture mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 26. " READRSTMODE34 ,Read reset mode enable" "Disabled,Enabled"
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x10 25. " TIEN34 ,Timer input gate enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CLKSRC34 ,Clock source" "Internal,External"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 22.--23. " ENAMODE34 ,Enabling mode" "Disabled,Enabled once,Enabled continously,Enabled continously reload"
|
|
textline " "
|
|
sif (cpu()!="DA828"&&cpu()!="DA830"&&cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x10 20.--21. " PWID34 ,Pulse width" "1,2,3,4"
|
|
bitfld.long 0x10 19. " CP34 ,Clock/Pulse bit" "Pulse,Clock"
|
|
textline " "
|
|
bitfld.long 0x10 18. " INVINP34 ,Invert TM64P_IN34" "Not inverted,Inverted"
|
|
bitfld.long 0x10 17. " INVOUTP34 ,Invert TM64P_OUT34" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TSTAT34 ,Timer status" "Not asserted,Asserted"
|
|
bitfld.long 0x10 12.--13. " CAPVTMODE12 ,Capture event mode" "Rising edge,Falling edge,Both edge,?..."
|
|
else
|
|
bitfld.long 0x10 12.--13. " CAPVTMODE12 ,Capture event mode" "Rising edge,Falling edge,Both edge,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 11. " CAPMODE12 ,Capture mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " READRSTMODE12 ,Read reset mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " TIEN12 ,Timer input gate enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CLKSRC12 ,Clock source" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x10 6.--7. " ENAMODE12 ,Enabling mode" "Disabled,Enabled once,Enabled continously,Enabled continously reload"
|
|
textline " "
|
|
bitfld.long 0x10 4.--5. " PWID12 ,Pulse width" "1,2,3,4"
|
|
bitfld.long 0x10 3. " CP12 ,Clock/Pulse bit" "Pulse,Clock"
|
|
textline " "
|
|
bitfld.long 0x10 2. " INVINP12 ,Invert TM64P_IN34" "Not inverted,Inverted"
|
|
bitfld.long 0x10 1. " INVOUTP12 ,Invert TM64P_OUT34" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x10 0. " TSTAT12 ,Timer status" "Not asserted,Asserted"
|
|
line.long 0x14 "TGCR,Timer Global Control Register"
|
|
hexmask.long.byte 0x14 12.--15. 1. " TDDR34 ,Timer divide-down ratio"
|
|
hexmask.long.byte 0x14 8.--11. 1. " PSC34 ,Prescale period"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PLUSEN ,Enable new timer plus features" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " TIMMODE ,Timer mode" "64-bit GP,32-bit unchained,64-bit watchdog,32-bit chained"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TIM34RS ,Timer 3:4 reset" "Reset,No reset"
|
|
bitfld.long 0x14 0. " TIM12RS ,Timer 1:2 reset" "Reset,No reset"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "WDTCR,Watchdog Timer Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WDKEY ,16-bit watchdog timer service key"
|
|
bitfld.long 0x00 15. " WDFLAG ,Watchdog flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " WDEN ,Watchdog timer enable" "Disabled,Enabled"
|
|
width 15.
|
|
group.long 0x34++0x13
|
|
line.long 0x00 "REL12,Timer Reload Register 12 Register"
|
|
line.long 0x04 "REL34,Timer Reload Register 34 Register"
|
|
line.long 0x08 "CAP12,Timer Capture Register 12 Register"
|
|
line.long 0x0c "CAP34,Timer Capture Register 34 Register"
|
|
line.long 0x10 "INTCTLSTAT,Timer Interrupt Control and Status Register"
|
|
eventfld.long 0x10 19. " EVTINTSTAT34 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " EVTINTEN34 ,Enables the interrupt generation" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 17. " PRDINTSTAT34 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " PRDINTEN34 ,Enable interrupt generation" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 3. " EVTINTSTAT12 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " EVTINTEN12 ,Enables the interrupt generation" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 1. " PRDINTSTAT12 ,Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " PRDINTEN12 ,Enable interrupt generation" "Disabled,Enabled"
|
|
group.long 0x60++0x1f
|
|
line.long 0x00 "CMP0,Compare Register 0"
|
|
line.long 0x04 "CMP1,Compare Register 1"
|
|
line.long 0x08 "CMP2,Compare Register 2"
|
|
line.long 0x0c "CMP3,Compare Register 3"
|
|
line.long 0x10 "CMP4,Compare Register 4"
|
|
line.long 0x14 "CMP5,Compare Register 5"
|
|
line.long 0x18 "CMP6,Compare Register 6"
|
|
line.long 0x1c "CMP7,Compare Register 7"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C 0"
|
|
base asd:0x01c22000
|
|
width 8.
|
|
if (((data.long(asd:0x01c22000+0x24))&0x100)==(0x000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "ICOAR,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OADDR ,Slave address of the I2C module"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "ICOAR,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OADDR ,Slave address of the I2C module"
|
|
endif
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "ICIMR,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 6. " AAS ,Address-as-slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCD ,Stop condition detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ICXRDY ,Transmit-data-ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ICRRDY ,Receive-data-ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARDY ,Register-access-ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,No-acknowledgment interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AL ,Arbitration-lost interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ICSTR,I2C Status Register"
|
|
eventfld.long 0x04 14. " SDIR ,Slave direction" "Receiver,Transmitter"
|
|
eventfld.long 0x04 13. " NACKSNT ,NACK sent" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " BB ,Bus busy" "Free,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RSFULL ,Receive shift register full" "No overrun,Overrun"
|
|
bitfld.long 0x04 10. " XSMT ,Transmit shift register empty" "Underflow,No underflow"
|
|
bitfld.long 0x04 9. " AAS ,Addressed-as-slave" "Cleared,Recognized"
|
|
textline " "
|
|
bitfld.long 0x04 8. " AD0 ,Address 0 bit" "Cleared,Detected"
|
|
eventfld.long 0x04 5. " SCD ,Stop condition detected" "Not detected,Detected"
|
|
eventfld.long 0x04 4. " ICXRDY ,Transmit-data-ready interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x04 3. " ICRRDY ,Receive-data-ready interrupt flag" "Not ready,Ready"
|
|
eventfld.long 0x04 2. " ARDY ,Register-access-ready interrupt flag" "Not ready,Ready"
|
|
eventfld.long 0x04 1. " NACK ,No-acknowledgement interrupt flag" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 0. " AL ,Arbitration-lost interrupt flag" "Not lost,Lost"
|
|
line.long 0x08 "ICCLKL,I2C Clock Divider Register Low"
|
|
hexmask.long.word 0x08 0.--15. 1. " ICCL ,Clock low-time divide-down value"
|
|
line.long 0x0c "ICCLKH,I2C Clock Divider Register High"
|
|
hexmask.long.word 0x0c 0.--15. 1. " ICCH ,Clock high-time divide-down value"
|
|
line.long 0x10 "ICCNT,I2C Data Count Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " ICDC ,Data count value"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "ICDRR,I2C Data Receive Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Receive data"
|
|
if (((data.long(asd:0x01c22000+0x24))&0x100)==(0x000))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSAR,I2C Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADDR ,Slave address transmitted in master-transmitter mode"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSAR,I2C Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " SADDR ,Slave address transmitted in master-transmitter mode"
|
|
endif
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "ICDXR,I2C Data Transmit Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Transmit data"
|
|
line.long 0x04 "ICMDR,I2C Mode Register"
|
|
bitfld.long 0x04 15. " NACKMOD ,NACK mode" "ACK,NACK"
|
|
bitfld.long 0x04 14. " FREE ,Emulation mode" "Stopped,Run free"
|
|
bitfld.long 0x04 13. " STT ,START condition" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x04 11. " STP ,STOP condition" "Not generated,Generated"
|
|
bitfld.long 0x04 10. " MST ,Master mode" "Slave,Master"
|
|
bitfld.long 0x04 09. " TRX ,Transmitter mode" "Receiver,Transmitter"
|
|
textline " "
|
|
bitfld.long 0x04 08. " XA ,Expanded address mode" "7-bit,10-bit"
|
|
bitfld.long 0x04 07. " RM ,Repeat mode" "Non-repeat,Repeat"
|
|
bitfld.long 0x04 06. " DLB ,Digital loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 05. " IRS ,I2C module reset" "Reset,No reset"
|
|
bitfld.long 0x04 04. " STB ,START byte mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 03. " FDF ,Free data format mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " BC ,Bit count" "8-bits/word,1-bit/word,2-bits/word,3-bits/word,4-bits/word,5-bits/word,6-bits/word,7-bits/word"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "ICIVR,I2C Interrupt Vector Register"
|
|
bitfld.long 0x00 0.--2. " INTCODE ,Interrupt code" "None,AL,NACK,ARDY,ICRRDY,ICXRDY,SCD,AAS"
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "ICEMDR,I2C Extended Mode Register"
|
|
bitfld.long 0x00 1. " IGNACK ,Ignore NACK mode" "Not ignored,Ignored"
|
|
bitfld.long 0x00 0. " BCM ,Backward compatibility mode" "More data,Data copied"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "ICPSC,I2C Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IPSC ,I2C prescaler divide-down value"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x00 "REVID1,I2C Revision Identification Register 1"
|
|
line.long 0x04 "REVID2,I2C Revision Identification Register 2"
|
|
sif (cpu()=="AM1806"||cpu()=="AM1802"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1705"||cpu()=="AM1707")
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "ICDMAC,I2C DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "ICPFUNC,I2C Pin Function Register"
|
|
bitfld.long 0x00 0. " PFUNC0 ,GPIO mode enable bit for SCL and SDA pins" "Disabled,Enabled"
|
|
group.long 0x4c++0xb
|
|
line.long 0x00 "ICPDIR,I2C Pin Direction Register"
|
|
bitfld.long 0x00 1. " PDIR1 ,SDA direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDIR0 ,SCL direction" "Input,Output"
|
|
line.long 0x04 "ICPDIN,I2C Pin Data Input Register"
|
|
bitfld.long 0x04 1. " PDIN1 ,Logic level present on the SDA pin" "Low,High"
|
|
bitfld.long 0x04 0. " PDIN0 ,Logic level present on the SCL pin" "Low,High"
|
|
line.long 0x08 "ICPDOUT,I2C Pin Data Output Register"
|
|
setclrfld.long 0x08 1. 0x0c 1. 0x10 1. " PDOUT1_set/clr ,Value driven on the SDA pin when configured as output" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0c 0. 0x10 0. " PDOUT0_set/clr ,Value driven on the SCL pin when configured as output" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C 1"
|
|
base asd:0x01e28000
|
|
width 8.
|
|
if (((data.long(asd:0x01e28000+0x24))&0x100)==(0x000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "ICOAR,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " OADDR ,Slave address of the I2C module"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "ICOAR,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " OADDR ,Slave address of the I2C module"
|
|
endif
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "ICIMR,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 6. " AAS ,Address-as-slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCD ,Stop condition detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ICXRDY ,Transmit-data-ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ICRRDY ,Receive-data-ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARDY ,Register-access-ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,No-acknowledgment interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AL ,Arbitration-lost interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ICSTR,I2C Status Register"
|
|
eventfld.long 0x04 14. " SDIR ,Slave direction" "Receiver,Transmitter"
|
|
eventfld.long 0x04 13. " NACKSNT ,NACK sent" "Not sent,Sent"
|
|
eventfld.long 0x04 12. " BB ,Bus busy" "Free,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RSFULL ,Receive shift register full" "No overrun,Overrun"
|
|
bitfld.long 0x04 10. " XSMT ,Transmit shift register empty" "Underflow,No underflow"
|
|
bitfld.long 0x04 9. " AAS ,Addressed-as-slave" "Cleared,Recognized"
|
|
textline " "
|
|
bitfld.long 0x04 8. " AD0 ,Address 0 bit" "Cleared,Detected"
|
|
eventfld.long 0x04 5. " SCD ,Stop condition detected" "Not detected,Detected"
|
|
eventfld.long 0x04 4. " ICXRDY ,Transmit-data-ready interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x04 3. " ICRRDY ,Receive-data-ready interrupt flag" "Not ready,Ready"
|
|
eventfld.long 0x04 2. " ARDY ,Register-access-ready interrupt flag" "Not ready,Ready"
|
|
eventfld.long 0x04 1. " NACK ,No-acknowledgement interrupt flag" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 0. " AL ,Arbitration-lost interrupt flag" "Not lost,Lost"
|
|
line.long 0x08 "ICCLKL,I2C Clock Divider Register Low"
|
|
hexmask.long.word 0x08 0.--15. 1. " ICCL ,Clock low-time divide-down value"
|
|
line.long 0x0c "ICCLKH,I2C Clock Divider Register High"
|
|
hexmask.long.word 0x0c 0.--15. 1. " ICCH ,Clock high-time divide-down value"
|
|
line.long 0x10 "ICCNT,I2C Data Count Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " ICDC ,Data count value"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "ICDRR,I2C Data Receive Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Receive data"
|
|
if (((data.long(asd:0x01e28000+0x24))&0x100)==(0x000))
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSAR,I2C Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADDR ,Slave address transmitted in master-transmitter mode"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSAR,I2C Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " SADDR ,Slave address transmitted in master-transmitter mode"
|
|
endif
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "ICDXR,I2C Data Transmit Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Transmit data"
|
|
line.long 0x04 "ICMDR,I2C Mode Register"
|
|
bitfld.long 0x04 15. " NACKMOD ,NACK mode" "ACK,NACK"
|
|
bitfld.long 0x04 14. " FREE ,Emulation mode" "Stopped,Run free"
|
|
bitfld.long 0x04 13. " STT ,START condition" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x04 11. " STP ,STOP condition" "Not generated,Generated"
|
|
bitfld.long 0x04 10. " MST ,Master mode" "Slave,Master"
|
|
bitfld.long 0x04 09. " TRX ,Transmitter mode" "Receiver,Transmitter"
|
|
textline " "
|
|
bitfld.long 0x04 08. " XA ,Expanded address mode" "7-bit,10-bit"
|
|
bitfld.long 0x04 07. " RM ,Repeat mode" "Non-repeat,Repeat"
|
|
bitfld.long 0x04 06. " DLB ,Digital loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 05. " IRS ,I2C module reset" "Reset,No reset"
|
|
bitfld.long 0x04 04. " STB ,START byte mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 03. " FDF ,Free data format mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " BC ,Bit count" "8-bits/word,1-bit/word,2-bits/word,3-bits/word,4-bits/word,5-bits/word,6-bits/word,7-bits/word"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "ICIVR,I2C Interrupt Vector Register"
|
|
bitfld.long 0x00 0.--2. " INTCODE ,Interrupt code" "None,AL,NACK,ARDY,ICRRDY,ICXRDY,SCD,AAS"
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "ICEMDR,I2C Extended Mode Register"
|
|
bitfld.long 0x00 1. " IGNACK ,Ignore NACK mode" "Not ignored,Ignored"
|
|
bitfld.long 0x00 0. " BCM ,Backward compatibility mode" "More data,Data copied"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "ICPSC,I2C Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IPSC ,I2C prescaler divide-down value"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x00 "REVID1,I2C Revision Identification Register 1"
|
|
line.long 0x04 "REVID2,I2C Revision Identification Register 2"
|
|
sif (cpu()=="AM1806"||cpu()=="AM1802"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1705"||cpu()=="AM1707")
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "ICDMAC,I2C DMA Control Register"
|
|
bitfld.long 0x00 1. " TXDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "ICPFUNC,I2C Pin Function Register"
|
|
bitfld.long 0x00 0. " PFUNC0 ,GPIO mode enable bit for SCL and SDA pins" "Disabled,Enabled"
|
|
group.long 0x4c++0xb
|
|
line.long 0x00 "ICPDIR,I2C Pin Direction Register"
|
|
bitfld.long 0x00 1. " PDIR1 ,SDA direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDIR0 ,SCL direction" "Input,Output"
|
|
line.long 0x04 "ICPDIN,I2C Pin Data Input Register"
|
|
bitfld.long 0x04 1. " PDIN1 ,Logic level present on the SDA pin" "Low,High"
|
|
bitfld.long 0x04 0. " PDIN0 ,Logic level present on the SCL pin" "Low,High"
|
|
line.long 0x08 "ICPDOUT,I2C Pin Data Output Register"
|
|
setclrfld.long 0x08 1. 0x0c 1. 0x10 1. " PDOUT1_set/clr ,Value driven on the SDA pin when configured as output" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0c 0. 0x10 0. " PDOUT0_set/clr ,Value driven on the SCL pin when configured as output" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART0"
|
|
width 13.
|
|
base asd:0x01c42000
|
|
if (((d.l(asd:0x01c42000+0xc))&0x80)==0x00)
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register"
|
|
in
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " EDSSI ,Enable modem status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ELSI ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ETBEI ,Transmitter holding register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DLL,Divisor LSB Latch"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor"
|
|
line.long 0x04 "DLH,Divisor MSB Latch"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor"
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.long 0x00 6.--7. " FIFOEN ,FIFOs enabled" "Non-FIFO,Reserved,Reserved,Enabled"
|
|
bitfld.long 0x00 1.--3. " INTID ,Interrupt type" "Reserved,THR empty,Receive data available,Receive line status,Reserved,Reserved,Character timeout indication,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPEND ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXFIFTL ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,14 bytes"
|
|
bitfld.long 0x00 3. " DMAMODE1 ,DMA MODE1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TXCLR ,Transmitter FIFO clear" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " RXCLR ,Receiver FIFO clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOEN ,Transmitter and receiver FIFOs mode enable" "Non-FIFO,Enabled"
|
|
if ((((d.l(asd:0x01c42000+0xc))&0xb)==0x9)||(((d.l(asd:0x01c42000+0xc))&0xb)==0xa)||(((d.l(asd:0x01c42000+0xc))&0xb)==0xb))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPS ,Even parity select" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
elif (((d.l(asd:0x01c42000+0xc))&0xb)==0x8)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPS ,Even parity select" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,1.5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
elif (((d.l(asd:0x01c42000+0xc))&0xb)==0x0)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,1.5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCR,Modem Control Register"
|
|
bitfld.long 0x00 5. " AFE ,Autoflow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOOP ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OUT2 ,OUT2" "0,1"
|
|
bitfld.long 0x00 2. " OUT1 ,OUT1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTS ,RTS control" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x00 7. " RXFIFOE ,Receiver FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TEMT ,Transmitter empty (TEMT) indicator" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " THRE ,Transmitter holding register empty (THRE) indicator" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " BI ,Break indicator" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FE ,Framing error (FE) indicator" "No error,Error"
|
|
bitfld.long 0x00 2. " PE ,Parity error (PE) indicator" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OE ,Overrun error (OE) indicator" "No overrun,Overrun"
|
|
bitfld.long 0x00 0. " DR ,Data-ready (DR) indicator for the receiver" "No ready,Ready"
|
|
if (((d.l(asd:0x01c42000+0x10))&0x10)==0x10)
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,Value of MCR bit 3 (diagnostic test mode)" "Low,High"
|
|
bitfld.long 0x00 6. " RI ,Value of MCR bit 2 (diagnostic test mode)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DSR ,Value of MCR bit 0 (diagnostic test mode)" "Low,High"
|
|
bitfld.long 0x00 4. " CTS ,Value of MCR bit 1 (diagnostic test mode)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,DCD input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " TERI ,RI input has changed from a low to a high" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDSRC ,DSR input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CTSC ,CTS input has changed state since the last read" "Not changed,Changed"
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 3. " DCD ,DCD input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " TERI ,RI input has changed from a low to a high" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDSRC ,DSR input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " DCTSC ,CTS input has changed state since the last read" "Not changed,Changed"
|
|
endif
|
|
rgroup.long 0x1c++0x7
|
|
line.long 0x00 "SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCR ,Scratch Pad"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "DLL,Divisor LSB Latch"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor"
|
|
line.long 0x04 "DLH,Divisor MSB Latch"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "REVID1,Revision Identification Register 1"
|
|
line.long 0x04 "REVID2,Revision Identification Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " REVID2 ,Peripheral Identification Number"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PWREMU_MGMT,Power and Emulation Management Register"
|
|
bitfld.long 0x00 14. " UTRST ,UART transmitter reset" "Reset,Enabled"
|
|
bitfld.long 0x00 13. " URRST ,UART receiver reset" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FREE ,Free-running enable mode" "Stopped,Free-running"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "MDR,Mode Definition Register"
|
|
bitfld.long 0x00 0. " OSM_SEL ,Over-sampling mode selection" "16x,13x"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART1"
|
|
width 13.
|
|
base asd:0x01d0c000
|
|
if (((d.l(asd:0x01d0c000+0xc))&0x80)==0x00)
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register"
|
|
in
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " EDSSI ,Enable modem status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ELSI ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ETBEI ,Transmitter holding register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DLL,Divisor LSB Latch"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor"
|
|
line.long 0x04 "DLH,Divisor MSB Latch"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor"
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.long 0x00 6.--7. " FIFOEN ,FIFOs enabled" "Non-FIFO,Reserved,Reserved,Enabled"
|
|
bitfld.long 0x00 1.--3. " INTID ,Interrupt type" "Reserved,THR empty,Receive data available,Receive line status,Reserved,Reserved,Character timeout indication,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPEND ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXFIFTL ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,14 bytes"
|
|
bitfld.long 0x00 3. " DMAMODE1 ,DMA MODE1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TXCLR ,Transmitter FIFO clear" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " RXCLR ,Receiver FIFO clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOEN ,Transmitter and receiver FIFOs mode enable" "Non-FIFO,Enabled"
|
|
if ((((d.l(asd:0x01d0c000+0xc))&0xb)==0x9)||(((d.l(asd:0x01d0c000+0xc))&0xb)==0xa)||(((d.l(asd:0x01d0c000+0xc))&0xb)==0xb))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPS ,Even parity select" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
elif (((d.l(asd:0x01d0c000+0xc))&0xb)==0x8)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPS ,Even parity select" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,1.5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
elif (((d.l(asd:0x01d0c000+0xc))&0xb)==0x0)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,1.5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCR,Modem Control Register"
|
|
bitfld.long 0x00 5. " AFE ,Autoflow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOOP ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OUT2 ,OUT2" "0,1"
|
|
bitfld.long 0x00 2. " OUT1 ,OUT1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTS ,RTS control" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x00 7. " RXFIFOE ,Receiver FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TEMT ,Transmitter empty (TEMT) indicator" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " THRE ,Transmitter holding register empty (THRE) indicator" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " BI ,Break indicator" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FE ,Framing error (FE) indicator" "No error,Error"
|
|
bitfld.long 0x00 2. " PE ,Parity error (PE) indicator" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OE ,Overrun error (OE) indicator" "No overrun,Overrun"
|
|
bitfld.long 0x00 0. " DR ,Data-ready (DR) indicator for the receiver" "No ready,Ready"
|
|
if (((d.l(asd:0x01d0c000+0x10))&0x10)==0x10)
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,Value of MCR bit 3 (diagnostic test mode)" "Low,High"
|
|
bitfld.long 0x00 6. " RI ,Value of MCR bit 2 (diagnostic test mode)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DSR ,Value of MCR bit 0 (diagnostic test mode)" "Low,High"
|
|
bitfld.long 0x00 4. " CTS ,Value of MCR bit 1 (diagnostic test mode)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,DCD input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " TERI ,RI input has changed from a low to a high" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDSRC ,DSR input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CTSC ,CTS input has changed state since the last read" "Not changed,Changed"
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 3. " DCD ,DCD input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " TERI ,RI input has changed from a low to a high" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDSRC ,DSR input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " DCTSC ,CTS input has changed state since the last read" "Not changed,Changed"
|
|
endif
|
|
rgroup.long 0x1c++0x7
|
|
line.long 0x00 "SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCR ,Scratch Pad"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "DLL,Divisor LSB Latch"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor"
|
|
line.long 0x04 "DLH,Divisor MSB Latch"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "REVID1,Revision Identification Register 1"
|
|
line.long 0x04 "REVID2,Revision Identification Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " REVID2 ,Peripheral Identification Number"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PWREMU_MGMT,Power and Emulation Management Register"
|
|
bitfld.long 0x00 14. " UTRST ,UART transmitter reset" "Reset,Enabled"
|
|
bitfld.long 0x00 13. " URRST ,UART receiver reset" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FREE ,Free-running enable mode" "Stopped,Free-running"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "MDR,Mode Definition Register"
|
|
bitfld.long 0x00 0. " OSM_SEL ,Over-sampling mode selection" "16x,13x"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART2"
|
|
width 13.
|
|
base asd:0x01d0d000
|
|
if (((d.l(asd:0x01d0d000+0xc))&0x80)==0x00)
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register"
|
|
in
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " EDSSI ,Enable modem status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ELSI ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ETBEI ,Transmitter holding register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "DLL,Divisor LSB Latch"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor"
|
|
line.long 0x04 "DLH,Divisor MSB Latch"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor"
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "IIR,Interrupt Identification Register"
|
|
bitfld.long 0x00 6.--7. " FIFOEN ,FIFOs enabled" "Non-FIFO,Reserved,Reserved,Enabled"
|
|
bitfld.long 0x00 1.--3. " INTID ,Interrupt type" "Reserved,THR empty,Receive data available,Receive line status,Reserved,Reserved,Character timeout indication,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPEND ,Interrupt pending" "Pending,Not pending"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 6.--7. " RXFIFTL ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,14 bytes"
|
|
bitfld.long 0x00 3. " DMAMODE1 ,DMA MODE1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TXCLR ,Transmitter FIFO clear" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " RXCLR ,Receiver FIFO clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOEN ,Transmitter and receiver FIFOs mode enable" "Non-FIFO,Enabled"
|
|
if ((((d.l(asd:0x01d0d000+0xc))&0xb)==0x9)||(((d.l(asd:0x01d0d000+0xc))&0xb)==0xa)||(((d.l(asd:0x01d0d000+0xc))&0xb)==0xb))
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPS ,Even parity select" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
elif (((d.l(asd:0x01d0d000+0xc))&0xb)==0x8)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPS ,Even parity select" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,1.5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
elif (((d.l(asd:0x01d0d000+0xc))&0xb)==0x0)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,1.5"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "LCR,Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access" "RBR/THR/IER,DLL/DLH"
|
|
bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SP ,Stick parity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEN ,Parity enable" "No parity,Enabled"
|
|
bitfld.long 0x00 2. " STB ,Number of STOP bits generated" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " WLS ,Word lenght select" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCR,Modem Control Register"
|
|
bitfld.long 0x00 5. " AFE ,Autoflow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOOP ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OUT2 ,OUT2" "0,1"
|
|
bitfld.long 0x00 2. " OUT1 ,OUT1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTS ,RTS control" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "LSR,Line Status Register"
|
|
bitfld.long 0x00 7. " RXFIFOE ,Receiver FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TEMT ,Transmitter empty (TEMT) indicator" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " THRE ,Transmitter holding register empty (THRE) indicator" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " BI ,Break indicator" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FE ,Framing error (FE) indicator" "No error,Error"
|
|
bitfld.long 0x00 2. " PE ,Parity error (PE) indicator" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OE ,Overrun error (OE) indicator" "No overrun,Overrun"
|
|
bitfld.long 0x00 0. " DR ,Data-ready (DR) indicator for the receiver" "No ready,Ready"
|
|
if (((d.l(asd:0x01d0d000+0x10))&0x10)==0x10)
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,Value of MCR bit 3 (diagnostic test mode)" "Low,High"
|
|
bitfld.long 0x00 6. " RI ,Value of MCR bit 2 (diagnostic test mode)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DSR ,Value of MCR bit 0 (diagnostic test mode)" "Low,High"
|
|
bitfld.long 0x00 4. " CTS ,Value of MCR bit 1 (diagnostic test mode)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,DCD input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " TERI ,RI input has changed from a low to a high" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDSRC ,DSR input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CTSC ,CTS input has changed state since the last read" "Not changed,Changed"
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "MSR,Modem Status Register"
|
|
bitfld.long 0x00 3. " DCD ,DCD input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " TERI ,RI input has changed from a low to a high" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DDSRC ,DSR input has changed state since the last read" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " DCTSC ,CTS input has changed state since the last read" "Not changed,Changed"
|
|
endif
|
|
rgroup.long 0x1c++0x7
|
|
line.long 0x00 "SCR,Scratch Pad Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCR ,Scratch Pad"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "DLL,Divisor LSB Latch"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor"
|
|
line.long 0x04 "DLH,Divisor MSB Latch"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "REVID1,Revision Identification Register 1"
|
|
line.long 0x04 "REVID2,Revision Identification Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " REVID2 ,Peripheral Identification Number"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "PWREMU_MGMT,Power and Emulation Management Register"
|
|
bitfld.long 0x00 14. " UTRST ,UART transmitter reset" "Reset,Enabled"
|
|
bitfld.long 0x00 13. " URRST ,UART receiver reset" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FREE ,Free-running enable mode" "Stopped,Free-running"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "MDR,Mode Definition Register"
|
|
bitfld.long 0x00 0. " OSM_SEL ,Over-sampling mode selection" "16x,13x"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "USB (Universal Serial Bus v2.0)"
|
|
sif (cpu()=="DA830")
|
|
tree "USB 1.1 OHCI Host Controller"
|
|
base asd:0x01e25000
|
|
width 21.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,OHCI Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI specification revision"
|
|
group.long 0x04++0x0b
|
|
line.long 0x00 "HCCONTROL,HC Operating Mode Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote wake-up connected" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IR ,Interrupt routing" "0,1"
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state" "Reset,Resume,Operational,Suspend"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLE ,Bulk list processing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control list processing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous ED processing enabled by host controller driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic list enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio" "1,2,3,4"
|
|
line.long 0x04 "HCCOMMANDSTATUS,HC Command and Status"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling overrun count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership change request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BLF ,Bulk list filled" "Not filled,Filled"
|
|
bitfld.long 0x04 1. " CLF ,Control list filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HCR ,Host controller reset" "No effect,Reset"
|
|
line.long 0x08 "HCINTERRUPTSTATUS,HC Interrupt Status"
|
|
bitfld.long 0x08 30. " OC ,Ownership change" "Not changed,Changed"
|
|
eventfld.long 0x08 6. " RHSC ,Root hub status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x08 5. " FNO ,Frame number overflow" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " UE ,Unrecoverable error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RD ,Resume detected" "Not issued,Issued"
|
|
eventfld.long 0x08 2. " SF ,Start of frame" "Not issued,Issued"
|
|
textline " "
|
|
eventfld.long 0x08 1. " WDH ,Write done head" "Not updated,Updated"
|
|
eventfld.long 0x08 0. " SO ,Scheduling overrun" "No overrun,Overrun"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HCINTERRUPTENABLE,HC Interrupt Enable"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " MIE_set/clr ,Master interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " OC_set/clr ,Ownership change" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " RHSC_set/clr ,Root hub status change" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " FNO_set/clr ,Frame number overflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " UE_set/clr ,Unrecoverable error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " RD_set/clr ,Resume detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SF_set/clr ,Start of frame" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WDH_set/clr ,Write done head" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SO_set/clr ,Scheduling overrun" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "HCHCCA,HC HCCA Address Register"
|
|
hexmask.long 0x00 8.--31. 0x100 " HCCA ,Physical address of the beginning of the HCCA"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "HCPERIODCURRENTED,HC Current Periodic Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PCED ,Physical address of current ED on the periodic ED list"
|
|
group.long 0x20++0xf
|
|
line.long 0x00 "HCCONTROLHEADED,HC Head Control Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " CHED ,Physical address of head ED on the control ED list"
|
|
line.long 0x04 "HCCONTROLCURRENTED,HC Current Control Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " CCED ,Physical address of current ED on the control ED list"
|
|
line.long 0x08 "HCBULKHEADED,HC Head Bulk Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " BHED ,Physical address of head ED on the bulk ED list"
|
|
line.long 0x0c "HCBULKCURRENTED,HC Current Bulk Register"
|
|
hexmask.long 0x0c 4.--31. 0x10 " BCED ,Physical address of current ED on the bulk ED list"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,HC Head Done Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Physical address of last TD that was added to the Done queue"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,HC Frame Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame interval toggle" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet size for full-speed packets"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame interval"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,HC Frame Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame remaining toggle" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining"
|
|
line.long 0x04 "HCFMNUMBER,HC Frame Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame number"
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "HCPERIODICSTART,HC Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic start"
|
|
line.long 0x04 "HCLSTHRESHOLD,HC Low-speed Threshold Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " LST ,Low-speed threshold"
|
|
line.long 0x08 "HCRHDESCRIPTORA,HC Root Hub A Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " POTPG ,Power-on to power-good time"
|
|
bitfld.long 0x08 12. " NOCP ,No overcurrent protection" "Protection,No protection"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OCPM ,Overcurrent protection mode" "0,1"
|
|
bitfld.long 0x08 10. " DT ,Device type" "Not compound,?..."
|
|
textline " "
|
|
bitfld.long 0x08 9. " NPS ,No power switching" "Supported,Not supported"
|
|
bitfld.long 0x08 8. " PSM ,Power switching mode" "Global,Individual"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " NDP ,Number of downstream ports"
|
|
line.long 0x0c "HCRHDESCRIPTORB,HC Root Hub B Register"
|
|
bitfld.long 0x0c 19. " PPCM[3] ,Gange D-power mask on port #3" "Global,Port"
|
|
bitfld.long 0x0c 18. " PPCM[2] ,Gange D-power mask on port #2" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " PPCM[1] ,Gange D-power mask on port #1" "Global,Port"
|
|
bitfld.long 0x0c 3. " DR[3] ,Device attached to port #3" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " DR[2] ,Device attached to port #2" "Removable,Not removable"
|
|
bitfld.long 0x0c 1. " DR[1] ,Device attached to port #1" "Removable,Not removable"
|
|
line.long 0x10 "HCRHSTATUS,HC Root Hub Status Register"
|
|
bitfld.long 0x10 31. " CRWE ,Clear remote wake-up enable" "No effect,Cleared"
|
|
eventfld.long 0x10 17. " OCIC ,Overcurrent indication change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 16. " LPSC ,Local power status change" "No effect,Changed"
|
|
bitfld.long 0x10 15. " DRWE ,Device remote wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " OCI ,Overcurrent indicator" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x10 0. " LPS ,Local power status" "No effect,Turned off"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_1,HC Port 1 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "Not changed,Changed"
|
|
bitfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 1 low-speed device attached/clear port power" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 1 power status/set port power" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 1 reset status/set port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI_CSS ,Port 1 overcurrent indicator/clear suspend status" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 1 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 1 status/set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 1 current connection status/clear port enable" "No device,Device"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_2,HC Port 2 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 2 reset status change" "Not changed,Changed"
|
|
bitfld.long 0x00 19. " OCIC ,Port 2 overcurrent indicator change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port 2 suspend status change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 2 enable status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 2 connect status change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 2 low-speed device attached/clear port power" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 2 power status/set port power" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 2 reset status/set port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI_CSS ,Port 2 overcurrent indicator/clear suspend status" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 2 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 2 status/set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 2 current connection status/clear port enable" "No device,Device"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "USB 2.0 OTG"
|
|
base asd:0x01e00000
|
|
width 13.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "REVID,Revision Identification Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CTRLR,Control Register"
|
|
bitfld.long 0x00 4. " RNDIS ,RNDIS mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " UINT ,USB non-PDR interrupt enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,Soft reset" "No effect,Reset"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "STATR,Status Register"
|
|
bitfld.long 0x0 0. " DRVVBUS ,Current DRVVBUS value" "Low,High"
|
|
group.long 0x0c++0x3
|
|
line.long 0x0 "EMUR,Emulation Register"
|
|
bitfld.long 0x0 2. " RT_SEL ,Real-time enable" "Enabled,No effect"
|
|
bitfld.long 0x0 1. " SOFT ,Soft stop" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " FREERUN ,Free run" "No effect,Enabled"
|
|
group.long 0x10++0xf
|
|
line.long 0x0 "MODE,Mode Register"
|
|
bitfld.long 0x0 28.--29. " RX4_MODE ,Receive endpoint 4 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x0 24.--25. " RX3_MODE ,Receive endpoint 3 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " RX2_MODE ,Receive endpoint 2 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x0 16.--17. " RX1_MODE ,Receive endpoint 1 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " TX4_MODE ,Transmit endpoint 4 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x0 8.--9. " TX3_MODE ,Transmit endpoint 3 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
textline " "
|
|
bitfld.long 0x0 4.--5. " TX2_MODE ,Transmit endpoint 2 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
bitfld.long 0x0 0.--1. " TX1_MODE ,Transmit endpoint 1 mode control" "Transparent,RNDIS,CDC,Generic RNDIS"
|
|
line.long 0x4 "AUTOREQ,Auto Request Register"
|
|
bitfld.long 0x4 6.--7. " RX4_AUTREQ ,RX endpoint 4 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req"
|
|
bitfld.long 0x4 4.--5. " RX3_AUTREQ ,RX endpoint 3 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req"
|
|
textline " "
|
|
bitfld.long 0x4 2.--3. " RX2_AUTREQ ,RX endpoint 2 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req"
|
|
bitfld.long 0x4 0.--1. " RX1_AUTREQ ,RX endpoint 1 Auto Req enable" "No auto req,Auto req (EOP),Reserved,Auto req"
|
|
line.long 0x8 "SRPFIXTIME,SRP Fix Time Register"
|
|
line.long 0xc "TEARDOWN,Teardown Register"
|
|
bitfld.long 0xc 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled"
|
|
bitfld.long 0xc 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0xc 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled"
|
|
bitfld.long 0xc 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled"
|
|
bitfld.long 0xc 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "INTSRCR,USB Interrupt Source Register"
|
|
setclrfld.long 0x0 24. 0x4 24. 0x8 24. " USB[8]_set/clr ,DRVVBUS level change caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 23. 0x4 23. 0x8 23. " USB[7]_set/clr ,VBus voltage < VBus Valid Threshold (VBus error) caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 22. 0x4 22. 0x8 22. " USB[6]_set/clr ,SRP detection caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 21. 0x4 21. 0x8 21. " USB[5]_set/clr ,Device disconnection (Valid in Host Mode) caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 20. 0x4 20. 0x8 20. " USB[4]_set/clr ,Device connection (Valid in Host Mode) caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 19. 0x4 19. 0x8 19. " USB[3]_set/clr ,SOF start caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 18. 0x4 18. 0x8 18. " USB[2]_set/clr ,Reset Signaling detection (In Peripheral Mode)/Babble detection (In Host Mode) caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 17. 0x4 17. 0x8 17. " USB[1]_set/clr ,Resume signaling detection caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 16. 0x4 16. 0x8 16. " USB[0]_set/clr ,Suspend Signaling detection caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 12. 0x4 12. 0x8 12. " RX[4]_set/clr ,Receive endpoint 4 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x4 11. 0x8 11. " RX[3]_set/clr ,Receive endpoint 3 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 10. 0x4 10. 0x8 10. " RX[2]_set/clr ,Receive endpoint 2 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " RX[1]_set/clr ,Receive endpoint 1 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " TX[4]_set/clr ,Transmit endpoint 4 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " TX[3]_set/clr ,Transmit endpoint 3 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " TX[2]_set/clr ,Transmit endpoint 2 caused interrupt" "Not caused,Caused"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " TX[1]_set/clr ,Transmit endpoint 1 caused interrupt" "Not caused,Caused"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " EP0_set/clr ,Endpoint 0 interrupt source" "Not caused,Caused"
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "INTMSKR,USB Interrupt Mask Register"
|
|
setclrfld.long 0x0 24. 0x4 24. 0x8 24. " USB[8]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 23. 0x4 23. 0x8 23. " USB[7]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 22. 0x4 22. 0x8 22. " USB[6]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 21. 0x4 21. 0x8 21. " USB[5]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 20. 0x4 20. 0x8 20. " USB[4]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 19. 0x4 19. 0x8 19. " USB[3]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. 0x4 18. 0x8 18. " USB[2]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 17. 0x4 17. 0x8 17. " USB[1]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 16. 0x4 16. 0x8 16. " USB[0]_set/clr ,USB interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 12. 0x4 12. 0x8 12. " RX[4]_set/clr ,Receive endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x4 11. 0x8 11. " RX[3]_set/clr ,Receive endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 10. 0x4 10. 0x8 10. " RX[2]_set/clr ,Receive endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " RX[1]_set/clr ,Receive endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " TX[4]_set/clr ,Transmit endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " TX[3]_set/clr ,Transmit endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " TX[2]_set/clr ,Transmit endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " TX[1]_set/clr ,Transmit endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " EP0_set/clr ,Endpoint 0 interrupt source mask" "Not masked,Masked"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "INTMASKEDR,USB Interrupt Source Masked Register"
|
|
bitfld.long 0x0 24. " USB[8] ,USB interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 23. " USB[7] ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 22. " USB[6] ,USB interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 21. " USB[5] ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 20. " USB[4] ,USB interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 19. " USB[3] ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 18. " USB[2] ,USB interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 17. " USB[1] ,USB interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 16. " USB[0] ,USB interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 12. " RX[4] ,Receive endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 11. " RX[3] ,Receive endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 10. " RX[2] ,Receive endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 9. " RX[1] ,Receive endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 4. " TX[4] ,Transmit endpoint 4 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 3. " TX[3] ,Transmit endpoint 3 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 2. " TX[2] ,Transmit endpoint 2 interrupt source mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TX[1] ,Transmit endpoint 1 interrupt source mask" "Not masked,Masked"
|
|
bitfld.long 0x0 0. " EP0 ,Endpoint 0 interrupt source masked" "Not masked,Masked"
|
|
group.long 0x3c++0x3
|
|
line.long 0x0 "EOIR,USB End of Interrupt Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " VECTOR ,End of Interrupt Vector"
|
|
sif (cpu()!="AM1705"&&cpu()!="AM1707"&&cpu()!="AM1808"&&cpu()!="AM1810"&&cpu()!="AM1802"&&cpu()!="AM1806")
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "INTVECTR,USB Interrupt Vector Register"
|
|
endif
|
|
sif (cpu()=="AM1705"||cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1810"||cpu()=="AM1802"||cpu()=="AM1806"||cpu()=="DA828"||cpu()=="DA830")
|
|
group.long 0x50++0xf
|
|
else
|
|
group.long 0x80++0xf
|
|
endif
|
|
line.long 0x0 "GENRNDISSZ1,Generic RNDIS EP1 Size Register"
|
|
hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packet size"
|
|
line.long 0x4 "GENRNDISSZ2,Generic RNDIS EP2 Size Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packet size"
|
|
line.long 0x8 "GENRNDISSZ3,Generic RNDIS EP3 Size Register"
|
|
hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packet size"
|
|
line.long 0xc "GENRNDISSZ4,Generic RNDIS EP4 Size Register"
|
|
hexmask.long.tbyte 0xc 0.--16. 1. " EP4_SIZE ,Generic RNDIS packet size"
|
|
width 10.
|
|
tree "Common USB Registers"
|
|
group.byte 0x400++0x1
|
|
line.byte 0x0 "FADDR,Function Address Register"
|
|
hexmask.byte 0x0 0.--6. 1. " FUNCADDR ,7_bit address of the peripheral part of the transaction"
|
|
line.byte 0x1 "POWER,Power Management Register"
|
|
bitfld.byte 0x1 7. " ISOUPDATE ,Waiting for SOF token" "No wait,Wait"
|
|
bitfld.byte 0x1 6. " SOFTCONN ,Soft Connect/Disconnect feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 5. " HSEN ,High-speed mode negotiation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 4. " HSMODE ,High-speed mode" "Full speed,High speed"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " RESET ,Reset" "No reset,Reset"
|
|
bitfld.byte 0x1 2. " RESUME ,Resume in suspend mode" "No resume,Resume"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " SUSPENDM ,Suspend mode" "No effect,Suspend mode"
|
|
bitfld.byte 0x1 0. " ENSUSPM ,SUSPENDM output enable" "Disabled,Enabled"
|
|
rgroup.word 0x402++0x3
|
|
line.word 0x0 "INTRTX,Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4"
|
|
bitfld.word 0x0 4. " EP4TX ,Tx Endpoint 4 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 3. " EP3TX ,Tx Endpoint 3 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 2. " EP2TX ,Tx Endpoint 2 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 1. " EP1TX ,Tx Endpoint 1 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 0. " EP0 ,Endpoint 0 interrupt active" "Not active,Active"
|
|
line.word 0x2 "INTRRX,Interrupt Register for Receive Endpoints 1 to 4"
|
|
bitfld.word 0x02 4. " EP4RX ,Receive Endpoint 4 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 3. " EP3RX ,Receive Endpoint 3 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 2. " EP2RX ,Receive Endpoint 2 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 1. " EP1RX ,Receive Endpoint 1 interrupt active" "Not active,Active"
|
|
group.word 0x406++0x3
|
|
line.word 0x0 "INTRTXE,Interrupt Enable Register for INTRTX"
|
|
bitfld.word 0x0 4. " EP4TX ,Tx Endpoint 4 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 3. " EP3TX ,Tx Endpoint 3 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 2. " EP2TX ,Tx Endpoint 2 interrupt active" "Not active,Active"
|
|
bitfld.word 0x0 1. " EP1TX ,Tx Endpoint 1 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x0 0. " EP0 ,Endpoint 0 interrupt active" "Not active,Active"
|
|
line.word 0x2 "INTRRXE,Interrupt Enable Register for INTRRX"
|
|
bitfld.word 0x02 4. " EP4RX ,Receive Endpoint 4 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 3. " EP3RX ,Receive Endpoint 3 interrupt active" "Not active,Active"
|
|
textline " "
|
|
bitfld.word 0x02 2. " EP2RX ,Receive Endpoint 2 interrupt active" "Not active,Active"
|
|
bitfld.word 0x02 1. " EP1RX ,Receive Endpoint 1 interrupt active" "Not active,Active"
|
|
hgroup.byte 0x40a++0x0
|
|
hide.byte 0x0 "INTRUSB,Interrupt Register for Common USB Interrupts"
|
|
in
|
|
group.byte 0x40b++0x0
|
|
line.byte 0x0 "INTRUSBE,Interrupt Enable Register for INTRUSB"
|
|
bitfld.byte 0x0 7. " VBUSERR ,Vbus error interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " SESSREQ ,Session request interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " DISCON ,Disconnect interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " CONN ,Connect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " SOF ,Start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " RESET_BABBLE ,Reset interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " RESUME ,Resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " SUSPEND ,Suspend interrupt enable" "Disabled,Enabled"
|
|
rgroup.word 0x40c++0x1
|
|
line.word 0x0 "FRAME,Frame Number Register"
|
|
hexmask.word 0x0 0.--10. 1. " FRAMENUMBER ,Last received frame number"
|
|
group.byte 0x40e++0x1
|
|
line.byte 0x0 "INDEX,Index Register for Selecting the Endpoint Status and Control Registers"
|
|
bitfld.byte 0x0 0.--3. " EPSEL ,Endpoint control/status register select" "EP 0,EP 1,EP 2,EP 3,EP 4,?..."
|
|
line.byte 0x1 "TESTMODE,Register to Enable the USB 2.0 Test Modes"
|
|
bitfld.byte 0x1 7. " FORCE_HOST ,Force Host mode" "Normal,Host"
|
|
bitfld.byte 0x1 6. " FIFO_ACCESS ,Transfer packet EP0 Tx FIFO to EP0 Receive FIFO" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.byte 0x1 5. " FORCE_FS ,Force full-speed mode" "Normal,Full speed"
|
|
bitfld.byte 0x1 4. " FORCE_HS ,Force high-speed mode" "Normal,High speed"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " TEST_PACKET ,Test_Packet test mode" "Normal,Test_Packet"
|
|
bitfld.byte 0x1 2. " TEST_K ,Test_K test mode" "Normal,Test_K"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " TEST_J ,Test_J test mode" "Normal,Test_J"
|
|
bitfld.byte 0x1 0. " TEST_SE0_NAK ,Test_SE0_NAK test mode" "Normal,Test_SE0_NAK"
|
|
tree.end
|
|
width 17.
|
|
tree "Indexed Registers"
|
|
if ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word 0x412++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x418++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte 0x41a++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte 0x41b++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte 0x41f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word 0x412++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word 0x418++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte 0x41f++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word 0x410++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word 0x412++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not received,Received"
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word 0x414++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word 0x416++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Enabling AUTOREQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word 0x418++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte 0x41a++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte 0x41b++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte 0x41c++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte 0x41d++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Recieve Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word 0x410++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word 0x412++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word 0x414++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word 0x416++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
else
|
|
group 0x00++0x0
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline "These registers are only available for Endpoints 0-4 choosed by EPSEL in INDEX register"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "FIFOx"
|
|
hgroup.long 0x420++0x3
|
|
hide.long 0x00 "FIFO0,Transmit and Receive FIFO Register for Endpoint 0"
|
|
in
|
|
hgroup.long 0x424++0x3
|
|
hide.long 0x0 "FIFO1,Transmit and Receive FIFO Register for Endpoint 1"
|
|
in
|
|
hgroup.long 0x428++0x3
|
|
hide.long 0x0 "FIFO2,Transmit and Receive FIFO Register for Endpoint 2"
|
|
in
|
|
hgroup.long 0x42c++0x3
|
|
hide.long 0x0 "FIFO3,Transmit and Receive FIFO Register for Endpoint 3"
|
|
in
|
|
hgroup.long 0x430++0x3
|
|
hide.long 0x0 "FIFO4,Transmit and Receive FIFO Register for Endpoint 4"
|
|
in
|
|
tree.end
|
|
width 12.
|
|
if (((d.b(asd:0x01e00000+0x460))&0x84)==0x84)
|
|
group.byte 0x460++0x0 "OTG Device Control"
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Initiate the Host Negotiation when Suspend mode is entered" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
elif (((d.b(asd:0x01e00000+0x460))&0x84)==0x4)
|
|
group.byte 0x460++0x0 "OTG Device Control"
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
elif (((d.b(asd:0x01e00000+0x460))&0x84)==0x80)
|
|
group.byte 0x460++0x0 "OTG Device Control"
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " HOSTREQ ,Initiate the Host Negotiation when Suspend mode is entered" "Not initiated,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
else
|
|
group.byte 0x460++0x0 "OTG Device Control"
|
|
line.byte 0x00 "DEVCTL,OTG Device Control Register"
|
|
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
|
|
endif
|
|
if (((data.byte(asd:0x01e00000+0x462))&(0x10))==0x0)
|
|
group.byte 0x462++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144"
|
|
else
|
|
group.byte 0x462++0x0 "Dynamic FIFO Control"
|
|
line.byte 0x00 "TXFIFOSZ,Transmit Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288"
|
|
endif
|
|
if (((data.byte(asd:0x01e00000+0x463))&0x10)==0x0)
|
|
group.byte 0x463++0x0
|
|
line.byte 0x00 "RXFIFOSZ,Receive Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144"
|
|
else
|
|
group.byte 0x463++0x0
|
|
line.byte 0x00 "RXFIFOSZ,Receive Endpoint FIFO Size"
|
|
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
|
|
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288"
|
|
endif
|
|
group.word 0x464++0x1
|
|
line.word 0x00 "TXFIFOADDR,Transmit Endpoint FIFO Address"
|
|
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
|
|
group.word 0x466++0x1
|
|
line.word 0x00 "RXFIFOADDR,Receive Endpoint FIFO Address"
|
|
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
|
|
rgroup.word 0x46c++0x1
|
|
line.word 0x00 "HWVERS,Hardware Version Register"
|
|
bitfld.word 0x00 15. " RC ,Release Candidate" "Not used,Used"
|
|
hexmask.word.byte 0x00 10.--14. 1. " REVMAJ ,Major version of RTL"
|
|
textline " "
|
|
hexmask.word 0x00 0.--9. 1. " REVMIN ,Minor version of RTL"
|
|
width 12.
|
|
tree "EPTRG0"
|
|
if ((d.b((asd:0x01e00000+0x460))&0x4)==0x4)
|
|
group.byte (0x480)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x480+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x480+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x480)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x480+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x480+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG1"
|
|
if ((d.b((asd:0x01e00000+0x460))&0x4)==0x4)
|
|
group.byte (0x488)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x488+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x488+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x488)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x488+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x488+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG2"
|
|
if ((d.b((asd:0x01e00000+0x460))&0x4)==0x4)
|
|
group.byte (0x490)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x490+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x490+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x490)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x490+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x490+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG3"
|
|
if ((d.b((asd:0x01e00000+0x460))&0x4)==0x4)
|
|
group.byte (0x498)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x498+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x498+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x498)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x498+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x498+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
tree "EPTRG4"
|
|
if ((d.b((asd:0x01e00000+0x460))&0x4)==0x4)
|
|
group.byte (0x4A0)++0x0
|
|
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x4A0+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
|
|
group.byte (0x4A0+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
|
|
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
|
|
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
|
|
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
|
|
else
|
|
hgroup.byte (0x4A0)++0x0
|
|
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
|
|
hgroup.byte (0x4A0+0x2)++0x2
|
|
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
|
|
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
|
|
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
|
|
hgroup.byte (0x4A0+0x6)++0x1
|
|
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
|
|
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
|
|
endif
|
|
tree.end
|
|
group 0x00++0x0 "Control and Status Registers for Endpoints"
|
|
width 17.
|
|
tree "EOCSR0"
|
|
if (((d.b((asd:0x01e00000+0x460))&0x4)==0x4)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x500+0x2)++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x500+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte (0x500+0xa)++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte (0x500+0xb)++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte (0x500+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x500+0x2)++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word (0x500+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte (0x500+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x500)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x500+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x500+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x500+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Enabling AUTOREQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x500+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x500+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x500+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x500+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x500+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x500)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x500+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x500+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x500+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
else
|
|
group 0x00++0x0
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline "These registers are only available for Endpoints 0-4 choosed by EPSEL in INDEX register"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR1"
|
|
if (((d.b((asd:0x01e00000+0x460))&0x4)==0x4)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x510+0x2)++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x510+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte (0x510+0xa)++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte (0x510+0xb)++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte (0x510+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x510+0x2)++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word (0x510+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte (0x510+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x510)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x510+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x510+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x510+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Enabling AUTOREQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x510+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x510+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x510+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x510+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x510+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x510)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x510+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x510+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x510+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
else
|
|
group 0x00++0x0
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline "These registers are only available for Endpoints 0-4 choosed by EPSEL in INDEX register"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR2"
|
|
if (((d.b((asd:0x01e00000+0x460))&0x4)==0x4)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x520+0x2)++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x520+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte (0x520+0xa)++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte (0x520+0xb)++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte (0x520+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x520+0x2)++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word (0x520+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte (0x520+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x520)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x520+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x520+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x520+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Enabling AUTOREQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x520+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x520+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x520+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x520+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x520+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x520)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x520+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x520+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x520+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
else
|
|
group 0x00++0x0
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline "These registers are only available for Endpoints 0-4 choosed by EPSEL in INDEX register"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR3"
|
|
if (((d.b((asd:0x01e00000+0x460))&0x4)==0x4)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x530+0x2)++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x530+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte (0x530+0xa)++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte (0x530+0xb)++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte (0x530+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x530+0x2)++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word (0x530+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte (0x530+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x530)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x530+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x530+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x530+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Enabling AUTOREQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x530+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x530+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x530+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x530+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x530+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x530)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x530+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x530+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x530+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
else
|
|
group 0x00++0x0
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline "These registers are only available for Endpoints 0-4 choosed by EPSEL in INDEX register"
|
|
endif
|
|
tree.end
|
|
tree "EOCSR4"
|
|
if (((d.b((asd:0x01e00000+0x460))&0x4)==0x4)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x540+0x2)++0x1
|
|
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
|
|
bitfld.word 0x00 11. " DISPING ,PING disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
|
|
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x540+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
group.byte (0x540+0xa)++0x0
|
|
line.byte 0x00 "HOST_TYPE0,Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
group.byte (0x540+0xb)++0x0
|
|
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
|
|
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
rgroup.byte (0x540+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x0))
|
|
group.word (0x540+0x2)++0x1
|
|
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
|
|
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
|
|
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
|
|
rgroup.word (0x540+0x8)++0x1
|
|
line.word 0x00 "COUNT0,Count 0 Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
|
|
rgroup.byte (0x540+0xf)++0x0
|
|
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
|
|
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
|
|
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little endian,Big endian"
|
|
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
|
|
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
|
|
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x4)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x540)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x540+0x2)++0x1
|
|
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
|
|
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x540+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x540+0x6)++0x1
|
|
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AUTOREQ ,Enabling AUTOREQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
|
|
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
rgroup.word (0x540+0x8)++0x1
|
|
line.word 0x00 "RXCOUNT,Receive Count Register"
|
|
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
|
|
group.byte (0x540+0xa)++0x0
|
|
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x540+0xb)++0x0
|
|
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
group.byte (0x540+0xc)++0x0
|
|
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
|
|
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,?..."
|
|
group.byte (0x540+0xd)++0x0
|
|
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
|
|
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
|
|
elif ((((d.b((asd:0x01e00000+0x460)))&0x4)==0x0)&&((((d.b((asd:0x01e00000+0x40e)))&0xf)==0x1)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x2)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x3)||(((d.b((asd:0x01e00000+0x40e)))&0xf)==0x4)))
|
|
group.word (0x540)++0x1
|
|
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
|
|
group.word (0x540+0x2)++0x1
|
|
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
|
|
bitfld.word 0x00 15. " AUTOSET ,Enabling the Tx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DMAMODE ,DMA mode (should always be 1)" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
|
|
textline " "
|
|
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
|
|
group.word (0x540+0x4)++0x1
|
|
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
|
|
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
|
|
group.word (0x540+0x6)++0x1
|
|
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
|
|
bitfld.word 0x00 15. " AUTOCLEAR ,Enabling the Rx DMA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
|
|
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
|
|
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
|
|
else
|
|
group 0x00++0x0
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline "These registers are only available for Endpoints 0-4 choosed by EPSEL in INDEX register"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "CDMA Registers"
|
|
rgroup.long 0x1000++0x3
|
|
line.long 0x0 "DMAREVID,CDMA Revision Identification Register"
|
|
group.long 0x1004++0x7
|
|
line.long 0x00 "TDFDQ,CDMA Teardown Free Descriptor Queue Control Register"
|
|
bitfld.long 0x00 12.--13. " TD_DESC_QMGR ,Controls DMA accesses to allocate a ch. teardown descriptor" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TD_DESC_QNUM ,Controls which of the 2K queues should be read to allocate the ch. TD descriptors"
|
|
line.long 0x04 "DMAEMU,CDMA Emulation Control Register"
|
|
bitfld.long 0x04 1. " SOFT ,Emulation mode functionality (upon suspend event)" "Not affected,Logic halted"
|
|
bitfld.long 0x04 0. " FREE ,Free run emulation control" "SOFT,FREE"
|
|
group.long 0x1800++0x3
|
|
line.long 0x00 "TXGCR[0],CDMA Transmit Channel 0 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long 0x1808++0x3
|
|
line.long 0x00 "RXGCR[0],CDMA Receive Channel 0 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
group.long 0x180C++0x3
|
|
line.long 0x00 "RXHPCRA[0],CDMA Receive Channel 0 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
group.long 0x1810++0x3
|
|
line.long 0x00 "RXHPCRB[0],CDMA Receive Channel 0 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1820++0x3
|
|
line.long 0x00 "TXGCR[1],CDMA Transmit Channel 1 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long 0x1828++0x3
|
|
line.long 0x00 "RXGCR[1],CDMA Receive Channel 1 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
group.long 0x182C++0x3
|
|
line.long 0x00 "RXHPCRA[1],CDMA Receive Channel 1 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
group.long 0x1830++0x3
|
|
line.long 0x00 "RXHPCRB[1],CDMA Receive Channel 1 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1840++0x3
|
|
line.long 0x00 "TXGCR[2],CDMA Transmit Channel 2 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long 0x1848++0x3
|
|
line.long 0x00 "RXGCR[2],CDMA Receive Channel 2 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
group.long 0x184C++0x3
|
|
line.long 0x00 "RXHPCRA[2],CDMA Receive Channel 2 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
group.long 0x1850++0x3
|
|
line.long 0x00 "RXHPCRB[2],CDMA Receive Channel 2 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
group.long 0x1860++0x3
|
|
line.long 0x00 "TXGCR[3],CDMA Transmit Channel 3 Global Configuration Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
|
|
group.long 0x1868++0x3
|
|
line.long 0x00 "RXGCR[3],CDMA Receive Channel 3 Global Configuration Register"
|
|
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive operation is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
|
|
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
|
|
group.long 0x186C++0x3
|
|
line.long 0x00 "RXHPCRA[3],CDMA Receive Channel 3 Host Packet Configuration Register A"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
|
|
group.long 0x1870++0x3
|
|
line.long 0x00 "RXHPCRB[3],CDMA Receive Channel 3 Host Packet Configuration Register B"
|
|
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool fourth be used for the second receive buffer"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
|
|
width 16.
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
group.long 0x2C00++0x3
|
|
else
|
|
group.long 0x2000++0x3
|
|
endif
|
|
line.long 0x00 "DMA_SCHED_CTRL,CDMA Scheduler Control Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Enable bit for the scheduler and is encoded" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LAST_ENTRY ,Last valid entry in the scheduler table"
|
|
width 11.
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
group.long 0x2D00++0xff
|
|
else
|
|
group.long 0x2800++0xff
|
|
endif
|
|
line.long 0x0 "WORD[0],CDMA Scheduler Table Word 0 Register"
|
|
bitfld.long 0x0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "WORD[1],CDMA Scheduler Table Word 1 Register"
|
|
bitfld.long 0x4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8 "WORD[2],CDMA Scheduler Table Word 2 Register"
|
|
bitfld.long 0x8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC "WORD[3],CDMA Scheduler Table Word 3 Register"
|
|
bitfld.long 0xC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "WORD[4],CDMA Scheduler Table Word 4 Register"
|
|
bitfld.long 0x10 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x10 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "WORD[5],CDMA Scheduler Table Word 5 Register"
|
|
bitfld.long 0x14 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x14 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "WORD[6],CDMA Scheduler Table Word 6 Register"
|
|
bitfld.long 0x18 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x18 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "WORD[7],CDMA Scheduler Table Word 7 Register"
|
|
bitfld.long 0x1C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x1C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "WORD[8],CDMA Scheduler Table Word 8 Register"
|
|
bitfld.long 0x20 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x20 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x20 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "WORD[9],CDMA Scheduler Table Word 9 Register"
|
|
bitfld.long 0x24 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x24 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x24 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "WORD[10],CDMA Scheduler Table Word 10 Register"
|
|
bitfld.long 0x28 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x28 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "WORD[11],CDMA Scheduler Table Word 11 Register"
|
|
bitfld.long 0x2C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x2C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "WORD[12],CDMA Scheduler Table Word 12 Register"
|
|
bitfld.long 0x30 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x30 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "WORD[13],CDMA Scheduler Table Word 13 Register"
|
|
bitfld.long 0x34 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x34 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "WORD[14],CDMA Scheduler Table Word 14 Register"
|
|
bitfld.long 0x38 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x38 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x38 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x3C "WORD[15],CDMA Scheduler Table Word 15 Register"
|
|
bitfld.long 0x3C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x3C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x40 "WORD[16],CDMA Scheduler Table Word 16 Register"
|
|
bitfld.long 0x40 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x40 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x40 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x44 "WORD[17],CDMA Scheduler Table Word 17 Register"
|
|
bitfld.long 0x44 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x44 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x48 "WORD[18],CDMA Scheduler Table Word 18 Register"
|
|
bitfld.long 0x48 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x48 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x48 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4C "WORD[19],CDMA Scheduler Table Word 19 Register"
|
|
bitfld.long 0x4C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x4C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x50 "WORD[20],CDMA Scheduler Table Word 20 Register"
|
|
bitfld.long 0x50 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x50 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x50 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x54 "WORD[21],CDMA Scheduler Table Word 21 Register"
|
|
bitfld.long 0x54 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x54 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x54 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x58 "WORD[22],CDMA Scheduler Table Word 22 Register"
|
|
bitfld.long 0x58 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x58 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x58 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x58 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x58 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x5C "WORD[23],CDMA Scheduler Table Word 23 Register"
|
|
bitfld.long 0x5C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x5C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x5C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x5C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x5C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x60 "WORD[24],CDMA Scheduler Table Word 24 Register"
|
|
bitfld.long 0x60 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x60 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x60 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x60 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x60 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x64 "WORD[25],CDMA Scheduler Table Word 25 Register"
|
|
bitfld.long 0x64 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x64 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x64 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x64 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x64 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x68 "WORD[26],CDMA Scheduler Table Word 26 Register"
|
|
bitfld.long 0x68 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x68 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x68 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x68 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x68 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x6C "WORD[27],CDMA Scheduler Table Word 27 Register"
|
|
bitfld.long 0x6C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x6C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x6C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x6C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x6C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x70 "WORD[28],CDMA Scheduler Table Word 28 Register"
|
|
bitfld.long 0x70 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x70 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x70 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x70 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x70 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x74 "WORD[29],CDMA Scheduler Table Word 29 Register"
|
|
bitfld.long 0x74 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x74 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x74 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x74 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x74 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x78 "WORD[30],CDMA Scheduler Table Word 30 Register"
|
|
bitfld.long 0x78 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x78 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x78 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x78 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x78 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x7C "WORD[31],CDMA Scheduler Table Word 31 Register"
|
|
bitfld.long 0x7C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x7C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x7C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x7C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x7C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x80 "WORD[32],CDMA Scheduler Table Word 32 Register"
|
|
bitfld.long 0x80 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x80 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x80 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x80 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x80 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x84 "WORD[33],CDMA Scheduler Table Word 33 Register"
|
|
bitfld.long 0x84 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x84 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x84 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x84 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x84 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x84 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x84 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x84 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x88 "WORD[34],CDMA Scheduler Table Word 34 Register"
|
|
bitfld.long 0x88 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x88 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x88 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8C "WORD[35],CDMA Scheduler Table Word 35 Register"
|
|
bitfld.long 0x8C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x8C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x90 "WORD[36],CDMA Scheduler Table Word 36 Register"
|
|
bitfld.long 0x90 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x90 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x90 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x94 "WORD[37],CDMA Scheduler Table Word 37 Register"
|
|
bitfld.long 0x94 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x94 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x94 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x98 "WORD[38],CDMA Scheduler Table Word 38 Register"
|
|
bitfld.long 0x98 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x98 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x98 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x9C "WORD[39],CDMA Scheduler Table Word 39 Register"
|
|
bitfld.long 0x9C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x9C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0x9C 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA0 "WORD[40],CDMA Scheduler Table Word 40 Register"
|
|
bitfld.long 0xA0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA4 "WORD[41],CDMA Scheduler Table Word 41 Register"
|
|
bitfld.long 0xA4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xA8 "WORD[42],CDMA Scheduler Table Word 42 Register"
|
|
bitfld.long 0xA8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xA8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xA8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xAC "WORD[43],CDMA Scheduler Table Word 43 Register"
|
|
bitfld.long 0xAC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xAC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xAC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB0 "WORD[44],CDMA Scheduler Table Word 44 Register"
|
|
bitfld.long 0xB0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB4 "WORD[45],CDMA Scheduler Table Word 45 Register"
|
|
bitfld.long 0xB4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xB8 "WORD[46],CDMA Scheduler Table Word 46 Register"
|
|
bitfld.long 0xB8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xB8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xB8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xBC "WORD[47],CDMA Scheduler Table Word 47 Register"
|
|
bitfld.long 0xBC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xBC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xBC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC0 "WORD[48],CDMA Scheduler Table Word 48 Register"
|
|
bitfld.long 0xC0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC4 "WORD[49],CDMA Scheduler Table Word 49 Register"
|
|
bitfld.long 0xC4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xC8 "WORD[50],CDMA Scheduler Table Word 50 Register"
|
|
bitfld.long 0xC8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xC8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xCC "WORD[51],CDMA Scheduler Table Word 51 Register"
|
|
bitfld.long 0xCC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xCC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xCC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD0 "WORD[52],CDMA Scheduler Table Word 52 Register"
|
|
bitfld.long 0xD0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD4 "WORD[53],CDMA Scheduler Table Word 53 Register"
|
|
bitfld.long 0xD4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xD8 "WORD[54],CDMA Scheduler Table Word 54 Register"
|
|
bitfld.long 0xD8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xD8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xD8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xDC "WORD[55],CDMA Scheduler Table Word 55 Register"
|
|
bitfld.long 0xDC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xDC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xDC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE0 "WORD[56],CDMA Scheduler Table Word 56 Register"
|
|
bitfld.long 0xE0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE4 "WORD[57],CDMA Scheduler Table Word 57 Register"
|
|
bitfld.long 0xE4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xE8 "WORD[58],CDMA Scheduler Table Word 58 Register"
|
|
bitfld.long 0xE8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xE8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xE8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xEC "WORD[59],CDMA Scheduler Table Word 59 Register"
|
|
bitfld.long 0xEC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xEC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xEC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF0 "WORD[60],CDMA Scheduler Table Word 60 Register"
|
|
bitfld.long 0xF0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF0 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF4 "WORD[61],CDMA Scheduler Table Word 61 Register"
|
|
bitfld.long 0xF4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF4 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xF8 "WORD[62],CDMA Scheduler Table Word 62 Register"
|
|
bitfld.long 0xF8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xF8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xF8 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xFC "WORD[63],CDMA Scheduler Table Word 63 Register"
|
|
bitfld.long 0xFC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 24.--27. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 16.--19. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 8.--11. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xFC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
|
|
bitfld.long 0xFC 0.--3. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 17.
|
|
tree "Queue Manager (QMGR) Registers"
|
|
rgroup.long 0x4000++0x3
|
|
line.long 0x00 "QMGRREVID,Queue Manager Revision Identification Register"
|
|
wgroup.long 0x4008++0x3
|
|
line.long 0x00 "DIVERSION,Queue Manager Queue Diversion Register"
|
|
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
|
|
hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number"
|
|
hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number"
|
|
hgroup.long 0x4020++0x03
|
|
hide.long 0x00 "FDBSC0,Queue Manager Free Descriptor/Buffer Starvation Count Register 0"
|
|
in
|
|
hgroup.long 0x4024++0x03
|
|
hide.long 0x00 "FDBSC1,Queue Manager Free Descriptor/Buffer Starvation Count Register 1"
|
|
in
|
|
hgroup.long 0x4028++0x03
|
|
hide.long 0x00 "FDBSC2,Queue Manager Free Descriptor/Buffer Starvation Count Register 2"
|
|
in
|
|
hgroup.long 0x402c++0x03
|
|
hide.long 0x00 "FDBSC3,Queue Manager Free Descriptor/Buffer Starvation Count Register 3"
|
|
in
|
|
group.long 0x4080++0xb
|
|
line.long 0x00 "LRAM0BASE,Queue Manager Linking RAM Region 0 Base Address Register"
|
|
line.long 0x04 "LRAM0SIZE,Queue Manager Linking RAM Region 0 Size Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " REGION0_SIZE ,Number of entries that are contained in the linking RAM region 0"
|
|
line.long 0x08 "LRAM1BASE,Queue Manager Linking RAM Region 1 Base Address Register"
|
|
rgroup.long 0x4090++0xb
|
|
line.long 0x00 "PEND0,Queue Manager Queue Pending Register 0"
|
|
line.long 0x04 "PEND1,Queue Manager Queue Pending Register 1"
|
|
group.long 0x5000++0x7
|
|
line.long 0x00 "QMEMRBASE[0],Queue Manager Memory Region 0 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[0],Queue Manager Memory Region 0 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5010++0x7
|
|
line.long 0x00 "QMEMRBASE[1],Queue Manager Memory Region 1 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[1],Queue Manager Memory Region 1 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5020++0x7
|
|
line.long 0x00 "QMEMRBASE[2],Queue Manager Memory Region 2 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[2],Queue Manager Memory Region 2 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5030++0x7
|
|
line.long 0x00 "QMEMRBASE[3],Queue Manager Memory Region 3 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[3],Queue Manager Memory Region 3 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5040++0x7
|
|
line.long 0x00 "QMEMRBASE[4],Queue Manager Memory Region 4 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[4],Queue Manager Memory Region 4 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5050++0x7
|
|
line.long 0x00 "QMEMRBASE[5],Queue Manager Memory Region 5 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[5],Queue Manager Memory Region 5 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5060++0x7
|
|
line.long 0x00 "QMEMRBASE[6],Queue Manager Memory Region 6 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[6],Queue Manager Memory Region 6 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5070++0x7
|
|
line.long 0x00 "QMEMRBASE[7],Queue Manager Memory Region 7 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[7],Queue Manager Memory Region 7 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5080++0x7
|
|
line.long 0x00 "QMEMRBASE[8],Queue Manager Memory Region 8 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[8],Queue Manager Memory Region 8 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x5090++0x7
|
|
line.long 0x00 "QMEMRBASE[9],Queue Manager Memory Region 9 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[9],Queue Manager Memory Region 9 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50A0++0x7
|
|
line.long 0x00 "QMEMRBASE[10],Queue Manager Memory Region 10 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[10],Queue Manager Memory Region 10 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50B0++0x7
|
|
line.long 0x00 "QMEMRBASE[11],Queue Manager Memory Region 11 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[11],Queue Manager Memory Region 11 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50C0++0x7
|
|
line.long 0x00 "QMEMRBASE[12],Queue Manager Memory Region 12 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[12],Queue Manager Memory Region 12 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50D0++0x7
|
|
line.long 0x00 "QMEMRBASE[13],Queue Manager Memory Region 13 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[13],Queue Manager Memory Region 13 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50E0++0x7
|
|
line.long 0x00 "QMEMRBASE[14],Queue Manager Memory Region 14 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[14],Queue Manager Memory Region 14 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x50F0++0x7
|
|
line.long 0x00 "QMEMRBASE[15],Queue Manager Memory Region 15 Base Address Registers"
|
|
line.long 0x04 "QMEMRCTRL[15],Queue Manager Memory Region 15 Control Registers"
|
|
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Start of index"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
|
|
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
|
|
group.long 0x600C++0x3
|
|
line.long 0x00 "CTRLD[0],Queue Manager Queue 0 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6800++0xb
|
|
line.long 0x00 "QSTATA[0],Queue Manager Queue 0 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[0],Queue Manager Queue 0 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[0],Queue Manager Queue 0 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x601C++0x3
|
|
line.long 0x00 "CTRLD[1],Queue Manager Queue 1 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6810++0xb
|
|
line.long 0x00 "QSTATA[1],Queue Manager Queue 1 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[1],Queue Manager Queue 1 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[1],Queue Manager Queue 1 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x602C++0x3
|
|
line.long 0x00 "CTRLD[2],Queue Manager Queue 2 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6820++0xb
|
|
line.long 0x00 "QSTATA[2],Queue Manager Queue 2 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[2],Queue Manager Queue 2 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[2],Queue Manager Queue 2 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x603C++0x3
|
|
line.long 0x00 "CTRLD[3],Queue Manager Queue 3 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6830++0xb
|
|
line.long 0x00 "QSTATA[3],Queue Manager Queue 3 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[3],Queue Manager Queue 3 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[3],Queue Manager Queue 3 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x604C++0x3
|
|
line.long 0x00 "CTRLD[4],Queue Manager Queue 4 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6840++0xb
|
|
line.long 0x00 "QSTATA[4],Queue Manager Queue 4 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[4],Queue Manager Queue 4 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[4],Queue Manager Queue 4 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x605C++0x3
|
|
line.long 0x00 "CTRLD[5],Queue Manager Queue 5 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6850++0xb
|
|
line.long 0x00 "QSTATA[5],Queue Manager Queue 5 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[5],Queue Manager Queue 5 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[5],Queue Manager Queue 5 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x606C++0x3
|
|
line.long 0x00 "CTRLD[6],Queue Manager Queue 6 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6860++0xb
|
|
line.long 0x00 "QSTATA[6],Queue Manager Queue 6 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[6],Queue Manager Queue 6 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[6],Queue Manager Queue 6 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x607C++0x3
|
|
line.long 0x00 "CTRLD[7],Queue Manager Queue 7 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6870++0xb
|
|
line.long 0x00 "QSTATA[7],Queue Manager Queue 7 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[7],Queue Manager Queue 7 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[7],Queue Manager Queue 7 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x608C++0x3
|
|
line.long 0x00 "CTRLD[8],Queue Manager Queue 8 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6880++0xb
|
|
line.long 0x00 "QSTATA[8],Queue Manager Queue 8 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[8],Queue Manager Queue 8 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[8],Queue Manager Queue 8 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x609C++0x3
|
|
line.long 0x00 "CTRLD[9],Queue Manager Queue 9 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6890++0xb
|
|
line.long 0x00 "QSTATA[9],Queue Manager Queue 9 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[9],Queue Manager Queue 9 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[9],Queue Manager Queue 9 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x60AC++0x3
|
|
line.long 0x00 "CTRLD[10],Queue Manager Queue 10 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68A0++0xb
|
|
line.long 0x00 "QSTATA[10],Queue Manager Queue 10 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[10],Queue Manager Queue 10 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[10],Queue Manager Queue 10 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x60BC++0x3
|
|
line.long 0x00 "CTRLD[11],Queue Manager Queue 11 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68B0++0xb
|
|
line.long 0x00 "QSTATA[11],Queue Manager Queue 11 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[11],Queue Manager Queue 11 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[11],Queue Manager Queue 11 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x60CC++0x3
|
|
line.long 0x00 "CTRLD[12],Queue Manager Queue 12 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68C0++0xb
|
|
line.long 0x00 "QSTATA[12],Queue Manager Queue 12 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[12],Queue Manager Queue 12 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[12],Queue Manager Queue 12 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x60DC++0x3
|
|
line.long 0x00 "CTRLD[13],Queue Manager Queue 13 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68D0++0xb
|
|
line.long 0x00 "QSTATA[13],Queue Manager Queue 13 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[13],Queue Manager Queue 13 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[13],Queue Manager Queue 13 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x60EC++0x3
|
|
line.long 0x00 "CTRLD[14],Queue Manager Queue 14 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68E0++0xb
|
|
line.long 0x00 "QSTATA[14],Queue Manager Queue 14 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[14],Queue Manager Queue 14 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[14],Queue Manager Queue 14 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x60FC++0x3
|
|
line.long 0x00 "CTRLD[15],Queue Manager Queue 15 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x68F0++0xb
|
|
line.long 0x00 "QSTATA[15],Queue Manager Queue 15 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[15],Queue Manager Queue 15 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[15],Queue Manager Queue 15 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x610C++0x3
|
|
line.long 0x00 "CTRLD[16],Queue Manager Queue 16 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6900++0xb
|
|
line.long 0x00 "QSTATA[16],Queue Manager Queue 16 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[16],Queue Manager Queue 16 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[16],Queue Manager Queue 16 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x611C++0x3
|
|
line.long 0x00 "CTRLD[17],Queue Manager Queue 17 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6910++0xb
|
|
line.long 0x00 "QSTATA[17],Queue Manager Queue 17 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[17],Queue Manager Queue 17 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[17],Queue Manager Queue 17 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x612C++0x3
|
|
line.long 0x00 "CTRLD[18],Queue Manager Queue 18 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6920++0xb
|
|
line.long 0x00 "QSTATA[18],Queue Manager Queue 18 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[18],Queue Manager Queue 18 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[18],Queue Manager Queue 18 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x613C++0x3
|
|
line.long 0x00 "CTRLD[19],Queue Manager Queue 19 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6930++0xb
|
|
line.long 0x00 "QSTATA[19],Queue Manager Queue 19 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[19],Queue Manager Queue 19 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[19],Queue Manager Queue 19 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x614C++0x3
|
|
line.long 0x00 "CTRLD[20],Queue Manager Queue 20 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6940++0xb
|
|
line.long 0x00 "QSTATA[20],Queue Manager Queue 20 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[20],Queue Manager Queue 20 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[20],Queue Manager Queue 20 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x615C++0x3
|
|
line.long 0x00 "CTRLD[21],Queue Manager Queue 21 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6950++0xb
|
|
line.long 0x00 "QSTATA[21],Queue Manager Queue 21 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[21],Queue Manager Queue 21 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[21],Queue Manager Queue 21 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x616C++0x3
|
|
line.long 0x00 "CTRLD[22],Queue Manager Queue 22 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6960++0xb
|
|
line.long 0x00 "QSTATA[22],Queue Manager Queue 22 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[22],Queue Manager Queue 22 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[22],Queue Manager Queue 22 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x617C++0x3
|
|
line.long 0x00 "CTRLD[23],Queue Manager Queue 23 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6970++0xb
|
|
line.long 0x00 "QSTATA[23],Queue Manager Queue 23 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[23],Queue Manager Queue 23 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[23],Queue Manager Queue 23 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x618C++0x3
|
|
line.long 0x00 "CTRLD[24],Queue Manager Queue 24 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6980++0xb
|
|
line.long 0x00 "QSTATA[24],Queue Manager Queue 24 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[24],Queue Manager Queue 24 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[24],Queue Manager Queue 24 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x619C++0x3
|
|
line.long 0x00 "CTRLD[25],Queue Manager Queue 25 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6990++0xb
|
|
line.long 0x00 "QSTATA[25],Queue Manager Queue 25 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[25],Queue Manager Queue 25 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[25],Queue Manager Queue 25 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x61AC++0x3
|
|
line.long 0x00 "CTRLD[26],Queue Manager Queue 26 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x69A0++0xb
|
|
line.long 0x00 "QSTATA[26],Queue Manager Queue 26 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[26],Queue Manager Queue 26 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[26],Queue Manager Queue 26 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x61BC++0x3
|
|
line.long 0x00 "CTRLD[27],Queue Manager Queue 27 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x69B0++0xb
|
|
line.long 0x00 "QSTATA[27],Queue Manager Queue 27 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[27],Queue Manager Queue 27 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[27],Queue Manager Queue 27 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x61CC++0x3
|
|
line.long 0x00 "CTRLD[28],Queue Manager Queue 28 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x69C0++0xb
|
|
line.long 0x00 "QSTATA[28],Queue Manager Queue 28 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[28],Queue Manager Queue 28 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[28],Queue Manager Queue 28 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x61DC++0x3
|
|
line.long 0x00 "CTRLD[29],Queue Manager Queue 29 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x69D0++0xb
|
|
line.long 0x00 "QSTATA[29],Queue Manager Queue 29 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[29],Queue Manager Queue 29 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[29],Queue Manager Queue 29 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x61EC++0x3
|
|
line.long 0x00 "CTRLD[30],Queue Manager Queue 30 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x69E0++0xb
|
|
line.long 0x00 "QSTATA[30],Queue Manager Queue 30 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[30],Queue Manager Queue 30 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[30],Queue Manager Queue 30 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x61FC++0x3
|
|
line.long 0x00 "CTRLD[31],Queue Manager Queue 31 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x69F0++0xb
|
|
line.long 0x00 "QSTATA[31],Queue Manager Queue 31 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[31],Queue Manager Queue 31 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[31],Queue Manager Queue 31 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x620C++0x3
|
|
line.long 0x00 "CTRLD[32],Queue Manager Queue 32 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A00++0xb
|
|
line.long 0x00 "QSTATA[32],Queue Manager Queue 32 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[32],Queue Manager Queue 32 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[32],Queue Manager Queue 32 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x621C++0x3
|
|
line.long 0x00 "CTRLD[33],Queue Manager Queue 33 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A10++0xb
|
|
line.long 0x00 "QSTATA[33],Queue Manager Queue 33 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[33],Queue Manager Queue 33 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[33],Queue Manager Queue 33 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x622C++0x3
|
|
line.long 0x00 "CTRLD[34],Queue Manager Queue 34 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A20++0xb
|
|
line.long 0x00 "QSTATA[34],Queue Manager Queue 34 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[34],Queue Manager Queue 34 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[34],Queue Manager Queue 34 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x623C++0x3
|
|
line.long 0x00 "CTRLD[35],Queue Manager Queue 35 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A30++0xb
|
|
line.long 0x00 "QSTATA[35],Queue Manager Queue 35 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[35],Queue Manager Queue 35 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[35],Queue Manager Queue 35 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x624C++0x3
|
|
line.long 0x00 "CTRLD[36],Queue Manager Queue 36 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A40++0xb
|
|
line.long 0x00 "QSTATA[36],Queue Manager Queue 36 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[36],Queue Manager Queue 36 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[36],Queue Manager Queue 36 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x625C++0x3
|
|
line.long 0x00 "CTRLD[37],Queue Manager Queue 37 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A50++0xb
|
|
line.long 0x00 "QSTATA[37],Queue Manager Queue 37 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[37],Queue Manager Queue 37 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[37],Queue Manager Queue 37 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x626C++0x3
|
|
line.long 0x00 "CTRLD[38],Queue Manager Queue 38 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A60++0xb
|
|
line.long 0x00 "QSTATA[38],Queue Manager Queue 38 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[38],Queue Manager Queue 38 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[38],Queue Manager Queue 38 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x627C++0x3
|
|
line.long 0x00 "CTRLD[39],Queue Manager Queue 39 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A70++0xb
|
|
line.long 0x00 "QSTATA[39],Queue Manager Queue 39 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[39],Queue Manager Queue 39 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[39],Queue Manager Queue 39 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x628C++0x3
|
|
line.long 0x00 "CTRLD[40],Queue Manager Queue 40 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A80++0xb
|
|
line.long 0x00 "QSTATA[40],Queue Manager Queue 40 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[40],Queue Manager Queue 40 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[40],Queue Manager Queue 40 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x629C++0x3
|
|
line.long 0x00 "CTRLD[41],Queue Manager Queue 41 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6A90++0xb
|
|
line.long 0x00 "QSTATA[41],Queue Manager Queue 41 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[41],Queue Manager Queue 41 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[41],Queue Manager Queue 41 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x62AC++0x3
|
|
line.long 0x00 "CTRLD[42],Queue Manager Queue 42 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6AA0++0xb
|
|
line.long 0x00 "QSTATA[42],Queue Manager Queue 42 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[42],Queue Manager Queue 42 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[42],Queue Manager Queue 42 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x62BC++0x3
|
|
line.long 0x00 "CTRLD[43],Queue Manager Queue 43 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6AB0++0xb
|
|
line.long 0x00 "QSTATA[43],Queue Manager Queue 43 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[43],Queue Manager Queue 43 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[43],Queue Manager Queue 43 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x62CC++0x3
|
|
line.long 0x00 "CTRLD[44],Queue Manager Queue 44 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6AC0++0xb
|
|
line.long 0x00 "QSTATA[44],Queue Manager Queue 44 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[44],Queue Manager Queue 44 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[44],Queue Manager Queue 44 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x62DC++0x3
|
|
line.long 0x00 "CTRLD[45],Queue Manager Queue 45 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6AD0++0xb
|
|
line.long 0x00 "QSTATA[45],Queue Manager Queue 45 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[45],Queue Manager Queue 45 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[45],Queue Manager Queue 45 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x62EC++0x3
|
|
line.long 0x00 "CTRLD[46],Queue Manager Queue 46 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6AE0++0xb
|
|
line.long 0x00 "QSTATA[46],Queue Manager Queue 46 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[46],Queue Manager Queue 46 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[46],Queue Manager Queue 46 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x62FC++0x3
|
|
line.long 0x00 "CTRLD[47],Queue Manager Queue 47 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6AF0++0xb
|
|
line.long 0x00 "QSTATA[47],Queue Manager Queue 47 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[47],Queue Manager Queue 47 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[47],Queue Manager Queue 47 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x630C++0x3
|
|
line.long 0x00 "CTRLD[48],Queue Manager Queue 48 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B00++0xb
|
|
line.long 0x00 "QSTATA[48],Queue Manager Queue 48 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[48],Queue Manager Queue 48 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[48],Queue Manager Queue 48 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x631C++0x3
|
|
line.long 0x00 "CTRLD[49],Queue Manager Queue 49 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B10++0xb
|
|
line.long 0x00 "QSTATA[49],Queue Manager Queue 49 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[49],Queue Manager Queue 49 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[49],Queue Manager Queue 49 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x632C++0x3
|
|
line.long 0x00 "CTRLD[50],Queue Manager Queue 50 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B20++0xb
|
|
line.long 0x00 "QSTATA[50],Queue Manager Queue 50 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[50],Queue Manager Queue 50 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[50],Queue Manager Queue 50 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x633C++0x3
|
|
line.long 0x00 "CTRLD[51],Queue Manager Queue 51 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B30++0xb
|
|
line.long 0x00 "QSTATA[51],Queue Manager Queue 51 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[51],Queue Manager Queue 51 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[51],Queue Manager Queue 51 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x634C++0x3
|
|
line.long 0x00 "CTRLD[52],Queue Manager Queue 52 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B40++0xb
|
|
line.long 0x00 "QSTATA[52],Queue Manager Queue 52 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[52],Queue Manager Queue 52 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[52],Queue Manager Queue 52 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x635C++0x3
|
|
line.long 0x00 "CTRLD[53],Queue Manager Queue 53 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B50++0xb
|
|
line.long 0x00 "QSTATA[53],Queue Manager Queue 53 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[53],Queue Manager Queue 53 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[53],Queue Manager Queue 53 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x636C++0x3
|
|
line.long 0x00 "CTRLD[54],Queue Manager Queue 54 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B60++0xb
|
|
line.long 0x00 "QSTATA[54],Queue Manager Queue 54 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[54],Queue Manager Queue 54 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[54],Queue Manager Queue 54 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x637C++0x3
|
|
line.long 0x00 "CTRLD[55],Queue Manager Queue 55 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B70++0xb
|
|
line.long 0x00 "QSTATA[55],Queue Manager Queue 55 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[55],Queue Manager Queue 55 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[55],Queue Manager Queue 55 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x638C++0x3
|
|
line.long 0x00 "CTRLD[56],Queue Manager Queue 56 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B80++0xb
|
|
line.long 0x00 "QSTATA[56],Queue Manager Queue 56 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[56],Queue Manager Queue 56 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[56],Queue Manager Queue 56 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x639C++0x3
|
|
line.long 0x00 "CTRLD[57],Queue Manager Queue 57 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6B90++0xb
|
|
line.long 0x00 "QSTATA[57],Queue Manager Queue 57 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[57],Queue Manager Queue 57 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[57],Queue Manager Queue 57 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x63AC++0x3
|
|
line.long 0x00 "CTRLD[58],Queue Manager Queue 58 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6BA0++0xb
|
|
line.long 0x00 "QSTATA[58],Queue Manager Queue 58 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[58],Queue Manager Queue 58 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[58],Queue Manager Queue 58 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x63BC++0x3
|
|
line.long 0x00 "CTRLD[59],Queue Manager Queue 59 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6BB0++0xb
|
|
line.long 0x00 "QSTATA[59],Queue Manager Queue 59 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[59],Queue Manager Queue 59 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[59],Queue Manager Queue 59 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x63CC++0x3
|
|
line.long 0x00 "CTRLD[60],Queue Manager Queue 60 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6BC0++0xb
|
|
line.long 0x00 "QSTATA[60],Queue Manager Queue 60 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[60],Queue Manager Queue 60 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[60],Queue Manager Queue 60 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x63DC++0x3
|
|
line.long 0x00 "CTRLD[61],Queue Manager Queue 61 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6BD0++0xb
|
|
line.long 0x00 "QSTATA[61],Queue Manager Queue 61 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[61],Queue Manager Queue 61 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[61],Queue Manager Queue 61 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x63EC++0x3
|
|
line.long 0x00 "CTRLD[62],Queue Manager Queue 62 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6BE0++0xb
|
|
line.long 0x00 "QSTATA[62],Queue Manager Queue 62 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[62],Queue Manager Queue 62 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[62],Queue Manager Queue 62 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
group.long 0x63FC++0x3
|
|
line.long 0x00 "CTRLD[63],Queue Manager Queue 63 Control Register D"
|
|
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
|
|
bitfld.long 0x00 0.--4. " DESC_SIZE ,The descriptor size is encoded in 4-byte increments" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
|
|
rgroup.long 0x6BF0++0xb
|
|
line.long 0x00 "QSTATA[63],Queue Manager Queue 63 Status Register A"
|
|
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
|
|
line.long 0x04 "QSTATB[63],Queue Manager Queue 63 Status Register B"
|
|
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
|
|
line.long 0x08 "QSTATC[63],Queue Manager Queue 63 Status Register C"
|
|
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Number of packets currently queued on the queue"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "HPI (Host Port Interface)"
|
|
base asd:0x01e10000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "PWREMU_MGMT,Power and Emulation Management Register"
|
|
bitfld.long 0x00 1. " SOFT ,Emulation mode functionality of the HPI" "Not affected,Halted"
|
|
bitfld.long 0x00 0. " FREE ,Free run emulation control" "SOFT control,Free run"
|
|
group.long 0x0c++0x13
|
|
line.long 0x00 "GPIO_EN,GPIO Enable Register"
|
|
bitfld.long 0x00 8. " GPIOEN8 ,Enable as GPIO for UHPI_HD[15:8] pins" "HPI,GPIO"
|
|
bitfld.long 0x00 7. " GPIOEN7 ,Enable as GPIO for UHPI_HD[7:0] pins" "HPI,GPIO"
|
|
bitfld.long 0x00 6. " GPIOEN6 ,Enable as GPIO for /UHPI_HINT pin" "HPI,GPIO"
|
|
bitfld.long 0x00 5. " GPIOEN5 ,Enable as GPIO for UHPI_HRDY pin" "HPI,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPIOEN4 ,Enable as GPIO for UHPI_HHWIL pin" "HPI,GPIO"
|
|
bitfld.long 0x00 2. " GPIOEN2 ,Enable as GPIO for /UHPI_HAS pin" "HPI,GPIO"
|
|
bitfld.long 0x00 1. " GPIOEN1 ,Enable as GPIO for UHPI_HCNTL[1:0] pins" "HPI,GPIO"
|
|
bitfld.long 0x00 0. " GPIOEN0 ,Enable as GPIO for /UHPI_HCS /UHPI_HDS1 /UHPI_HDS2 UHPI_HR/W pins" "HPI,GPIO"
|
|
line.long 0x04 "GPIO_DIR1,GPIO Direction 1 Register"
|
|
bitfld.long 0x04 15. " HD15 ,Direction control for UHPI_HD15 pin" "Input,Output"
|
|
bitfld.long 0x04 14. " HD14 ,Direction control for UHPI_HD14 pin" "Input,Output"
|
|
bitfld.long 0x04 13. " HD13 ,Direction control for UHPI_HD13 pin" "Input,Output"
|
|
bitfld.long 0x04 12. " HD12 ,Direction control for UHPI_HD12 pin" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HD11 ,Direction control for UHPI_HD11 pin" "Input,Output"
|
|
bitfld.long 0x04 10. " HD10 ,Direction control for UHPI_HD10 pin" "Input,Output"
|
|
bitfld.long 0x04 9. " HD9 ,Direction control for UHPI_HD9 pin" "Input,Output"
|
|
bitfld.long 0x04 8. " HD8 ,Direction control for UHPI_HD8 pin" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HD7 ,Direction control for UHPI_HD7 pin" "Input,Output"
|
|
bitfld.long 0x04 6. " HD6 ,Direction control for UHPI_HD6 pin" "Input,Output"
|
|
bitfld.long 0x04 5. " HD5 ,Direction control for UHPI_HD5 pin" "Input,Output"
|
|
bitfld.long 0x04 4. " HD4 ,Direction control for UHPI_HD4 pin" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HD3 ,Direction control for UHPI_HD3 pin" "Input,Output"
|
|
bitfld.long 0x04 2. " HD2 ,Direction control for UHPI_HD2 pin" "Input,Output"
|
|
bitfld.long 0x04 1. " HD1 ,Direction control for UHPI_HD1 pin" "Input,Output"
|
|
bitfld.long 0x04 0. " HD0 ,Direction control for UHPI_HD0 pin" "Input,Output"
|
|
line.long 0x08 "GPIO_DAT1,GPIO Data 1 Register"
|
|
bitfld.long 0x08 15. " HD15 ,Data read from/written to UHPI_HD15 pin" "R,W"
|
|
bitfld.long 0x08 14. " HD14 ,Data read from/written to UHPI_HD14 pin" "R,W"
|
|
bitfld.long 0x08 13. " HD13 ,Data read from/written to UHPI_HD13 pin" "R,W"
|
|
bitfld.long 0x08 12. " HD12 ,Data read from/written to UHPI_HD12 pin" "R,W"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HD11 ,Data read from/written to UHPI_HD11 pin" "R,W"
|
|
bitfld.long 0x08 10. " HD10 ,Data read from/written to UHPI_HD10 pin" "R,W"
|
|
bitfld.long 0x08 9. " HD9 ,Data read from/written to UHPI_HD9 pin" "R,W"
|
|
bitfld.long 0x08 8. " HD8 ,Data read from/written to UHPI_HD8 pin" "R,W"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HD7 ,Data read from/written to UHPI_HD7 pin" "R,W"
|
|
bitfld.long 0x08 6. " HD6 ,Data read from/written to UHPI_HD6 pin" "R,W"
|
|
bitfld.long 0x08 5. " HD5 ,Data read from/written to UHPI_HD5 pin" "R,W"
|
|
bitfld.long 0x08 4. " HD4 ,Data read from/written to UHPI_HD4 pin" "R,W"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HD3 ,Data read from/written to UHPI_HD3 pin" "R,W"
|
|
bitfld.long 0x08 2. " HD2 ,Data read from/written to UHPI_HD2 pin" "R,W"
|
|
bitfld.long 0x08 1. " HD1 ,Data read from/written to UHPI_HD1 pin" "R,W"
|
|
bitfld.long 0x08 0. " HD0 ,Data read from/written to UHPI_HD0 pin" "R,W"
|
|
line.long 0x0c "GPIO_DIR2,GPIO Direction 2 Register"
|
|
bitfld.long 0x0C 9. " HRDY ,Direction control for UHPI_HRDY pin" "Input,Output"
|
|
bitfld.long 0x0C 8. " HINTZ ,Direction control for /UHPI_HINT pin" "Input,Output"
|
|
bitfld.long 0x0C 7. " HCNTL0 ,Direction control for UHPI_HCNTL0 pin" "Input,Output"
|
|
bitfld.long 0x0C 6. " HCNTL1 ,Direction control for UHPI_HCNTL1 pin" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " HHWIL ,Direction control for UHPI_HHWIL pin" "Input,Output"
|
|
bitfld.long 0x0C 4. " HRW ,Direction control for UHPI_HR/W pin" "Input,Output"
|
|
bitfld.long 0x0C 3. " HDS2Z ,Direction control for /UHPI_HDS2 pin" "Input,Output"
|
|
bitfld.long 0x0C 2. " HDS1Z ,Direction control for /UHPI_HDS1 pin" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " HCSZ ,Direction control for /UHPI_HCS pin" "Input,Output"
|
|
bitfld.long 0x0C 0. " HASZ ,Direction control for /UHPI_HAS pin" "Input,Output"
|
|
line.long 0x10 "GPIO_DAT2,GPIO Data 2 Register"
|
|
bitfld.long 0x10 9. " HRDY ,Data read from/written to UHPI_HRDY pin" "R,W"
|
|
bitfld.long 0x10 8. " HINTZ ,Data read from/written to /UHPI_HINT pin" "R,W"
|
|
bitfld.long 0x10 7. " HCNTL0 ,Data read from/written to UHPI_HCNTL0 pin" "R,W"
|
|
bitfld.long 0x10 6. " HCNTL1 ,Data read from/written to UHPI_HCNTL1 pin" "R,W"
|
|
textline " "
|
|
bitfld.long 0x10 5. " HHWIL ,Data read from/written to UHPI_HHWIL pin" "R,W"
|
|
bitfld.long 0x10 4. " HRW ,Data read from/written to UHPI_HR/W pin" "R,W"
|
|
bitfld.long 0x10 3. " HDS2Z ,Data read from/written to /UHPI_HDS2 pin" "R,W"
|
|
bitfld.long 0x10 2. " HDS1Z ,Data read from/written to /UHPI_HDS1 pin" "R,W"
|
|
textline " "
|
|
bitfld.long 0x10 1. " HCSZ ,Data read from/written to /UHPI_HCS pin" "R,W"
|
|
bitfld.long 0x10 0. " HASZ ,Data read from/written to /UHPI_HAS pin" "R,W"
|
|
sif (cpu()!="AM1707")
|
|
group.long 0x20++0x7
|
|
line.long 0x00 "GPIO_DIR3,GPIO Direction 3 Register"
|
|
line.long 0x04 "GPIO_DAT3,GPIO Data 3 Register"
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "HPIC,HPI Control Register"
|
|
bitfld.long 0x00 11. " HPIASEL ,HPI address register select bit" "HPIAW,HPIAR"
|
|
bitfld.long 0x00 9. " DUALHPIA ,Dual-HPIA mode bit" "Single-HPIA,Dual-HPIA"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HWOBSTAT ,HWOB status" "0,1"
|
|
bitfld.long 0x00 7. " HPIRST ,HPI reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FETCH ,Host data fetch command" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " HINT ,Processor-to-host interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSPINT ,Host-to-processor interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " HWOB ,Halfword order" "Most significant,Least significant"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "HPIAW,HPI Address Registers"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "HPIAR,HPI Address Registers"
|
|
width 0xb
|
|
tree.end
|
|
tree "MPU (Memory Protection Unit)"
|
|
tree "MPU 1"
|
|
base asd:0x01E14000
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
line.long 0x04 "CONFIG,Configuration Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ADDR_WIDTH ,Address alignment for range checking"
|
|
bitfld.long 0x04 20.--23. " NUM_FIXED ,Number of fixed address ranges" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " NUM_PROG ,Number of programmable address ranges" "1,2,3,4,5,6,..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " NUM_AIDS ,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 0. " ASSUME_ALLOWED ,Assume allowed" "Disallowed,Allowed"
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "IRAWSTAT,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x00 1. " ADDRERR ,Address violation error" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PROTERR ,Protection violation error" "Disabled,Enabled"
|
|
line.long 0x04 "IENSTAT,Interrupt Enable Status/Clear Register"
|
|
bitfld.long 0x04 1. " ADDRERR ,Addressing violation error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " PROTERR ,Protection violation error interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "IENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x08 1. " ADDRERR_EN ,Addressing violation error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PROTERR_EN ,Protection violation error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0c "IENCLR,Interrupt Enable Clear Register"
|
|
bitfld.long 0x0C 1. " ADDRERR_CLR ,Addressing violation error interrupt clear" "-,Cleared"
|
|
bitfld.long 0x0C 0. " PROTERR_CLR ,Protection violation error interrupt clear" "-,Cleared"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "PROG0_MPSAR,Programmable Range 0 Start Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG0_MPEAR,Programmable Range 0 End Address Registers"
|
|
hexmask.long 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG0_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x210++0x0B
|
|
line.long 0x00 "PROG1_MPSAR,Programmable Range 1 Start Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG1_MPEAR,Programmable Range 1 End Address Registers"
|
|
hexmask.long 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG1_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x220++0x0B
|
|
line.long 0x00 "PROG2_MPSAR,Programmable Range 2 Start Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG2_MPEAR,Programmable Range 2 End Address Registers"
|
|
hexmask.long 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG2_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "PROG3_MPSAR,Programmable Range 3 Start Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG3_MPEAR,Programmable Range 3 End Address Registers"
|
|
hexmask.long 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG3_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x240++0x0B
|
|
line.long 0x00 "PROG4_MPSAR,Programmable Range 4 Start Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG4_MPEAR,Programmable Range 4 End Address Registers"
|
|
hexmask.long 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG4_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x250++0x0B
|
|
line.long 0x00 "PROG5_MPSAR,Programmable Range 5 Start Address Register"
|
|
hexmask.long 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG5_MPEAR,Programmable Range 5 End Address Registers"
|
|
hexmask.long 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG5_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
width 13.
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "MPFAR,Fault Address Register"
|
|
line.long 0x04 "MPFSR,Fault Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MSTID ,Master ID of fault transfer"
|
|
hexmask.long.byte 0x04 9.--12. 1. " PRIVID ,Privilege ID of fault transfer"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " TYPE ,Fault type" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Relaxed cache write back fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Relaxed cache line fill fault"
|
|
wgroup.long 0x308++0x03
|
|
line.long 0x00 "MPFCR,Fault Clear Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Command to clear the current fault" "No effect,Cleared"
|
|
else
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "PROG1_MPSAR,Programmable Range 1 Start Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG1_MPEAR,Programmable Range 1 End Address Registers"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG1_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x210++0x0B
|
|
line.long 0x00 "PROG2_MPSAR,Programmable Range 2 Start Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG2_MPEAR,Programmable Range 2 End Address Registers"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG2_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x220++0x0B
|
|
line.long 0x00 "PROG3_MPSAR,Programmable Range 3 Start Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG3_MPEAR,Programmable Range 3 End Address Registers"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG3_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "PROG4_MPSAR,Programmable Range 4 Start Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG4_MPEAR,Programmable Range 4 End Address Registers"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG4_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x240++0x0B
|
|
line.long 0x00 "PROG5_MPSAR,Programmable Range 5 Start Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG5_MPEAR,Programmable Range 5 End Address Registers"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG5_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x250++0x0B
|
|
line.long 0x00 "PROG6_MPSAR,Programmable Range 6 Start Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG6_MPEAR,Programmable Range 6 End Address Registers"
|
|
hexmask.long.tbyte 0x04 10.--31. 0x400 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG6_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
width 13.
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "FLTADDRR,Fault Address Register"
|
|
line.long 0x04 "FLTSTAT,Fault Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MSTID ,Master ID of fault transfer"
|
|
hexmask.long.byte 0x04 9.--12. 1. " PRIVID ,Privilege ID of fault transfer"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " TYPE ,Fault type" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Relaxed cache write back fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Relaxed cache line fill fault"
|
|
wgroup.long 0x308++0x03
|
|
line.long 0x00 "FLTCLR,Fault Clear Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Command to clear the current fault" "No effect,Cleared"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree "MPU 2"
|
|
base asd:0x01E15000
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "REVID,Revision ID Register"
|
|
line.long 0x04 "CONFIG,Configuration Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ADDR_WIDTH ,Address alignment for range checking"
|
|
bitfld.long 0x04 20.--23. " NUM_FIXED ,Number of fixed address ranges" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " NUM_PROG ,Number of programmable address ranges" "1,2,3,4,5,6,7,8,9,10,11,12,..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " NUM_AIDS ,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 0. " ASSUME_ALLOWED ,Assume allowed" "Disallowed,Allowed"
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "IRAWSTAT,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x00 1. " ADDRERR ,Address violation error" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PROTERR ,Protection violation error" "Disabled,Enabled"
|
|
line.long 0x04 "IENSTAT,Interrupt Enable Status/Clear Register"
|
|
bitfld.long 0x04 1. " ADDRERR ,Addressing violation error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " PROTERR ,Protection violation error interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "IENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x08 1. " ADDRERR_EN ,Addressing violation error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PROTERR_EN ,Protection violation error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0c "IENCLR,Interrupt Enable Clear Register"
|
|
bitfld.long 0x0C 1. " ADDRERR_CLR ,Addressing violation error interrupt clear" "-,Cleared"
|
|
bitfld.long 0x0C 0. " PROTERR_CLR ,Protection violation error interrupt clear" "-,Cleared"
|
|
sif (cpu()=="AM1808"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802"||cpu()=="DA828"||cpu()=="DA830")
|
|
hgroup.long 0x100++0x07
|
|
hide.long 0x00 "FXD_MPSAR,Fixed Range Start Address Register"
|
|
hide.long 0x04 "FXD_MPEAR,Fixed Range End Address Register"
|
|
else
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "FXD_MPSAR,Fixed Range Start Address Register"
|
|
line.long 0x04 "FXD_MPEAR,Fixed Range End Address Register"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FXD_MPPA,Fixed Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x00 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x00 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x00 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x00 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x00 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x00 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x00 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x00 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x00 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x00 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x00 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x00 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x00 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x00 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "PROG0_MPSAR,Programmable Range 0 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG0_MPEAR,Programmable Range 0 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG0_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x210++0x0B
|
|
line.long 0x00 "PROG1_MPSAR,Programmable Range 1 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG1_MPEAR,Programmable Range 1 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG1_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x220++0x0B
|
|
line.long 0x00 "PROG2_MPSAR,Programmable Range 2 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG2_MPEAR,Programmable Range 2 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG2_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "PROG3_MPSAR,Programmable Range 3 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG3_MPEAR,Programmable Range 3 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG3_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x240++0x0B
|
|
line.long 0x00 "PROG4_MPSAR,Programmable Range 4 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG4_MPEAR,Programmable Range 4 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG4_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x250++0x0B
|
|
line.long 0x00 "PROG5_MPSAR,Programmable Range 5 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG5_MPEAR,Programmable Range 5 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG5_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x260++0x0B
|
|
line.long 0x00 "PROG6_MPSAR,Programmable Range 6 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG6_MPEAR,Programmable Range 6 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG6_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x270++0x0B
|
|
line.long 0x00 "PROG7_MPSAR,Programmable Range 7 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG7_MPEAR,Programmable Range 7 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG7_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "PROG8_MPSAR,Programmable Range 8 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG8_MPEAR,Programmable Range 8 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG8_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x290++0x0B
|
|
line.long 0x00 "PROG9_MPSAR,Programmable Range 9 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG9_MPEAR,Programmable Range 9 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG9_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x2A0++0x0B
|
|
line.long 0x00 "PROG10_MPSAR,Programmable Range 10 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG10_MPEAR,Programmable Range 10 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG10_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x2B0++0x0B
|
|
line.long 0x00 "PROG11_MPSAR,Programmable Range 11 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG11_MPEAR,Programmable Range 11 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG11_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
width 13.
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "MPFAR,Fault Address Register"
|
|
line.long 0x04 "MPFSR,Fault Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MSTID ,Master ID of fault transfer"
|
|
hexmask.long.byte 0x04 9.--12. 1. " PRIVID ,Privilege ID of fault transfer"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " TYPE ,Fault type" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Relaxed cache write back fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Relaxed cache line fill fault"
|
|
wgroup.long 0x308++0x03
|
|
line.long 0x00 "MPFCR,Fault Clear Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Command to clear the current fault" "No effect,Cleared"
|
|
else
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "PROG1_MPSAR,Programmable Range 1 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG1_MPEAR,Programmable Range 1 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG1_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x210++0x0B
|
|
line.long 0x00 "PROG2_MPSAR,Programmable Range 2 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG2_MPEAR,Programmable Range 2 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG2_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x220++0x0B
|
|
line.long 0x00 "PROG3_MPSAR,Programmable Range 3 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG3_MPEAR,Programmable Range 3 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG3_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "PROG4_MPSAR,Programmable Range 4 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG4_MPEAR,Programmable Range 4 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG4_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x240++0x0B
|
|
line.long 0x00 "PROG5_MPSAR,Programmable Range 5 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG5_MPEAR,Programmable Range 5 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG5_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x250++0x0B
|
|
line.long 0x00 "PROG6_MPSAR,Programmable Range 6 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG6_MPEAR,Programmable Range 6 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG6_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x260++0x0B
|
|
line.long 0x00 "PROG7_MPSAR,Programmable Range 7 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG7_MPEAR,Programmable Range 7 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG7_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x270++0x0B
|
|
line.long 0x00 "PROG8_MPSAR,Programmable Range 8 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG8_MPEAR,Programmable Range 8 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG8_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "PROG9_MPSAR,Programmable Range 9 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG9_MPEAR,Programmable Range 9 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG9_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x290++0x0B
|
|
line.long 0x00 "PROG10_MPSAR,Programmable Range 10 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG10_MPEAR,Programmable Range 10 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG10_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x2A0++0x0B
|
|
line.long 0x00 "PROG11_MPSAR,Programmable Range 11 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG11_MPEAR,Programmable Range 11 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG11_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
group.long 0x2B0++0x0B
|
|
line.long 0x00 "PROG12_MPSAR,Programmable Range 12 Start Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " START_ADDR ,Start address for range N"
|
|
line.long 0x04 "PROG12_MPEAR,Programmable Range 12 End Address Registers"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " END_ADDR ,End address for range N"
|
|
line.long 0x08 "PROG12_MPPA,Programmable Range Memory Protection Page Attributes Register"
|
|
bitfld.long 0x08 21. " AID11 ,Controls access from ID = 11" "Denied,Granted"
|
|
bitfld.long 0x08 20. " AID10 ,Controls access from ID = 10" "Denied,Granted"
|
|
bitfld.long 0x08 19. " AID9 ,Controls access from ID = 9" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 18. " AID8 ,Controls access from ID = 8" "Denied,Granted"
|
|
bitfld.long 0x08 17. " AID7 ,Controls access from ID = 7" "Denied,Granted"
|
|
bitfld.long 0x08 16. " AID6 ,Controls access from ID = 6" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x08 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x08 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " AID2 ,Controls access from ID =2" "Denied,Granted"
|
|
bitfld.long 0x08 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x08 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " AIDX ,Controls access from ID > 11" "Denied,Granted"
|
|
bitfld.long 0x08 5. " SR ,Supervisor Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 4. " SW ,Supervisor Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SX ,Supervisor Execute permission" "Denied,Allowed"
|
|
bitfld.long 0x08 2. " UR ,User Read permission" "Denied,Allowed"
|
|
bitfld.long 0x08 1. " UW ,User Write permission" "Denied,Allowed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UX ,User Execute permission" "Denied,Allowed"
|
|
width 13.
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "FLTADDRR,Fault Address Register"
|
|
line.long 0x04 "FLTSTAT,Fault Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MSTID ,Master ID of fault transfer"
|
|
hexmask.long.byte 0x04 9.--12. 1. " PRIVID ,Privilege ID of fault transfer"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " TYPE ,Fault type" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Relaxed cache write back fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Relaxed cache line fill fault"
|
|
wgroup.long 0x308++0x03
|
|
line.long 0x00 "FLTCLR,Fault Clear Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Command to clear the current fault" "No effect,Cleared"
|
|
endif
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "PSC (Power and Sleep Controller)"
|
|
tree "PSC 0"
|
|
base asd:0x01c10000
|
|
width 10.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INTEVAL,Interrupt Evaluation Register"
|
|
bitfld.long 0x00 0. " ALLEV ,Evaluate PSC interrupt" "No effect,Re-evaluated"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MERRPR0,Module Error Pending Register 0"
|
|
sif (CPU()=="AM1808"||CPU()=="AM1707"||CPU()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 14. " M[14] ,Module interrupt status bit for module 14" "No error,Error"
|
|
elif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x00 15. " M[15] ,Module interrupt status bit for module 15" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 15. " M[15] ,Module interrupt status bit for module 15" "No error,Error"
|
|
bitfld.long 0x00 14. " M[14] ,Module interrupt status bit for module 14" "No error,Error"
|
|
endif
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "MERRCR0,Module Error Clear Register 0"
|
|
sif (CPU()=="AM1808"||CPU()=="AM1707"||CPU()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
bitfld.long 0x00 14. " M[14] ,Module interrupt clear bit for modules 14" "No effect,Clear"
|
|
elif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x00 15. " M[15] ,Module interrupt status bit for module 15" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 15. " M[15] ,Module interrupt clear bit for modules 15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " M[14] ,Module interrupt clear bit for modules 14" "No effect,Clear"
|
|
endif
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "PERRPR,Power Error Pending Register"
|
|
bitfld.long 0x00 1. " P[1] ,RAM/Pseudo (PD1) power domain interrupt status" "No error,Error"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "PERRCR,Power Error Clear Register"
|
|
bitfld.long 0x00 1. " P[1] ,Clears the interrupt status bit" "No effect,Clear"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PTCMD,Power Domain Transition Command Register"
|
|
bitfld.long 0x00 1. " GO[1] , RAM/Pseudo (PD1) power domain GO transition command" "No effect,Next state"
|
|
bitfld.long 0x00 0. " GO[0] , AlwaysOn Power domain GO transition command" "No effect,Next state"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "PTSTAT,Power Domain Transition Status Register"
|
|
bitfld.long 0x00 1. " GOSTAT[1] ,RAM/Pseudo (PD1) power domain transition status" "Not in progress,In progress"
|
|
bitfld.long 0x00 0. " GOSTAT[0] ,AlwaysOn Power domain transition status" "Not in progress,In progress"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "PDSTAT0,Power Domain Status 0 Register"
|
|
bitfld.long 0x00 11. " EMUIHB ,Emulation alters domain state" "Not active,Active"
|
|
bitfld.long 0x00 9. " PORDONE ,Power_On_Reset done status" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POR ,Power domain Power_On_Reset status" "Asserted,Not asserted"
|
|
bitfld.long 0x00 0.--4. " STATE ,Power domain status" "Off,On,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,?..."
|
|
line.long 0x04 "PDSTAT1,Power Domain Status 1 Register"
|
|
bitfld.long 0x04 11. " EMUIHB ,Emulation alters domain state" "Not active,Active"
|
|
bitfld.long 0x04 9. " PORDONE ,Power_On_Reset done status" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 8. " POR ,Power domain Power_On_Reset status" "Asserted,Not asserted"
|
|
bitfld.long 0x04 0.--4. " STATE ,Power domain status" "Off,On,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,?..."
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "PDCTL0,Power Domain Control 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WAKECNT ,RAM wake count delay value"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PDMODE ,Power down mode" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Core on. RAM array on. RAM periphery on"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMUIHBIE ,Emulation alters power domain state interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NEXT ,Power domain next state" "Off,On"
|
|
line.long 0x04 "PDCTL1,Power Domain Control 1 Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " WAKECNT ,RAM wake count delay value"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " PDMODE ,Power down mode (Core/RAM array/RAM periphery)" "Off/Off/Off,Off/Retention/Off(deep sleep),Reserved,Reserved,Retention/Off/Off,Retention/Retention/Off(deep sleep),Reserved,Reserved,On/Off/Off,On/Retention/Off(deep sleep),On/Retention/Off(light sleep),On/Retention/On,Reserved,Reserved,Reserved,On/On/On"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EMUIHBIE ,Emulation alters power domain state interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " NEXT ,Power domain next state" "Off,On"
|
|
rgroup.long 0x400++0x07
|
|
line.long 0x00 "PDCFG0,Power Domain 0 Configuration Register"
|
|
bitfld.long 0x00 3. " PD_LOCK ,PDCTL.NEXT lock" "Locked,Not locked"
|
|
bitfld.long 0x00 2. " ICEPICK ,IcePick support" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAM_PSM ,RAM power domain" "Not RAM,RAM"
|
|
bitfld.long 0x00 0. " ALWAYSON ,Always ON power domain" "Not Always ON,Always ON"
|
|
line.long 0x04 "PDCFG1,Power Domain 1 Configuration Register"
|
|
bitfld.long 0x04 3. " PD_LOCK ,PDCTL.NEXT lock" "Locked,Not locked"
|
|
bitfld.long 0x04 2. " ICEPICK ,IcePick support" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RAM_PSM ,RAM power domain" "Not RAM,RAM"
|
|
bitfld.long 0x04 0. " ALWAYSON ,Always ON power domain" "Not Always ON,Always ON"
|
|
rgroup.long 0x800++0x3f
|
|
line.long 0x0 "MDSTAT0,Module Status 0 Register"
|
|
bitfld.long 0x0 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x0 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x0 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x4 "MDSTAT1,Module Status 1 Register"
|
|
bitfld.long 0x4 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x4 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x4 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x8 "MDSTAT2,Module Status 2 Register"
|
|
bitfld.long 0x8 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x8 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x8 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0xC "MDSTAT3,Module Status 3 Register"
|
|
bitfld.long 0xC 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0xC 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0xC 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x10 "MDSTAT4,Module Status 4 Register"
|
|
bitfld.long 0x10 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x10 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x10 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x14 "MDSTAT5,Module Status 5 Register"
|
|
bitfld.long 0x14 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x14 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x14 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x18 "MDSTAT6,Module Status 6 Register"
|
|
bitfld.long 0x18 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x18 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x18 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x1C "MDSTAT7,Module Status 7 Register"
|
|
bitfld.long 0x1C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x1C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x20 "MDSTAT8,Module Status 8 Register"
|
|
bitfld.long 0x20 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x20 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x20 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x24 "MDSTAT9,Module Status 9 Register"
|
|
bitfld.long 0x24 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x24 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x24 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x28 "MDSTAT10,Module Status 10 Register"
|
|
bitfld.long 0x28 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x28 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x28 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x2C "MDSTAT11,Module Status 11 Register"
|
|
bitfld.long 0x2C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x2C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x30 "MDSTAT12,Module Status 12 Register"
|
|
bitfld.long 0x30 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x30 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x30 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x34 "MDSTAT13,Module Status 13 Register"
|
|
bitfld.long 0x34 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x34 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x34 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
line.long 0x38 "MDSTAT14,Module Status 14 Register"
|
|
bitfld.long 0x38 17. " EMUIHB ,Emulation alters module state" "No emulation,Emulation"
|
|
bitfld.long 0x38 16. " EMURST ,Emulation alters module reset" "No emulation,Emulation"
|
|
textline " "
|
|
bitfld.long 0x38 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x38 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " LRSTDONE ,Local reset done" "Not done,Done"
|
|
bitfld.long 0x38 8. " LRST ,Module local reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x38 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x3c "MDSTAT15,Module Status 15 Register"
|
|
bitfld.long 0x3c 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x3c 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
else
|
|
line.long 0x38 "MDSTAT14,Module Status 14 Register"
|
|
bitfld.long 0x38 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x38 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x38 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x3c "MDSTAT15,Module Status 15 Register"
|
|
bitfld.long 0x3c 17. " EMUIHB ,Emulation alters module state" "No emulation,Emulation"
|
|
bitfld.long 0x3c 16. " EMURST ,Emulation alters module reset" "No emulation,Emulation"
|
|
textline " "
|
|
bitfld.long 0x3c 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x3c 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x3c 9. " LRSTDONE ,Local reset done" "Not done,Done"
|
|
bitfld.long 0x3c 8. " LRST ,Module local reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
endif
|
|
group.long 0xA00++0x3f
|
|
line.long 0x0 "MDCTL0,Module Control 0 Register"
|
|
bitfld.long 0x0 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x4 "MDCTL1,Module Control 1 Register"
|
|
bitfld.long 0x4 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x8 "MDCTL2,Module Control 2 Register"
|
|
bitfld.long 0x8 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0xC "MDCTL3,Module Control 3 Register"
|
|
bitfld.long 0xC 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x10 "MDCTL4,Module Control 4 Register"
|
|
bitfld.long 0x10 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x14 "MDCTL5,Module Control 5 Register"
|
|
bitfld.long 0x14 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x18 "MDCTL6,Module Control 6 Register"
|
|
bitfld.long 0x18 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x1C "MDCTL7,Module Control 7 Register"
|
|
bitfld.long 0x1C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x20 "MDCTL8,Module Control 8 Register"
|
|
bitfld.long 0x20 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x24 "MDCTL9,Module Control 9 Register"
|
|
bitfld.long 0x24 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x28 "MDCTL10,Module Control 10 Register"
|
|
bitfld.long 0x28 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x2C "MDCTL11,Module Control 11 Register"
|
|
bitfld.long 0x2C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x30 "MDCTL12,Module Control 12 Register"
|
|
bitfld.long 0x30 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x34 "MDCTL13,Module Control 13 Register"
|
|
bitfld.long 0x34 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
line.long 0x38 "MDCTL14,Module Control 14 Register"
|
|
bitfld.long 0x38 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 10. " EMUIHBIE ,Interrupt enable for emulation alters module state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 9. " EMURSTIE ,Interrupt enable for emulation alters reset" "Disabled,Enabled"
|
|
bitfld.long 0x38 8. " LRST ,Module local reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x3c "MDCTL15,Module Control 15 Register"
|
|
bitfld.long 0x3c 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
elif (cpu()=="DA828"||cpu()=="DA830")
|
|
line.long 0x38 "MDCTL14,Module Control 14 Register"
|
|
bitfld.long 0x38 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x3c "MDCTL15,Module Control 15 Register"
|
|
bitfld.long 0x3c 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
bitfld.long 0x3c 10. " EMUIHBIE ,Interrupt enable for emulation alters module state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 9. " EMURSTIE ,Interrupt enable for emulation alters reset" "Disabled,Enabled"
|
|
bitfld.long 0x3c 8. " LRST ,Module local reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
else
|
|
line.long 0x38 "MDCTL14,Module Control 14 Register"
|
|
bitfld.long 0x38 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x3c "MDCTL15,Module Control 15 Register"
|
|
bitfld.long 0x3c 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
bitfld.long 0x3c 10. " EMUIHBIE ,Interrupt enable for emulation alters module state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 9. " EMURSTIE ,Interrupt enable for emulation alters reset" "Disabled,Enabled"
|
|
bitfld.long 0x3c 8. " LRST ,Module local reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "PSC 1"
|
|
base asd:0x01e27000
|
|
width 10.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVID,Revision Identification Register"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INTEVAL,Interrupt Evaluation Register"
|
|
bitfld.long 0x00 0. " ALLEV ,Evaluate PSC interrupt" "No effect,Re-evaluated"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "PERRPR,Power Error Pending Register"
|
|
bitfld.long 0x00 1. " P[1] ,RAM/Pseudo (PD1) power domain interrupt status" "No error,Error"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "PERRCR,Power Error Clear Register"
|
|
bitfld.long 0x00 1. " P[1] ,Clears the interrupt status bit" "No effect,Clear"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PTCMD,Power Domain Transition Command Register"
|
|
bitfld.long 0x00 1. " GO[1] , RAM/Pseudo (PD1) power domain GO transition command" "No effect,Next state"
|
|
bitfld.long 0x00 0. " GO[0] , AlwaysOn Power domain GO transition command" "No effect,Next state"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "PTSTAT,Power Domain Transition Status Register"
|
|
bitfld.long 0x00 1. " GOSTAT[1] ,RAM/Pseudo (PD1) power domain transition status" "Not in progress,In progress"
|
|
bitfld.long 0x00 0. " GOSTAT[0] ,AlwaysOn Power domain transition status" "Not in progress,In progress"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "PDSTAT0,Power Domain Status 0 Register"
|
|
bitfld.long 0x00 11. " EMUIHB ,Emulation alters domain state" "Not active,Active"
|
|
bitfld.long 0x00 9. " PORDONE ,Power_On_Reset done status" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POR ,Power domain Power_On_Reset status" "Asserted,Not asserted"
|
|
bitfld.long 0x00 0.--4. " STATE ,Power domain status" "Off,On,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,?..."
|
|
line.long 0x04 "PDSTAT1,Power Domain Status 1 Register"
|
|
bitfld.long 0x04 11. " EMUIHB ,Emulation alters domain state" "Not active,Active"
|
|
bitfld.long 0x04 9. " PORDONE ,Power_On_Reset done status" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 8. " POR ,Power domain Power_On_Reset status" "Asserted,Not asserted"
|
|
bitfld.long 0x04 0.--4. " STATE ,Power domain status" "Off,On,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,?..."
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "PDCTL0,Power Domain Control 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WAKECNT ,RAM wake count delay value"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PDMODE ,Power down mode" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Core on. RAM array on. RAM periphery on"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMUIHBIE ,Emulation alters power domain state interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NEXT ,Power domain next state" "Off,On"
|
|
line.long 0x04 "PDCTL1,Power Domain Control 1 Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " WAKECNT ,RAM wake count delay value"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " PDMODE ,Power down mode (Core/RAM array/RAM periphery)" "Off/Off/Off,Off/Retention/Off(deep sleep),Reserved,Reserved,Retention/Off/Off,Retention/Retention/Off(deep sleep),Reserved,Reserved,On/Off/Off,On/Retention/Off(deep sleep),On/Retention/Off(light sleep),On/Retention/On,Reserved,Reserved,Reserved,On/On/On"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EMUIHBIE ,Emulation alters power domain state interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " NEXT ,Power domain next state" "Off,On"
|
|
rgroup.long 0x400++0x07
|
|
line.long 0x00 "PDCFG0,Power Domain 0 Configuration Register"
|
|
bitfld.long 0x00 3. " PD_LOCK ,PDCTL.NEXT lock" "Locked,Not locked"
|
|
bitfld.long 0x00 2. " ICEPICK ,IcePick support" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RAM_PSM ,RAM power domain" "Not RAM,RAM"
|
|
bitfld.long 0x00 0. " ALWAYSON ,Always ON power domain" "Not Always ON,Always ON"
|
|
line.long 0x04 "PDCFG1,Power Domain 1 Configuration Register"
|
|
bitfld.long 0x04 3. " PD_LOCK ,PDCTL.NEXT lock" "Locked,Not locked"
|
|
bitfld.long 0x04 2. " ICEPICK ,IcePick support" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RAM_PSM ,RAM power domain" "Not RAM,RAM"
|
|
bitfld.long 0x04 0. " ALWAYSON ,Always ON power domain" "Not Always ON,Always ON"
|
|
rgroup.long 0x800++0x7f
|
|
line.long 0x0 "MDSTAT0,Module Status 0 Register"
|
|
bitfld.long 0x0 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x0 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x0 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x4 "MDSTAT1,Module Status 1 Register"
|
|
bitfld.long 0x4 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x4 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x4 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x8 "MDSTAT2,Module Status 2 Register"
|
|
bitfld.long 0x8 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x8 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x8 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0xC "MDSTAT3,Module Status 3 Register"
|
|
bitfld.long 0xC 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0xC 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0xC 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x10 "MDSTAT4,Module Status 4 Register"
|
|
bitfld.long 0x10 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x10 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x10 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x14 "MDSTAT5,Module Status 5 Register"
|
|
bitfld.long 0x14 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x14 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x14 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x18 "MDSTAT6,Module Status 6 Register"
|
|
bitfld.long 0x18 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x18 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x18 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x1C "MDSTAT7,Module Status 7 Register"
|
|
bitfld.long 0x1C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x1C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x20 "MDSTAT8,Module Status 8 Register"
|
|
bitfld.long 0x20 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x20 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x20 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x24 "MDSTAT9,Module Status 9 Register"
|
|
bitfld.long 0x24 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x24 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x24 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x28 "MDSTAT10,Module Status 10 Register"
|
|
bitfld.long 0x28 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x28 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x28 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x2C "MDSTAT11,Module Status 11 Register"
|
|
bitfld.long 0x2C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x2C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x30 "MDSTAT12,Module Status 12 Register"
|
|
bitfld.long 0x30 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x30 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x30 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x34 "MDSTAT13,Module Status 13 Register"
|
|
bitfld.long 0x34 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x34 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x34 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
line.long 0x38 "MDSTAT14,Module Status 14 Register"
|
|
bitfld.long 0x38 17. " EMUIHB ,Emulation alters module state" "No emulation,Emulation"
|
|
bitfld.long 0x38 16. " EMURST ,Emulation alters module reset" "No emulation,Emulation"
|
|
textline " "
|
|
bitfld.long 0x38 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x38 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " LRSTDONE ,Local reset done" "Not done,Done"
|
|
bitfld.long 0x38 8. " LRST ,Module local reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x38 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x3c "MDSTAT15,Module Status 15 Register"
|
|
bitfld.long 0x3c 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x3c 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
else
|
|
line.long 0x38 "MDSTAT14,Module Status 14 Register"
|
|
bitfld.long 0x38 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x38 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x38 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x3c "MDSTAT15,Module Status 15 Register"
|
|
bitfld.long 0x3c 17. " EMUIHB ,Emulation alters module state" "No emulation,Emulation"
|
|
bitfld.long 0x3c 16. " EMURST ,Emulation alters module reset" "No emulation,Emulation"
|
|
textline " "
|
|
bitfld.long 0x3c 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x3c 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x3c 9. " LRSTDONE ,Local reset done" "Not done,Done"
|
|
bitfld.long 0x3c 8. " LRST ,Module local reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
endif
|
|
line.long 0x40 "MDSTAT16,Module Status 16 Register"
|
|
bitfld.long 0x40 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x40 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x40 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x44 "MDSTAT17,Module Status 17 Register"
|
|
bitfld.long 0x44 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x44 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x44 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x48 "MDSTAT18,Module Status 18 Register"
|
|
bitfld.long 0x48 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x48 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x48 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x4C "MDSTAT19,Module Status 19 Register"
|
|
bitfld.long 0x4C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x4C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x4C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x50 "MDSTAT20,Module Status 20 Register"
|
|
bitfld.long 0x50 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x50 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x50 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x54 "MDSTAT21,Module Status 21 Register"
|
|
bitfld.long 0x54 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x54 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x54 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x58 "MDSTAT22,Module Status 22 Register"
|
|
bitfld.long 0x58 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x58 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x58 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x5C "MDSTAT23,Module Status 23 Register"
|
|
bitfld.long 0x5C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x5C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x5C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x60 "MDSTAT24,Module Status 24 Register"
|
|
bitfld.long 0x60 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x60 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x60 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x64 "MDSTAT25,Module Status 25 Register"
|
|
bitfld.long 0x64 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x64 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x64 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x68 "MDSTAT26,Module Status 26 Register"
|
|
bitfld.long 0x68 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x68 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x68 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x6C "MDSTAT27,Module Status 27 Register"
|
|
bitfld.long 0x6C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x6C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x6C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x70 "MDSTAT28,Module Status 28 Register"
|
|
bitfld.long 0x70 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x70 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x70 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x74 "MDSTAT29,Module Status 29 Register"
|
|
bitfld.long 0x74 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x74 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x74 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x78 "MDSTAT30,Module Status 30 Register"
|
|
bitfld.long 0x78 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x78 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x78 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
line.long 0x7C "MDSTAT31,Module Status 31 Register"
|
|
bitfld.long 0x7C 12. " MCKOUT ,Module clock output status" "Off,On"
|
|
bitfld.long 0x7C 10. " MRST ,Module reset status" "Asserted,Not asserted"
|
|
textline " "
|
|
bitfld.long 0x7C 0.--5. " STATE ,Module state status" "SwRstDisable,SyncReset,Disable,Enable,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition,Transition"
|
|
group.long 0xA00++0x7f
|
|
line.long 0x0 "MDCTL0,Module Control 0 Register"
|
|
bitfld.long 0x0 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x4 "MDCTL1,Module Control 1 Register"
|
|
bitfld.long 0x4 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x8 "MDCTL2,Module Control 2 Register"
|
|
bitfld.long 0x8 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0xC "MDCTL3,Module Control 3 Register"
|
|
bitfld.long 0xC 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x10 "MDCTL4,Module Control 4 Register"
|
|
bitfld.long 0x10 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x14 "MDCTL5,Module Control 5 Register"
|
|
bitfld.long 0x14 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x18 "MDCTL6,Module Control 6 Register"
|
|
bitfld.long 0x18 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x1C "MDCTL7,Module Control 7 Register"
|
|
bitfld.long 0x1C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x20 "MDCTL8,Module Control 8 Register"
|
|
bitfld.long 0x20 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x24 "MDCTL9,Module Control 9 Register"
|
|
bitfld.long 0x24 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x28 "MDCTL10,Module Control 10 Register"
|
|
bitfld.long 0x28 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x2C "MDCTL11,Module Control 11 Register"
|
|
bitfld.long 0x2C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x30 "MDCTL12,Module Control 12 Register"
|
|
bitfld.long 0x30 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x34 "MDCTL13,Module Control 13 Register"
|
|
bitfld.long 0x34 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
sif (cpu()=="AM1707"||cpu()=="AM1808"||cpu()=="AM1705"||CPU()=="AM1806"||CPU()=="AM1810"||CPU()=="AM1802")
|
|
line.long 0x38 "MDCTL14,Module Control 14 Register"
|
|
bitfld.long 0x38 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 10. " EMUIHBIE ,Interrupt enable for emulation alters module state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 9. " EMURSTIE ,Interrupt enable for emulation alters reset" "Disabled,Enabled"
|
|
bitfld.long 0x38 8. " LRST ,Module local reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x3c "MDCTL15,Module Control 15 Register"
|
|
bitfld.long 0x3c 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
elif (cpu()=="DA828"||cpu()=="DA830")
|
|
line.long 0x38 "MDCTL14,Module Control 14 Register"
|
|
bitfld.long 0x38 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x3c "MDCTL15,Module Control 15 Register"
|
|
bitfld.long 0x3c 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
else
|
|
line.long 0x38 "MDCTL14,Module Control 14 Register"
|
|
bitfld.long 0x38 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x3c "MDCTL15,Module Control 15 Register"
|
|
bitfld.long 0x3c 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
bitfld.long 0x3c 10. " EMUIHBIE ,Interrupt enable for emulation alters module state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 9. " EMURSTIE ,Interrupt enable for emulation alters reset" "Disabled,Enabled"
|
|
bitfld.long 0x3c 8. " LRST ,Module local reset control" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x3c 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
endif
|
|
line.long 0x40 "MDCTL16,Module Control 16 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x40 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x40 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x44 "MDCTL17,Module Control 17 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x44 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x44 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x48 "MDCTL18,Module Control 18 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x48 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x48 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x4C "MDCTL19,Module Control 19 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x4C 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x4C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x50 "MDCTL20,Module Control 20 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x50 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x50 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x54 "MDCTL21,Module Control 21 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x54 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x54 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x58 "MDCTL22,Module Control 22 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x58 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x58 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x5C "MDCTL23,Module Control 23 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x5C 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x5C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x60 "MDCTL24,Module Control 24 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x60 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x60 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x64 "MDCTL25,Module Control 25 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x64 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x64 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x68 "MDCTL26,Module Control 26 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x68 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x68 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x6C "MDCTL27,Module Control 27 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x6C 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x6C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x70 "MDCTL28,Module Control 28 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x70 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x70 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x74 "MDCTL29,Module Control 29 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x74 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x74 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x78 "MDCTL30,Module Control 30 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x78 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x78 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
line.long 0x7C "MDCTL31,Module Control 31 Register"
|
|
sif (cpu()=="DA828"||cpu()=="DA830")
|
|
bitfld.long 0x7C 31. " FORCE ,Force enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x7C 0.--2. " NEXT ,Module next state" "SwRstDisable,SyncReset,Disabled,Enabled,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base asd:0x01c23000
|
|
width 0x14
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "SECOND,Seconds Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x00 04.--07. " SEC ,Second" "0,1,2,3,4,5,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 04.--06. " SEC ,Second" "0,1,2,3,4,5,-,-"
|
|
endif
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0004++0x03
|
|
line.long 0x00 "MINUTE,Minutes Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
|
|
bitfld.long 0x00 04.--07. " MIN ,Minute" "0,1,2,3,4,5,-,-,-,-,-,-,-,?..."
|
|
else
|
|
bitfld.long 0x00 04.--06. " MIN ,Minute" "0,1,2,3,4,5,-,-"
|
|
endif
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if ((data.long(asd:0x01c23000+0x40)&0x08)==0x08)&&((data.long(asd:0x01c23000+0x08)&0x30)==0x10)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(asd:0x01c23000+0x40)&0x08)==0x08)&&((data.long(asd:0x01c23000+0x08)&0x30)!=0x10)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(asd:0x01c23000+0x40)&0x08)==0x00)&&((data.long(asd:0x01c23000+0x08)&0x30)==0x20)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "HOUR,Hours Register"
|
|
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(asd:0x01c23000+0x10)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(asd:0x01c23000+0x0c))&0x30)==0x30)
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x10)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(asd:0x01c23000+0x0c))&0x30)!=0x30)
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x10)&0x1f)==0x02))
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x10)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(asd:0x01c23000+0x0c))&0x30)==0x30)
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x000C++0x03
|
|
line.long 0x00 "DAY,Days Register"
|
|
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(asd:0x01c23000+0x10)&0x10)==0x10))
|
|
//MONTH->MONTH[4.]=='1'
|
|
group.long 0x0010++0x03
|
|
line.long 0x00 "MONTH,Months Register"
|
|
bitfld.long 0x00 04. " MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0010++0x03
|
|
line.long 0x00 "MONTH,Months Register"
|
|
bitfld.long 0x00 04. " MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0014++0x03
|
|
line.long 0x00 "YEAR,Years Register"
|
|
bitfld.long 0x00 04.--07. " YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0018++0x03
|
|
line.long 0x00 "DOTW,Day of the Week Register"
|
|
bitfld.long 0x00 00.--02. " DOTW ,Day of the week" "Sun,Mon,Tue,Wed,Thu,Fri,Sat,-"
|
|
group.long 0x0020++0x03
|
|
line.long 0x00 "ALARMSECOND,Alarm Seconds Register"
|
|
bitfld.long 0x00 04.--06. " AL_SEC ,Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0024++0x03
|
|
line.long 0x00 "ALARMMINUTE,Alarm Minutes Register"
|
|
bitfld.long 0x00 04.--06. " AL_MIN ,Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if ((data.long(asd:0x01c23000+0x40)&0x08)==0x08)&&((data.long(asd:0x01c23000+0x28)&0x30)==0x10)
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(asd:0x01c23000+0x40)&0x08)==0x08)&&((data.long(asd:0x01c23000+0x28)&0x30)!=0x10)
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(asd:0x01c23000+0x40)&0x08)==0x00)&&((data.long(asd:0x01c23000+0x28)&0x30)==0x20)
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0028++0x03
|
|
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(asd:0x01c23000+0x30)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(asd:0x01c23000+0x2c))&0x30)==0x30)
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x30)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(asd:0x01c23000+0x2c))&0x30)!=0x30)
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x30)&0x1f)==0x02))
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((data.long(asd:0x01c23000+0x30)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(asd:0x01c23000+0x2c))&0x30)==0x30)
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x002C++0x03
|
|
line.long 0x00 "ALARMDAY,Alarm Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(asd:0x01c23000+0x30))&0x10)==0x10)
|
|
group.long 0x0030++0x03
|
|
line.long 0x00 "ALARMMONTH,Alarm Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x30))&0x10)==0x00)
|
|
group.long 0x0030++0x03
|
|
line.long 0x00 "ALARMMONTH,Alarm Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0034++0x03
|
|
line.long 0x00 "ALARMYEAR,Alarm Years Register"
|
|
bitfld.long 0x00 04.--07. " AL_YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0040++0x13
|
|
line.long 0x00 "CTRL,RTC Control Register"
|
|
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
|
|
bitfld.long 0x00 07. " SPLITPOWER ,Enable split power" "Disabled,Enabled"
|
|
bitfld.long 0x00 06. " RTCDISABLE ,Disable RTC" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 06. " RTCDISABLE ,Disable RTC" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET32COUNTER ,Set the 32-kHz counter" "No action,Set"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 04. " TESTMODE ,Test mode" "Functional,Test"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " HOURMODE ,Mode 12-hours or 24-hours" "24-hour,12-hour"
|
|
bitfld.long 0x00 02. " AUTOCOMP ,Enable autocompensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " ROUNDMIN ,Round time to the closest minute" "Not rounded,Rounded"
|
|
bitfld.long 0x00 00. " RUN ,Stop RTC" "Stopped,Running"
|
|
line.long 0x04 "STATUS,RTC Status Register"
|
|
sif (cpuis("DRA62*"))
|
|
eventfld.long 0x04 07. " ALARM2 ,Alarm2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 06. " ALARM ,Alarm interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 05. " DAYEVT ,One day has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 04. " HREVT ,One hour has occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 03. " MINEVT ,One minute has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x04 02. " SECEVT ,One second has occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 01. " RUN ,RTC run" "Stopped,Running"
|
|
bitfld.long 0x04 00. " BUSY ,Updating event in more than 15 us" "Not busy,Busy"
|
|
line.long 0x08 "INTERRUPT,RTC Interrupt Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x08 04. " ALARM2 ,Enable one interrupt when the alarm2 value is reached" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 03. " ALARM ,Enable one interrupt when the alarm value is reached" "Disabled,Enabled"
|
|
bitfld.long 0x08 02. " TIMER ,Enable periodic interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 00.--01. " EVERY ,Interrupt period" "Every second,Every minute,Every hour,Every day"
|
|
line.long 0x0c "COMPLSB,RTC Compensation LSB Register"
|
|
hexmask.long.byte 0x0c 00.--07. 1. " COMPLSB ,Lower bits of the 16-bit compensation value"
|
|
line.long 0x10 "COMPMSB,RTC Compensation MSB Register"
|
|
hexmask.long.byte 0x10 00.--07. 1. " COMPMSB ,Higher bits of the 16-bit compensation value"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
group.long 0x0054++0x03
|
|
else
|
|
wgroup.long 0x0054++0x03
|
|
endif
|
|
line.long 0x00 "OSC,RTC Oscillator Register"
|
|
sif (cpuis("DRA62*"))
|
|
bitfld.long 0x00 6. " 32KCLK_EN ,32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OSC32K_GZ ,Disable the oscillator and apply high impedance to the output" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " 32KCLK_SEL ,32-kHz clock source select" "rtc_32k_clk_rtc_32k_aux_clk,rtc_32k_clk_rtc_32k_clk"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RES_SELECT ,External feedback resistor" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW2 ,Inverter size adjustment" "Low,High"
|
|
bitfld.long 0x00 0. " SW1 ,Inverter size adjustment" "Low,High"
|
|
else
|
|
bitfld.long 0x00 05. " SWRESET ,Software reset" "No effect,Reset"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
bitfld.long 0x00 04. " OSC32KPWRDNR ,Control of 32 kHz Oscillator powerdown" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 00.--03. " SWRESPROG ,Value of the oscillator resistance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x0060++0x013
|
|
line.long 0x00 "SCRATCH0,Scratch Register 0"
|
|
line.long 0x04 "SCRATCH1,Scratch Register 1"
|
|
line.long 0x08 "SCRATCH2,Scratch Register 2"
|
|
line.long 0x0c "KICK0R,Kick 0 Register"
|
|
line.long 0x10 "KICK1R,Kick 1 Register"
|
|
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
|
|
rgroup.long 0x0074++0x03
|
|
line.long 0x00 "REVISION,RTC Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
|
|
group.long 0x0078++0x07
|
|
line.long 0x00 "SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 0.--1. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
|
|
line.long 0x04 "IRQWAKEEN,Wakeup Enable Register"
|
|
bitfld.long 0x04 1. " ALARM_WAKEEN ,Wakeup generation for event Alarm" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TIMER_WAKEEN ,Wakeup generation for event Timer" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("DRA62*"))
|
|
group.long 0x0080++0x03
|
|
line.long 0x00 "ALARM2SECOND,Alarm2 Seconds Register"
|
|
bitfld.long 0x00 04.--06. " AL_SEC ,Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
group.long 0x0084++0x03
|
|
line.long 0x00 "ALARM2MINUTE,Alarm2 Minutes Register"
|
|
bitfld.long 0x00 04.--06. " AL_MIN ,Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
if ((data.long(asd:0x01c23000+0x40)&0x08)==0x08)&&((data.long(asd:0x01c23000+0x88)&0x30)==0x10)
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(asd:0x01c23000+0x40)&0x08)==0x08)&&((data.long(asd:0x01c23000+0x88)&0x30)!=0x10)
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
|
|
elif ((data.long(asd:0x01c23000+0x40)&0x08)==0x00)&&((data.long(asd:0x01c23000+0x88)&0x30)==0x20)
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0088++0x03
|
|
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
|
|
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(asd:0x01c23000+0x90)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(asd:0x01c23000+0x8c))&0x30)==0x30)
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x90)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(asd:0x01c23000+0x8c))&0x30)!=0x30)
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x90)&0x1f)==0x02))
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,-"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((data.long(asd:0x01c23000+0x90)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(asd:0x01c23000+0x8c))&0x30)==0x30)
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x008C++0x03
|
|
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
|
|
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
if (((data.long(asd:0x01c23000+0x90))&0x10)==0x10)
|
|
group.long 0x0090++0x03
|
|
line.long 0x00 "ALARM2MONTH,Alarm2 Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
elif (((data.long(asd:0x01c23000+0x90))&0x10)==0x00)
|
|
group.long 0x0090++0x03
|
|
line.long 0x00 "ALARM2MONTH,Alarm2 Months Register"
|
|
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
|
|
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x0094++0x0B
|
|
line.long 0x00 "ALARM2YEAR,Alarm2 Years Register"
|
|
bitfld.long 0x00 04.--07. " AL_YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
line.long 0x04 "RTC_PMIC,RTC PMIC Register"
|
|
bitfld.long 0x04 17.--18. " PWR_ENABL_SM ,Power state machine state" "Idle,Shutdown,Time-based wakeup,External-event-based wakeup"
|
|
bitfld.long 0x04 16. " PWR_ENABLE_EN ,PWR_enable enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 15. " EXT_WAKEUP_STATUS[3] ,External wakeup status 3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 14. " EXT_WAKEUP_STATUS[2] ,External wakeup status 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 13. " EXT_WAKEUP_STATUS[1] ,External wakeup status 1" "Not occurred,Occurred"
|
|
eventfld.long 0x04 12. " EXT_WAKEUP_STATUS[0] ,External wakeup status 0" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EXT_WAKEUP_DB_EN[3] ,External wakeup debounce enabled 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EXT_WAKEUP_DB_EN[2] ,External wakeup debounce enabled 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EXT_WAKEUP_DB_EN[1] ,External wakeup debounce enabled 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EXT_WAKEUP_DB_EN[0] ,External wakeup debounce enabled 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EXT_WAKEUP_POL[3] ,External wakeup inputs polarity 3" "Active high,Active low"
|
|
bitfld.long 0x04 6. " EXT_WAKEUP_POL[2] ,External wakeup inputs polarity 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EXT_WAKEUP_POL[1] ,External wakeup inputs polarity 1" "Active high,Active low"
|
|
bitfld.long 0x04 4. " EXT_WAKEUP_POL[0] ,External wakeup inputs polarity 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EXT_WAKEUP_EN[3] ,Enable external wakeup inputs 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EXT_WAKEUP_EN[2] ,Enable external wakeup inputs 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EXT_WAKEUP_EN[1] ,Enable external wakeup inputs 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EXT_WAKEUP_EN[0] ,Enable external wakeup inputs 0" "Disabled,Enabled"
|
|
line.long 0x08 "RTC_DEBOUNCE,RTC Debounce Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " XX ,xx"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DEBOUNCE_REG ,Debounce time"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
textline ""
|